//*****************************************************************************

//

// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/

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//*****************************************************************************

#ifndef __HW_OCP_SHARED_H__

#define __HW_OCP_SHARED_H__

//*****************************************************************************

//

// The following are defines for the OCP_SHARED register offsets.

//

//*****************************************************************************

#define OCP_SHARED_O_SEMAPHORE1 0x00000000

#define OCP_SHARED_O_SEMAPHORE2 0x00000004

#define OCP_SHARED_O_SEMAPHORE3 0x00000008

#define OCP_SHARED_O_SEMAPHORE4 0x0000000C

#define OCP_SHARED_O_SEMAPHORE5 0x00000010

#define OCP_SHARED_O_SEMAPHORE6 0x00000014

#define OCP_SHARED_O_SEMAPHORE7 0x00000018

#define OCP_SHARED_O_SEMAPHORE8 0x0000001C

#define OCP_SHARED_O_SEMAPHORE9 0x00000020

#define OCP_SHARED_O_SEMAPHORE10 \

0x00000024

#define OCP_SHARED_O_SEMAPHORE11 \

0x00000028

#define OCP_SHARED_O_SEMAPHORE12 \

0x0000002C

#define OCP_SHARED_O_IC_LOCKER_ID \

0x00000030

#define OCP_SHARED_O_MCU_SEMAPHORE_PEND \

0x00000034

#define OCP_SHARED_O_WL_SEMAPHORE_PEND \

0x00000038

#define OCP_SHARED_O_PLATFORM_DETECTION_RD_ONLY \

0x0000003C

#define OCP_SHARED_O_SEMAPHORES_STATUS_RD_ONLY \

0x00000040

#define OCP_SHARED_O_CC3XX_CONFIG_CTRL \

0x00000044

#define OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_LSB \

0x00000048

#define OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_MSB \

0x0000004C

#define OCP_SHARED_O_WLAN_ELP_WAKE_EN \

0x00000050

#define OCP_SHARED_O_DEVINIT_ROM_START_ADDR \

0x00000054

#define OCP_SHARED_O_DEVINIT_ROM_END_ADDR \

0x00000058

#define OCP_SHARED_O_SSBD_SEED 0x0000005C

#define OCP_SHARED_O_SSBD_CHK 0x00000060

#define OCP_SHARED_O_SSBD_POLY_SEL \

0x00000064

#define OCP_SHARED_O_SPARE_REG_0 \

0x00000068

#define OCP_SHARED_O_SPARE_REG_1 \

0x0000006C

#define OCP_SHARED_O_SPARE_REG_2 \

0x00000070

#define OCP_SHARED_O_SPARE_REG_3 \

0x00000074

#define OCP_SHARED_O_GPIO_PAD_CONFIG_0 \

0x000000A0

#define OCP_SHARED_O_GPIO_PAD_CONFIG_1 \

0x000000A4

#define OCP_SHARED_O_GPIO_PAD_CONFIG_2 \

0x000000A8

#define OCP_SHARED_O_GPIO_PAD_CONFIG_3 \

0x000000AC

#define OCP_SHARED_O_GPIO_PAD_CONFIG_4 \

0x000000B0

#define OCP_SHARED_O_GPIO_PAD_CONFIG_5 \

0x000000B4

#define OCP_SHARED_O_GPIO_PAD_CONFIG_6 \

0x000000B8

#define OCP_SHARED_O_GPIO_PAD_CONFIG_7 \

0x000000BC

#define OCP_SHARED_O_GPIO_PAD_CONFIG_8 \

0x000000C0

#define OCP_SHARED_O_GPIO_PAD_CONFIG_9 \

0x000000C4

#define OCP_SHARED_O_GPIO_PAD_CONFIG_10 \

0x000000C8

#define OCP_SHARED_O_GPIO_PAD_CONFIG_11 \

0x000000CC

#define OCP_SHARED_O_GPIO_PAD_CONFIG_12 \

0x000000D0

#define OCP_SHARED_O_GPIO_PAD_CONFIG_13 \

0x000000D4

#define OCP_SHARED_O_GPIO_PAD_CONFIG_14 \

0x000000D8

#define OCP_SHARED_O_GPIO_PAD_CONFIG_15 \

0x000000DC

#define OCP_SHARED_O_GPIO_PAD_CONFIG_16 \

0x000000E0

#define OCP_SHARED_O_GPIO_PAD_CONFIG_17 \

0x000000E4

#define OCP_SHARED_O_GPIO_PAD_CONFIG_18 \

0x000000E8

#define OCP_SHARED_O_GPIO_PAD_CONFIG_19 \

0x000000EC

#define OCP_SHARED_O_GPIO_PAD_CONFIG_20 \

0x000000F0

#define OCP_SHARED_O_GPIO_PAD_CONFIG_21 \

0x000000F4

#define OCP_SHARED_O_GPIO_PAD_CONFIG_22 \

0x000000F8

#define OCP_SHARED_O_GPIO_PAD_CONFIG_23 \

0x000000FC

#define OCP_SHARED_O_GPIO_PAD_CONFIG_24 \

0x00000100

#define OCP_SHARED_O_GPIO_PAD_CONFIG_25 \

0x00000104

#define OCP_SHARED_O_GPIO_PAD_CONFIG_26 \

0x00000108

#define OCP_SHARED_O_GPIO_PAD_CONFIG_27 \

0x0000010C

#define OCP_SHARED_O_GPIO_PAD_CONFIG_28 \

0x00000110

#define OCP_SHARED_O_GPIO_PAD_CONFIG_29 \

0x00000114

#define OCP_SHARED_O_GPIO_PAD_CONFIG_30 \

0x00000118

#define OCP_SHARED_O_GPIO_PAD_CONFIG_31 \

0x0000011C

#define OCP_SHARED_O_GPIO_PAD_CONFIG_32 \

0x00000120

#define OCP_SHARED_O_GPIO_PAD_CONFIG_33 \

0x00000124

#define OCP_SHARED_O_GPIO_PAD_CONFIG_34 \

0x00000128

#define OCP_SHARED_O_GPIO_PAD_CONFIG_35 \

0x0000012C

#define OCP_SHARED_O_GPIO_PAD_CONFIG_36 \

0x00000130

#define OCP_SHARED_O_GPIO_PAD_CONFIG_37 \

0x00000134

#define OCP_SHARED_O_GPIO_PAD_CONFIG_38 \

0x00000138

#define OCP_SHARED_O_GPIO_PAD_CONFIG_39 \

0x0000013C

#define OCP_SHARED_O_GPIO_PAD_CONFIG_40 \

0x00000140

#define OCP_SHARED_O_GPIO_PAD_CMN_CONFIG \

0x00000144 // This register provide control to

// GPIO_CC3XXV1 IO PAD. Common

// control signals to all bottom Die

// IO's are controlled via this.

#define OCP_SHARED_O_D2D_DEV_PAD_CMN_CONFIG \

0x00000148

#define OCP_SHARED_O_D2D_TOSTACK_PAD_CONF \

0x0000014C

#define OCP_SHARED_O_D2D_MISC_PAD_CONF \

0x00000150

#define OCP_SHARED_O_SOP_CONF_OVERRIDE \

0x00000154

#define OCP_SHARED_O_CC3XX_DEBUGSS_STATUS \

0x00000158

#define OCP_SHARED_O_CC3XX_DEBUGMUX_SEL \

0x0000015C

#define OCP_SHARED_O_ALT_PC_VAL_NW \

0x00000160

#define OCP_SHARED_O_ALT_PC_VAL_APPS \

0x00000164

#define OCP_SHARED_O_SPARE_REG_4 \

0x00000168

#define OCP_SHARED_O_SPARE_REG_5 \

0x0000016C

#define OCP_SHARED_O_SH_SPI_CS_MASK \

0x00000170

#define OCP_SHARED_O_CC3XX_DEVICE_TYPE \

0x00000174

#define OCP_SHARED_O_MEM_TOPMUXCTRL_IFORCE \

0x00000178

#define OCP_SHARED_O_CC3XX_DEV_PACKAGE_DETECT \

0x0000017C

#define OCP_SHARED_O_AUTONMS_SPICLK_SEL \

0x00000180

#define OCP_SHARED_O_CC3XX_DEV_PADCONF \

0x00000184

#define OCP_SHARED_O_SPARE_REG_8 \

0x00000188

#define OCP_SHARED_O_SPARE_REG_6 \

0x0000018C

#define OCP_SHARED_O_SPARE_REG_7 \

0x00000190

#define OCP_SHARED_O_APPS_WLAN_ORBIT \

0x00000194

#define OCP_SHARED_O_APPS_WLAN_SCRATCH_PAD \

0x00000198

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_SEMAPHORE1 register.

//

//******************************************************************************

#define OCP_SHARED_SEMAPHORE1_MEM_SEMAPHORE1_M \

0x00000003 // General Purpose Semaphore for SW

// Usage. If any of the 2 bits of a

// given register is set to 1, it

// means that the semaphore is

// locked by one of the masters.

// Each bit represents a master IP

// as follows: {WLAN,NWP}. The JTAG

// cannot capture the semaphore but

// it can release it. As a master IP

// reads the semaphore, it will be

// caputed and the masters

// correlating bit will be set to 1

// (set upon read). As any IP writes

// to this address (independent of

// the written data) the semaphore

// will be set to 2'b00.

#define OCP_SHARED_SEMAPHORE1_MEM_SEMAPHORE1_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_SEMAPHORE2 register.

//

//******************************************************************************

#define OCP_SHARED_SEMAPHORE2_MEM_SEMAPHORE2_M \

0x00000003 // General Purpose Semaphore for SW

// Usage. If any of the 2 bits of a

// given register is set to 1, it

// means that the semaphore is

// locked by one of the masters.

// Each bit represents a master IP

// as follows: {WLAN,NWP}. The JTAG

// cannot capture the semaphore but

// it can release it. As a master IP

// reads the semaphore, it will be

// caputed and the masters

// correlating bit will be set to 1

// (set upon read). As any IP writes

// to this address (independent of

// the written data) the semaphore

// will be set to 2'b00.

#define OCP_SHARED_SEMAPHORE2_MEM_SEMAPHORE2_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_SEMAPHORE3 register.

//

//******************************************************************************

#define OCP_SHARED_SEMAPHORE3_MEM_SEMAPHORE3_M \

0x00000003 // General Purpose Semaphore for SW

// Usage. If any of the 2 bits of a

// given register is set to 1, it

// means that the semaphore is

// locked by one of the masters.

// Each bit represents a master IP

// as follows: {WLAN,NWP}. The JTAG

// cannot capture the semaphore but

// it can release it. As a master IP

// reads the semaphore, it will be

// caputed and the masters

// correlating bit will be set to 1

// (set upon read). As any IP writes

// to this address (independent of

// the written data) the semaphore

// will be set to 2'b00.

#define OCP_SHARED_SEMAPHORE3_MEM_SEMAPHORE3_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_SEMAPHORE4 register.

//

//******************************************************************************

#define OCP_SHARED_SEMAPHORE4_MEM_SEMAPHORE4_M \

0x00000003 // General Purpose Semaphore for SW

// Usage. If any of the 2 bits of a

// given register is set to 1, it

// means that the semaphore is

// locked by one of the masters.

// Each bit represents a master IP

// as follows: {WLAN,NWP}. The JTAG

// cannot capture the semaphore but

// it can release it. As a master IP

// reads the semaphore, it will be

// caputed and the masters

// correlating bit will be set to 1

// (set upon read). As any IP writes

// to this address (independent of

// the written data) the semaphore

// will be set to 2'b00.

#define OCP_SHARED_SEMAPHORE4_MEM_SEMAPHORE4_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_SEMAPHORE5 register.

//

//******************************************************************************

#define OCP_SHARED_SEMAPHORE5_MEM_SEMAPHORE5_M \

0x00000003 // General Purpose Semaphore for SW

// Usage. If any of the 2 bits of a

// given register is set to 1, it

// means that the semaphore is

// locked by one of the masters.

// Each bit represents a master IP

// as follows: {WLAN,NWP}. The JTAG

// cannot capture the semaphore but

// it can release it. As a master IP

// reads the semaphore, it will be

// caputed and the masters

// correlating bit will be set to 1

// (set upon read). As any IP writes

// to this address (independent of

// the written data) the semaphore

// will be set to 2'b00.

#define OCP_SHARED_SEMAPHORE5_MEM_SEMAPHORE5_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_SEMAPHORE6 register.

//

//******************************************************************************

#define OCP_SHARED_SEMAPHORE6_MEM_SEMAPHORE6_M \

0x00000003 // General Purpose Semaphore for SW

// Usage. If any of the 2 bits of a

// given register is set to 1, it

// means that the semaphore is

// locked by one of the masters.

// Each bit represents a master IP

// as follows: {WLAN,NWP}. The JTAG

// cannot capture the semaphore but

// it can release it. As a master IP

// reads the semaphore, it will be

// caputed and the masters

// correlating bit will be set to 1

// (set upon read). As any IP writes

// to this address (independent of

// the written data) the semaphore

// will be set to 2'b00.

#define OCP_SHARED_SEMAPHORE6_MEM_SEMAPHORE6_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_SEMAPHORE7 register.

//

//******************************************************************************

#define OCP_SHARED_SEMAPHORE7_MEM_SEMAPHORE7_M \

0x00000003 // General Purpose Semaphore for SW

// Usage. If any of the 2 bits of a

// given register is set to 1, it

// means that the semaphore is

// locked by one of the masters.

// Each bit represents a master IP

// as follows: {WLAN,NWP}. The JTAG

// cannot capture the semaphore but

// it can release it. As a master IP

// reads the semaphore, it will be

// caputed and the masters

// correlating bit will be set to 1

// (set upon read). As any IP writes

// to this address (independent of

// the written data) the semaphore

// will be set to 2'b00.

#define OCP_SHARED_SEMAPHORE7_MEM_SEMAPHORE7_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_SEMAPHORE8 register.

//

//******************************************************************************

#define OCP_SHARED_SEMAPHORE8_MEM_SEMAPHORE8_M \

0x00000003 // General Purpose Semaphore for SW

// Usage. If any of the 2 bits of a

// given register is set to 1, it

// means that the semaphore is

// locked by one of the masters.

// Each bit represents a master IP

// as follows: {WLAN,NWP}. The JTAG

// cannot capture the semaphore but

// it can release it. As a master IP

// reads the semaphore, it will be

// caputed and the masters

// correlating bit will be set to 1

// (set upon read). As any IP writes

// to this address (independent of

// the written data) the semaphore

// will be set to 2'b00.

#define OCP_SHARED_SEMAPHORE8_MEM_SEMAPHORE8_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_SEMAPHORE9 register.

//

//******************************************************************************

#define OCP_SHARED_SEMAPHORE9_MEM_SEMAPHORE9_M \

0x00000003 // General Purpose Semaphore for SW

// Usage. If any of the 2 bits of a

// given register is set to 1, it

// means that the semaphore is

// locked by one of the masters.

// Each bit represents a master IP

// as follows: {WLAN,NWP}. The JTAG

// cannot capture the semaphore but

// it can release it. As a master IP

// reads the semaphore, it will be

// caputed and the masters

// correlating bit will be set to 1

// (set upon read). As any IP writes

// to this address (independent of

// the written data) the semaphore

// will be set to 2'b00.

#define OCP_SHARED_SEMAPHORE9_MEM_SEMAPHORE9_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_SEMAPHORE10 register.

//

//******************************************************************************

#define OCP_SHARED_SEMAPHORE10_MEM_SEMAPHORE10_M \

0x00000003 // General Purpose Semaphore for SW

// Usage. If any of the 2 bits of a

// given register is set to 1, it

// means that the semaphore is

// locked by one of the masters.

// Each bit represents a master IP

// as follows: {WLAN,NWP}. The JTAG

// cannot capture the semaphore but

// it can release it. As a master IP

// reads the semaphore, it will be

// caputed and the masters

// correlating bit will be set to 1

// (set upon read). As any IP writes

// to this address (independent of

// the written data) the semaphore

// will be set to 2'b00.

#define OCP_SHARED_SEMAPHORE10_MEM_SEMAPHORE10_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_SEMAPHORE11 register.

//

//******************************************************************************

#define OCP_SHARED_SEMAPHORE11_MEM_SEMAPHORE11_M \

0x00000003 // General Purpose Semaphore for SW

// Usage. If any of the 2 bits of a

// given register is set to 1, it

// means that the semaphore is

// locked by one of the masters.

// Each bit represents a master IP

// as follows: {WLAN,NWP}. The JTAG

// cannot capture the semaphore but

// it can release it. As a master IP

// reads the semaphore, it will be

// caputed and the masters

// correlating bit will be set to 1

// (set upon read). As any IP writes

// to this address (independent of

// the written data) the semaphore

// will be set to 2'b00.

#define OCP_SHARED_SEMAPHORE11_MEM_SEMAPHORE11_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_SEMAPHORE12 register.

//

//******************************************************************************

#define OCP_SHARED_SEMAPHORE12_MEM_SEMAPHORE12_M \

0x00000003 // General Purpose Semaphore for SW

// Usage. If any of the 2 bits of a

// given register is set to 1, it

// means that the semaphore is

// locked by one of the masters.

// Each bit represents a master IP

// as follows: {WLAN,NWP}. The JTAG

// cannot capture the semaphore but

// it can release it. As a master IP

// reads the semaphore, it will be

// caputed and the masters

// correlating bit will be set to 1

// (set upon read). As any IP writes

// to this address (independent of

// the written data) the semaphore

// will be set to 2'b00.

#define OCP_SHARED_SEMAPHORE12_MEM_SEMAPHORE12_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_IC_LOCKER_ID register.

//

//******************************************************************************

#define OCP_SHARED_IC_LOCKER_ID_MEM_IC_LOCKER_ID_M \

0x00000007 // This register is used for

// allowing only one master OCP to

// perform write transactions to the

// OCP slaves. Each bit represents

// an IP in the following format: {

// JTAG,WLAN, NWP mcu}. As any of

// the bits is set to one, the

// correlating IP is preventing the

// other IP's from performing write

// transactions to the slaves. As

// the Inter Connect is locked, the

// only the locking IP can write to

// the register and by that

// releasing the lock. 3'b000 => IC

// is not locked. 3'b001 => IC is

// locked by NWP mcu. 3'b010 => IC

// is locked by WLAN. 3'b100 => IC

// is locked by JTAG.

#define OCP_SHARED_IC_LOCKER_ID_MEM_IC_LOCKER_ID_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_MCU_SEMAPHORE_PEND register.

//

//******************************************************************************

#define OCP_SHARED_MCU_SEMAPHORE_PEND_MEM_MCU_SEMAPHORE_PEND_M \

0x0000FFFF // This register specifies the

// semaphore for which the NWP mcu

// is waiting to be released. It is

// set to the serial number of a

// given locked semaphore after it

// was read by the NWP mcu. Only

// [11:0] is used.

#define OCP_SHARED_MCU_SEMAPHORE_PEND_MEM_MCU_SEMAPHORE_PEND_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_WL_SEMAPHORE_PEND register.

//

//******************************************************************************

#define OCP_SHARED_WL_SEMAPHORE_PEND_MEM_WL_SEMAPHORE_PEND_M \

0x0000FFFF // This register specifies the

// semaphore for which the WLAN is

// waiting to be released. It is set

// to the serial number of a given

// locked semaphore after it was

// read by the WLAN. Only [11:0] is

// used.

#define OCP_SHARED_WL_SEMAPHORE_PEND_MEM_WL_SEMAPHORE_PEND_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_PLATFORM_DETECTION_RD_ONLY register.

//

//******************************************************************************

#define OCP_SHARED_PLATFORM_DETECTION_RD_ONLY_PLATFORM_DETECTION_M \

0x0000FFFF // This information serves the IPs

// for knowing in which platform are

// they integrated at: 0 = CC31XX.

#define OCP_SHARED_PLATFORM_DETECTION_RD_ONLY_PLATFORM_DETECTION_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_SEMAPHORES_STATUS_RD_ONLY register.

//

//******************************************************************************

#define OCP_SHARED_SEMAPHORES_STATUS_RD_ONLY_SEMAPHORES_STATUS_M \

0x00000FFF // Captured/released semaphores

// status for the 12 semaphores.

// Each bit of the 12 bits

// represents a semaphore. 0 =>

// Semaphore Free. 1 => Semaphore

// Captured.

#define OCP_SHARED_SEMAPHORES_STATUS_RD_ONLY_SEMAPHORES_STATUS_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_CC3XX_CONFIG_CTRL register.

//

//******************************************************************************

#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_IC_TO_EN \

0x00000010 // This bit is used to enable

// timeout mechanism for top_ocp_ic

// (for debug puropse). When 1 value

// , in case any ocp slave doesn't

// give sresponse within 16 cylcles

// top_ic will give error response

// itself to avoid bus hange.

#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_ALT_PC_EN_APPS \

0x00000008 // 1 bit should be accessible only

// in devinit. This will enable 0x4

// hack for apps processor

#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_ALT_PC_EN_NW \

0x00000004 // 1 bit, should be accessible only

// in devinit. This will enable 0x4

// hack for nw processor

#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_EXTEND_NW_ROM \

0x00000002 // When set NW can take over apps

// rom and flash via IDCODE bus.

// Apps will able to access this

// register only during devinit and

// reset value should be 0.

#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_WLAN_HOST_INTF_SEL \

0x00000001 // When this bit is set to 0 WPSI

// host interface wil be selected,

// when this bit is set to 1 , WLAN

// host async bridge will be

// selected.

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_LSB register.

//

//******************************************************************************

#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_LSB_MEM_SHARED_MEM_SEL_LSB_M \

0x3FFFFFFF // This register provides memss RAM

// column configuration for column 0

// to 9. 3 bits are allocated per

// column. This register is required

// to be configured before starting

// RAM access. Changing register

// setting while code is running

// will result into unpredictable

// memory behaviour. Register is

// supported to configured ones

// after core is booted up. 3 bit

// encoding per column is as

// follows: when 000 : WLAN, 001:

// NWP, 010: APPS, 011: PHY, 100:

// OCLA column 0 select: bit [2:0]

// :when 000 -> WLAN,001 -> NWP,010

// -> APPS, 011 -> PHY, 100 -> OCLA

// column 1 select: bit [5:3]

// :column 2 select: bit [8 : 6]:

// column 3 select : bit [11: 9]

// column 4 select : bit [14:12]

// column 5 select : bit [17:15]

// column 6 select : bit [20:18]

// column 7 select : bit [23:21]

// column 8 select : bit [26:24]

// column 9 select : bit [29:27]

// column 10 select

#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_LSB_MEM_SHARED_MEM_SEL_LSB_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_MSB register.

//

//******************************************************************************

#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_MSB_MEM_SHARED_MEM_SEL_MSB_M \

0x00000FFF // This register provides memss RAM

// column configuration for column

// 10 to 15. 3 bits are allocated

// per column. This register is

// required to be configured before

// starting RAM access. Changing

// register setting while code is

// running will result into

// unpredictable memory behaviour.

// Register is supported to

// configured ones after core is

// booted up. 3 bit encoding per

// column is as follows: when 000 :

// WLAN, 001: NWP, 010: APPS, 011:

// PHY, 100: OCLA column 11 select :

// bit [2:0] column 12 select : bit

// [5:3] column 13 select : bit [8 :

// 6] column 14 select :

#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_MSB_MEM_SHARED_MEM_SEL_MSB_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_WLAN_ELP_WAKE_EN register.

//

//******************************************************************************

#define OCP_SHARED_WLAN_ELP_WAKE_EN_MEM_WLAN_ELP_WAKE_EN \

0x00000001 // when '1' : signal will enabled

// ELP power doamin when '0': ELP is

// not powered up.

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_DEVINIT_ROM_START_ADDR register.

//

//******************************************************************************

#define OCP_SHARED_DEVINIT_ROM_START_ADDR_MEM_DEVINIT_ROM_START_ADDR_M \

0xFFFFFFFF // 32 bit, Writable only during

// devinit, and whole 32 bit should

// be output of the config register

// module. This register is not used

// , similar register availble in

// GPRCM space.

#define OCP_SHARED_DEVINIT_ROM_START_ADDR_MEM_DEVINIT_ROM_START_ADDR_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_DEVINIT_ROM_END_ADDR register.

//

//******************************************************************************

#define OCP_SHARED_DEVINIT_ROM_END_ADDR_MEM_DEVINIT_ROM_END_ADDR_M \

0xFFFFFFFF // 32 bit, Writable only during

// devinit, and whole 32 bit should

// be output of the config register

// module.

#define OCP_SHARED_DEVINIT_ROM_END_ADDR_MEM_DEVINIT_ROM_END_ADDR_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_SSBD_SEED register.

//

//******************************************************************************

#define OCP_SHARED_SSBD_SEED_MEM_SSBD_SEED_M \

0xFFFFFFFF // 32 bit, Writable only during

// devinit, and whole 32 bit should

// be output of the config register

// module.

#define OCP_SHARED_SSBD_SEED_MEM_SSBD_SEED_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_SSBD_CHK register.

//

//******************************************************************************

#define OCP_SHARED_SSBD_CHK_MEM_SSBD_CHK_M \

0xFFFFFFFF // 32 bit, Writable only during

// devinit, and whole 32 bit should

// be output of the config register

// module.

#define OCP_SHARED_SSBD_CHK_MEM_SSBD_CHK_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_SSBD_POLY_SEL register.

//

//******************************************************************************

#define OCP_SHARED_SSBD_POLY_SEL_MEM_SSBD_POLY_SEL_M \

0x00000003 // 2 bit, Writable only during

// devinit, and whole 2 bit should

// be output of the config register

// module.

#define OCP_SHARED_SSBD_POLY_SEL_MEM_SSBD_POLY_SEL_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_SPARE_REG_0 register.

//

//******************************************************************************

#define OCP_SHARED_SPARE_REG_0_MEM_SPARE_REG_0_M \

0xFFFFFFFF // Devinit code should look for

// whether corresponding fuse is

// blown and if blown write to the

// 11th bit of this register to

// disable flshtst interface

#define OCP_SHARED_SPARE_REG_0_MEM_SPARE_REG_0_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_SPARE_REG_1 register.

//

//******************************************************************************

#define OCP_SHARED_SPARE_REG_1_MEM_SPARE_REG_1_M \

0xFFFFFFFF // NWP Software register

#define OCP_SHARED_SPARE_REG_1_MEM_SPARE_REG_1_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_SPARE_REG_2 register.

//

//******************************************************************************

#define OCP_SHARED_SPARE_REG_2_MEM_SPARE_REG_2_M \

0xFFFFFFFF // NWP Software register

#define OCP_SHARED_SPARE_REG_2_MEM_SPARE_REG_2_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_SPARE_REG_3 register.

//

//******************************************************************************

#define OCP_SHARED_SPARE_REG_3_MEM_SPARE_REG_3_M \

0xFFFFFFFF // APPS Software register

#define OCP_SHARED_SPARE_REG_3_MEM_SPARE_REG_3_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_GPIO_PAD_CONFIG_0 register.

//

//******************************************************************************

#define OCP_SHARED_GPIO_PAD_CONFIG_0_MEM_GPIO_PAD_CONFIG_0_M \

0x00000FFF // GPIO 0 register: "Bit 0 - 3 is

// used for PAD IO mode selection.

// io_register={ "" 0 =>

// """"CONFMODE[0]"""""" "" 1 =>

// """"CONFMODE[1]"""""" "" 2 =>

// """"CONFMODE[2]"""""" "" 3 =>

// """"CONFMODE[3]"""" 4 =>

// """"IODEN"""" --> When level ‘1’

// this disables the PMOS xtors of

// the output stages making them

// open-drain type." "For example in

// case of I2C Value gets latched at

// rising edge of RET33.""" """ 5 =>

// """"I2MAEN"""" --> Level ‘1’

// enables the approx 2mA output

// stage""" """ 6 => """"I4MAEN""""

// --> Level ‘1’ enables the approx

// 4mA output stage""" """ 7 =>

// """"I8MAEN"""" --> Level ‘1’

// enables the approx 8mA output

// stage. Note: any drive strength

// between 2mA and 14mA can be

// obtained with combination of 2mA

// 4mA and 8mA.""" """ 8 =>

// """"IWKPUEN"""" --> 10uA pull up

// (weak strength)""" """ 9 =>

// """"IWKPDEN"""" --> 10uA pull

// down (weak strength)""" """ 10 =>

// """"IOE_N"""" --> output enable

// value. level ‘0’ enables the IDO

// to PAD path. Else PAD is

// tristated (except for the PU/PD

// which are independent)." "Value

// gets latched at rising edge of

// RET33""" """ 11 =>""""

// IOE_N_OV"""" --> output enable

// overirde. when bit is set to

// logic '1' IOE_N (bit 4) value

// will control IO IOE_N signal else

// IOE_N is control via selected HW

// logic. strong PULL UP and PULL

// Down control is disabled for all

// IO's. both controls are tied to

// logic level '0'.

#define OCP_SHARED_GPIO_PAD_CONFIG_0_MEM_GPIO_PAD_CONFIG_0_S 0

//******************************************************************************

//

// The following are defines for the bit fields in the

// OCP_SHARED_O_GPIO_PAD_CONFIG_1 register.

//

//******************************************************************************

#define OCP_SHARED_GPIO_PAD_CONFIG_1_MEM_GPIO_PAD_CONFIG_1_M \

0x00000FFF // GPIO 0 register: "Bit 0 - 3 is

// used for PAD IO mode selection.

// io_register={ "" 0 =>

// """"CONFMODE[0]"""""" "" 1 =>

// """"CONFMODE[1]"""""" "" 2 =>

// """"CONFMODE[2]"""""" "" 3 =>

// """"CONFMODE[3]"""" 4 =>

// """"IODEN"""" --> When level ‘1’

// this disables the PMOS xtors of

// the output stages making them

// open-drain type." it can be used

// for I2C type of peripherals. 5 =>

// """"I2MAEN"""" --> Level ‘1’

// enables the approx 2mA output

// stage""" """ 6 => """"I4MAEN""""

// --> Level ‘1’ enables the approx

// 4mA output stage""" """ 7 =>

// """"I8MAEN"""" --> Level ‘1’

// enables the approx 8mA output

// stage. Note: any drive strength

// between 2mA and 14mA can be

// obtained with combination of 2mA

// 4mA and 8mA.""" """ 8 =>

// """"IWKPUEN"""" --> 10uA pull up