//*****************************************************************************

//

// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/

//

//

// Redistribution and use in source and binary forms, with or without

// modification, are permitted provided that the following conditions

// are met:

//

// Redistributions of source code must retain the above copyright

// notice, this list of conditions and the following disclaimer.

//

// Redistributions in binary form must reproduce the above copyright

// notice, this list of conditions and the following disclaimer in the

// documentation and/or other materials provided with the

// distribution.

//

// Neither the name of Texas Instruments Incorporated nor the names of

// its contributors may be used to endorse or promote products derived

// from this software without specific prior written permission.

//

// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR

// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT

// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,

// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,

// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY

// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

//

//*****************************************************************************

//*****************************************************************************

//

// hw_nvic.h - Macros used when accessing the NVIC hardware.

//

//*****************************************************************************

#ifndef __HW_NVIC_H__

#define __HW_NVIC_H__

//*****************************************************************************

//

// The following are defines for the NVIC register addresses.

//

//*****************************************************************************

#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg

#define NVIC_ACTLR 0xE000E008 // Auxiliary Control

#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status

// Register

#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register

#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register

#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg

#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable

#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable

#define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable

#define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable

#define NVIC_EN4 0xE000E110 // Interrupt 128-131 Set Enable

#define NVIC_EN5 0xE000E114 // Interrupt 160-191 Set Enable

#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable

#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable

#define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable

#define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable

#define NVIC_DIS4 0xE000E190 // Interrupt 128-131 Clear Enable

#define NVIC_DIS5 0xE000E194 // Interrupt 160-191 Clear Enable

#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending

#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending

#define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending

#define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending

#define NVIC_PEND4 0xE000E210 // Interrupt 128-131 Set Pending

#define NVIC_PEND5 0xE000E214 // Interrupt 160-191 Set Pending

#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending

#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending

#define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending

#define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending

#define NVIC_UNPEND4 0xE000E290 // Interrupt 128-131 Clear Pending

#define NVIC_UNPEND5 0xE000E294 // Interrupt 160-191 Clear Pending

#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit

#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit

#define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit

#define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit

#define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-131 Active Bit

#define NVIC_ACTIVE5 0xE000E314 // Interrupt 160-191 Active Bit

#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority

#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority

#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority

#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority

#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority

#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority

#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority

#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority

#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority

#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority

#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority

#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority

#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority

#define NVIC_PRI13 0xE000E434 // Interrupt 52-53 Priority

#define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority

#define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority

#define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority

#define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority

#define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority

#define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority

#define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority

#define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority

#define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority

#define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority

#define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority

#define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority

#define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority

#define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority

#define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority

#define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority

#define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority

#define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority

#define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority

#define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority

#define NVIC_PRI34 0xE000E488 // Interrupt 136-139 Priority

#define NVIC_PRI35 0xE000E48C // Interrupt 140-143 Priority

#define NVIC_PRI36 0xE000E490 // Interrupt 144-147 Priority

#define NVIC_PRI37 0xE000E494 // Interrupt 148-151 Priority

#define NVIC_PRI38 0xE000E498 // Interrupt 152-155 Priority

#define NVIC_PRI39 0xE000E49C // Interrupt 156-159 Priority

#define NVIC_PRI40 0xE000E4A0 // Interrupt 160-163 Priority

#define NVIC_PRI41 0xE000E4A4 // Interrupt 164-167 Priority

#define NVIC_PRI42 0xE000E4A8 // Interrupt 168-171 Priority

#define NVIC_PRI43 0xE000E4AC // Interrupt 172-175 Priority

#define NVIC_PRI44 0xE000E4B0 // Interrupt 176-179 Priority

#define NVIC_PRI45 0xE000E4B4 // Interrupt 180-183 Priority

#define NVIC_PRI46 0xE000E4B8 // Interrupt 184-187 Priority

#define NVIC_PRI47 0xE000E4BC // Interrupt 188-191 Priority

#define NVIC_PRI48 0xE000E4C0 // Interrupt 192-195 Priority

#define NVIC_CPUID 0xE000ED00 // CPU ID Base

#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State

#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset

#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset

// Control

#define NVIC_SYS_CTRL 0xE000ED10 // System Control

#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control

#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1

#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2

#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3

#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State

#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status

#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status

#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register

#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address

#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address

#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type

#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control

#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number

#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address

#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size

#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1

#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size

// Alias 1

#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2

#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size

// Alias 2

#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3

#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size

// Alias 3

#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg

#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select

#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data

#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control

#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_INT_TYPE register.

//

//*****************************************************************************

#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)

#define NVIC_INT_TYPE_LINES_S 0

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_ACTLR register.

//

//*****************************************************************************

#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding

#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer

#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple

// Cycle Instructions

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_ST_CTRL register.

//

//*****************************************************************************

#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag

#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source

#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable

#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_ST_RELOAD register.

//

//*****************************************************************************

#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value

#define NVIC_ST_RELOAD_S 0

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_ST_CURRENT

// register.

//

//*****************************************************************************

#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value

#define NVIC_ST_CURRENT_S 0

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_ST_CAL register.

//

//*****************************************************************************

#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock

#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew

#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value

#define NVIC_ST_CAL_ONEMS_S 0

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_EN0 register.

//

//*****************************************************************************

#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable

#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable

#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable

#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable

#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable

#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable

#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable

#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable

#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable

#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable

#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable

#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable

#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable

#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable

#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable

#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable

#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable

#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable

#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable

#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable

#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable

#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable

#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable

#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable

#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable

#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable

#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable

#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable

#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable

#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable

#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable

#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable

#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_EN1 register.

//

//*****************************************************************************

#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable

#undef NVIC_EN1_INT_M

#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable

#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable

#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable

#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable

#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable

#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable

#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable

#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable

#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable

#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable

#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable

#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable

#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable

#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable

#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable

#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable

#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable

#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable

#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable

#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable

#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable

#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable

#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable

#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_EN2 register.

//

//*****************************************************************************

#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_EN3 register.

//

//*****************************************************************************

#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_EN4 register.

//

//*****************************************************************************

#define NVIC_EN4_INT_M 0x0000000F // Interrupt Enable

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_DIS0 register.

//

//*****************************************************************************

#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable

#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable

#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable

#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable

#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable

#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable

#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable

#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable

#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable

#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable

#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable

#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable

#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable

#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable

#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable

#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable

#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable

#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable

#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable

#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable

#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable

#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable

#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable

#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable

#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable

#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable

#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable

#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable

#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable

#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable

#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable

#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable

#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_DIS1 register.

//

//*****************************************************************************

#define NVIC_DIS1_INT_M 0x00FFFFFF // Interrupt Disable

#undef NVIC_DIS1_INT_M

#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable

#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable

#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable

#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable

#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable

#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable

#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable

#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable

#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable

#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable

#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable

#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable

#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable

#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable

#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable

#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable

#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable

#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable

#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable

#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable

#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable

#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable

#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable

#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable

#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_DIS2 register.

//

//*****************************************************************************

#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_DIS3 register.

//

//*****************************************************************************

#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_DIS4 register.

//

//*****************************************************************************

#define NVIC_DIS4_INT_M 0x0000000F // Interrupt Disable

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PEND0 register.

//

//*****************************************************************************

#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending

#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend

#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend

#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend

#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend

#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend

#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend

#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend

#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend

#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend

#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend

#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend

#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend

#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend

#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend

#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend

#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend

#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend

#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend

#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend

#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend

#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend

#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend

#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend

#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend

#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend

#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend

#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend

#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend

#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend

#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend

#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend

#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PEND1 register.

//

//*****************************************************************************

#define NVIC_PEND1_INT_M 0x00FFFFFF // Interrupt Set Pending

#undef NVIC_PEND1_INT_M

#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending

#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend

#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend

#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend

#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend

#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend

#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend

#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend

#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend

#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend

#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend

#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend

#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend

#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend

#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend

#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend

#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend

#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend

#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend

#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend

#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend

#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend

#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend

#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend

#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PEND2 register.

//

//*****************************************************************************

#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PEND3 register.

//

//*****************************************************************************

#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PEND4 register.

//

//*****************************************************************************

#define NVIC_PEND4_INT_M 0x0000000F // Interrupt Set Pending

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_UNPEND0 register.

//

//*****************************************************************************

#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending

#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend

#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend

#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend

#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend

#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend

#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend

#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend

#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend

#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend

#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend

#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend

#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend

#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend

#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend

#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend

#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend

#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend

#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend

#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend

#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend

#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend

#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend

#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend

#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend

#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend

#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend

#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend

#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend

#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend

#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend

#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend

#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_UNPEND1 register.

//

//*****************************************************************************

#define NVIC_UNPEND1_INT_M 0x00FFFFFF // Interrupt Clear Pending

#undef NVIC_UNPEND1_INT_M

#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending

#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend

#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend

#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend

#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend

#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend

#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend

#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend

#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend

#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend

#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend

#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend

#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend

#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend

#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend

#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend

#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend

#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend

#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend

#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend

#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend

#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend

#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend

#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend

#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_UNPEND2 register.

//

//*****************************************************************************

#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_UNPEND3 register.

//

//*****************************************************************************

#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_UNPEND4 register.

//

//*****************************************************************************

#define NVIC_UNPEND4_INT_M 0x0000000F // Interrupt Clear Pending

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_ACTIVE0 register.

//

//*****************************************************************************

#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active

#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active

#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active

#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active

#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active

#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active

#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active

#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active

#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active

#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active

#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active

#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active

#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active

#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active

#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active

#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active

#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active

#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active

#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active

#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active

#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active

#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active

#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active

#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active

#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active

#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active

#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active

#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active

#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active

#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active

#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active

#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active

#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_ACTIVE1 register.

//

//*****************************************************************************

#define NVIC_ACTIVE1_INT_M 0x00FFFFFF // Interrupt Active

#undef NVIC_ACTIVE1_INT_M

#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active

#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active

#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active

#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active

#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active

#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active

#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active

#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active

#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active

#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active

#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active

#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active

#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active

#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active

#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active

#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active

#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active

#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active

#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active

#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active

#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active

#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active

#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active

#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active

#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_ACTIVE2 register.

//

//*****************************************************************************

#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_ACTIVE3 register.

//

//*****************************************************************************

#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_ACTIVE4 register.

//

//*****************************************************************************

#define NVIC_ACTIVE4_INT_M 0x0000000F // Interrupt Active

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI0 register.

//

//*****************************************************************************

#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask

#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask

#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask

#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask

#define NVIC_PRI0_INT3_S 29

#define NVIC_PRI0_INT2_S 21

#define NVIC_PRI0_INT1_S 13

#define NVIC_PRI0_INT0_S 5

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI1 register.

//

//*****************************************************************************

#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask

#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask

#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask

#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask

#define NVIC_PRI1_INT7_S 29

#define NVIC_PRI1_INT6_S 21

#define NVIC_PRI1_INT5_S 13

#define NVIC_PRI1_INT4_S 5

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI2 register.

//

//*****************************************************************************

#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask

#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask

#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask

#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask

#define NVIC_PRI2_INT11_S 29

#define NVIC_PRI2_INT10_S 21

#define NVIC_PRI2_INT9_S 13

#define NVIC_PRI2_INT8_S 5

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI3 register.

//

//*****************************************************************************

#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask

#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask

#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask

#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask

#define NVIC_PRI3_INT15_S 29

#define NVIC_PRI3_INT14_S 21

#define NVIC_PRI3_INT13_S 13

#define NVIC_PRI3_INT12_S 5

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI4 register.

//

//*****************************************************************************

#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask

#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask

#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask

#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask

#define NVIC_PRI4_INT19_S 29

#define NVIC_PRI4_INT18_S 21

#define NVIC_PRI4_INT17_S 13

#define NVIC_PRI4_INT16_S 5

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI5 register.

//

//*****************************************************************************

#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask

#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask

#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask

#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask

#define NVIC_PRI5_INT23_S 29

#define NVIC_PRI5_INT22_S 21

#define NVIC_PRI5_INT21_S 13

#define NVIC_PRI5_INT20_S 5

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI6 register.

//

//*****************************************************************************

#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask

#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask

#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask

#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask

#define NVIC_PRI6_INT27_S 29

#define NVIC_PRI6_INT26_S 21

#define NVIC_PRI6_INT25_S 13

#define NVIC_PRI6_INT24_S 5

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI7 register.

//

//*****************************************************************************

#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask

#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask

#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask

#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask

#define NVIC_PRI7_INT31_S 29

#define NVIC_PRI7_INT30_S 21

#define NVIC_PRI7_INT29_S 13

#define NVIC_PRI7_INT28_S 5

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI8 register.

//

//*****************************************************************************

#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask

#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask

#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask

#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask

#define NVIC_PRI8_INT35_S 29

#define NVIC_PRI8_INT34_S 21

#define NVIC_PRI8_INT33_S 13

#define NVIC_PRI8_INT32_S 5

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI9 register.

//

//*****************************************************************************

#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask

#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask

#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask

#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask

#define NVIC_PRI9_INT39_S 29

#define NVIC_PRI9_INT38_S 21

#define NVIC_PRI9_INT37_S 13

#define NVIC_PRI9_INT36_S 5

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI10 register.

//

//*****************************************************************************

#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask

#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask

#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask

#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask

#define NVIC_PRI10_INT43_S 29

#define NVIC_PRI10_INT42_S 21

#define NVIC_PRI10_INT41_S 13

#define NVIC_PRI10_INT40_S 5

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI11 register.

//

//*****************************************************************************

#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask

#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask

#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask

#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask

#define NVIC_PRI11_INT47_S 29

#define NVIC_PRI11_INT46_S 21

#define NVIC_PRI11_INT45_S 13

#define NVIC_PRI11_INT44_S 5

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI12 register.

//

//*****************************************************************************

#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask

#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask

#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask

#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask

#define NVIC_PRI12_INT51_S 29

#define NVIC_PRI12_INT50_S 21

#define NVIC_PRI12_INT49_S 13

#define NVIC_PRI12_INT48_S 5

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI13 register.

//

//*****************************************************************************

#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask

#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask

#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask

#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask

#define NVIC_PRI13_INT55_S 29

#define NVIC_PRI13_INT54_S 21

#define NVIC_PRI13_INT53_S 13

#define NVIC_PRI13_INT52_S 5

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI14 register.

//

//*****************************************************************************

#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask

#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask

#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask

#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask

#define NVIC_PRI14_INTD_S 29

#define NVIC_PRI14_INTC_S 21

#define NVIC_PRI14_INTB_S 13

#define NVIC_PRI14_INTA_S 5

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI15 register.

//

//*****************************************************************************

#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask

#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask

#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask

#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask

#define NVIC_PRI15_INTD_S 29

#define NVIC_PRI15_INTC_S 21

#define NVIC_PRI15_INTB_S 13

#define NVIC_PRI15_INTA_S 5

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI16 register.

//

//*****************************************************************************

#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask

#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask

#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask

#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask

#define NVIC_PRI16_INTD_S 29

#define NVIC_PRI16_INTC_S 21

#define NVIC_PRI16_INTB_S 13

#define NVIC_PRI16_INTA_S 5

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI17 register.

//

//*****************************************************************************

#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask

#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask

#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask

#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask

#define NVIC_PRI17_INTD_S 29

#define NVIC_PRI17_INTC_S 21

#define NVIC_PRI17_INTB_S 13

#define NVIC_PRI17_INTA_S 5

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI18 register.

//

//*****************************************************************************

#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask

#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask

#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask

#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask

#define NVIC_PRI18_INTD_S 29

#define NVIC_PRI18_INTC_S 21

#define NVIC_PRI18_INTB_S 13

#define NVIC_PRI18_INTA_S 5

//*****************************************************************************

//

// The following are defines for the bit fields in the NVIC_PRI19 register.

//

//*****************************************************************************

#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask

#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask

#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask

#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask