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// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/

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// Redistributions of source code must retain the above copyright

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#ifndef __HW_FLASH_CTRL_H__

#define __HW_FLASH_CTRL_H__

//*****************************************************************************

//

// The following are defines for the FLASH_CTRL register offsets.

//

//*****************************************************************************

#define FLASH_CTRL_O_FMA 0x00000000 // Flash Memory Address (FMA)

// offset 0x000 During a write

// operation this register contains

// a 4-byte-aligned address and

// specifies where the data is

// written. During erase operations

// this register contains a 1

// KB-aligned CPU byte address and

// specifies which block is erased.

// Note that the alignment

// requirements must be met by

// software or the results of the

// operation are unpredictable.

#define FLASH_CTRL_O_FMD 0x00000004 // Flash Memory Data (FMD) offset

// 0x004 This register contains the

// data to be written during the

// programming cycle or read during

// the read cycle. Note that the

// contents of this register are

// undefined for a read access of an

// execute-only block. This register

// is not used during erase cycles.

#define FLASH_CTRL_O_FMC 0x00000008 // Flash Memory Control (FMC)

// offset 0x008 When this register

// is written the Flash memory

// controller initiates the

// appropriate access cycle for the

// location specified by the Flash

// Memory Address (FMA) register .

// If the access is a write access

// the data contained in the Flash

// Memory Data (FMD) register is

// written to the specified address.

// This register must be the final

// register written and initiates

// the memory operation. The four

// control bits in the lower byte of

// this register are used to

// initiate memory operations.

#define FLASH_CTRL_O_FCRIS 0x0000000C // Flash Controller Raw Interrupt

// Status (FCRIS) offset 0x00C This

// register indicates that the Flash

// memory controller has an

// interrupt condition. An interrupt

// is sent to the interrupt

// controller only if the

// corresponding FCIM register bit

// is set.

#define FLASH_CTRL_O_FCIM 0x00000010 // Flash Controller Interrupt Mask

// (FCIM) offset 0x010 This register

// controls whether the Flash memory

// controller generates interrupts

// to the controller.

#define FLASH_CTRL_O_FCMISC 0x00000014 // Flash Controller Masked

// Interrupt Status and Clear

// (FCMISC) offset 0x014 This

// register provides two functions.

// First it reports the cause of an

// interrupt by indicating which

// interrupt source or sources are

// signalling the interrupt. Second

// it serves as the method to clear

// the interrupt reporting.

#define FLASH_CTRL_O_FMC2 0x00000020 // Flash Memory Control 2 (FMC2)

// offset 0x020 When this register

// is written the Flash memory

// controller initiates the

// appropriate access cycle for the

// location specified by the Flash

// Memory Address (FMA) register .

// If the access is a write access

// the data contained in the Flash

// Write Buffer (FWB) registers is

// written. This register must be

// the final register written as it

// initiates the memory operation.

#define FLASH_CTRL_O_FWBVAL 0x00000030 // Flash Write Buffer Valid

// (FWBVAL) offset 0x030 This

// register provides a bitwise

// status of which FWBn registers

// have been written by the

// processor since the last write of

// the Flash memory write buffer.

// The entries with a 1 are written

// on the next write of the Flash

// memory write buffer. This

// register is cleared after the

// write operation by hardware. A

// protection violation on the write

// operation also clears this

// status. Software can program the

// same 32 words to various Flash

// memory locations by setting the

// FWB[n] bits after they are

// cleared by the write operation.

// The next write operation then

// uses the same data as the

// previous one. In addition if a

// FWBn register change should not

// be written to Flash memory

// software can clear the

// corresponding FWB[n] bit to

// preserve the existing data when

// the next write operation occurs.

#define FLASH_CTRL_O_FWB1 0x00000100 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB2 0x00000104 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB3 0x00000108 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB4 0x0000010C // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB5 0x00000110 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB6 0x00000114 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB7 0x00000118 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB8 0x0000011C // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB9 0x00000120 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB10 0x00000124 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB11 0x00000128 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB12 0x0000012C // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB13 0x00000130 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB14 0x00000134 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB15 0x00000138 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB16 0x0000013C // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB17 0x00000140 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB18 0x00000144 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB19 0x00000148 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB20 0x0000014C // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB21 0x00000150 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB22 0x00000154 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB23 0x00000158 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB24 0x0000015C // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB25 0x00000160 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB26 0x00000164 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB27 0x00000168 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB28 0x0000016C // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB29 0x00000170 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB30 0x00000174 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB31 0x00000178 // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FWB32 0x0000017C // Flash Write Buffer n (FWBn)

// offset 0x100 - 0x17C These 32

// registers hold the contents of

// the data to be written into the

// Flash memory on a buffered Flash

// memory write operation. The

// offset selects one of the 32-bit

// registers. Only FWBn registers

// that have been updated since the

// preceding buffered Flash memory

// write operation are written into

// the Flash memory so it is not

// necessary to write the entire

// bank of registers in order to

// write 1 or 2 words. The FWBn

// registers are written into the

// Flash memory with the FWB0

// register corresponding to the

// address contained in FMA. FWB1 is

// written to the address FMA+0x4

// etc. Note that only data bits

// that are 0 result in the Flash

// memory being modified. A data bit

// that is 1 leaves the content of

// the Flash memory bit at its

// previous value.

#define FLASH_CTRL_O_FSIZE 0x00000FC0 // Flash Size (FSIZE) offset 0xFC0

// This register indicates the size

// of the on-chip Flash memory.

// Important: This register should

// be used to determine the size of

// the Flash memory that is

// implemented on this

// microcontroller. However to

// support legacy software the DC0

// register is available. A read of

// the DC0 register correctly

// identifies legacy memory sizes.

// Software must use the FSIZE

// register for memory sizes that

// are not listed in the DC0

// register description.

#define FLASH_CTRL_O_SSIZE 0x00000FC4 // SRAM Size (SSIZE) offset 0xFC4

// This register indicates the size

// of the on-chip SRAM. Important:

// This register should be used to

// determine the size of the SRAM