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torvaldstorvalds
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Merge branch 'x86-process-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pul x86/process updates from Ingo Molnar: "The main change in this cycle was to add the ARCH_[GET|SET]_CPUID prctl() ABI extension to control the availability of the CPUID instruction, analogously to the existing PR_GET|SET_TSC ABI that controls RDTSC. Motivation: the 'rr' user-space record-and-replay execution debugger would like to trap and emulate the CPUID instruction - which instruction is normally unprivileged. Trapping CPUID is possible on IvyBridge and later Intel CPUs - expose this hardware capability" * 'x86-process-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/syscalls/32: Ignore arch_prctl for other architectures um/arch_prctl: Fix fallout from x86 arch_prctl() rework x86/arch_prctl: Add ARCH_[GET|SET]_CPUID x86/cpufeature: Detect CPUID faulting support x86/syscalls/32: Wire up arch_prctl on x86-32 x86/arch_prctl: Add do_arch_prctl_common() x86/arch_prctl/64: Rename do_arch_prctl() to do_arch_prctl_64() x86/arch_prctl/64: Use SYSCALL_DEFINE2 to define sys_arch_prctl() x86/arch_prctl: Rename 'code' argument to 'option' x86/msr: Rename MISC_FEATURE_ENABLES to MISC_FEATURES_ENABLES x86/process: Optimize TIF_NOTSC switch x86/process: Correct and optimize TIF_BLOCKSTEP switch x86/process: Optimize TIF checks in __switch_to_xtra()
2 parents 207fb8c + f3e4559 commit 6dc2cce

23 files changed

Lines changed: 259 additions & 88 deletions

File tree

‎arch/um/include/shared/os.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -302,8 +302,8 @@ extern int ignore_sigio_fd(int fd);
302302
extern void maybe_sigio_broken(int fd, int read);
303303
extern void sigio_broken(int fd, int read);
304304

305-
/* sys-x86_64/prctl.c */
306-
extern int os_arch_prctl(int pid, int code, unsigned long *addr);
305+
/* prctl.c */
306+
extern int os_arch_prctl(int pid, int option, unsigned long *arg2);
307307

308308
/* tty.c */
309309
extern int get_pty(void);

‎arch/x86/entry/syscalls/syscall_32.tbl‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -390,3 +390,4 @@
390390
381 i386 pkey_alloc sys_pkey_alloc
391391
382 i386 pkey_free sys_pkey_free
392392
383 i386 statx sys_statx
393+
384 i386 arch_prctl sys_arch_prctl compat_sys_arch_prctl

‎arch/x86/include/asm/cpufeatures.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -187,6 +187,7 @@
187187
* Reuse free bits when adding new feature flags!
188188
*/
189189
#define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT */
190+
#define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */
190191
#define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */
191192
#define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
192193
#define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* Cache Allocation Technology L3 */

‎arch/x86/include/asm/msr-index.h‎

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,8 @@
4545
#define MSR_IA32_PERFCTR1 0x000000c2
4646
#define MSR_FSB_FREQ 0x000000cd
4747
#define MSR_PLATFORM_INFO 0x000000ce
48+
#define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31
49+
#define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
4850

4951
#define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
5052
#define NHM_C3_AUTO_DEMOTE (1UL << 25)
@@ -127,6 +129,7 @@
127129

128130
/* DEBUGCTLMSR bits (others vary by model): */
129131
#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
132+
#define DEBUGCTLMSR_BTF_SHIFT 1
130133
#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
131134
#define DEBUGCTLMSR_TR (1UL << 6)
132135
#define DEBUGCTLMSR_BTS (1UL << 7)
@@ -552,10 +555,12 @@
552555
#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
553556
#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
554557

555-
/* MISC_FEATURE_ENABLES non-architectural features */
556-
#define MSR_MISC_FEATURE_ENABLES 0x00000140
558+
/* MISC_FEATURES_ENABLES non-architectural features */
559+
#define MSR_MISC_FEATURES_ENABLES 0x00000140
557560

558-
#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT 1
561+
#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0
562+
#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT)
563+
#define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1
559564

560565
#define MSR_IA32_TSC_DEADLINE 0x000006E0
561566

‎arch/x86/include/asm/processor.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -884,6 +884,8 @@ extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
884884
extern int get_tsc_mode(unsigned long adr);
885885
extern int set_tsc_mode(unsigned int val);
886886

887+
DECLARE_PER_CPU(u64, msr_misc_features_shadow);
888+
887889
/* Register/unregister a process' MPX related resource */
888890
#define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
889891
#define MPX_DISABLE_MANAGEMENT() mpx_disable_management()

‎arch/x86/include/asm/proto.h‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@ void syscall_init(void);
99

1010
#ifdef CONFIG_X86_64
1111
void entry_SYSCALL_64(void);
12+
long do_arch_prctl_64(struct task_struct *task, int option, unsigned long arg2);
1213
#endif
1314

1415
#ifdef CONFIG_X86_32
@@ -30,6 +31,7 @@ void x86_report_nx(void);
3031

3132
extern int reboot_force;
3233

33-
long do_arch_prctl(struct task_struct *task, int code, unsigned long addr);
34+
long do_arch_prctl_common(struct task_struct *task, int option,
35+
unsigned long cpuid_enabled);
3436

3537
#endif /* _ASM_X86_PROTO_H */

‎arch/x86/include/asm/thread_info.h‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -87,6 +87,7 @@ struct thread_info {
8787
#define TIF_SECCOMP 8 /* secure computing */
8888
#define TIF_USER_RETURN_NOTIFY 11 /* notify kernel of userspace return */
8989
#define TIF_UPROBE 12 /* breakpointed or singlestepping */
90+
#define TIF_NOCPUID 15 /* CPUID is not accessible in userland */
9091
#define TIF_NOTSC 16 /* TSC is not accessible in userland */
9192
#define TIF_IA32 17 /* IA32 compatibility process */
9293
#define TIF_NOHZ 19 /* in adaptive nohz mode */
@@ -110,6 +111,7 @@ struct thread_info {
110111
#define _TIF_SECCOMP (1 << TIF_SECCOMP)
111112
#define _TIF_USER_RETURN_NOTIFY (1 << TIF_USER_RETURN_NOTIFY)
112113
#define _TIF_UPROBE (1 << TIF_UPROBE)
114+
#define _TIF_NOCPUID (1 << TIF_NOCPUID)
113115
#define _TIF_NOTSC (1 << TIF_NOTSC)
114116
#define _TIF_IA32 (1 << TIF_IA32)
115117
#define _TIF_NOHZ (1 << TIF_NOHZ)
@@ -138,7 +140,7 @@ struct thread_info {
138140

139141
/* flags to check in __switch_to() */
140142
#define _TIF_WORK_CTXSW \
141-
(_TIF_IO_BITMAP|_TIF_NOTSC|_TIF_BLOCKSTEP)
143+
(_TIF_IO_BITMAP|_TIF_NOCPUID|_TIF_NOTSC|_TIF_BLOCKSTEP)
142144

143145
#define _TIF_WORK_CTXSW_PREV (_TIF_WORK_CTXSW|_TIF_USER_RETURN_NOTIFY)
144146
#define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW)
@@ -239,6 +241,8 @@ static inline int arch_within_stack_frames(const void * const stack,
239241
extern void arch_task_cache_init(void);
240242
extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
241243
extern void arch_release_task_struct(struct task_struct *tsk);
244+
extern void arch_setup_new_exec(void);
245+
#define arch_setup_new_exec arch_setup_new_exec
242246
#endif /* !__ASSEMBLY__ */
243247

244248
#endif /* _ASM_X86_THREAD_INFO_H */

‎arch/x86/include/asm/tlbflush.h‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -110,6 +110,16 @@ static inline void cr4_clear_bits(unsigned long mask)
110110
}
111111
}
112112

113+
static inline void cr4_toggle_bits(unsigned long mask)
114+
{
115+
unsigned long cr4;
116+
117+
cr4 = this_cpu_read(cpu_tlbstate.cr4);
118+
cr4 ^= mask;
119+
this_cpu_write(cpu_tlbstate.cr4, cr4);
120+
__write_cr4(cr4);
121+
}
122+
113123
/* Read the CR4 shadow. */
114124
static inline unsigned long cr4_read_shadow(void)
115125
{

‎arch/x86/include/uapi/asm/prctl.h‎

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,13 @@
11
#ifndef _ASM_X86_PRCTL_H
22
#define _ASM_X86_PRCTL_H
33

4-
#define ARCH_SET_GS 0x1001
5-
#define ARCH_SET_FS 0x1002
6-
#define ARCH_GET_FS 0x1003
7-
#define ARCH_GET_GS 0x1004
4+
#define ARCH_SET_GS 0x1001
5+
#define ARCH_SET_FS 0x1002
6+
#define ARCH_GET_FS 0x1003
7+
#define ARCH_GET_GS 0x1004
8+
9+
#define ARCH_GET_CPUID 0x1011
10+
#define ARCH_SET_CPUID 0x1012
811

912
#define ARCH_MAP_VDSO_X32 0x2001
1013
#define ARCH_MAP_VDSO_32 0x2002

‎arch/x86/kernel/cpu/intel.c‎

Lines changed: 32 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -90,16 +90,12 @@ static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
9090
return;
9191
}
9292

93-
if (ring3mwait_disabled) {
94-
msr_clear_bit(MSR_MISC_FEATURE_ENABLES,
95-
MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT);
93+
if (ring3mwait_disabled)
9694
return;
97-
}
98-
99-
msr_set_bit(MSR_MISC_FEATURE_ENABLES,
100-
MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT);
10195

10296
set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
97+
this_cpu_or(msr_misc_features_shadow,
98+
1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT);
10399

104100
if (c == &boot_cpu_data)
105101
ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
@@ -488,6 +484,34 @@ static void intel_bsp_resume(struct cpuinfo_x86 *c)
488484
init_intel_energy_perf(c);
489485
}
490486

487+
static void init_cpuid_fault(struct cpuinfo_x86 *c)
488+
{
489+
u64 msr;
490+
491+
if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
492+
if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
493+
set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
494+
}
495+
}
496+
497+
static void init_intel_misc_features(struct cpuinfo_x86 *c)
498+
{
499+
u64 msr;
500+
501+
if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))
502+
return;
503+
504+
/* Clear all MISC features */
505+
this_cpu_write(msr_misc_features_shadow, 0);
506+
507+
/* Check features and update capabilities and shadow control bits */
508+
init_cpuid_fault(c);
509+
probe_xeon_phi_r3mwait(c);
510+
511+
msr = this_cpu_read(msr_misc_features_shadow);
512+
wrmsrl(MSR_MISC_FEATURES_ENABLES, msr);
513+
}
514+
491515
static void init_intel(struct cpuinfo_x86 *c)
492516
{
493517
unsigned int l2 = 0;
@@ -602,7 +626,7 @@ static void init_intel(struct cpuinfo_x86 *c)
602626

603627
init_intel_energy_perf(c);
604628

605-
probe_xeon_phi_r3mwait(c);
629+
init_intel_misc_features(c);
606630
}
607631

608632
#ifdef CONFIG_X86_32

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