diff --git a/contrib.html b/contrib.html
index 969cd379..6e69d183 100644
--- a/contrib.html
+++ b/contrib.html
@@ -42,7 +42,7 @@
     <div id="header">
       <h1 id="logo">Intel® Implicit SPMD Program Compiler</h1>
       <div id="slogan">An open-source compiler for high-performance SIMD programming on
-      the CPU</div>
+      the CPU and GPU</div>
     </div>
     <div id="nav">
       <div id="nbar">
@@ -83,15 +83,20 @@ <h1>Contributors</h1>
         <p>
           Thanks also to the additional contributors:
 Alex Reece,
+Aleksandr Bezzubikov,
+Aleksandr Pronin,
 Andreas Wendleder,
 Andrey Guskov,
 Anton Mitrokhin,
 Anton Schreiner,
 Ben Harper,
 Daniel Schubert,
+Dmitry Ryabtsev,
 Evghenii Gaburov,
 Gabe Weisz,
 Ilia Filippov,
+Jan Zielinski,
+Jefferson Amstutz,
 John Poole,
 Lu Guanqun,
 Mark Lacey,
diff --git a/documentation.html b/documentation.html
index 4e464f31..b42fd30e 100644
--- a/documentation.html
+++ b/documentation.html
@@ -42,7 +42,7 @@
     <div id="header">
       <h1 id="logo">Intel® Implicit SPMD Program Compiler</h1>
       <div id="slogan">An open-source compiler for high-performance SIMD programming on
-      the CPU</div>
+      the CPU and GPU</div>
     </div>
     <div id="nav">
       <div id="nbar">
@@ -97,7 +97,7 @@ <h1>Documentation</h1>
         serial C++ implementations, which makes it easy to compare the
         differences between <tt>ispc</tt> and C++ implementations of
         various algorithms.  (You can also browse this
-        code <a href="https://github.com/ispc/ispc/tree/master/examples">directly
+        code <a href="https://github.com/ispc/ispc/tree/main/examples">directly
         on github</a>.)</p>
 
         <p>A technical paper
diff --git a/downloads.html b/downloads.html
index c9db4535..e216fb38 100644
--- a/downloads.html
+++ b/downloads.html
@@ -42,7 +42,7 @@
     <div id="header">
       <h1 id="logo">Intel® Implicit SPMD Program Compiler</h1>
       <div id="slogan">An open-source compiler for high-performance SIMD programming on
-      the CPU</div>
+      the CPU and GPU</div>
     </div>
     <div id="nav">
       <div id="nbar">
@@ -77,27 +77,27 @@ <h1>Downloading The Intel® Implicit SPMD Program Compiler</h1>
           The Intel® Implicit SPMD Program Compiler (Intel® ISPC) is available in both
           source and binary form.
         </p>
-        <p>
-          Here are latest released ISPC binaries based on LLVM 10.0.1:
-        </p>
-          <ul>
-            <li><a href="https://github.com/ispc/ispc/releases/download/v1.14.0/ispc-v1.14.0-windows.zip">Windows (64 bit)
-            ispc binary and examples (v1.14.0)</a></li>
-            <li><a href="https://github.com/ispc/ispc/releases/download/v1.14.0/ispc-v1.14.0-macOS.tar.gz">macOS (64 bit, 10.10 Yosemite)
-            ispc binary and examples (v1.14.0)</a></li>
-            <li><a href="https://github.com/ispc/ispc/releases/download/v1.14.0/ispc-v1.14.0-linux.tar.gz">Linux (64 bit)
-            ispc binary and examples (v1.14.0)</a></li>
-            <li><a href="https://github.com/ispc/ispc/releases/download/v1.14.0/ispc-v1.14.0-gen-alpha-linux.tax.gz">Linux (64 bit)
-            GPU-enabled ispc binary and examples ("alpha" release based on v1.14.0)</a></li>
-          </ul>
-          <p>
-            Here are latest ISPC binaries corresponding to master branch (based on LLVM 10.0.1):
-          </p>
-          <ul>
-            <li><a href="https://ci.appveyor.com/api/projects/ispc/ispc/artifacts/build%2Fispc-trunk-windows.zip?job=Environment%3A%20APPVEYOR_BUILD_WORKER_IMAGE%3DVisual%20Studio%202019%2C%20LLVM_VERSION%3Dlatest">Windows (64 bit)
-            ispc binary and examples (v1.14.0dev)</a></li>
-			<li><a href="https://ci.appveyor.com/api/projects/ispc/ispc/artifacts/build%2Fispc-trunk-linux.tar.gz?job=Environment%3A%20APPVEYOR_BUILD_WORKER_IMAGE%3DUbuntu1604%2C%20LLVM_VERSION%3Dlatest">Linux (64 bit)
-            ispc binary and examples (v1.14.0dev)</a></li>
+        <p>
+          Here are latest released ISPC binaries based on LLVM 11.0.0:
+        </p>
+          <ul>
+            <li><a href="https://github.com/ispc/ispc/releases/download/v1.15.0/ispc-v1.15.0-windows.msi">Windows (64 bit)
+            ispc binary and examples (v1.15.0)</a></li>
+            <li><a href="https://github.com/ispc/ispc/releases/download/v1.15.0/ispc-v1.15.0-macOS.tar.gz">macOS (64 bit, 10.10 Yosemite)
+            ispc binary and examples (v1.15.0)</a></li>
+            <li><a href="https://github.com/ispc/ispc/releases/download/v1.15.0/ispc-v1.15.0-linux.tar.gz">Linux (64 bit)
+            ispc binary and examples (v1.15.0)</a></li>
+            <li><a href="https://github.com/ispc/ispc/releases/download/v1.15.0/ispc-v1.15.0-gen-beta-linux.tar.gz">Linux (64 bit)
+            GPU-enabled ispc binary and examples ("beta" release based on v1.15.0)</a></li>
+          </ul>
+          <p>
+            Here are latest ISPC binaries corresponding to main branch (based on LLVM 10.0.1):
+          </p>
+          <ul>
+            <li><a href="https://ci.appveyor.com/api/projects/ispc/ispc/artifacts/build%2Fispc-trunk-windows.zip?job=Environment%3A%20APPVEYOR_BUILD_WORKER_IMAGE%3DVisual%20Studio%202019%2C%20LLVM_VERSION%3Dlatest">Windows (64 bit)
+            ispc binary and examples (v1.16.0dev)</a></li>
+			<li><a href="https://ci.appveyor.com/api/projects/ispc/ispc/artifacts/build%2Fispc-trunk-linux.tar.gz?job=Environment%3A%20APPVEYOR_BUILD_WORKER_IMAGE%3DUbuntu1604%2C%20LLVM_VERSION%3Dlatest">Linux (64 bit)
+            ispc binary and examples (v1.16.0dev)</a></li>
             </ul>
           <p>
             Here is LLVM 3.5 based binary with experimental NVPTX support:
@@ -130,14 +130,14 @@ <h1>Downloading The Intel® Implicit SPMD Program Compiler</h1>
             Finally, zip and tar files of the source can be downloaded:
           </p>
           <ul>
-            <li> <a href="https://github.com/ispc/ispc/zipball/master">zip
+            <li> <a href="https://github.com/ispc/ispc/zipball/main">zip
                 file of the top-of-tree source.</a></li>
-            <li> <a href="https://github.com/ispc/ispc/tarball/master">tar.gz file
+            <li> <a href="https://github.com/ispc/ispc/tarball/main">tar.gz file
                 of the top-of-tree source.</a></li>
-            <li> <a href="https://github.com/ispc/ispc/zipball/v1.14.0">zip
-            file of the v1.14.0 source</a>, corresponding to the binaries above.</li>
-            <li> <a href="https://github.com/ispc/ispc/tarball/v1.14.0">tar.gz
-            file of the v1.14.0 source</a>, corresponding to the binaries above.</li>
+            <li> <a href="https://github.com/ispc/ispc/zipball/v1.15.0">zip
+            file of the v1.15.0 source</a>, corresponding to the binaries above.</li>
+            <li> <a href="https://github.com/ispc/ispc/tarball/v1.15.0">tar.gz
+            file of the v1.15.0 source</a>, corresponding to the binaries above.</li>
             </ul>
           <p> There is a page in the <tt>ispc</tt> wiki with instructions
           about <a href="https://github.com/ispc/ispc/wiki/Building-ispc">building
diff --git a/example.html b/example.html
index 4872ee8a..8f39d038 100644
--- a/example.html
+++ b/example.html
@@ -42,7 +42,7 @@
     <div id="header">
       <h1 id="logo">Intel® Implicit SPMD Program Compiler</h1>
       <div id="slogan">An open-source compiler for high-performance SIMD programming on
-      the CPU</div>
+      the CPU and GPU</div>
     </div>
     <div id="nav">
       <div id="nbar">
@@ -153,7 +153,7 @@ <h1>A Simple ispc Example</h1>
 Next, the function loops over the pixels of the image with a doubly-nested
 loop.  The outer loop is a regular loop over scanlines, while the inner
 loop introduces a new looping construct provided
-by <tt>ispc</tt>, <tt>foreach</tt>.  In general, <tt>foreach</tt> specfies
+by <tt>ispc</tt>, <tt>foreach</tt>.  In general, <tt>foreach</tt> specifies
 parallel iteration over an n-dimensional range of integer values.  In this
 case, it specifies parallel iteration over a 1-D range of pixels in a
 scanline.  Each time through the loop, the iteration variable <tt>i</tt>
@@ -232,7 +232,7 @@ <h1>A Simple ispc Example</h1>
 
 <p>To compile this example, install the <tt>ispc</tt> compiler in a
   directory that is in your <tt>PATH</tt>, and run <tt>make</tt> on Mac OS
-  X or Linux, or build the with the <tt>mandelbrot.vcxproj</tt> build file
+  X or Linux, or build using the <tt>mandelbrot.vcxproj</tt> build file
   with MSVC 2010.  Note that the <tt>ispc</tt> compiler generates regular
   object files that you can just link with object files compiled with C/C++
   compilers.  (Here is the <a href="mandelbrot.txt">assembly language
diff --git a/faq.html b/faq.html
index 096ba00b..5dfd1443 100644
--- a/faq.html
+++ b/faq.html
@@ -3,7 +3,7 @@
 <html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
 <head>
 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
-<meta name="generator" content="Docutils 0.15.2: http://docutils.sourceforge.net/" />
+<meta name="generator" content="Docutils 0.14: http://docutils.sourceforge.net/" />
 <title>Frequently Asked Questions About Intel® ISPC</title>
 <script type="text/javascript">
 
@@ -27,7 +27,7 @@
     <div id="header">
       <h1 id="logo">Intel® Implicit SPMD Program Compiler</h1>
       <div id="slogan">An open-source compiler for high-performance SIMD programming on
-      the CPU</div>
+      the CPU and GPU</div>
     </div>
     <div id="nav">
       <div id="nbar">
diff --git a/favicon.ico b/favicon.ico
index 0aa2ff8e..100180c1 100644
Binary files a/favicon.ico and b/favicon.ico differ
diff --git a/favicon.png b/favicon.png
index f03d5b5e..5a6b7816 100644
Binary files a/favicon.png and b/favicon.png differ
diff --git a/features.html b/features.html
index 0ba6346e..44370853 100644
--- a/features.html
+++ b/features.html
@@ -42,7 +42,7 @@
     <div id="header">
       <h1 id="logo">Intel® Implicit SPMD Program Compiler</h1>
       <div id="slogan">An open-source compiler for high-performance SIMD programming on
-      the CPU</div>
+      the CPU and GPU</div>
     </div>
     <div id="nav">
       <div id="nbar">
diff --git a/index.html b/index.html
index 30633e96..233fc5f7 100644
--- a/index.html
+++ b/index.html
@@ -42,7 +42,7 @@
     <div id="header">
       <h1 id="logo">Intel® Implicit SPMD Program Compiler</h1>
       <div id="slogan">An open-source compiler for high-performance SIMD programming on
-      the CPU</div>
+      the CPU and GPU</div>
     </div>
     <div id="nav">
       <div id="nbar">
@@ -84,21 +84,20 @@ <h1>Overview</h1>
           more details and examples that illustrate this concept.)</p>
 
         <p><tt>ispc</tt> compiles a C-based SPMD programming language to
-          run on the SIMD units of CPUs and the Intel Xeon
-          Phi&trade; architecture; it frequently provides a 3x or more
-          speedup on CPUs with 4-wide vector SSE units and 5x-6x on CPUs
-          with 8-wide AVX vector units, without any of the difficulty of
-          writing intrinsics code.  Parallelization across multiple cores
-          is also supported by <tt>ispc</tt>, making it possible to write
-          programs that achieve performance improvement that scales by both
-          number of cores and vector unit size.
+          run on the SIMD units of CPUs and GPUs; it frequently provides 
+          a 3x or more speedup on architectures with 4-wide vector SSE units
+          and 5x-6x on archituctures with 8-wide AVX vector units, without 
+          any of the difficulty of writing intrinsics code.  Parallelization
+          across multiple cores is also supported by <tt>ispc</tt>, making it
+          possible to write programs that achieve performance improvement 
+          that scales by both number of cores and vector unit size.
         </p>
 
         <p>There are a few key principles in the design of <tt>ispc</tt>:
         <ul>
           <li>To build a small set of extensions to the C language that
             would deliver excellent performance to performance-oriented
-            programmers who want to run SPMD programs on the CPU.</li>
+            programmers who want to run SPMD programs on the CPU and GPU.</li>
           <li>To provide a thin abstraction layer between the programmer
             and the hardware&mdash;in particular, to have an execution and
             data model where the programmer can cleanly reason about the
@@ -114,14 +113,16 @@ <h1>Overview</h1>
             copying or reformatting.</li>
           </ul>
         <p><tt>ispc</tt> is an open source compiler with a
-          <a href="https://github.com/ispc/ispc/blob/master/LICENSE.txt">BSD
+          <a href="https://github.com/ispc/ispc/blob/main/LICENSE.txt">BSD
           license</a>.  It uses the remarkable
           <a href="http://llvm.org">LLVM Compiler Infrastructure</a> for
           back-end code generation and optimization and
           is <a href="http://github.com/ispc/ispc/">hosted on
-          github</a>. It supports Windows, Mac, and Linux, with both x86
+          github</a>. On CPU it supports Windows, Mac, and Linux, with both x86
           and x86-64 targets.  It currently supports the SSE2, SSE4, AVX1, 
-          AVX2, AVX512, and Xeon Phi "Knight's Corner" instruction sets.
+          AVX2, AVX512, and Xeon Phi "Knight's Corner" instruction sets. On GPU
+          <tt>ispc</tt> supports Intel(R) Processor Graphics Gen9 and later
+          on Linux platform.
         </p>
         <p><tt>ispc</tt> support is provided provided through github issues and the
 	  <a href="https://groups.google.com/forum/#!forum/ispc-users">Intel Implicit SPMD Compiler Users Forum</a>.
diff --git a/ispc.html b/ispc.html
index 8cc75499..84b207ce 100644
--- a/ispc.html
+++ b/ispc.html
@@ -3,7 +3,7 @@
 <html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
 <head>
 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
-<meta name="generator" content="Docutils 0.15.2: http://docutils.sourceforge.net/" />
+<meta name="generator" content="Docutils 0.14: http://docutils.sourceforge.net/" />
 <title>Intel® ISPC User's Guide</title>
 <script type="text/javascript">
 
@@ -27,7 +27,7 @@
     <div id="header">
       <h1 id="logo">Intel® Implicit SPMD Program Compiler</h1>
       <div id="slogan">An open-source compiler for high-performance SIMD programming on
-      the CPU</div>
+      the CPU and GPU</div>
     </div>
     <div id="nav">
       <div id="nbar">
@@ -60,7 +60,7 @@ <h1 class="title">Intel® ISPC User's Guide</h1>
 
 <div id="content">
 <p>The Intel® Implicit SPMD Program Compiler (Intel® ISPC) is a compiler for
-writing SPMD (single program multiple data) programs to run on the CPU.
+writing SPMD (single program multiple data) programs to run on the CPU and GPU.
 The SPMD
 programming approach is widely known to graphics and GPGPU programmers; it
 is used for GPU shaders and CUDA* and OpenCL* kernels, for example.  The
@@ -73,7 +73,7 @@ <h1 class="title">Intel® ISPC User's Guide</h1>
 <ul class="simple">
 <li>Build a variant of the C programming language that delivers good
 performance to performance-oriented programmers who want to run SPMD
-programs on CPUs.</li>
+programs on CPUs and GPUs.</li>
 <li>Provide a thin abstraction layer between the programmer and the
 hardware--in particular, to follow the lesson from C for serial programs
 of having an execution and data model where the programmer can cleanly
@@ -111,6 +111,8 @@ <h1 class="title">Intel® ISPC User's Guide</h1>
 <li><a class="reference internal" href="#updating-ispc-programs-for-changes-in-ispc-1-12-0">Updating ISPC Programs For Changes In ISPC 1.12.0</a></li>
 <li><a class="reference internal" href="#updating-ispc-programs-for-changes-in-ispc-1-13-0">Updating ISPC Programs For Changes In ISPC 1.13.0</a></li>
 <li><a class="reference internal" href="#updating-ispc-programs-for-changes-in-ispc-1-14-0">Updating ISPC Programs For Changes In ISPC 1.14.0</a></li>
+<li><a class="reference internal" href="#updating-ispc-programs-for-changes-in-ispc-1-14-1">Updating ISPC Programs For Changes In ISPC 1.14.1</a></li>
+<li><a class="reference internal" href="#updating-ispc-programs-for-changes-in-ispc-1-15-0">Updating ISPC Programs For Changes In ISPC 1.15.0</a></li>
 </ul>
 </li>
 <li><a class="reference internal" href="#getting-started-with-ispc">Getting Started with ISPC</a><ul>
@@ -243,11 +245,10 @@ <h1 class="title">Intel® ISPC User's Guide</h1>
 </ul>
 </li>
 <li><a class="reference internal" href="#notices-disclaimers">Notices &amp; Disclaimers</a></li>
-<li><a class="reference internal" href="#optimization-notice">Optimization Notice</a></li>
 </ul>
 <div class="section" id="recent-changes-to-ispc">
 <h1>Recent Changes to ISPC</h1>
-<p>See the file <a class="reference external" href="https://raw.github.com/ispc/ispc/master/docs/ReleaseNotes.txt">ReleaseNotes.txt</a> in the <tt class="docutils literal">ispc</tt> distribution for a list
+<p>See the file <a class="reference external" href="https://raw.github.com/ispc/ispc/main/docs/ReleaseNotes.txt">ReleaseNotes.txt</a> in the <tt class="docutils literal">ispc</tt> distribution for a list
 of recent changes to the compiler.</p>
 <div class="section" id="updating-ispc-programs-for-changes-in-ispc-1-1">
 <h2>Updating ISPC Programs For Changes In ISPC 1.1</h2>
@@ -452,6 +453,17 @@ <h2>Updating ISPC Programs For Changes In ISPC 1.14.0</h2>
 <p>Windows x86_64 target now supports <tt class="docutils literal">__vectorcall</tt> calling convention.
 It's off by default, can be enabled by <tt class="docutils literal"><span class="pre">--vectorcall</span></tt> command line switch.</p>
 </div>
+<div class="section" id="updating-ispc-programs-for-changes-in-ispc-1-14-1">
+<h2>Updating ISPC Programs For Changes In ISPC 1.14.1</h2>
+<p>The release doesn't contain language changes, which may affect compatibility with
+older versions.</p>
+</div>
+<div class="section" id="updating-ispc-programs-for-changes-in-ispc-1-15-0">
+<h2>Updating ISPC Programs For Changes In ISPC 1.15.0</h2>
+<p>The release has several new language features, which do not affect compatibility.
+Namely, packed_[load|store]_active() stdlib functions for 64 bit types, and loop
+unroll pragmas: &quot;#pragma unroll&quot; and &quot;#pragma nounroll&quot;.</p>
+</div>
 </div>
 <div class="section" id="getting-started-with-ispc">
 <h1>Getting Started with ISPC</h1>
@@ -493,9 +505,9 @@ <h2>Compiling and Running a Simple ISPC Program</h2>
 variables are non-vector quantities--this concept is discussed in detail in the
 <a class="reference internal" href="#uniform-and-varying-qualifiers">&quot;uniform&quot; and &quot;varying&quot; Qualifiers</a> section.</p>
 <p>Each iteration of the <tt class="docutils literal">foreach</tt> loop works on a number of input values in
-parallel--depending on the compilation target chosen, it may be 4, 8, or
-even 16 elements of the <tt class="docutils literal">vin</tt> array, processed efficiently with the CPU's
-SIMD hardware.  Here, the variable <tt class="docutils literal">index</tt> takes all values from 0 to
+parallel--depending on the compilation target chosen, it may be 4, 8, 16, 32, or
+even 64 elements of the <tt class="docutils literal">vin</tt> array, processed efficiently with the CPU's or
+GPU's SIMD hardware.  Here, the variable <tt class="docutils literal">index</tt> takes all values from 0 to
 <tt class="docutils literal"><span class="pre">count-1</span></tt>.  After the load from the array to the variable <tt class="docutils literal">v</tt>, the
 program can then proceed, doing computation and control flow based on the
 values loaded.  The result from the running program instances is written to
@@ -608,7 +620,7 @@ <h2>Basic Command-line Options</h2>
 <div class="section" id="selecting-the-compilation-target">
 <h2>Selecting The Compilation Target</h2>
 <p>There are four options that affect the compilation target: <tt class="docutils literal"><span class="pre">--arch</span></tt>,
-which sets the target architecture, <tt class="docutils literal"><span class="pre">--cpu</span></tt>, which sets the target CPU,
+which sets the target architecture, <tt class="docutils literal"><span class="pre">--cpu</span></tt>, which sets the target CPU or GPU,
 <tt class="docutils literal"><span class="pre">--target</span></tt>, which sets the target instruction set, and <tt class="docutils literal"><span class="pre">--target-os</span></tt>,
 which sets the target operating system.</p>
 <p>If none of these options is specified, <tt class="docutils literal">ispc</tt> generates code for the host
@@ -619,7 +631,12 @@ <h2>Selecting The Compilation Target</h2>
 <pre class="literal-block">
 ispc foo.ispc -o foo.obj --arch=x86
 </pre>
-<p>Currently-supported architectures are <tt class="docutils literal"><span class="pre">x86-64</span></tt>, <tt class="docutils literal">x86</tt>, and <tt class="docutils literal">arm</tt>.</p>
+<p>To compile for Intel TGLLP platform:</p>
+<pre class="literal-block">
+ispc foo.ispc -o foo.bin --target=genx-x16 --cpu=TGLLP --emit-zebin
+</pre>
+<p>Currently-supported architectures are <tt class="docutils literal">x86</tt>, <tt class="docutils literal"><span class="pre">x86-64</span></tt>, <tt class="docutils literal">genx32</tt>,
+<tt class="docutils literal">genx64</tt>, and <tt class="docutils literal">arm</tt>.</p>
 <p>The target CPU determines both the default instruction set used as well as
 which CPU architecture the code is tuned for.  <tt class="docutils literal">ispc <span class="pre">--help</span></tt> provides a
 list of all of the supported CPUs.  By default, the CPU type of the system
@@ -662,6 +679,12 @@ <h2>Selecting The Compilation Target</h2>
 <tr><td>sse4</td>
 <td>SSE4 (generally 2008-2010 Intel CPUs)</td>
 </tr>
+<tr><td>genx-x8</td>
+<td>Intel GPU 8-wide SIMD</td>
+</tr>
+<tr><td>genx-x16</td>
+<td>Intel GPU 16-wide SIMD</td>
+</tr>
 </tbody>
 </table>
 <p>Consult your CPU's manual for specifics on which vector instruction set it
@@ -822,9 +845,17 @@ <h2>The Preprocessor</h2>
 </td>
 <td>Detecting if uint8/uint16/uint32/uint64 types are defined in the ISPC version.</td>
 </tr>
+<tr><td>ISPC_FP64_SUPPORTED</td>
+<td><ol class="first last arabic simple">
+<li></li>
+</ol>
+</td>
+<td>Detecting if double type is supported by the target.</td>
+</tr>
 </tbody>
 </table>
-<p><tt class="docutils literal">ispc</tt> also provides <tt class="docutils literal">#pragma ignore warning</tt> directives to ignore compiler warnings for individual lines.</p>
+<p><tt class="docutils literal">ispc</tt> supports the following <tt class="docutils literal">#pragma</tt> directives.</p>
+<p><tt class="docutils literal">#pragma ignore warning</tt> directives direct the compiler to ignore compiler warnings for individual lines.</p>
 <table border="1" class="docutils">
 <caption><tt class="docutils literal">#pragma ignore warning</tt> directives and their functions:</caption>
 <colgroup>
@@ -847,6 +878,30 @@ <h2>The Preprocessor</h2>
 </tbody>
 </table>
 <p>When using <tt class="docutils literal">#pragma ignore warning</tt> before a call to a macro, it suppresses warnings from the expanded macro code.</p>
+<p><tt class="docutils literal">#pragma unroll</tt> and <tt class="docutils literal">#pragma nounroll</tt> directives provide loop unrolling optimization hints to the compiler.
+This pragma is placed immediately before a loop statement. Currently, this functionality is limited to uniform <tt class="docutils literal">for</tt> and <tt class="docutils literal"><span class="pre">do-while</span></tt>.</p>
+<table border="1" class="docutils">
+<caption><tt class="docutils literal">#pragma unroll</tt> and <tt class="docutils literal">#pragma nounroll</tt> directives and their functions:</caption>
+<colgroup>
+<col width="50%" />
+<col width="50%" />
+</colgroup>
+<tbody valign="top">
+<tr><td><tt class="docutils literal">#pragma</tt> name</td>
+<td>Use</td>
+</tr>
+<tr><td><tt class="docutils literal">#pragma unroll COUNT</tt></td>
+<td>Directs the loop unroller to unroll the loop <tt class="docutils literal">COUNT</tt> times.
+The parameter may optionally be enclosed in parentheses:  <tt class="docutils literal">#pragma unroll (COUNT)</tt>.</td>
+</tr>
+<tr><td><tt class="docutils literal">#pragma unroll</tt></td>
+<td>Directs the loop unroller to fully unroll the loop if possible.</td>
+</tr>
+<tr><td><tt class="docutils literal">#pragma nounroll</tt></td>
+<td>Directs the loop unroller to not unroll the loop.</td>
+</tr>
+</tbody>
+</table>
 </div>
 <div class="section" id="debugging">
 <h2>Debugging</h2>
@@ -943,9 +998,10 @@ <h2>Basic Concepts: Program Instances and Gangs of Program Instances</h2>
 and high performance.</p>
 <p>The number of program instances in a gang is relatively small; in practice,
 it's no more than 2-4x the native SIMD width of the hardware it is
-executing on.  (Thus, four or eight program instances in a gang on a CPU
-using the the 4-wide SSE instruction set, and eight or sixteen on a CPU
-using 8-wide AVX.)</p>
+executing on.  Thus, four or eight program instances in a gang on a CPU
+using the 4-wide SSE instruction set, eight or sixteen on a CPU
+using 8-wide AVX/AVX2, eight, sixteen, thirty two, or sixty four on AVX512 CPU,
+and eight or sixteen on a Intel GPU.</p>
 </div>
 <div class="section" id="control-flow-within-a-gang">
 <h2>Control Flow Within A Gang</h2>
@@ -1327,7 +1383,7 @@ <h2>Tasking Model</h2>
 <h1>The ISPC Language</h1>
 <p><tt class="docutils literal">ispc</tt> is an extended version of the C programming language, providing a
 number of new features that make it easy to write high-performance SPMD
-programs for the CPU.  Note that between not only the few small syntactic
+programs for the CPU and GPU.  Note that between not only the few small syntactic
 differences between <tt class="docutils literal">ispc</tt> and C code but more importantly <tt class="docutils literal">ispc</tt>'s
 fundamentally parallel execution model, C code can't just be recompiled to
 correctly run in parallel with <tt class="docutils literal">ispc</tt>.  However, starting with working C
@@ -4494,36 +4550,8 @@ <h2>Restructuring Existing Programs to Use ISPC</h2>
 </div>
 <div class="section" id="notices-disclaimers">
 <h1>Notices &amp; Disclaimers</h1>
-<p>Software and workloads used in performance tests may have been optimized for
-performance only on Intel microprocessors.</p>
-<p>Performance tests, such as SYSmark and MobileMark, are measured using specific
-computer systems, components, software, operations and functions.  Any change
-to any of those factors may cause the results to vary.  You should consult
-other information and performance tests to assist you in fully evaluating your
-contemplated purchases, including the performance of that product when combined
-with other products.   For more complete information visit
-www.intel.com/benchmarks.</p>
-<p>Performance results are based on testing as of dates shown in configurations and
-may not reflect all publicly available updates.  See backup for configuration
-details.  No product or component can be absolutely secure.</p>
-<p>Your costs and results may vary.</p>
-<p>Intel technologies may require enabled hardware, software or service activation.</p>
-<p>© Intel Corporation.  Intel, the Intel logo, and other Intel marks are
-trademarks of Intel Corporation or its subsidiaries.  Other names and brands may
-be claimed as the property of others.</p>
-</div>
-<div class="section" id="optimization-notice">
-<h1>Optimization Notice</h1>
-<p>Intel's compilers may or may not optimize to the same degree for non-Intel
-microprocessors for optimizations that are not unique to Intel microprocessors.
-These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other
-optimizations. Intel does not guarantee the availability, functionality, or
-effectiveness of any optimization on microprocessors not manufactured by Intel.
-Microprocessor-dependent optimizations in this product are intended for use with
-Intel microprocessors. Certain optimizations not specific to Intel
-microarchitecture are reserved for Intel microprocessors. Please refer to the
-applicable product User and Reference Guides for more information regarding the
-specific instruction sets covered by this notice.</p>
+<p>Performance varies by use, configuration and other factors. Learn more at
+www.intel.com/PerformanceIndex.</p>
 </div>
 </div>
     <div class="clearfix"></div>
diff --git a/ispc_for_gen.html b/ispc_for_gen.html
index 91e655db..d4c2f79f 100644
--- a/ispc_for_gen.html
+++ b/ispc_for_gen.html
@@ -3,7 +3,7 @@
 <html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
 <head>
 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
-<meta name="generator" content="Docutils 0.15.2: http://docutils.sourceforge.net/" />
+<meta name="generator" content="Docutils 0.14: http://docutils.sourceforge.net/" />
 <title>Intel® ISPC for GEN</title>
 <script type="text/javascript">
 
@@ -27,7 +27,7 @@
     <div id="header">
       <h1 id="logo">Intel® Implicit SPMD Program Compiler</h1>
       <div id="slogan">An open-source compiler for high-performance SIMD programming on
-      the CPU</div>
+      the CPU and GPU</div>
     </div>
     <div id="nav">
       <div id="nbar">
@@ -77,31 +77,38 @@ <h1 class="title">Intel® ISPC for GEN</h1>
 <li><a class="reference internal" href="#ispc-run-time-ispcrt">ISPC Run Time (ISPCRT)</a><ul>
 <li><a class="reference internal" href="#ispcrt-objects">ISPCRT Objects</a></li>
 <li><a class="reference internal" href="#execution-model">Execution Model</a></li>
+<li><a class="reference internal" href="#configuration">Configuration</a></li>
 </ul>
 </li>
 <li><a class="reference internal" href="#compiling-and-running-simple-ispc-program">Compiling and Running Simple ISPC Program</a></li>
 <li><a class="reference internal" href="#language-limitations-and-known-issues">Language Limitations and Known Issues</a></li>
-<li><a class="reference internal" href="#performance">Performance</a></li>
+<li><a class="reference internal" href="#performance">Performance</a><ul>
+<li><a class="reference internal" href="#performance-guide-for-gpu-programming">Performance Guide for GPU Programming</a></li>
+</ul>
+</li>
 <li><a class="reference internal" href="#faq">FAQ</a><ul>
 <li><a class="reference internal" href="#how-to-get-an-assembly-file-from-spir-v">How to Get an Assembly File from SPIR-V?</a></li>
+<li><a class="reference internal" href="#how-to-debug-on-gpu">How to Debug on GPU?</a></li>
 </ul>
 </li>
 </ul>
 <div class="section" id="using-the-ispc-compiler">
 <h1>Using The ISPC Compiler</h1>
-<p>The output from <tt class="docutils literal">ispc</tt> for GEN targets is SPIR-V file. SPIR-V output format
-is selected by default when one of <tt class="docutils literal">genx</tt> targets is used:</p>
+<p>The output from <tt class="docutils literal">ispc</tt> for GEN targets is SPIR-V file by default. It is used
+when one of <tt class="docutils literal">genx</tt> targets is selected:</p>
 <pre class="literal-block">
 ispc foo.ispc --target=genx-x8 -o foo.spv
 </pre>
 <p>The SPIR-V file is consumed by the runtime for further compilation and execution
 on GPU.</p>
+<p>You can also generate L0 binary using <tt class="docutils literal"><span class="pre">--emit-zebin</span></tt> flag. Please note that
+currently SPIR-V format is more stable but feel free to experiment with L0 binary.</p>
 <div class="section" id="environment">
 <h2>Environment</h2>
 <p>Currently, <tt class="docutils literal">Intel® ISPC for GEN</tt> is supported on Linux only but it is planned
 to be extended for Windows as well in a future release.
 Recommended and tested Linux distribution is Ubuntu 18.04.</p>
-<p>You need to have a system with <tt class="docutils literal">Intel(R) Processor Graphics Gen9</tt>.</p>
+<p>You need to have a system with <tt class="docutils literal">Intel(R) Processor Graphics Gen9</tt> or later.</p>
 <p>For the execution of ISPC programs on GPU, please install <a class="reference external" href="https://github.com/intel/compute-runtime/releases">Intel(R)
 Graphics Compute Runtime</a>
 and <a class="reference external" href="https://github.com/oneapi-src/level-zero/releases">Level Zero Loader</a>.</p>
@@ -117,6 +124,9 @@ <h2>Basic Command-line Options</h2>
 <pre class="literal-block">
 ispc --target=genx-x8 --emit-spirv foo.ispc -o foo.spv
 </pre>
+<p>To generate L0 binary, use <tt class="docutils literal"><span class="pre">--emit-zebin</span></tt> flag. When you use L0 binary you may
+want to pass some additional options to the vector backend. You can do this using
+<tt class="docutils literal"><span class="pre">--vc-options</span></tt> flag.</p>
 <p>Also two new <tt class="docutils literal">arch</tt> options were introduced: <tt class="docutils literal">genx32</tt> and <tt class="docutils literal">genx64</tt>.
 <tt class="docutils literal">genx64</tt> is default and corresponds to 64-bit host and has 64-bit pointer size,
 <tt class="docutils literal">genx32</tt> corresponds to 32-bit host and has 32-bit pointer size.</p>
@@ -146,7 +156,12 @@ <h1>ISPC Run Time (ISPCRT)</h1>
 link to.
 Examples in <tt class="docutils literal">ispc/examples/portable/genx/</tt> directory demonstrate how to use
 this API to run SPMD programs on CPU or GPU. You can see how to use
-<tt class="docutils literal">oneAPI Level Zero</tt> runtime in <tt class="docutils literal">sgemm</tt> example.</p>
+<tt class="docutils literal">oneAPI Level Zero</tt> runtime in <tt class="docutils literal">sgemm</tt> example.
+It is also possible to run ISPC kernels and DPCPP kernels written with <tt class="docutils literal">oneAPI
+DPC++ Compiler</tt> using <tt class="docutils literal">oneAPI Level Zero</tt> from the same process and share data
+between them. Try <tt class="docutils literal"><span class="pre">Simple-DPCPP</span></tt> and <tt class="docutils literal"><span class="pre">Pipeline-DPCPP</span></tt> examples to learn
+more about this possibility. Please keep in mind though that this
+feature is experimental.</p>
 <div class="section" id="ispcrt-objects">
 <h2>ISPCRT Objects</h2>
 <p>The <tt class="docutils literal">ISPC Run Time</tt> uses the following abstractions to manage code execution:</p>
@@ -195,6 +210,27 @@ <h2>Execution Model</h2>
 that purpose (such as <tt class="docutils literal">taskIndex</tt>, <tt class="docutils literal">taskCount</tt>, <tt class="docutils literal">programIndex</tt>,
 <tt class="docutils literal">programCount</tt>) are available for use on GPU.</p>
 </div>
+<div class="section" id="configuration">
+<h2>Configuration</h2>
+<p>The behavior of <tt class="docutils literal">ISPCRT</tt> can be configured using the following environment
+variables:</p>
+<ul class="simple">
+<li><tt class="docutils literal">ISPCRT_USE_ZEBIN</tt> - use experimental L0 native binary format.
+Unlike SPIR-V files, zebin files are not portable between different GPU types.</li>
+<li><tt class="docutils literal">ISPCRT_IGC_OPTIONS</tt> - <tt class="docutils literal">ISPCRT</tt> is using an Intel® Graphics Compiler (IGC)
+to produce binary code that can be executed on the GPU. <tt class="docutils literal">ISPCRT</tt> allows
+for passing certain options to the IGC via <tt class="docutils literal">ISPCRT_IGC_OPTIONS</tt> variable.
+The content of this variable should be prefixed with <tt class="docutils literal">+</tt> or <tt class="docutils literal">=</tt> sign.
+<tt class="docutils literal">+</tt> means that the content of the variable should be added to the default
+IGC options already passsed by the <tt class="docutils literal">ISPCRT</tt>, while <tt class="docutils literal">=</tt> tells the <tt class="docutils literal">ISPCRT</tt>
+to replace the default options with the content of the environment variable.</li>
+<li><tt class="docutils literal">ISPCRT_GPU_DEVICE</tt> - if more than one supported GPU is present in the system,
+the user can select the GPU device to be used by the <tt class="docutils literal">ISPCRT</tt> using <tt class="docutils literal">ISPCRT_GPU_DEVICE</tt>
+variable. It should be set to a number of a device as enumerated
+by the Level Zero runtime. For example, in a system with two GPUs present,
+the variable can be set to <tt class="docutils literal">0</tt> or <tt class="docutils literal">1</tt>.</li>
+</ul>
+</div>
 </div>
 <div class="section" id="compiling-and-running-simple-ispc-program">
 <h1>Compiling and Running Simple ISPC Program</h1>
@@ -236,7 +272,7 @@ <h1>Compiling and Running Simple ISPC Program</h1>
 in this program is the usage of the <tt class="docutils literal">task</tt> keyword in the function definition
 instead of <tt class="docutils literal">export</tt>; this indicates that this function is a <tt class="docutils literal">kernel</tt> so it
 can be called from the host.</p>
-<p>Second thing to notice is <tt class="docutils literal">DEFINE_CPU_ENTRY_POINT</tt> which tells <tt class="docutils literal">ISPCRT</tt> what
+<p>The second thing to notice is <tt class="docutils literal">DEFINE_CPU_ENTRY_POINT</tt> which tells <tt class="docutils literal">ISPCRT</tt> what
 function is an entry point for CPU. If you look into the definition of
 <tt class="docutils literal">DEFINE_CPU_ENTRY_POINT</tt>, it is just simple <tt class="docutils literal">launch</tt> call:</p>
 <pre class="literal-block">
@@ -364,7 +400,7 @@ <h1>Compiling and Running Simple ISPC Program</h1>
 <pre class="literal-block">
 cmake ../ -DISPC_EXECUTABLE_GPU=/home/install/bin/ispc &amp;&amp; make
 </pre>
-<p>You can also run separate compilation commands to achive the same result:</p>
+<p>You can also run separate compilation commands to achieve the same result:</p>
 <ul>
 <li><p class="first">Compile ISPC kernel for GPU:</p>
 <pre class="literal-block">
@@ -398,43 +434,179 @@ <h1>Compiling and Running Simple ISPC Program</h1>
 </pre>
 </li>
 </ul>
+<dl class="docutils">
+<dt>By default examples uses SPIR-V format. You can try them with L0 binary format:</dt>
+<dd><pre class="first last literal-block">
+cd examples/portable/genx/build
+cmake -DISPC_GENX_FORMAT=zebin ../
+export ISPCRT_USE_ZEBIN=y
+cd simple &amp;&amp; ./host_simple --gpu
+</pre>
+</dd>
+</dl>
 </div>
 <div class="section" id="language-limitations-and-known-issues">
 <h1>Language Limitations and Known Issues</h1>
-<p>The current release of <tt class="docutils literal">Intel® ISPC for GEN</tt> is in alpha state so not all
-functionality is implemented yet. However, it is actively developed so we
-expect to cover missing features in the nearest future releases.
+<p>The current release of <tt class="docutils literal">Intel® ISPC for GEN</tt> is in beta state so you may face
+some issues. However, it is actively developed so we expect to fix remaining
+issues in the nearest future releases.
 Below is the list of known limitations:</p>
 <ul class="simple">
-<li>No function pointers support</li>
+<li>Limited function pointers support</li>
+<li>Double math functions like <tt class="docutils literal">sin</tt>, <tt class="docutils literal">cos</tt>, <tt class="docutils literal">log</tt> etc. are extremely slow.</li>
+<li>Integer fast division is not fast yet especially for unisgned types.</li>
+<li><tt class="docutils literal">print</tt> doesn't work perfectly especially in deep control flow statements.
+Also <tt class="docutils literal">print</tt> is not supported with L0 binary format.</li>
 <li>No <tt class="docutils literal">prefetch</tt> support</li>
-<li>No global atomics</li>
-<li>No double precision math functions</li>
-<li>Foreach inside varying control flow is not supported by default. However you
-can enable it by using experimental flag <tt class="docutils literal"><span class="pre">--opt=enable-genx-foreach-varying</span></tt>
-but performance will degrade with this flag.</li>
 </ul>
-<p>There are several features which we do not plan to implement for GPU:</p>
+<p>There are several features that we do not plan to implement for GPU:</p>
 <ul class="simple">
 <li><tt class="docutils literal">launch</tt> and <tt class="docutils literal">sync</tt> keywords are not supported for GPU in ISPC program
 since kernel execution is managed in the host code now.</li>
-<li><tt class="docutils literal">New</tt> and <tt class="docutils literal">delete</tt> keywords are not expected to be supported in ISPC
+<li><tt class="docutils literal">new</tt> and <tt class="docutils literal">delete</tt> keywords are not expected to be supported in ISPC
 program for GEN target. We expect all memory to be set up on the host side.</li>
 <li><tt class="docutils literal">export</tt> functions must return <tt class="docutils literal">void</tt> for GEN targets.</li>
 </ul>
 </div>
 <div class="section" id="performance">
 <h1>Performance</h1>
-<p>The performance of <tt class="docutils literal">Intel® ISPC for GEN</tt> is not the goal of the current release.
-It has a room for improvements and we're working hard to make it better for
+<p>The performance of <tt class="docutils literal">Intel® ISPC for GEN</tt> was significantly improved in this release
+but still has room for improvements and we're working hard to make it better for
 the next release. Here are our results for <tt class="docutils literal">mandelbrot</tt> which were obtained on
 Intel(R) Core(TM) i9-9900K CPU &#64; 3.60GHz with Intel(R) Gen9 HD Graphics
 (max compute units 24):</p>
 <ul class="simple">
 <li>&#64;time of CPU run:                     [16.343] milliseconds</li>
-<li>&#64;time of GPU run:                     [29.583] milliseconds</li>
-<li>&#64;time of serial run:                  [566] milliseconds</li>
+<li>&#64;time of GPU run:                     [17.294] milliseconds</li>
+<li>&#64;time of serial run:                  [562] milliseconds</li>
+</ul>
+<p>Talking about real-world workloads, usually we demonstrate a good performance on GPU
+that is on par with CPU.</p>
+<div class="section" id="performance-guide-for-gpu-programming">
+<h2>Performance Guide for GPU Programming</h2>
+<p>There are several rules for GPU programming which can bring you better performance.</p>
+<p><strong>Reduce register pressure</strong></p>
+<p>The first guidance is to reduce number of local variables. All variables are stored
+in GPU registers, and in the case when number of variables exceeds the number of
+registers, time-costly <tt class="docutils literal">register spill</tt> occurs.</p>
+<p>For example, Intel(R) Gen9 register file size is 128x8x32bit. Each 32-bit
+varying value takes 8x32bit in SIMD-8, and 16x32bit in SIMD-16.</p>
+<p>To reduce number of local variables you can follow these simple rules:</p>
+<ul class="simple">
+<li>Use uniform instead of varyings wherever it is possible. This practice
+is good for both CPU and GPU but on GPU it is essential.</li>
+</ul>
+<pre class="literal-block">
+// Good example
+for(uniform int j=0;  j&lt;3; j++) {
+    do_something();
+}
+</pre>
+<pre class="literal-block">
+// Bad example
+for(int j=0;  j&lt;3; j++) {
+    do_something();
+}
+</pre>
+<ul class="simple">
+<li>Avoid deep nesting code with lot of local variables. It is more effective
+to split kernel into stages with separate variable scopes.</li>
+<li>Avoid returning complex structures from functions. Instead of operation that
+may need work on structure copy, consider to use reference or pointer. We're
+working to make such optimization automatically for future release:</li>
+</ul>
+<pre class="literal-block">
+// Instead of this:
+struct ExampleStructure
+{
+  //...
+}
+
+ExampleStructure createExampleStructure()
+{
+  ExampleStructure retVal;
+  //... initialize
+  return retVal;
+}
+
+int test()
+{
+  ExampleStructure s;
+  s = createExampleStructure();
+}
+</pre>
+<pre class="literal-block">
+// Consider using pointer:
+struct ExampleStructure
+{
+  //...
+}
+
+void initExampleStructure(ExampleStructure* init)
+{
+  //... initialize
+}
+
+int test()
+{
+  ExampleStructure s;
+  initExampleStructure( &amp;s );
+}
+</pre>
+<ul class="simple">
+<li>Avoid recursion.</li>
+<li>Use SIMD-8 where it is impossible to fit in the available register number.
+If you see the warning message below during runtime, consider compiling your code
+for SIMD-8 target (<tt class="docutils literal"><span class="pre">--target=genx-x8</span></tt>)</li>
+</ul>
+<pre class="literal-block">
+Spill memory used = 32 bytes for kernel kernel_name___vyi
+</pre>
+<p><strong>Code Branching</strong></p>
+<p>The second set of rules is related to code branching.</p>
+<ul class="simple">
+<li>Use <tt class="docutils literal">select</tt> instead of branching:</li>
 </ul>
+<pre class="literal-block">
+if (x &gt; 0)
+  a = x;
+else
+  a = 7;
+</pre>
+<pre class="literal-block">
+// May be implemented without branch:
+a = (x &gt; 0)? x : 7;
+</pre>
+<ul class="simple">
+<li>Keep branches as small as possible. Common operations should be moved outside the branch.
+In case when large code branches are necessary, consider changing your algorithm to group
+data processed by one task to follow the same path in the branch.</li>
+</ul>
+<pre class="literal-block">
+// Both branches execute memory access to 'array'. In the case of split branch between
+// different lanes, two memory access instructions would be executed.
+if (x &gt; 0)
+  a = array[x];
+else
+  a = array[0];
+</pre>
+<pre class="literal-block">
+// Instead move common part outside of the branch:
+int i;
+if (x &gt; 0)
+  i = x;
+else
+  i = 0;
+a = array[i];
+</pre>
+<p><strong>Memory Operations</strong></p>
+<p>Remember that memory operations on GPU are expensive. We do not support dynamic
+memory allocations in kernel code for GPU so use fixed-size buffers preallocated
+by the host.</p>
+<p>We have several memory optimizations for GPU like gather/scatter coalescing. However
+current implementation covers only limited number of cases and we expect to improve it
+for the next release.</p>
+</div>
 </div>
 <div class="section" id="faq">
 <h1>FAQ</h1>
@@ -451,6 +623,13 @@ <h2>How to Get an Assembly File from SPIR-V?</h2>
 </pre>
 <p>You will get <tt class="docutils literal">.asm</tt> files for each kernel in &lt;FOLDER_TO_DUMP&gt;.</p>
 </div>
+<div class="section" id="how-to-debug-on-gpu">
+<h2>How to Debug on GPU?</h2>
+<p>To debug your application, you can use oneAPI Debugger as described here:
+<a class="reference external" href="https://software.intel.com/get-started-with-debugging-dpcpp-linux">Get Started with GDB* for oneAPI on Linux* OS Host</a>.
+Debugger support is quite limited at this time but you can set breakpoints
+in kernel code, do step-by-step execution and print variables.</p>
+</div>
 </div>
 </div>
     <div class="clearfix"></div>
diff --git a/perf.html b/perf.html
index 9a4367bb..8dd8d3af 100644
--- a/perf.html
+++ b/perf.html
@@ -3,7 +3,7 @@
 <html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
 <head>
 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
-<meta name="generator" content="Docutils 0.15.2: http://docutils.sourceforge.net/" />
+<meta name="generator" content="Docutils 0.14: http://docutils.sourceforge.net/" />
 <title>Performance</title>
 <script type="text/javascript">
 
@@ -27,7 +27,7 @@
     <div id="header">
       <h1 id="logo">Intel® Implicit SPMD Program Compiler</h1>
       <div id="slogan">An open-source compiler for high-performance SIMD programming on
-      the CPU</div>
+      the CPU and GPU</div>
     </div>
     <div id="nav">
       <div id="nbar">
@@ -83,39 +83,39 @@ <h1 class="title">Performance</h1>
 <td><tt class="docutils literal">ispc</tt>, 1 core</td>
 <td><tt class="docutils literal">ispc</tt>, 4 cores</td>
 </tr>
-<tr><td><a class="reference external" href="https://github.com/ispc/ispc/tree/master/examples/aobench">AOBench</a> (512 x 512 resolution)</td>
+<tr><td><a class="reference external" href="https://github.com/ispc/ispc/tree/main/examples/aobench">AOBench</a> (512 x 512 resolution)</td>
 <td>6.19x</td>
 <td>28.06x</td>
 </tr>
-<tr><td><a class="reference external" href="https://github.com/ispc/ispc/tree/master/examples/options">Binomial Options</a> (128k options)</td>
+<tr><td><a class="reference external" href="https://github.com/ispc/ispc/tree/main/examples/options">Binomial Options</a> (128k options)</td>
 <td>7.94x</td>
 <td>33.43x</td>
 </tr>
-<tr><td><a class="reference external" href="https://github.com/ispc/ispc/tree/master/examples/options">Black-Scholes Options</a> (128k options)</td>
+<tr><td><a class="reference external" href="https://github.com/ispc/ispc/tree/main/examples/options">Black-Scholes Options</a> (128k options)</td>
 <td>8.45x</td>
 <td>32.48x</td>
 </tr>
-<tr><td><a class="reference external" href="https://github.com/ispc/ispc/tree/master/examples/deferred">Deferred Shading</a> (1280p)</td>
+<tr><td><a class="reference external" href="https://github.com/ispc/ispc/tree/main/examples/deferred">Deferred Shading</a> (1280p)</td>
 <td>5.02x</td>
 <td>23.06x</td>
 </tr>
-<tr><td><a class="reference external" href="https://github.com/ispc/ispc/tree/master/examples/mandelbrot_tasks">Mandelbrot Set</a></td>
+<tr><td><a class="reference external" href="https://github.com/ispc/ispc/tree/main/examples/mandelbrot_tasks">Mandelbrot Set</a></td>
 <td>6.21x</td>
 <td>20.28x</td>
 </tr>
-<tr><td><a class="reference external" href="https://github.com/ispc/ispc/tree/master/examples/noise">Perlin Noise Function</a></td>
+<tr><td><a class="reference external" href="https://github.com/ispc/ispc/tree/main/examples/noise">Perlin Noise Function</a></td>
 <td>5.37x</td>
 <td>n/a</td>
 </tr>
-<tr><td><a class="reference external" href="https://github.com/ispc/ispc/tree/master/examples/rt">Ray Tracer</a> (Sponza dataset)</td>
+<tr><td><a class="reference external" href="https://github.com/ispc/ispc/tree/main/examples/rt">Ray Tracer</a> (Sponza dataset)</td>
 <td>4.31x</td>
 <td>20.29x</td>
 </tr>
-<tr><td><a class="reference external" href="https://github.com/ispc/ispc/tree/master/examples/stencil">3D Stencil</a></td>
+<tr><td><a class="reference external" href="https://github.com/ispc/ispc/tree/main/examples/stencil">3D Stencil</a></td>
 <td>4.05x</td>
 <td>15.53x</td>
 </tr>
-<tr><td><a class="reference external" href="https://github.com/ispc/ispc/tree/master/examples/volume_rendering">Volume Rendering</a></td>
+<tr><td><a class="reference external" href="https://github.com/ispc/ispc/tree/main/examples/volume_rendering">Volume Rendering</a></td>
 <td>3.60x</td>
 <td>17.53x</td>
 </tr>
@@ -156,36 +156,8 @@ <h1 class="title">Performance</h1>
 </table>
 <div class="section" id="notices-disclaimers">
 <h1>Notices &amp; Disclaimers</h1>
-<p>Software and workloads used in performance tests may have been optimized for
-performance only on Intel microprocessors.</p>
-<p>Performance tests, such as SYSmark and MobileMark, are measured using specific
-computer systems, components, software, operations and functions.  Any change
-to any of those factors may cause the results to vary.  You should consult
-other information and performance tests to assist you in fully evaluating your
-contemplated purchases, including the performance of that product when combined
-with other products.   For more complete information visit
-www.intel.com/benchmarks.</p>
-<p>Performance results are based on testing as of dates shown in configurations and
-may not reflect all publicly available updates.  See backup for configuration
-details.  No product or component can be absolutely secure.</p>
-<p>Your costs and results may vary.</p>
-<p>Intel technologies may require enabled hardware, software or service activation.</p>
-<p>© Intel Corporation.  Intel, the Intel logo, and other Intel marks are
-trademarks of Intel Corporation or its subsidiaries.  Other names and brands may
-be claimed as the property of others.</p>
-</div>
-<div class="section" id="optimization-notice">
-<h1>Optimization Notice</h1>
-<p>Intel's compilers may or may not optimize to the same degree for non-Intel
-microprocessors for optimizations that are not unique to Intel microprocessors.
-These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other
-optimizations. Intel does not guarantee the availability, functionality, or
-effectiveness of any optimization on microprocessors not manufactured by Intel.
-Microprocessor-dependent optimizations in this product are intended for use with
-Intel microprocessors. Certain optimizations not specific to Intel
-microarchitecture are reserved for Intel microprocessors. Please refer to the
-applicable product User and Reference Guides for more information regarding the
-specific instruction sets covered by this notice.</p>
+<p>Performance varies by use, configuration and other factors. Learn more at
+www.intel.com/PerformanceIndex.</p>
 </div>
 </div>
     <div class="clearfix"></div>
diff --git a/perfguide.html b/perfguide.html
index 640bb598..accc8262 100644
--- a/perfguide.html
+++ b/perfguide.html
@@ -3,7 +3,7 @@
 <html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
 <head>
 <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
-<meta name="generator" content="Docutils 0.15.2: http://docutils.sourceforge.net/" />
+<meta name="generator" content="Docutils 0.14: http://docutils.sourceforge.net/" />
 <title>Intel® ISPC Performance Guide</title>
 <script type="text/javascript">
 
@@ -27,7 +27,7 @@
     <div id="header">
       <h1 id="logo">Intel® Implicit SPMD Program Compiler</h1>
       <div id="slogan">An open-source compiler for high-performance SIMD programming on
-      the CPU</div>
+      the CPU and GPU</div>
     </div>
     <div id="nav">
       <div id="nbar">
@@ -88,7 +88,6 @@ <h1 class="title">Intel® ISPC Performance Guide</h1>
 </ul>
 </li>
 <li><a class="reference internal" href="#notices-disclaimers">Notices &amp; Disclaimers</a></li>
-<li><a class="reference internal" href="#optimization-notice">Optimization Notice</a></li>
 </ul>
 <div class="section" id="key-concepts">
 <h1>Key Concepts</h1>
@@ -670,36 +669,8 @@ <h2>Choosing A Target Vector Width</h2>
 </div>
 <div class="section" id="notices-disclaimers">
 <h1>Notices &amp; Disclaimers</h1>
-<p>Software and workloads used in performance tests may have been optimized for
-performance only on Intel microprocessors.</p>
-<p>Performance tests, such as SYSmark and MobileMark, are measured using specific
-computer systems, components, software, operations and functions.  Any change
-to any of those factors may cause the results to vary.  You should consult
-other information and performance tests to assist you in fully evaluating your
-contemplated purchases, including the performance of that product when combined
-with other products.   For more complete information visit
-www.intel.com/benchmarks.</p>
-<p>Performance results are based on testing as of dates shown in configurations and
-may not reflect all publicly available updates.  See backup for configuration
-details.  No product or component can be absolutely secure.</p>
-<p>Your costs and results may vary.</p>
-<p>Intel technologies may require enabled hardware, software or service activation.</p>
-<p>© Intel Corporation.  Intel, the Intel logo, and other Intel marks are
-trademarks of Intel Corporation or its subsidiaries.  Other names and brands may
-be claimed as the property of others.</p>
-</div>
-<div class="section" id="optimization-notice">
-<h1>Optimization Notice</h1>
-<p>Intel's compilers may or may not optimize to the same degree for non-Intel
-microprocessors for optimizations that are not unique to Intel microprocessors.
-These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other
-optimizations. Intel does not guarantee the availability, functionality, or
-effectiveness of any optimization on microprocessors not manufactured by Intel.
-Microprocessor-dependent optimizations in this product are intended for use with
-Intel microprocessors. Certain optimizations not specific to Intel
-microarchitecture are reserved for Intel microprocessors. Please refer to the
-applicable product User and Reference Guides for more information regarding the
-specific instruction sets covered by this notice.</p>
+<p>Performance varies by use, configuration and other factors. Learn more at
+www.intel.com/PerformanceIndex.</p>
 </div>
 </div>
     <div class="clearfix"></div>