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Use correct spelling of "U-Boot"
Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
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Lines changed: 606 additions & 606 deletions

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‎README‎

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@@ -460,7 +460,7 @@ The following options need to be configured:
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CONFIG_SYS_CPC_REINIT_F
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This CONFIG is defined when the CPC is configured as SRAM at the
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time of U-boot entry and is required to be re-initialized.
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time of U-Boot entry and is required to be re-initialized.
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CONFIG_DEEP_SLEEP
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Indicates this SoC supports deep sleep feature. If deep sleep is
@@ -2963,7 +2963,7 @@ CBFS (Coreboot Filesystem) support
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- Parallel Flash support:
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CONFIG_SYS_NO_FLASH
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Traditionally U-boot was run on systems with parallel NOR
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Traditionally U-Boot was run on systems with parallel NOR
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flash. This option is used to disable support for parallel NOR
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flash. This option should be defined if the board does not have
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parallel flash.

‎arch/arm/cpu/arm926ejs/lpc32xx/cpu.c‎

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@@ -46,7 +46,7 @@ void reset_cpu(ulong addr)
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int arch_cpu_init(void)
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{
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/*
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* It might be necessary to flush data cache, if U-boot is loaded
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* It might be necessary to flush data cache, if U-Boot is loaded
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* from kickstart bootloader, e.g. from S1L loader
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*/
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flush_dcache_all();

‎arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S‎

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@@ -41,5 +41,5 @@ lowlevel_init:
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orr r0, #0x00000004
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str r0, [r1]
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/* Return to U-boot via saved link register */
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/* Return to U-Boot via saved link register */
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mov pc, lr

‎arch/arm/cpu/armv7/nonsec_virt.S‎

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@@ -37,7 +37,7 @@ _monitor_vectors:
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/*
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* secure monitor handler
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* U-boot calls this "software interrupt" in start.S
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* U-Boot calls this "software interrupt" in start.S
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* This is executed on a "smc" instruction, we use a "smc #0" to switch
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* to non-secure state.
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* r0, r1, r2: passed to the callee

‎arch/arm/cpu/armv8/Kconfig‎

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@@ -1,6 +1,6 @@
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if ARM64
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config ARMV8_MULTIENTRY
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boolean "Enable multiple CPUs to enter into U-boot"
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boolean "Enable multiple CPUs to enter into U-Boot"
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endif

‎arch/arm/dts/uniphier-ph1-ld4-ref.dts‎

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@@ -59,7 +59,7 @@
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status = "okay";
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};
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/* for U-boot only */
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/* for U-Boot only */
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/ {
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soc {
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u-boot,dm-pre-reloc;

‎arch/arm/dts/uniphier-ph1-ld6b-ref.dts‎

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@@ -61,7 +61,7 @@
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status = "okay";
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};
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/* for U-boot only */
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/* for U-Boot only */
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/ {
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soc {
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u-boot,dm-pre-reloc;

‎arch/arm/dts/uniphier-ph1-pro4-ref.dts‎

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@@ -66,7 +66,7 @@
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status = "okay";
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};
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/* for U-boot only */
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/* for U-Boot only */
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/ {
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soc {
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u-boot,dm-pre-reloc;

‎arch/arm/dts/uniphier-ph1-pro5-4kbox.dts‎

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@@ -47,7 +47,7 @@
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status = "okay";
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};
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/* for U-boot only */
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/* for U-Boot only */
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/ {
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soc {
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u-boot,dm-pre-reloc;

‎arch/arm/dts/uniphier-ph1-sld3-ref.dts‎

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@@ -68,7 +68,7 @@
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status = "okay";
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};
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/* for U-boot only */
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/* for U-Boot only */
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&serial0 {
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u-boot,dm-pre-reloc;
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};

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