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Yuanhan Liuneilbrown
Yuanhan Liu
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neilbrown
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lib/raid6: Add AVX2 optimized gen_syndrome functions
Add AVX2 optimized gen_syndrom functions, which is simply based on sse2.c written by hpa. Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com> Reviewed-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Jim Kukunas <james.t.kukunas@linux.intel.com> Signed-off-by: NeilBrown <neilb@suse.de>
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‎include/linux/raid/pq.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -98,6 +98,9 @@ extern const struct raid6_calls raid6_altivec1;
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extern const struct raid6_calls raid6_altivec2;
9999
extern const struct raid6_calls raid6_altivec4;
100100
extern const struct raid6_calls raid6_altivec8;
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extern const struct raid6_calls raid6_avx2x1;
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extern const struct raid6_calls raid6_avx2x2;
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extern const struct raid6_calls raid6_avx2x4;
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102105
struct raid6_recov_calls {
103106
void (*data2)(int, size_t, int, int, void **);

‎lib/raid6/Makefile‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ obj-$(CONFIG_RAID6_PQ) += raid6_pq.o
22

33
raid6_pq-y += algos.o recov.o recov_ssse3.o recov_avx2.o tables.o int1.o int2.o int4.o \
44
int8.o int16.o int32.o altivec1.o altivec2.o altivec4.o \
5-
altivec8.o mmx.o sse1.o sse2.o
5+
altivec8.o mmx.o sse1.o sse2.o avx2.o
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hostprogs-y += mktables
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quiet_cmd_unroll = UNROLL $@

‎lib/raid6/algos.c‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,11 +45,20 @@ const struct raid6_calls * const raid6_algos[] = {
4545
&raid6_sse1x2,
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&raid6_sse2x1,
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&raid6_sse2x2,
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#ifdef CONFIG_AS_AVX2
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&raid6_avx2x1,
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&raid6_avx2x2,
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#endif
4852
#endif
4953
#if defined(__x86_64__) && !defined(__arch_um__)
5054
&raid6_sse2x1,
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&raid6_sse2x2,
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&raid6_sse2x4,
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#ifdef CONFIG_AS_AVX2
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&raid6_avx2x1,
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&raid6_avx2x2,
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&raid6_avx2x4,
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#endif
5362
#endif
5463
#ifdef CONFIG_ALTIVEC
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&raid6_altivec1,

‎lib/raid6/avx2.c‎

Lines changed: 251 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,251 @@
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/* -*- linux-c -*- ------------------------------------------------------- *
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*
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* Copyright (C) 2012 Intel Corporation
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* Author: Yuanhan Liu <yuanhan.liu@linux.intel.com>
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*
6+
* Based on sse2.c: Copyright 2002 H. Peter Anvin - All Rights Reserved
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, Inc., 53 Temple Place Ste 330,
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* Boston MA 02111-1307, USA; either version 2 of the License, or
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* (at your option) any later version; incorporated herein by reference.
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*
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* ----------------------------------------------------------------------- */
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/*
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* AVX2 implementation of RAID-6 syndrome functions
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*
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*/
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#ifdef CONFIG_AS_AVX2
23+
24+
#include <linux/raid/pq.h>
25+
#include "x86.h"
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static const struct raid6_avx2_constants {
28+
u64 x1d[4];
29+
} raid6_avx2_constants __aligned(32) = {
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{ 0x1d1d1d1d1d1d1d1dULL, 0x1d1d1d1d1d1d1d1dULL,
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0x1d1d1d1d1d1d1d1dULL, 0x1d1d1d1d1d1d1d1dULL,},
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};
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static int raid6_have_avx2(void)
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{
36+
return boot_cpu_has(X86_FEATURE_AVX2) && boot_cpu_has(X86_FEATURE_AVX);
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}
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/*
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* Plain AVX2 implementation
41+
*/
42+
static void raid6_avx21_gen_syndrome(int disks, size_t bytes, void **ptrs)
43+
{
44+
u8 **dptr = (u8 **)ptrs;
45+
u8 *p, *q;
46+
int d, z, z0;
47+
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z0 = disks - 3; /* Highest data disk */
49+
p = dptr[z0+1]; /* XOR parity */
50+
q = dptr[z0+2]; /* RS syndrome */
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52+
kernel_fpu_begin();
53+
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asm volatile("vmovdqa %0,%%ymm0" : : "m" (raid6_avx2_constants.x1d[0]));
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asm volatile("vpxor %ymm3,%ymm3,%ymm3"); /* Zero temp */
56+
57+
for (d = 0; d < bytes; d += 32) {
58+
asm volatile("prefetchnta %0" : : "m" (dptr[z0][d]));
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asm volatile("vmovdqa %0,%%ymm2" : : "m" (dptr[z0][d]));/* P[0] */
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asm volatile("prefetchnta %0" : : "m" (dptr[z0-1][d]));
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asm volatile("vmovdqa %ymm2,%ymm4");/* Q[0] */
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asm volatile("vmovdqa %0,%%ymm6" : : "m" (dptr[z0-1][d]));
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for (z = z0-2; z >= 0; z--) {
64+
asm volatile("prefetchnta %0" : : "m" (dptr[z][d]));
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asm volatile("vpcmpgtb %ymm4,%ymm3,%ymm5");
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asm volatile("vpaddb %ymm4,%ymm4,%ymm4");
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asm volatile("vpand %ymm0,%ymm5,%ymm5");
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asm volatile("vpxor %ymm5,%ymm4,%ymm4");
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asm volatile("vpxor %ymm6,%ymm2,%ymm2");
70+
asm volatile("vpxor %ymm6,%ymm4,%ymm4");
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asm volatile("vmovdqa %0,%%ymm6" : : "m" (dptr[z][d]));
72+
}
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asm volatile("vpcmpgtb %ymm4,%ymm3,%ymm5");
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asm volatile("vpaddb %ymm4,%ymm4,%ymm4");
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asm volatile("vpand %ymm0,%ymm5,%ymm5");
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asm volatile("vpxor %ymm5,%ymm4,%ymm4");
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asm volatile("vpxor %ymm6,%ymm2,%ymm2");
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asm volatile("vpxor %ymm6,%ymm4,%ymm4");
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asm volatile("vmovntdq %%ymm2,%0" : "=m" (p[d]));
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asm volatile("vpxor %ymm2,%ymm2,%ymm2");
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asm volatile("vmovntdq %%ymm4,%0" : "=m" (q[d]));
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asm volatile("vpxor %ymm4,%ymm4,%ymm4");
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}
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86+
asm volatile("sfence" : : : "memory");
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kernel_fpu_end();
88+
}
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90+
const struct raid6_calls raid6_avx2x1 = {
91+
raid6_avx21_gen_syndrome,
92+
raid6_have_avx2,
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"avx2x1",
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1 /* Has cache hints */
95+
};
96+
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/*
98+
* Unrolled-by-2 AVX2 implementation
99+
*/
100+
static void raid6_avx22_gen_syndrome(int disks, size_t bytes, void **ptrs)
101+
{
102+
u8 **dptr = (u8 **)ptrs;
103+
u8 *p, *q;
104+
int d, z, z0;
105+
106+
z0 = disks - 3; /* Highest data disk */
107+
p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
109+
110+
kernel_fpu_begin();
111+
112+
asm volatile("vmovdqa %0,%%ymm0" : : "m" (raid6_avx2_constants.x1d[0]));
113+
asm volatile("vpxor %ymm1,%ymm1,%ymm1"); /* Zero temp */
114+
115+
/* We uniformly assume a single prefetch covers at least 32 bytes */
116+
for (d = 0; d < bytes; d += 64) {
117+
asm volatile("prefetchnta %0" : : "m" (dptr[z0][d]));
118+
asm volatile("prefetchnta %0" : : "m" (dptr[z0][d+32]));
119+
asm volatile("vmovdqa %0,%%ymm2" : : "m" (dptr[z0][d]));/* P[0] */
120+
asm volatile("vmovdqa %0,%%ymm3" : : "m" (dptr[z0][d+32]));/* P[1] */
121+
asm volatile("vmovdqa %ymm2,%ymm4"); /* Q[0] */
122+
asm volatile("vmovdqa %ymm3,%ymm6"); /* Q[1] */
123+
for (z = z0-1; z >= 0; z--) {
124+
asm volatile("prefetchnta %0" : : "m" (dptr[z][d]));
125+
asm volatile("prefetchnta %0" : : "m" (dptr[z][d+32]));
126+
asm volatile("vpcmpgtb %ymm4,%ymm1,%ymm5");
127+
asm volatile("vpcmpgtb %ymm6,%ymm1,%ymm7");
128+
asm volatile("vpaddb %ymm4,%ymm4,%ymm4");
129+
asm volatile("vpaddb %ymm6,%ymm6,%ymm6");
130+
asm volatile("vpand %ymm0,%ymm5,%ymm5");
131+
asm volatile("vpand %ymm0,%ymm7,%ymm7");
132+
asm volatile("vpxor %ymm5,%ymm4,%ymm4");
133+
asm volatile("vpxor %ymm7,%ymm6,%ymm6");
134+
asm volatile("vmovdqa %0,%%ymm5" : : "m" (dptr[z][d]));
135+
asm volatile("vmovdqa %0,%%ymm7" : : "m" (dptr[z][d+32]));
136+
asm volatile("vpxor %ymm5,%ymm2,%ymm2");
137+
asm volatile("vpxor %ymm7,%ymm3,%ymm3");
138+
asm volatile("vpxor %ymm5,%ymm4,%ymm4");
139+
asm volatile("vpxor %ymm7,%ymm6,%ymm6");
140+
}
141+
asm volatile("vmovntdq %%ymm2,%0" : "=m" (p[d]));
142+
asm volatile("vmovntdq %%ymm3,%0" : "=m" (p[d+32]));
143+
asm volatile("vmovntdq %%ymm4,%0" : "=m" (q[d]));
144+
asm volatile("vmovntdq %%ymm6,%0" : "=m" (q[d+32]));
145+
}
146+
147+
asm volatile("sfence" : : : "memory");
148+
kernel_fpu_end();
149+
}
150+
151+
const struct raid6_calls raid6_avx2x2 = {
152+
raid6_avx22_gen_syndrome,
153+
raid6_have_avx2,
154+
"avx2x2",
155+
1 /* Has cache hints */
156+
};
157+
158+
#ifdef CONFIG_X86_64
159+
160+
/*
161+
* Unrolled-by-4 AVX2 implementation
162+
*/
163+
static void raid6_avx24_gen_syndrome(int disks, size_t bytes, void **ptrs)
164+
{
165+
u8 **dptr = (u8 **)ptrs;
166+
u8 *p, *q;
167+
int d, z, z0;
168+
169+
z0 = disks - 3; /* Highest data disk */
170+
p = dptr[z0+1]; /* XOR parity */
171+
q = dptr[z0+2]; /* RS syndrome */
172+
173+
kernel_fpu_begin();
174+
175+
asm volatile("vmovdqa %0,%%ymm0" : : "m" (raid6_avx2_constants.x1d[0]));
176+
asm volatile("vpxor %ymm1,%ymm1,%ymm1"); /* Zero temp */
177+
asm volatile("vpxor %ymm2,%ymm2,%ymm2"); /* P[0] */
178+
asm volatile("vpxor %ymm3,%ymm3,%ymm3"); /* P[1] */
179+
asm volatile("vpxor %ymm4,%ymm4,%ymm4"); /* Q[0] */
180+
asm volatile("vpxor %ymm6,%ymm6,%ymm6"); /* Q[1] */
181+
asm volatile("vpxor %ymm10,%ymm10,%ymm10"); /* P[2] */
182+
asm volatile("vpxor %ymm11,%ymm11,%ymm11"); /* P[3] */
183+
asm volatile("vpxor %ymm12,%ymm12,%ymm12"); /* Q[2] */
184+
asm volatile("vpxor %ymm14,%ymm14,%ymm14"); /* Q[3] */
185+
186+
for (d = 0; d < bytes; d += 128) {
187+
for (z = z0; z >= 0; z--) {
188+
asm volatile("prefetchnta %0" : : "m" (dptr[z][d]));
189+
asm volatile("prefetchnta %0" : : "m" (dptr[z][d+32]));
190+
asm volatile("prefetchnta %0" : : "m" (dptr[z][d+64]));
191+
asm volatile("prefetchnta %0" : : "m" (dptr[z][d+96]));
192+
asm volatile("vpcmpgtb %ymm4,%ymm1,%ymm5");
193+
asm volatile("vpcmpgtb %ymm6,%ymm1,%ymm7");
194+
asm volatile("vpcmpgtb %ymm12,%ymm1,%ymm13");
195+
asm volatile("vpcmpgtb %ymm14,%ymm1,%ymm15");
196+
asm volatile("vpaddb %ymm4,%ymm4,%ymm4");
197+
asm volatile("vpaddb %ymm6,%ymm6,%ymm6");
198+
asm volatile("vpaddb %ymm12,%ymm12,%ymm12");
199+
asm volatile("vpaddb %ymm14,%ymm14,%ymm14");
200+
asm volatile("vpand %ymm0,%ymm5,%ymm5");
201+
asm volatile("vpand %ymm0,%ymm7,%ymm7");
202+
asm volatile("vpand %ymm0,%ymm13,%ymm13");
203+
asm volatile("vpand %ymm0,%ymm15,%ymm15");
204+
asm volatile("vpxor %ymm5,%ymm4,%ymm4");
205+
asm volatile("vpxor %ymm7,%ymm6,%ymm6");
206+
asm volatile("vpxor %ymm13,%ymm12,%ymm12");
207+
asm volatile("vpxor %ymm15,%ymm14,%ymm14");
208+
asm volatile("vmovdqa %0,%%ymm5" : : "m" (dptr[z][d]));
209+
asm volatile("vmovdqa %0,%%ymm7" : : "m" (dptr[z][d+32]));
210+
asm volatile("vmovdqa %0,%%ymm13" : : "m" (dptr[z][d+64]));
211+
asm volatile("vmovdqa %0,%%ymm15" : : "m" (dptr[z][d+96]));
212+
asm volatile("vpxor %ymm5,%ymm2,%ymm2");
213+
asm volatile("vpxor %ymm7,%ymm3,%ymm3");
214+
asm volatile("vpxor %ymm13,%ymm10,%ymm10");
215+
asm volatile("vpxor %ymm15,%ymm11,%ymm11");
216+
asm volatile("vpxor %ymm5,%ymm4,%ymm4");
217+
asm volatile("vpxor %ymm7,%ymm6,%ymm6");
218+
asm volatile("vpxor %ymm13,%ymm12,%ymm12");
219+
asm volatile("vpxor %ymm15,%ymm14,%ymm14");
220+
}
221+
asm volatile("vmovntdq %%ymm2,%0" : "=m" (p[d]));
222+
asm volatile("vpxor %ymm2,%ymm2,%ymm2");
223+
asm volatile("vmovntdq %%ymm3,%0" : "=m" (p[d+32]));
224+
asm volatile("vpxor %ymm3,%ymm3,%ymm3");
225+
asm volatile("vmovntdq %%ymm10,%0" : "=m" (p[d+64]));
226+
asm volatile("vpxor %ymm10,%ymm10,%ymm10");
227+
asm volatile("vmovntdq %%ymm11,%0" : "=m" (p[d+96]));
228+
asm volatile("vpxor %ymm11,%ymm11,%ymm11");
229+
asm volatile("vmovntdq %%ymm4,%0" : "=m" (q[d]));
230+
asm volatile("vpxor %ymm4,%ymm4,%ymm4");
231+
asm volatile("vmovntdq %%ymm6,%0" : "=m" (q[d+32]));
232+
asm volatile("vpxor %ymm6,%ymm6,%ymm6");
233+
asm volatile("vmovntdq %%ymm12,%0" : "=m" (q[d+64]));
234+
asm volatile("vpxor %ymm12,%ymm12,%ymm12");
235+
asm volatile("vmovntdq %%ymm14,%0" : "=m" (q[d+96]));
236+
asm volatile("vpxor %ymm14,%ymm14,%ymm14");
237+
}
238+
239+
asm volatile("sfence" : : : "memory");
240+
kernel_fpu_end();
241+
}
242+
243+
const struct raid6_calls raid6_avx2x4 = {
244+
raid6_avx24_gen_syndrome,
245+
raid6_have_avx2,
246+
"avx2x4",
247+
1 /* Has cache hints */
248+
};
249+
#endif
250+
251+
#endif /* CONFIG_AS_AVX2 */

‎lib/raid6/test/Makefile‎

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,16 @@ AWK = awk -f
1111
AR = ar
1212
RANLIB = ranlib
1313

14+
ARCH := $(shell uname -m 2>/dev/null | sed -e /s/i.86/i386/)
15+
ifeq ($(ARCH),i386)
16+
CFLAGS += -DCONFIG_X86_32
17+
endif
18+
ifeq ($(ARCH),x86_64)
19+
CFLAGS += -DCONFIG_X86_64
20+
endif
21+
CFLAGS += $(shell echo "vpbroadcastb %xmm0, %ymm1"| gcc -c -x assembler - &&\
22+
rm ./-.o && echo -DCONFIG_AS_AVX2=1)
23+
1424
.c.o:
1525
$(CC) $(CFLAGS) -c -o $@ $<
1626

@@ -22,7 +32,7 @@ RANLIB = ranlib
2232

2333
all: raid6.a raid6test
2434

25-
raid6.a: int1.o int2.o int4.o int8.o int16.o int32.o mmx.o sse1.o sse2.o \
35+
raid6.a: int1.o int2.o int4.o int8.o int16.o int32.o mmx.o sse1.o sse2.o avx2.o \
2636
altivec1.o altivec2.o altivec4.o altivec8.o recov.o recov_ssse3.o recov_avx2.o algos.o \
2737
tables.o
2838
rm -f $@

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