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Merge tag 'pci-v4.14-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas: - add enhanced Downstream Port Containment support, which prints more details about Root Port Programmed I/O errors (Dongdong Liu) - add Layerscape ls1088a and ls2088a support (Hou Zhiqiang) - add MediaTek MT2712 and MT7622 support (Ryder Lee) - add MediaTek MT2712 and MT7622 MSI support (Honghui Zhang) - add Qualcom IPQ8074 support (Varadarajan Narayanan) - add R-Car r8a7743/5 device tree support (Biju Das) - add Rockchip per-lane PHY support for better power management (Shawn Lin) - fix IRQ mapping for hot-added devices by replacing the pci_fixup_irqs() boot-time design with a host bridge hook called at probe-time (Lorenzo Pieralisi, Matthew Minter) - fix race when enabling two devices that results in upstream bridge not being enabled correctly (Srinath Mannam) - fix pciehp power fault infinite loop (Keith Busch) - fix SHPC bridge MSI hotplug events by enabling bus mastering (Aleksandr Bezzubikov) - fix a VFIO issue by correcting PCIe capability sizes (Alex Williamson) - fix an INTD issue on Xilinx and possibly other drivers by unifying INTx IRQ domain support (Paul Burton) - avoid IOMMU stalls by marking AMD Stoney GPU ATS as broken (Joerg Roedel) - allow APM X-Gene device assignment to guests by adding an ACS quirk (Feng Kan) - fix driver crashes by disabling Extended Tags on Broadcom HT2100 (Extended Tags support is required for PCIe Receivers but not Requesters, and we now enable them by default when Requesters support them) (Sinan Kaya) - fix MSIs for devices that use phantom RIDs for DMA by assuming MSIs use the real Requester ID (not a phantom RID) (Robin Murphy) - prevent assignment of Intel VMD children to guests (which may be supported eventually, but isn't yet) by not associating an IOMMU with them (Jon Derrick) - fix Intel VMD suspend/resume by releasing IRQs on suspend (Scott Bauer) - fix a Function-Level Reset issue with Intel 750 NVMe by waiting longer (up to 60sec instead of 1sec) for device to become ready (Sinan Kaya) - fix a Function-Level Reset issue on iProc Stingray by working around hardware defects in the CRS implementation (Oza Pawandeep) - fix an issue with Intel NVMe P3700 after an iProc reset by adding a delay during shutdown (Oza Pawandeep) - fix a Microsoft Hyper-V lockdep issue by polling instead of blocking in compose_msi_msg() (Stephen Hemminger) - fix a wireless LAN driver timeout by clearing DesignWare MSI interrupt status after it is handled, not before (Faiz Abbas) - fix DesignWare ATU enable checking (Jisheng Zhang) - reduce Layerscape dependencies on the bootloader by doing more initialization in the driver (Hou Zhiqiang) - improve Intel VMD performance allowing allocation of more IRQ vectors than present CPUs (Keith Busch) - improve endpoint framework support for initial DMA mask, different BAR sizes, configurable page sizes, MSI, test driver, etc (Kishon Vijay Abraham I, Stan Drozd) - rework CRS support to add periodic messages while we poll during enumeration and after Function-Level Reset and prepare for possible other uses of CRS (Sinan Kaya) - clean up Root Port AER handling by removing unnecessary code and moving error handler methods to struct pcie_port_service_driver (Christoph Hellwig) - clean up error handling paths in various drivers (Bjorn Andersson, Fabio Estevam, Gustavo A. R. Silva, Harunobu Kurokawa, Jeffy Chen, Lorenzo Pieralisi, Sergei Shtylyov) - clean up SR-IOV resource handling by disabling VF decoding before updating the corresponding resource structs (Gavin Shan) - clean up DesignWare-based drivers by unifying quirks to update Class Code and Interrupt Pin and related handling of write-protected registers (Hou Zhiqiang) - clean up by adding empty generic pcibios_align_resource() and pcibios_fixup_bus() and removing empty arch-specific implementations (Palmer Dabbelt) - request exclusive reset control for several drivers to allow cleanup elsewhere (Philipp Zabel) - constify various structures (Arvind Yadav, Bhumika Goyal) - convert from full_name() to %pOF (Rob Herring) - remove unused variables from iProc, HiSi, Altera, Keystone (Shawn Lin) * tag 'pci-v4.14-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (170 commits) PCI: xgene: Clean up whitespace PCI: xgene: Define XGENE_PCI_EXP_CAP and use generic PCI_EXP_RTCTL offset PCI: xgene: Fix platform_get_irq() error handling PCI: xilinx-nwl: Fix platform_get_irq() error handling PCI: rockchip: Fix platform_get_irq() error handling PCI: altera: Fix platform_get_irq() error handling PCI: spear13xx: Fix platform_get_irq() error handling PCI: artpec6: Fix platform_get_irq() error handling PCI: armada8k: Fix platform_get_irq() error handling PCI: dra7xx: Fix platform_get_irq() error handling PCI: exynos: Fix platform_get_irq() error handling PCI: iproc: Clean up whitespace PCI: iproc: Rename PCI_EXP_CAP to IPROC_PCI_EXP_CAP PCI: iproc: Add 500ms delay during device shutdown PCI: Fix typos and whitespace errors PCI: Remove unused "res" variable from pci_resource_io() PCI: Correct kernel-doc of pci_vpd_srdt_size(), pci_vpd_srdt_tag() PCI/AER: Reformat AER register definitions iommu/vt-d: Prevent VMD child devices from being remapping targets x86/PCI: Use is_vmd() rather than relying on the domain number ...
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‎CREDITS‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2090,7 +2090,7 @@ S: Kuala Lumpur, Malaysia
20902090

20912091
N: Mohit Kumar
20922092
D: ST Microelectronics SPEAr13xx PCI host bridge driver
2093-
D: Synopsys Designware PCI host bridge driver
2093+
D: Synopsys DesignWare PCI host bridge driver
20942094

20952095
N: Gabor Kuti
20962096
E: seasons@falcon.sch.bme.hu

‎Documentation/devicetree/bindings/pci/83xx-512x-pci.txt‎

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@@ -1,11 +1,11 @@
11
* Freescale 83xx and 512x PCI bridges
22

3-
Freescale 83xx and 512x SOCs include the same pci bridge core.
3+
Freescale 83xx and 512x SOCs include the same PCI bridge core.
44

55
83xx/512x specific notes:
66
- reg: should contain two address length tuples
7-
The first is for the internal pci bridge registers
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The second is for the pci config space access registers
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The first is for the internal PCI bridge registers
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The second is for the PCI config space access registers
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1010
Example (MPC8313ERDB)
1111
pci0: pci@e0008500 {

‎Documentation/devicetree/bindings/pci/altera-pcie.txt‎

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@@ -7,21 +7,21 @@ Required properties:
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"Txs": TX slave port region
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"Cra": Control register access region
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- interrupt-parent: interrupt source phandle.
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- interrupts: specifies the interrupt source of the parent interrupt controller.
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The format of the interrupt specifier depends on the parent interrupt
12-
controller.
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- interrupts: specifies the interrupt source of the parent interrupt
11+
controller. The format of the interrupt specifier depends
12+
on the parent interrupt controller.
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- device_type: must be "pci"
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- #size-cells: set to <2>
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- #interrupt-cells: set to <1>
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- ranges: describes the translation of addresses for root ports and standard
18-
PCI regions.
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- ranges: describes the translation of addresses for root ports and
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standard PCI regions.
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- interrupt-map-mask and interrupt-map: standard PCI properties to define the
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mapping of the PCIe interface to interrupt numbers.
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2222
Optional properties:
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- msi-parent: Link to the hardware entity that serves as the MSI controller for this PCIe
24-
controller.
23+
- msi-parent: Link to the hardware entity that serves as the MSI controller
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for this PCIe controller.
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- bus-range: PCI bus numbers covered
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2727
Example
@@ -45,5 +45,5 @@ Example
4545
<0 0 0 3 &pcie_0 3>,
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<0 0 0 4 &pcie_0 4>;
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ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
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0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
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0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
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};

‎Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt‎

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@@ -6,7 +6,7 @@ and thus inherits all the common properties defined in designware-pcie.txt.
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Required properties:
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- compatible: "axis,artpec6-pcie", "snps,dw-pcie"
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- reg: base addresses and lengths of the PCIe controller (DBI),
9-
the phy controller, and configuration address space.
9+
the PHY controller, and configuration address space.
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- reg-names: Must include the following entries:
1111
- "dbi"
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- "phy"

‎Documentation/devicetree/bindings/pci/designware-pcie.txt‎

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@@ -1,4 +1,4 @@
1-
* Synopsys Designware PCIe interface
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* Synopsys DesignWare PCIe interface
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33
Required properties:
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- compatible: should contain "snps,dw-pcie" to identify the core.
@@ -17,29 +17,27 @@ RC mode:
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properties to define the mapping of the PCIe interface to interrupt
1818
numbers.
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EP mode:
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- num-ib-windows: number of inbound address translation
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windows
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- num-ob-windows: number of outbound address translation
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windows
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- num-ib-windows: number of inbound address translation windows
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- num-ob-windows: number of outbound address translation windows
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Optional properties:
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- num-lanes: number of lanes to use (this property should be specified unless
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the link is brought already up in BIOS)
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- reset-gpio: gpio pin number of power good signal
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- reset-gpio: GPIO pin number of power good signal
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- "pcie"
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- "pcie_bus"
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RC mode:
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- num-viewport: number of view ports configured in
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hardware. If a platform does not specify it, the driver assumes 2.
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- bus-range: PCI bus numbers covered (it is recommended
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for new devicetrees to specify this property, to keep backwards
39-
compatibility a range of 0x00-0xff is assumed if not present)
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- num-viewport: number of view ports configured in hardware. If a platform
34+
does not specify it, the driver assumes 2.
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- bus-range: PCI bus numbers covered (it is recommended for new devicetrees
36+
to specify this property, to keep backwards compatibility a range of
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0x00-0xff is assumed if not present)
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4039
EP mode:
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- max-functions: maximum number of functions that can be
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configured
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- max-functions: maximum number of functions that can be configured
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Example configuration:
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‎Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt‎

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* Freescale i.MX6 PCIe interface
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3-
This PCIe host controller is based on the Synopsis Designware PCIe IP
3+
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
44
and thus inherits all the common properties defined in designware-pcie.txt.
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66
Required properties:

‎Documentation/devicetree/bindings/pci/hisilicon-pcie.txt‎

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11
HiSilicon Hip05 and Hip06 PCIe host bridge DT description
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HiSilicon PCIe host controller is based on Designware PCI core.
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It shares common functions with PCIe Designware core driver and inherits
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HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core.
4+
It shares common functions with the PCIe DesignWare core driver and inherits
55
common properties defined in
66
Documentation/devicetree/bindings/pci/designware-pci.txt.
77

‎Documentation/devicetree/bindings/pci/kirin-pcie.txt‎

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@@ -1,8 +1,8 @@
11
HiSilicon Kirin SoCs PCIe host DT description
22

3-
Kirin PCIe host controller is based on Designware PCI core.
4-
It shares common functions with PCIe Designware core driver
5-
and inherits common properties defined in
3+
Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
4+
It shares common functions with the PCIe DesignWare core driver and
5+
inherits common properties defined in
66
Documentation/devicetree/bindings/pci/designware-pci.txt.
77

88
Additional properties are described here:
@@ -16,7 +16,7 @@ Required properties
1616
"apb": apb Ctrl register defined by Kirin;
1717
"phy": apb PHY register defined by Kirin;
1818
"config": PCIe configuration space registers.
19-
- reset-gpios: The gpio to generate PCIe perst assert and deassert signal.
19+
- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
2020

2121
Optional properties:
2222

‎Documentation/devicetree/bindings/pci/layerscape-pci.txt‎

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@@ -15,8 +15,10 @@ Required properties:
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- compatible: should contain the platform identifier such as:
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"fsl,ls1021a-pcie", "snps,dw-pcie"
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"fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie"
18+
"fsl,ls2088a-pcie"
19+
"fsl,ls1088a-pcie"
1820
"fsl,ls1046a-pcie"
19-
- reg: base addresses and lengths of the PCIe controller
21+
- reg: base addresses and lengths of the PCIe controller register blocks.
2022
- interrupts: A list of interrupt outputs of the controller. Must contain an
2123
entry for each entry in the interrupt-names property.
2224
- interrupt-names: Must include the following entries:

‎Documentation/devicetree/bindings/pci/mediatek,mt7623-pcie.txt‎

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