diff --git a/README.md b/README.md index 7611474..956d837 100644 --- a/README.md +++ b/README.md @@ -1,106 +1,106 @@ -# Intel Processor Microcode Package for Linux - -## About - -The Intel Processor Microcode Update (MCU) Package provides a mechanism to release updates for security advisories and functional issues, including errata. In addition, MCUs are responsible for starting the SGX enclave (on processors that support the SGX feature), implementing complex behaviors (such as assists), and more. The preferred method to apply MCUs is using the system BIOS. For a subset of Intel's processors, the MCU can also be updated at runtime using the operating system. The Intel Microcode Package shared here contains updates for those processors that support OS loading of MCUs. - -## Why update the microcode? -Updating your microcode can help to mitigate certain potential security vulnerabilities in CPUs as well as address certain functional issues that could, for example, result in unpredictable system behavior such as hangs, crashes, unexpected reboots, data errors, etc. To learn more about applying MCUs to an Intel processor, see [Microcode Update Guidance](https://software.intel.com/security-software-guidance/insights/microcode-update-guidance). - -## Loading microcode updates - -This package is provided for Linux distributors for inclusion in their OS releases. Intel recommends obtaining the latest MCUs using the OS vendor update mechanism. A good starting point is [OS and Software Vendor](https://software.intel.com/security-software-guidance/insights/guidance-system-administrators-mitigate-transient-execution-side-channel-issues). Expert users can update their microcode directly outside the OS vendor mechanism. However, this method is complex and could result in errors if performed incorrectly. Such errors could include but are not limited to system freezes, inability to boot, performance impacts, logical processors loading different updates, and some updates not taking effect. As a result, this method should be attempted by expert users only. - -MCUs are best loaded from the BIOS. Certain MCUs must only be applied from the BIOS. Such MCUs are never packaged in this package since they are not appropriate for OS distribution. An OEM may receive microcode update packages that are a superset of what is contained in this package for inclusion in a BIOS. - -OS vendors may choose to provide an MCU that the kernel can consume for early loading. For example, Linux can apply an MCU very early in the kernel boot sequence. In situations where a BIOS update isn't available, early loading is the next best alternative to updating processor microcode. **Microcode states are reset on a power reset, hence its required that the MCU be loaded every time during boot process.** - -## Recommendation - -Using the initrd method to load an MCU is recommended as this method will load the MCU at the earliest time for the most coverage. Systems that cannot tolerate downtime may use the late-load method to update a running system without a reboot. - -## About Processor Signature, Family, Model, Stepping and Platform ID - -The Processor Signature is a number identifying the model and version of an Intel processor. It can be obtained using the *CPUID instruction*, via the command *lscpu*, or from the content of */proc/cpuinfo*. It's usually presented as 3 fields: Family, Model, and Stepping. - -For example, if a processor returns a value of "0x000906eb" from the *CPUID instruction*: - -| Reserved | Extended Family | Extended Model | Reserved | Processor Type | Family Code | Model Number | Stepping ID | -|:---------|:----------------|:---------------|:---------|:---------------|:------------|:-------------|:------------| -| 31:28 | 27:20 | 19:16 | 15:14 | 13:12 | 11:8 | 7:4 | 3:0 | -| xxxx | 00000000b | 1001b | xx | 00b | 0110b | 1110b | 1011b | - - -The corresponding Linux formatted file name will be "06-9e-0b", where: -- Extended Family + Family = 0x06 -- Extended Model + Model Number = 0x9e -- Stepping ID = 0xb - -A processor may be implemented for multiple platform types. Intel processors have a 3bit Platform ID field in MSR(17H) that specifies the platform type for up to 8 types. An MCU file for a specified processor model may support multiple platforms. The Platform ID(s) supported by an MCU is an 8bit mask where each set bit indicates a platform type that the MCU supports. The Platform ID of a processor can be read in Linux using rdmsr from [msr-tools](https://github.com/intel/msr-tools). - -## Microcode update instructions - -The [intel-ucode](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/tree/main/intel-ucode) directory contains binary MCU files named in the `family-model-stepping` format. This file format is supported by most modern Linux distributions. It's generally located in the /lib/firmware directory and can be updated through the microcode reload interface following the late-load update instructions below. - -### Early-load update -To update early loading initrd, consult your Linux distribution on how to package MCU files for early loading. Some distributions use `update-initramfs` or `dracut`. Use the OS vendors recommended method to help ensure that the MCU file is updated for early loading before attempting the late-load procedure below. - -### Late-load update -To update the intel-ucode package to the system: -1. Ensure the existence of `/sys/devices/system/cpu/microcode/reload` -2. Download the latest microcode firmware
`$ git clone https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files.git` or
`$ wget https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/archive/main.zip` -3. Copy `intel-ucode` directory to `/lib/firmware`, overwriting the files in /lib/firmware/intel-ucode/ -4. Write the reload interface to 1 to reload the microcode files, e.g.
- `$ echo 1 > /sys/devices/system/cpu/microcode/reload`
- Microcode updates will be applied automatically without rebooting the system. -5. Update an existing initramfs so that next time it gets loaded via kernel:
-`$ sudo update-initramfs -u`
-`$ sudo reboot` -6. Verify that the microcode was updated on boot or reloaded by echo command:
-`$ dmesg | grep microcode` or
-`$ cat /proc/cpuinfo | grep microcode | sort | uniq` - -If you are using the OS vendor method to apply an MCU, the above steps may have been done automatically during the update process. - -The [intel-ucode-with-caveats](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/tree/main/intel-ucode-with-caveats) directory contains MCUs that need special handling. The BDX-ML MCU is provided in this directory because it requires special commits in the Linux kernel otherwise updating it might result in unexpected system behavior. OS vendors must ensure that the late loader patches (provided in [linux-kernel-patches](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/tree/main/linux-kernel-patches)) are included in the distribution before packaging the BDX-ML MCU for late-loading. - -The [linux-kernel-patches](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/tree/main/linux-kernel-patches) directory consists of kernel patches that address various issues related to applying MCUs. - -## Notes - -* You can only update to a higher MCU version (downgrade is not possible with the provided instructions) -* To calculate Family-Model-Stepping, use Linux command:
-`$ printf "%x\n" ` -* There are multiple ways to check the MCU version number BEFORE update. After cloning this Intel Microcode update repo , run the following: - - `$ iucode_tool -l intel-ucode | grep -wF sig` ([iucode_tool](https://gitlab.com/iucode-tool/iucode-tool/-/wikis/home) package is required) - - `$ od -t x4 ` will read the first 16 bytes of the microcode binary header specified in \. The third block is the microcode version. For example: -`$ od -t x4 06-55-04`
-`0000000 00000001 *02000065* 09052019 00050654` - -## License - -See the [license](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/blob/main/license) file for details. - -## Security Policy - -See the [security.md](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/blob/main/security.md) file for details. - -## Release Note - -See the [releasenote.md](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/blob/main/releasenote.md) file for details. - -## Disclaimers - -Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software, or service activation. Performance varies depending on system configuration. Check with your system manufacturer or retailer or learn more at [www.intel.com](https://www.intel.com). - -No product or component can be absolutely secure. - -All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. - -The products and services described may contain defects or errors known as errata which may cause deviations from published specifications. Current characterized errata are available on request. - -Intel provides these materials as-is, with no express or implied warranties. - -© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. - +# Intel Processor Microcode Package for Linux + +## About + +The Intel Processor Microcode Update (MCU) Package provides a mechanism to release updates for security advisories and functional issues, including errata. In addition, MCUs are responsible for starting the SGX enclave (on processors that support the SGX feature), implementing complex behaviors (such as assists), and more. The preferred method to apply MCUs is using the system BIOS. For a subset of Intel's processors, the MCU can also be updated at runtime using the operating system. The Intel Microcode Package shared here contains updates for those processors that support OS loading of MCUs. + +## Why update the microcode? +Updating your microcode can help to mitigate certain potential security vulnerabilities in CPUs as well as address certain functional issues that could, for example, result in unpredictable system behavior such as hangs, crashes, unexpected reboots, data errors, etc. To learn more about applying MCUs to an Intel processor, see [Microcode Update Guidance](https://software.intel.com/security-software-guidance/insights/microcode-update-guidance). + +## Loading microcode updates + +This package is provided for Linux distributors for inclusion in their OS releases. Intel recommends obtaining the latest MCUs using the OS vendor update mechanism. A good starting point is [OS and Software Vendor](https://software.intel.com/security-software-guidance/insights/guidance-system-administrators-mitigate-transient-execution-side-channel-issues). Expert users can update their microcode directly outside the OS vendor mechanism. However, this method is complex and could result in errors if performed incorrectly. Such errors could include but are not limited to system freezes, inability to boot, performance impacts, logical processors loading different updates, and some updates not taking effect. As a result, this method should be attempted by expert users only. + +MCUs are best loaded from the BIOS. Certain MCUs must only be applied from the BIOS. Such MCUs are never packaged in this package since they are not appropriate for OS distribution. An OEM may receive microcode update packages that are a superset of what is contained in this package for inclusion in a BIOS. + +OS vendors may choose to provide an MCU that the kernel can consume for early loading. For example, Linux can apply an MCU very early in the kernel boot sequence. In situations where a BIOS update isn't available, early loading is the next best alternative to updating processor microcode. **Microcode states are reset on a power reset, hence its required that the MCU be loaded every time during boot process.** + +## Recommendation + +Using the initrd method to load an MCU is recommended as this method will load the MCU at the earliest time for the most coverage. Systems that cannot tolerate downtime may use the late-load method to update a running system without a reboot. + +## About Processor Signature, Family, Model, Stepping and Platform ID + +The Processor Signature is a number identifying the model and version of an Intel processor. It can be obtained using the *CPUID instruction*, via the command *lscpu*, or from the content of */proc/cpuinfo*. It's usually presented as 3 fields: Family, Model, and Stepping. + +For example, if a processor returns a value of "0x000906eb" from the *CPUID instruction*: + +| Reserved | Extended Family | Extended Model | Reserved | Processor Type | Family Code | Model Number | Stepping ID | +|:---------|:----------------|:---------------|:---------|:---------------|:------------|:-------------|:------------| +| 31:28 | 27:20 | 19:16 | 15:14 | 13:12 | 11:8 | 7:4 | 3:0 | +| xxxx | 00000000b | 1001b | xx | 00b | 0110b | 1110b | 1011b | + + +The corresponding Linux formatted file name will be "06-9e-0b", where: +- Extended Family + Family = 0x06 +- Extended Model + Model Number = 0x9e +- Stepping ID = 0xb + +A processor may be implemented for multiple platform types. Intel processors have a 3bit Platform ID field in MSR(17H) that specifies the platform type for up to 8 types. An MCU file for a specified processor model may support multiple platforms. The Platform ID(s) supported by an MCU is an 8bit mask where each set bit indicates a platform type that the MCU supports. The Platform ID of a processor can be read in Linux using rdmsr from [msr-tools](https://github.com/intel/msr-tools). + +## Microcode update instructions + +The [intel-ucode](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/tree/main/intel-ucode) directory contains binary MCU files named in the `family-model-stepping` format. This file format is supported by most modern Linux distributions. It's generally located in the /lib/firmware directory and can be updated through the microcode reload interface following the late-load update instructions below. + +### Early-load update +To update early loading initrd, consult your Linux distribution on how to package MCU files for early loading. Some distributions use `update-initramfs` or `dracut`. Use the OS vendors recommended method to help ensure that the MCU file is updated for early loading before attempting the late-load procedure below. + +### Late-load update +To update the intel-ucode package to the system: +1. Ensure the existence of `/sys/devices/system/cpu/microcode/reload` +2. Download the latest microcode firmware
`$ git clone https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files.git` or
`$ wget https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/archive/main.zip` +3. Copy `intel-ucode` directory to `/lib/firmware`, overwriting the files in /lib/firmware/intel-ucode/ +4. Write the reload interface to 1 to reload the microcode files, e.g.
+ `$ echo 1 > /sys/devices/system/cpu/microcode/reload`
+ Microcode updates will be applied automatically without rebooting the system. +5. Update an existing initramfs so that next time it gets loaded via kernel:
+`$ sudo update-initramfs -u`
+`$ sudo reboot` +6. Verify that the microcode was updated on boot or reloaded by echo command:
+`$ dmesg | grep microcode` or
+`$ cat /proc/cpuinfo | grep microcode | sort | uniq` + +If you are using the OS vendor method to apply an MCU, the above steps may have been done automatically during the update process. + +The [intel-ucode-with-caveats](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/tree/main/intel-ucode-with-caveats) directory contains MCUs that need special handling. The BDX-ML MCU is provided in this directory because it requires special commits in the Linux kernel otherwise updating it might result in unexpected system behavior. OS vendors must ensure that the late loader patches (provided in [linux-kernel-patches](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/tree/main/linux-kernel-patches)) are included in the distribution before packaging the BDX-ML MCU for late-loading. + +The [linux-kernel-patches](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/tree/main/linux-kernel-patches) directory consists of kernel patches that address various issues related to applying MCUs. + +## Notes + +* You can only update to a higher MCU version (downgrade is not possible with the provided instructions) +* To calculate Family-Model-Stepping, use Linux command:
+`$ printf "%x\n" ` +* There are multiple ways to check the MCU version number BEFORE update. After cloning this Intel Microcode update repo , run the following: + - `$ iucode_tool -l intel-ucode | grep -wF sig` ([iucode_tool](https://gitlab.com/iucode-tool/iucode-tool/-/wikis/home) package is required) + - `$ od -t x4 ` will read the first 16 bytes of the microcode binary header specified in \. The third block is the microcode version. For example: +`$ od -t x4 06-55-04`
+`0000000 00000001 *02000065* 09052019 00050654` + +## License + +See the [license](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/blob/main/license) file for details. + +## Security Policy + +See the [security.md](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/blob/main/security.md) file for details. + +## Release Note + +See the [releasenote.md](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/blob/main/releasenote.md) file for details. + +## Disclaimers + +Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software, or service activation. Performance varies depending on system configuration. Check with your system manufacturer or retailer or learn more at [www.intel.com](https://www.intel.com). + +No product or component can be absolutely secure. + +All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. + +The products and services described may contain defects or errors known as errata which may cause deviations from published specifications. Current characterized errata are available on request. + +Intel provides these materials as-is, with no express or implied warranties. + +© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. + *Other names and brands may be claimed as the property of others. \ No newline at end of file diff --git a/intel-ucode/06-55-06 b/intel-ucode/06-55-06 deleted file mode 100644 index e7365a0..0000000 Binary files a/intel-ucode/06-55-06 and /dev/null differ diff --git a/intel-ucode/06-55-07 b/intel-ucode/06-55-07 index eb51392..4412b80 100644 Binary files a/intel-ucode/06-55-07 and b/intel-ucode/06-55-07 differ diff --git a/intel-ucode/06-55-0b b/intel-ucode/06-55-0b index b59300e..150bede 100644 Binary files a/intel-ucode/06-55-0b and b/intel-ucode/06-55-0b differ diff --git a/intel-ucode/06-6a-06 b/intel-ucode/06-6a-06 index d4a366f..264f59b 100644 Binary files a/intel-ucode/06-6a-06 and b/intel-ucode/06-6a-06 differ diff --git a/intel-ucode/06-6c-01 b/intel-ucode/06-6c-01 index 1676c98..057950b 100644 Binary files a/intel-ucode/06-6c-01 and b/intel-ucode/06-6c-01 differ diff --git a/intel-ucode/06-7a-08 b/intel-ucode/06-7a-08 index 06a4a8a..25ed1f0 100644 Binary files a/intel-ucode/06-7a-08 and b/intel-ucode/06-7a-08 differ diff --git a/intel-ucode/06-7e-05 b/intel-ucode/06-7e-05 index 419b489..eb4f618 100644 Binary files a/intel-ucode/06-7e-05 and b/intel-ucode/06-7e-05 differ diff --git a/intel-ucode/06-8c-01 b/intel-ucode/06-8c-01 index 8fc08a2..6cbf881 100644 Binary files a/intel-ucode/06-8c-01 and b/intel-ucode/06-8c-01 differ diff --git a/intel-ucode/06-8c-02 b/intel-ucode/06-8c-02 index b371e6a..91ca264 100644 Binary files a/intel-ucode/06-8c-02 and b/intel-ucode/06-8c-02 differ diff --git a/intel-ucode/06-8d-01 b/intel-ucode/06-8d-01 index 4b4bf88..531c30e 100644 Binary files a/intel-ucode/06-8d-01 and b/intel-ucode/06-8d-01 differ diff --git a/intel-ucode/06-8e-0c b/intel-ucode/06-8e-0c index 6cf5f12..45a7c81 100644 Binary files a/intel-ucode/06-8e-0c and b/intel-ucode/06-8e-0c differ diff --git a/intel-ucode/06-8f-07 b/intel-ucode/06-8f-07 index ba8c8fd..b2bf829 100644 Binary files a/intel-ucode/06-8f-07 and b/intel-ucode/06-8f-07 differ diff --git a/intel-ucode/06-8f-08 b/intel-ucode/06-8f-08 index 7bc6a8f..6869e8e 100644 Binary files a/intel-ucode/06-8f-08 and b/intel-ucode/06-8f-08 differ diff --git a/intel-ucode/06-97-02 b/intel-ucode/06-97-02 index 600a5ee..485396c 100644 Binary files a/intel-ucode/06-97-02 and b/intel-ucode/06-97-02 differ diff --git a/intel-ucode/06-97-05 b/intel-ucode/06-97-05 index 600a5ee..485396c 100644 Binary files a/intel-ucode/06-97-05 and b/intel-ucode/06-97-05 differ diff --git a/intel-ucode/06-9a-03 b/intel-ucode/06-9a-03 index fe20c2c..7b9a998 100644 Binary files a/intel-ucode/06-9a-03 and b/intel-ucode/06-9a-03 differ diff --git a/intel-ucode/06-9a-04 b/intel-ucode/06-9a-04 index 0268fc4..a6cb812 100644 Binary files a/intel-ucode/06-9a-04 and b/intel-ucode/06-9a-04 differ diff --git a/intel-ucode/06-9e-0d b/intel-ucode/06-9e-0d index 949389d..e4c29b5 100644 Binary files a/intel-ucode/06-9e-0d and b/intel-ucode/06-9e-0d differ diff --git a/intel-ucode/06-a5-02 b/intel-ucode/06-a5-02 index a6fdab7..bfd70de 100644 Binary files a/intel-ucode/06-a5-02 and b/intel-ucode/06-a5-02 differ diff --git a/intel-ucode/06-a5-03 b/intel-ucode/06-a5-03 index aadd8c9..674e83b 100644 Binary files a/intel-ucode/06-a5-03 and b/intel-ucode/06-a5-03 differ diff --git a/intel-ucode/06-a5-05 b/intel-ucode/06-a5-05 index 1ac94fb..d7761aa 100644 Binary files a/intel-ucode/06-a5-05 and b/intel-ucode/06-a5-05 differ diff --git a/intel-ucode/06-a6-00 b/intel-ucode/06-a6-00 index 82b2316..a517682 100644 Binary files a/intel-ucode/06-a6-00 and b/intel-ucode/06-a6-00 differ diff --git a/intel-ucode/06-a6-01 b/intel-ucode/06-a6-01 index fbd5a15..a2c2aef 100644 Binary files a/intel-ucode/06-a6-01 and b/intel-ucode/06-a6-01 differ diff --git a/intel-ucode/06-a7-01 b/intel-ucode/06-a7-01 index 32eeaac..07c0f41 100644 Binary files a/intel-ucode/06-a7-01 and b/intel-ucode/06-a7-01 differ diff --git a/intel-ucode/06-aa-04 b/intel-ucode/06-aa-04 index 267b835..dd66342 100644 Binary files a/intel-ucode/06-aa-04 and b/intel-ucode/06-aa-04 differ diff --git a/intel-ucode/06-ad-01 b/intel-ucode/06-ad-01 new file mode 100644 index 0000000..e85c839 Binary files /dev/null and b/intel-ucode/06-ad-01 differ diff --git a/intel-ucode/06-ae-01 b/intel-ucode/06-ae-01 new file mode 100644 index 0000000..dc0a8bd Binary files /dev/null and b/intel-ucode/06-ae-01 differ diff --git a/intel-ucode/06-af-03 b/intel-ucode/06-af-03 index 9629bae..95d0fe2 100644 Binary files a/intel-ucode/06-af-03 and b/intel-ucode/06-af-03 differ diff --git a/intel-ucode/06-b5-00 b/intel-ucode/06-b5-00 new file mode 100644 index 0000000..fad2ff3 Binary files /dev/null and b/intel-ucode/06-b5-00 differ diff --git a/intel-ucode/06-b7-01 b/intel-ucode/06-b7-01 index a0b16ee..93ded41 100644 Binary files a/intel-ucode/06-b7-01 and b/intel-ucode/06-b7-01 differ diff --git a/intel-ucode/06-b7-04 b/intel-ucode/06-b7-04 new file mode 100644 index 0000000..93ded41 Binary files /dev/null and b/intel-ucode/06-b7-04 differ diff --git a/intel-ucode/06-ba-02 b/intel-ucode/06-ba-02 index 7359151..7034728 100644 Binary files a/intel-ucode/06-ba-02 and b/intel-ucode/06-ba-02 differ diff --git a/intel-ucode/06-ba-03 b/intel-ucode/06-ba-03 index 7359151..7034728 100644 Binary files a/intel-ucode/06-ba-03 and b/intel-ucode/06-ba-03 differ diff --git a/intel-ucode/06-bd-01 b/intel-ucode/06-bd-01 new file mode 100644 index 0000000..6672b19 Binary files /dev/null and b/intel-ucode/06-bd-01 differ diff --git a/intel-ucode/06-be-00 b/intel-ucode/06-be-00 index 2a61c4a..fb949dc 100644 Binary files a/intel-ucode/06-be-00 and b/intel-ucode/06-be-00 differ diff --git a/intel-ucode/06-bf-02 b/intel-ucode/06-bf-02 index 600a5ee..485396c 100644 Binary files a/intel-ucode/06-bf-02 and b/intel-ucode/06-bf-02 differ diff --git a/intel-ucode/06-bf-05 b/intel-ucode/06-bf-05 index 600a5ee..485396c 100644 Binary files a/intel-ucode/06-bf-05 and b/intel-ucode/06-bf-05 differ diff --git a/intel-ucode/06-c5-02 b/intel-ucode/06-c5-02 new file mode 100644 index 0000000..44f95f7 Binary files /dev/null and b/intel-ucode/06-c5-02 differ diff --git a/intel-ucode/06-c6-02 b/intel-ucode/06-c6-02 new file mode 100644 index 0000000..44f95f7 Binary files /dev/null and b/intel-ucode/06-c6-02 differ diff --git a/intel-ucode/06-cc-02 b/intel-ucode/06-cc-02 new file mode 100644 index 0000000..5ed9dad Binary files /dev/null and b/intel-ucode/06-cc-02 differ diff --git a/intel-ucode/06-cc-03 b/intel-ucode/06-cc-03 new file mode 100644 index 0000000..5ed9dad Binary files /dev/null and b/intel-ucode/06-cc-03 differ diff --git a/intel-ucode/06-cf-01 b/intel-ucode/06-cf-01 deleted file mode 100644 index 937187a..0000000 Binary files a/intel-ucode/06-cf-01 and /dev/null differ diff --git a/intel-ucode/06-cf-02 b/intel-ucode/06-cf-02 index 937187a..becec6b 100644 Binary files a/intel-ucode/06-cf-02 and b/intel-ucode/06-cf-02 differ diff --git a/intel-ucode/06-d5-01 b/intel-ucode/06-d5-01 new file mode 100644 index 0000000..58c4ee6 Binary files /dev/null and b/intel-ucode/06-d5-01 differ diff --git a/intel-ucode/06-d7-00 b/intel-ucode/06-d7-00 new file mode 100644 index 0000000..93ded41 Binary files /dev/null and b/intel-ucode/06-d7-00 differ diff --git a/releasenote.md b/releasenote.md index 300576b..c105ca7 100644 --- a/releasenote.md +++ b/releasenote.md @@ -1,3 +1,384 @@ +# Release Notes +## [microcode-20260812](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20260812) + +### Purpose + +- Removed MTL/06-aa-04/c0 due to functional issues observed when loading the MCU in some platforms. + + +# Release Notes +## [microcode-20260811](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20260811) + +### Purpose +- Security updates for [INTEL-SA-01379](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01379.html) +- Security updates for [INTEL-SA-01404](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01404.html) +- Security updates for [INTEL-SA-01423](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01423.html) +- Security updates for [INTEL-SA-01428](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01428.html) +- Security updates for [INTEL-SA-01435](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01435.html) +- Security updates for [INTEL-SA-01441](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01441.html) +- Security updates for [INTEL-SA-01442](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01442.html) +- Security updates for [INTEL-SA-01443](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01443.html) +- Update for functional issues. Refer to [10th Gen Intel® Core™ Processor Families Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/341079) for details. +- Update for functional issues. Refer to [13th/14th Gen Intel® Core™ Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/740518) for details. +- Update for functional issues. Refer to [3rd Generation Intel® Xeon® Processor Scalable Family Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/637780) for details. +- Update for functional issues. Refer to [4th Gen Intel® Xeon® Scalable Processors Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/772415) for details. +- Update for functional issues. Refer to [5th Gen Intel® Xeon® Scalable Processors Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/793902) for details. +- Update for functional issues. Refer to Intel ®Core Series 2 Processors with P-cores for details. +- Update for functional issues. Refer to [Intel® Core™ Processors (Series 3)](https://cdrdv2.intel.com/v1/dl/getContent/914196) for details. +- Update for functional issues. Refer to [Intel® Core™ Ultra 200 V Series Processor](https://cdrdv2.intel.com/v1/dl/getContent/827538) for details. +- Update for functional issues. Refer to [Intel® Core™ Ultra Processor (Series 2)](https://cdrdv2.intel.com/v1/dl/getContent/834774) for details. +- Update for functional issues. Refer to [Intel® Core™ Ultra Processor](https://cdrdv2.intel.com/v1/dl/getContent/792254) for details. +- Update for functional issues. Refer to [Intel® Core™ Ultra Processors (Series 3)](https://cdrdv2.intel.com/v1/dl/getContent/869992) for details. +- Update for functional issues. Refer to [Intel® Xeon® 6700 Series Processors with E-cores](https://cdrdv2.intel.com/v1/dl/getContent/820922) for details. +- Update for functional issues. Refer to [Intel® Xeon® 6700P-B/6500P-B-Series SoC with P-Cores](https://cdrdv2.intel.com/v1/dl/getContent/843306) for details. +- Update for functional issues. Refer to [Intel® Xeon® 6900/6700/6500 Series Processors with P-cores](https://cdrdv2.intel.com/v1/dl/getContent/835486) for details. +- Update for functional issues. Refer to [Intel® Xeon® D-2700 Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/714071) for details. +- Update for functional issues. Refer to [Intel® Xeon® E-2300 Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/709192) for details. + +### New Platforms + +| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products +|:---------------|:---------|:------------|:---------|:---------|:--------- +| BTL-S12P | A0 | 06-d7-00/36 | | 00000137 | Intel Core Series 2 Processors with P-cores +| BTL-S816 | B0 | 06-b7-04/36 | | 00000137 | Intel Core Series 2 Processors with P-cores +| WCL | A1 | 06-d5-01/c0 | | 0000000c | Intel Core Processors (Series 3) + + +### Updated Platforms + +| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products +|:---------------|:---------|:------------|:---------|:---------|:--------- +| ARL-H | A1 | 06-c5-02/82 | 00000121 | 00000122 | Core Ultra Processor (Series 2) +| ARL-S/HX (8P) | B0 | 06-c6-02/82 | 00000121 | 00000122 | Core Ultra Processor (Series 2) +| ARL-U | A0 | 06-b5-00/80 | 0000000d | 0000000e | Core Ultra Processor (Series 2) +| EMR-SP | A1 | 06-cf-02/87 | 210002e0 | 210002f4 | Xeon Scalable Gen5 +| GNR-AP/SP | Bx/Hx/Lx | 06-ad-01/95 | 01000423 | 01000434 | Xeon 6900/6700/6500 Series Processors with P-Cores +| GNR-D | B0/B1 | 06-ae-01/97 | 01000307 | 01000309 | Xeon 6700P-B/6500P-B Series SoC with P-Cores +| GNR-SP R1S | Bx/Hx/Lx | 06-ad-01/20 | 0a000142 | 0a000151 | Xeon 6700/6500-Series Processors with P-Cores +| ICL-D | B0 | 06-6c-01/10 | 010002f1 | 01000301 | Xeon D-17xx, D-27xx +| ICL-U/Y | D1 | 06-7e-05/80 | 000000cc | 000000ce | Core Gen10 Mobile +| ICX-SP | Dx/M1 | 06-6a-06/87 | 0d000421 | 0d000433 | Xeon Scalable Gen3 +| LNL | B0 | 06-bd-01/80 | 00000126 | 00000128 | Core Ultra 200 V Series Processor +| MTL | C0 | 06-aa-04/e6 | 00000028 | 0000002a | Core Ultra Processor +| PTL-404/H204 | A1 | 06-cc-03/94 | 0000011b | 0000011c | Intel Core Ultra processor (Series 3) +| PTL-H484/PTL-H12Xe | B0/A0| 06-cc-02/94 | 0000011b | 0000011c | Intel Core Ultra processor (Series 3) +| RKL-S | B0 | 06-a7-01/02 | 00000065 | 00000066 | Core Gen11 +| RPL-E/HX/S | B0 | 06-b7-01/36 | 00000133 | 00000137 | Core Gen13/Gen14 +| SPR-HBM | Bx | 06-8f-08/10 | 2c000421 | 2c000435 | Xeon Max +| SPR-SP | E4/S2 | 06-8f-07/87 | 2b000670 | 2b000685 | Xeon Scalable Gen4 +| SPR-SP | E5/S3 | 06-8f-08/87 | 2b000670 | 2b000685 | Xeon Scalable Gen4 +| SRF-AP/SP | C0 | 06-af-03/01 | 030003a3 | 030003b2 | Xeon 6900/6700-Series Processors with E-Cores + + +# Release Notes +## [microcode-20260512](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20260512) + +### Purpose + +- Security updates for [INTEL-SA-01420](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01420.html) +- Update for functional issues. Refer to [4th Gen Intel® Xeon® Scalable Processors Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/772415) for details. +- Update for functional issues. Refer to [5th Gen Intel® Xeon® Scalable Processors Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/793902) for details. +- Update for functional issues. Refer to [Intel® Core™ Ultra 200 V Series Processor](https://cdrdv2.intel.com/v1/dl/getContent/827538) for details. +- Update for functional issues. Refer to [Intel® Core™ Ultra Processors (Series 2)](https://cdrdv2.intel.com/v1/dl/getContent/834774) for details. +- Update for functional issues. Refer to [Intel® Core™ Ultra Processors (Series 3)](https://cdrdv2.intel.com/v1/dl/getContent/869992) for details. +- Update for functional issues. Refer to [Intel® Xeon® 6700 Series Processors with E-cores](https://cdrdv2.intel.com/v1/dl/getContent/820922) for details. +- Update for functional issues. Refer to [Intel® Xeon® 6900/6700/6500 Series Processors with P-cores](https://cdrdv2.intel.com/v1/dl/getContent/835486) for details. +- Update for functional issues. Refer to [Intel® Xeon® 6700P-B/6500P-B-Series SoC with P-Cores](https://cdrdv2.intel.com/v1/dl/getContent/843306) for details. + +### New Platforms + +| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products +|:---------------|:---------|:------------|:---------|:---------|:--------- +| PTL 404 | A1 | 06-cc-03/90 | | 0000011b | Intel Core Ultra Processor (Series 3) +| PTL-H 484/12Xe | A0/B0 | 06-cc-02/90 | | 0000011b | Intel Core Ultra Processor (Series 3) + +### Updated Platforms + +| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products +|:---------------|:---------|:------------|:---------|:---------|:--------- +| ARL-H | A1 | 06-c5-02/82 | 0000011b | 00000121 | Core Ultra Processor (Series 2) +| ARL-S/HX (8P) | B0 | 06-c6-02/82 | 0000011b | 00000121 | Core Ultra Processor (Series 2) +| EMR-SP | A1 | 06-cf-02/87 | 210002d3 | 210002e0 | Xeon Scalable Gen5 +| GNR-AP/SP | Bx/Hx/Lx | 06-ad-01/95 | 01000405 | 01000423 | Xeon 6900/6700/6500 Series Processors with P-Cores +| GNR-D | B0/B1 | 06-ae-01/97 | 01000303 | 01000307 | Xeon 6700P-B/6500P-B Series SoC with P-Cores +| GNR-SP R1S | Bx/Hx/Lx | 06-ad-01/20 | 0a000133 | 0a000142 | Xeon 6700/6500-Series Processors with P-Cores +| LNL | B0 | 06-bd-01/80 | 00000125 | 00000126 | Core Ultra 200 V Series Processor +| SPR-SP | E4/S2 | 06-8f-07/87 | 2b000661 | 2b000670 | Xeon Scalable Gen4 +| SPR-SP | E5/S3 | 06-8f-08/87 | 2b000661 | 2b000670 | Xeon Scalable Gen4 +| SRF-AP/SP | C0 | 06-af-03/01 | 03000382 | 030003a3 | Xeon 6900/6700-Series Processors with E-Cores + + +# Release Notes +## [microcode-20260227](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20260227) + +### Purpose +- Update for functional issues. Refer to [Intel® Xeon® 6700P-B/6500P-B-Series SoC with P-Cores](https://cdrdv2.intel.com/v1/dl/getContent/843306/view?wapkw=intel%20xeon%206700P-B) for details. + + +### Updated Platforms + +| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products +|:---------------|:---------|:------------|:---------|:---------|:--------- +| GNR-D | B0/B1 | 06-ae-01/97 | 010002f3 | 01000303 | Xeon 6700P-B/6500P-B Series SoC with P-Cores + + +# Release Notes +## [microcode-20260210](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20260210) + +### Purpose +- Updated security updates for INTEL-SA-01083 originally published on Aug 13, 2024 [INTEL-SA-01083](https://www.intel.com/content/www/us/en/security-center/advisory/INTEL-SA-01083.html) +- Security updates for [INTEL-SA-01396](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01396.html) +- Update for functional issues. Refer to [10th Gen Intel® Core™ Processor Families Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/341079) for details. +- Update for functional issues. Refer to [11th Gen Intel® Core™ Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/631123) for details. +- Update for functional issues. Refer to [12th Generation Intel® Core™ Processor Family](https://cdrdv2.intel.com/v1/dl/getContent/682436) for details. +- Update for functional issues. Refer to [13th Generation Intel® Core™ Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/740518) for details. +- Update for functional issues. Refer to [13th/14th Gen Intel® Core™ Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/740518) for details. +- Update for functional issues. Refer to [3rd Generation Intel® Xeon® Processor Scalable Family Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/637780) for details. +- Update for functional issues. Refer to [4th Gen Intel® Xeon® Scalable Processors Specification Update ](https://cdrdv2.intel.com/v1/dl/getContent/772415) for details. +- Update for functional issues. Refer to [5th Gen Intel® Xeon® Scalable Processors Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/793902) for details. +- Update for functional issues. Refer to [Intel® Core™ Ultra Processor ](https://cdrdv2.intel.com/v1/dl/getContent/792254) for details. +- Update for functional issues. Refer to [Intel® Core™ Ultra Processor (Series 2)](https://cdrdv2.intel.com/v1/dl/getContent/834774?explicitVersion=true?) for details. +- Update for functional issues. Refer to [Intel® Processors and Intel® Core™ i3 N-Series](https://cdrdv2.intel.com/v1/dl/getContent/764616) for details. +- Update for functional issues. Refer to [Intel® Xeon® 6900/6700/6500 Series Processors with P-cores](https://cdrdv2.intel.com/v1/dl/getContent/835486) for details. +- Update for functional issues. Refer to [Intel® Xeon® D-2700 Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/714071) for details. +- Update for functional issues. Refer to [Intel® Xeon® E-2300 Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/709192) for details. +- Update for functional issues. Refer to [Intel® Xeon® 6700P-B/6500P-B-Series SoC with P-Cores](https://cdrdv2.intel.com/v1/dl/getContent/843306/view?wapkw=intel%20xeon%206700P-B) for details. + + +### New Platforms + +| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products +|:---------------|:---------|:------------|:---------|:---------|:--------- + + +### Updated Platforms + +| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products +|:---------------|:---------|:------------|:---------|:---------|:--------- +| ADL | C0 | 06-97-02/07 | 0000003d | 0000003e | Core Gen12 +| ADL | H0 | 06-97-05/07 | 0000003d | 0000003e | Core Gen12 +| ADL | L0 | 06-9a-03/80 | 0000043a | 0000043b | Core Gen12 +| ADL | R0 | 06-9a-04/80 | 0000043a | 0000043b | Core Gen12 +| ADL-N | N0 | 06-be-00/19 | 0000001e | 00000021 | Core i3-N305/N300, N50/N97/N100/N200, Atom x7211E/x7213E/x7425E +| ARL-H | A1 | 06-c5-02/82 | 0000011a | 0000011b | Core Ultra Processor (Series 2) +| ARL-S/HX (8P) | B0 | 06-c6-02/82 | 0000011a | 0000011b | Core Ultra Processor (Series 2) +| ARL-U | A0 | 06-b5-00/80 | 0000000a | 0000000d | Core Ultra Processor (Series 2) +| AZB | A0/R0 | 06-9a-04/40 | 0000000b | 0000000c | Atom C1100 +| EMR-SP | A1 | 06-cf-02/87 | 210002c0 | 210002d3 | Xeon Scalable Gen5 +| GNR-AP/SP | Bx/Hx/Lx | 06-ad-01/95 | 010003f0 | 01000405 | Xeon 6900/6700/6500 Series Processors with P-Cores +| GNR-D | B0/B1 | 06-ae-01/97 | 01000273 | 010002f3 | Xeon 6700P-B/6500P-B Series SoC with P-Cores +| GNR-SP R1S | Bx/Hx/Lx | 06-ad-01/20 | 0a000124 | 0a000133 | Xeon 6700/6500-Series Processors with P-Cores +| ICL-D | B0 | 06-6c-01/10 | 010002e0 | 010002f1 | Xeon D-17xx, D-27xx +| ICL-U/Y | D1 | 06-7e-05/80 | 000000ca | 000000cc | Core Gen10 Mobile +| ICX-SP | Dx/M1 | 06-6a-06/87 | 0d000410 | 0d000421 | Xeon Scalable Gen3 +| MTL | C0 | 06-aa-04/e6 | 00000025 | 00000028 | Core™ Ultra Processor +| RKL-S | B0 | 06-a7-01/02 | 00000064 | 00000065 | Core Gen11 +| RPL-E/HX/S | B0 | 06-b7-01/32 | 00000132 | 00000133 | Core Gen13/Gen14 +| RPL-H/P/PX 6+8 | J0 | 06-ba-02/e0 | 00006133 | 00006134 | Core Gen13 +| RPL-HX/S | C0 | 06-bf-02/07 | 0000003d | 0000003e | Core Gen13/Gen14 +| RPL-S | H0 | 06-bf-05/07 | 0000003d | 0000003e | Core Gen13/Gen14 +| RPL-U 2+8 | Q0 | 06-ba-03/e0 | 00006133 | 00006134 | Core Gen13 +| SPR-HBM | Bx | 06-8f-08/10 | 2c000410 | 2c000421 | Xeon Max +| SPR-SP | E4/S2 | 06-8f-07/87 | 2b000650 | 2b000661 | Xeon Scalable Gen4 +| SPR-SP | E5/S3 | 06-8f-08/87 | 2b000650 | 2b000661 | Xeon Scalable Gen4 +| TGL | B0/B1 | 06-8c-01/80 | 000000bc | 000000be | Core Gen11 Mobile +| TGL-H | R0 | 06-8d-01/c2 | 00000056 | 00000058 | Core Gen11 Mobile +| TGL-R | C0 | 06-8c-02/c2 | 0000003c | 0000003e | Core Gen11 Mobile +| TWL | N0 | 06-be-00/19 | 0000001e | 00000021 | Core i3-N305/N300, N50/N97/N100/N200, Atom x7211E/x7213E/x7425E + + +# Release Notes +## [microcode-20251111](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20251111) + +### Purpose +- Update for functional issues. Refer to [12th Generation Intel® Core™ Processor Family](https://cdrdv2.intel.com/v1/dl/getContent/682436) for details. +- Update for functional issues. Refer to [13th/14th Gen Intel® Core™ Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/740518) for details. +- Update for functional issues. Refer to [4th Gen Intel® Xeon® Scalable Processors Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/772415) for details. +- Update for functional issues. Refer to [5th Gen Intel® Xeon® Scalable Processors Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/793902) for details. +- Update for functional issues. Refer to [Intel® Core™ Ultra 200 V Series Processor ](https://cdrdv2.intel.com/v1/dl/getContent/827538) for details. +- Update for functional issues. Refer to [Intel® Core™ Ultra Processor (Series 2)](https://cdrdv2.intel.com/v1/dl/getContent/834774) for details. +- Update for functional issues. Refer to [Intel® Processors and Intel® Core™ i3 N-Series](https://cdrdv2.intel.com/v1/dl/getContent/764616) for details. +- Update for functional issues. Refer to [Intel® Xeon® 6700 Series Processors with E-cores](https://cdrdv2.intel.com/v1/dl/getContent/820922) for details. +- Update for functional issues. Refer to [Intel® Xeon® 6900/6700/6500 Series Processors with P-cores](https://cdrdv2.intel.com/v1/dl/getContent/835486) for details. +- Update for functional issues. Refer to [Intel® Xeon® 6700P-B/6500P-B-Series SoC with P-Cores](https://cdrdv2.intel.com/v1/dl/getContent/843306) for details. + +### New Platforms + +| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products +|:---------------|:---------|:------------|:---------|:---------|:--------- +| GNR-D | B0/B1 | 06-ae-01/97 | | 01000273 | Xeon 6700P-B/6500P-B Series SoC with P-Cores + +### Updated Platforms + +| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products +|:---------------|:---------|:------------|:---------|:---------|:--------- +| ADL | C0 | 06-97-02/07 | 0000003a | 0000003d | Core Gen12 +| ADL | H0 | 06-97-05/07 | 0000003a | 0000003d | Core Gen12 +| ADL | L0 | 06-9a-03/80 | 00000437 | 0000043a | Core Gen12 +| ADL | R0 | 06-9a-04/80 | 00000437 | 0000043a | Core Gen12 +| ADL-N | N0 | 06-be-00/19 | 0000001d | 0000001e | Core i3-N305/N300, N50/N97/N100/N200, Atom x7211E/x7213E/x7425E +| ARL-H | A1 | 06-c5-02/82 | 00000119 | 0000011a | Core Ultra Processor (Series 2) +| ARL-S/HX (8P) | B0 | 06-c6-02/82 | 00000119 | 0000011a | Core Ultra Processor (Series 2) +| AZB | A0/R0 | 06-9a-04/40 | 0000000a | 0000000b | Atom C1100 +| EMR-SP | A1 | 06-cf-02/87 | 210002b3 | 210002c0 | Xeon Scalable Gen5 +| GNR-AP/SP | Bx/Hx/Lx | 06-ad-01/95 | 010003d0 | 010003f0 | Xeon 6900-6700/6500-Series Processors with P-Cores +| GNR-SP R1S | Bx/Hx/Lx | 06-ad-01/20 | 0a000100 | 0a000124 | Xeon 6700/6500-Series Processors with P-Cores +| LNL | B0 | 06-bd-01/80 | 00000123 | 00000125 | Core Ultra 200 V Series Processor +| RPL-E/HX/S | B0 | 06-b7-01/32 | 0000012f | 00000132 | Core Gen13/Gen14 +| RPL-H/P/PX 6+8 | J0 | 06-ba-02/e0 | 00004129 | 00006133 | Core Gen13 +| RPL-HX/S | C0 | 06-bf-02/07 | 0000003a | 0000003d | Core Gen13/Gen14 +| RPL-S | H0 | 06-bf-05/07 | 0000003a | 0000003d | Core Gen13/Gen14 +| RPL-U 2+8 | Q0 | 06-ba-03/e0 | 00004129 | 00006133 | Core Gen13 +| SPR-HBM | Bx | 06-8f-08/10 | 2c000401 | 2c000410 | Xeon Max +| SPR-SP | E4/S2 | 06-8f-07/87 | 2b000643 | 2b000650 | Xeon Scalable Gen4 +| SPR-SP | E5/S3 | 06-8f-08/87 | 2b000643 | 2b000650 | Xeon Scalable Gen4 +| SRF-AP/SP | C0 | 06-af-03/01 | 03000362 | 03000382 | Xeon 6900/6700-Series Processors with E-Cores +| TWL | N0 | 06-be-00/19 | 0000001d | 0000001e | Core i3-N305/N300, N50/N97/N100/N200, Atom x7211E/x7213E/x7425E + +### Change History +General updates to current Release Notes: Correction of Xeon 6 family processors names. + + +# Release Notes +## [microcode-20250812](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20250812) + +### Purpose +- Security updates for [INTEL-SA-01249](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01249.html) +- Security updates for [INTEL-SA-01308](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01308.html) +- Security updates for [INTEL-SA-01310](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01310.html) +- Security updates for [INTEL-SA-01311](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01311.html) +- Security updates for [INTEL-SA-01313](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01313.html) +- Security updates for [INTEL-SA-01367](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01367.html) +- Update for functional issues. Refer to [13th/14th Gen Intel® Core™ Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/740518) for details. +- Update for functional issues. Refer to [3rd Gen Intel® Xeon® Processor Scalable Family Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/637780) for details. +- Update for functional issues. Refer to [4th Gen Intel® Xeon® Scalable Processors Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/772415) for details. +- Update for functional issues. Refer to [5th Gen Intel® Xeon® Scalable Processors Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/793902) for details. +- Update for functional issues. Refer to [6th Gen Intel® Xeon® Scalable Processors Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/835486) for details. +- Update for functional issues. Refer to [Intel® Core™ Ultra 200 V Series Processor](https://cdrdv2.intel.com/v1/dl/getContent/827538) for details. +- Update for functional issues. Refer to [Intel® Core™ Ultra Processor](https://cdrdv2.intel.com/v1/dl/getContent/792254) for details. +- Update for functional issues. Refer to [Intel® Core™ Ultra Processor (Series 2)](https://cdrdv2.intel.com/v1/dl/getContent/834774) for details. +- Update for functional issues. Refer to [Intel® Xeon® 6700-Series Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/820922) for details. +- Update for functional issues. Refer to [Intel® Xeon® D-2700 Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/714071) for details. + + +### New Platforms + +| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products +|:---------------|:---------|:------------|:---------|:---------|:--------- + + +### Updated Platforms + +| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products +|:---------------|:---------|:------------|:---------|:---------|:--------- +| ARL-H | A1 | 06-c5-02/82 | 00000118 | 00000119 | Core Ultra Processor (Series 2) +| ARL-S/HX (8P) | B0 | 06-c6-02/82 | 00000118 | 00000119 | Core Ultra Processor (Series 2) +| EMR-SP | A1 | 06-cf-02/87 | 210002a9 | 210002b3 | Xeon Scalable Gen5 +| GNR-AP/SP | B0 | 06-ad-01/95 | 010003a2 | 010003d0 | Xeon Scalable Gen6 +| GNR-AP/SP | H0 | 06-ad-01/20 | 0a0000d1 | 0a000100 | Xeon Scalable Gen6 +| ICL-D | B0 | 06-6c-01/10 | 010002d0 | 010002e0 | Xeon D-17xx, D-27xx +| ICX-SP | Dx/M1 | 06-6a-06/87 | 0d000404 | 0d000410 | Xeon Scalable Gen3 +| LNL | B0 | 06-bd-01/80 | 0000011f | 00000123 | Core Ultra 200 V Series Processor +| MTL | C0 | 06-aa-04/e6 | 00000024 | 00000025 | Core™ Ultra Processor +| RPL-H/P/PX 6+8 | J0 | 06-ba-02/e0 | 00004128 | 00004129 | Core Gen13 +| RPL-U 2+8 | Q0 | 06-ba-03/e0 | 00004128 | 00004129 | Core Gen13 +| SPR-HBM | Bx | 06-8f-08/10 | 2c0003f7 | 2c000401 | Xeon Max +| SPR-SP | E4/S2 | 06-8f-07/87 | 2b000639 | 2b000643 | Xeon Scalable Gen4 +| SPR-SP | E5/S3 | 06-8f-08/87 | 2b000639 | 2b000643 | Xeon Scalable Gen4 +| SRF-SP | C0 | 06-af-03/01 | 03000341 | 03000362 | Xeon 6700-Series Processors with E-Cores + + +### New Disclosures Updated in Prior Releases + +All ADL, RPL, SPR, EMR, MTL, ARL Microcode patches previously released in May 2025. + +# Release Notes +## [microcode-20250512](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20250512) + +### Purpose + +- Security updates for [INTEL-SA-01153](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01153.html) +- Security updates for [INTEL-SA-01244](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01244.html) +- Security updates for [INTEL-SA-01247](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01247.html) +- Security updates for [INTEL-SA-01322](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01322.html) +# Note: INTEL-SA-01244 and INTEL-SA-01247 will be published on May 13th 2025 + + +- Update for functional issues. Refer to [Intel® Core™ Ultra 200 V Series Processor (Series2)](https://cdrdv2.intel.com/v1/dl/getContent/834774) for details. +- Update for functional issues. Refer to [Intel® Core™ Ultra 200 V Series Processor](https://cdrdv2.intel.com/v1/dl/getContent/827538) for details. +- Update for functional issues. Refer to [Intel® Core™ Ultra Processor](https://cdrdv2.intel.com/v1/dl/getContent/792254) for details. +- Update for functional issues. Refer to [14th/13th Generation Intel® Core™ Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/740518) for details. +- Update for functional issues. Refer to [12th Generation Intel® Core™ Processor Family](https://cdrdv2.intel.com/v1/dl/getContent/682436) for details. +- Update for functional issues. Refer to [11th Gen Intel® Core™ Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/631123) for details. +- Update for functional issues. Refer to [10th Gen Intel® Core™ Processor Families Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/341079) for details. +- Update for functional issues. Refer to [10th Gen Intel® Core™ Processor Families Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/615213) for details. +- Update for functional issues. Refer to [8th and 9th Generation Intel® Core™ Processor Family Spec Update](https://cdrdv2.intel.com/v1/dl/getContent/337346) for details. +- Update for functional issues. Refer to [6th Gen Intel® Xeon® Scalable Processors Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/835486) for details. +- Update for functional issues. Refer to [5th Gen Intel® Xeon® Processor Scalable Family](https://cdrdv2.intel.com/v1/dl/getContent/793902) for details. +- Update for functional issues. Refer to [4th Gen Intel® Xeon® Scalable Processors Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/772415) for details. +- Update for functional issues. Refer to [3rd Generation Intel® Xeon® Scalable Processors Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/634897) for details. +- Update for functional issues. Refer to [3rd Generation Intel® Xeon® Scalable Processors Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/637780) for details. +- Update for functional issues. Refer to [2nd Generation Intel® Xeon® Processor Scalable Family Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/338848) for details. +- Update for functional issues. Refer to [Intel® Xeon® 6700-Series Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/820922) for details. +- Update for functional issues. Refer to [Intel® Xeon® E-2300 Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/709192) for details. +- Update for functional issues. Refer to [Intel® Xeon® D-2700 Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/714071) for details. +- Update for functional issues. Refer to [Intel® Processors and Intel® Core™ i3 N-Series](https://cdrdv2.intel.com/v1/dl/getContent/764616) for details. +- Update for functional issues. Refer to [Intel® Pentium® Silver and Intel® Celeron® Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/336562) + +### New Platforms + +| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products +|:---------------|:---------|:------------|:---------|:---------|:--------- +| ARL-U | A1 | 06-b5-00/80 | | 0000000a | Core™ Ultra Processor (Series2) +| ARL-S/HX (8P) | B0 | 06-c6-02/82 | | 00000118 | Core™ Ultra Processor (Series2) +| ARL-H | A1 | 06-c5-02/82 | | 00000118 | Core™ Ultra Processor (Series2) +| GNR-AP/SP | B0 | 06-ad-01/95 | | 010003a2 | Xeon Scalable Gen6 +| GNR-AP/SP | H0 | 06-ad-01/20 | | 0a0000d1 | Xeon Scalable Gen6 +| LNL | B0 | 06-bd-01/80 | | 0000011f | Core™ Ultra 200 V Series Processor + +### Updated Platforms + +| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products +|:---------------|:---------|:------------|:---------|:---------|:--------- +| ADL | C0 | 06-97-02/07 | 00000038 | 0000003a | Core Gen12 +| ADL | H0 | 06-97-05/07 | 00000038 | 0000003a | Core Gen12 +| ADL | L0 | 06-9a-03/80 | 00000436 | 00000437 | Core Gen12 +| ADL | R0 | 06-9a-04/80 | 00000436 | 00000437 | Core Gen12 +| ADL-N | N0 | 06-be-00/19 | 0000001c | 0000001d | Core i3-N305/N300, N50/N97/N100/N200, Atom x7211E/x7213E/x7425E +| AML-Y42 | V0 | 06-8e-0c/94 | 000000fc | 00000100 | Core Gen10 Mobile +| AZB | A0/R0 | 06-9a-04/40 | 00000009 | 0000000a | Intel(R) Atom(R) C1100 +| CFL-H | R0 | 06-9e-0d/22 | 00000102 | 00000104 | Core Gen9 Mobile +| CLX-SP | B1 | 06-55-07/bf | 05003707 | 05003901 | Xeon Scalable Gen2 +| CML-H | R1 | 06-a5-02/20 | 000000fc | 00000100 | Core Gen10 Mobile +| CML-S102 | Q0 | 06-a5-05/22 | 000000fc | 00000100 | Core Gen10 +| CML-S62 | G1 | 06-a5-03/22 | 000000fc | 00000100 | Core Gen10 +| CML-U42 | V0 | 06-8e-0c/94 | 000000fc | 00000100 | Core Gen10 Mobile +| CML-U62 V1 | A0 | 06-a6-00/80 | 000000fe | 00000102 | Core Gen10 Mobile +| CML-U62 V2 | K1 | 06-a6-01/80 | 000000fc | 00000100 | Core Gen10 Mobile +| CML-Y42 | V0 | 06-8e-0c/94 | 000000fc | 00000100 | Core Gen10 Mobile +| CPX-SP | A1 | 06-55-0b/bf | 07002904 | 07002b01 | Xeon Scalable Gen3 +| EMR-SP | A1 | 06-cf-02/87 | 21000291 | 210002a9 | Xeon Scalable Gen5 +| GLK-R | R0 | 06-7a-08/01 | 00000024 | 00000026 | Pentium J5040/N5030, Celeron J4125/J4025/N4020/N4120 +| ICL-D | B0 | 06-6c-01/10 | 010002c0 | 010002d0 | Xeon D-17xx, D-27xx +| ICL-U/Y | D1 | 06-7e-05/80 | 000000c6 | 000000ca | Core Gen10 Mobile +| ICX-SP | Dx/M1 | 06-6a-06/87 | 0d0003f5 | 0d000404 | Xeon Scalable Gen3 +| MTL | C0 | 06-aa-04/e6 | 00000020 | 00000024 | Core™ Ultra Processor +| RKL-S | B0 | 06-a7-01/02 | 00000063 | 00000064 | Core Gen11 +| RPL-E/HX/S | B0 | 06-b7-01/32 | 0000012c | 0000012f | Core Gen13/Gen14 +| RPL-H/P/PX 6+8 | J0 | 06-ba-02/e0 | 00004124 | 00004128 | Core Gen13 +| RPL-HX/S | C0 | 06-bf-02/07 | 00000038 | 0000003a | Core Gen13/Gen14 +| RPL-S | H0 | 06-bf-05/07 | 00000038 | 0000003a | Core Gen13/Gen14 +| RPL-U 2+8 | Q0 | 06-ba-03/e0 | 00004124 | 00004128 | Core Gen13 +| SPR-HBM | Bx | 06-8f-08/10 | 2c0003e0 | 2c0003f7 | Xeon Max +| SPR-SP | E4/S2 | 06-8f-07/87 | 2b000620 | 2b000639 | Xeon Scalable Gen4 +| SPR-SP | E5/S3 | 06-8f-08/87 | 2b000620 | 2b000639 | Xeon Scalable Gen4 +| SRF-SP | C0 | 06-af-03/01 | 03000330 | 03000341 | Xeon 6700-Series Processors with E-Cores +| TGL | B0/B1 | 06-8c-01/80 | 000000b8 | 000000bc | Core Gen11 Mobile +| TGL-H | R0 | 06-8d-01/c2 | 00000052 | 00000056 | Core Gen11 Mobile +| TGL-R | C0 | 06-8c-02/c2 | 00000038 | 0000003c | Core Gen11 Mobile +| TWL | N0 | 06-be-00/19 | 0000001c | 0000001d | Core i3-N305/N300, N50/N97/N100/N200, Atom x7211E/x7213E/x7425E +| WHL-U | V0 | 06-8e-0c/94 | 000000fc | 00000100 | Core Gen8 Mobile + # Release Notes ## [microcode-20250211](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20250211) @@ -61,6 +442,7 @@ |:---------------|:---------|:------------|:---------|:---------|:--------- | CFL-H/S | P0 | 06-9e-0c/22 | 000000f6 | 000000f8 | Core Gen9 +# Release Notes ## [microcode-20241112](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20241112) ### Purpose diff --git a/security.md b/security.md index 3193a4d..c39feb7 100644 --- a/security.md +++ b/security.md @@ -1,39 +1,39 @@ -# Security Policy - -## Report a Vulnerability - -If you have information about a security issue or vulnerability with an **Intel branded product or technology**, please send an e-mail to [secure@intel.com](mailto:secure@intel.com). Encrypt sensitive information using our [PGP public key](https://www.intel.com/content/www/us/en/security-center/pgp-public-key.html). - -Please provide as much information as possible, including: - -- The products and versions affected -- Detailed description of the vulnerability -- Information on known exploits - -A member of the Intel Product Security Team will review your e-mail and contact you to collaborate on resolving the issue. For more information on how Intel works to resolve security issues, see: - -- [Vulnerability handling guidelines](https://www.intel.com/content/www/us/en/security-center/vulnerability-handling-guidelines.html) - -For issues related to Intel's external web presence (Intel.com and related subdomains), please contact [Intel's External Security Research team](mailto:external.security.research@intel.com). - -## Intel's Bug Bounty Program - -Intel Corporation believes that working with skilled security researchers across the globe is a crucial part of identifying and mitigating security vulnerabilities in Intel products. - -Like other major technology companies, Intel incentivizes security researchers to report security vulnerabilities in Intel products to us to enable a coordinated response. To encourage closer collaboration with the security research community on these kinds of issues, Intel created its Bug Bounty Program. - -If you believe you've found a security vulnerability in an Intel product or technology, we encourage you to notify us through our program and work with us to mitigate and to coordinate disclosure of the vulnerability. - -[Read full details.](https://www.intel.com/content/www/us/en/security-center/bug-bounty-program.html) - -## Need product support? - -The [secure@intel.com](mailto:secure@intel.com) e-mail address should only be used for reporting security issues. - -If you... - -- Have questions about the security features of an Intel product -- Require technical support -- Want product updates or patches - -Please visit [Support & Downloads](https://www.intel.com/content/www/us/en/support.html). +# Security Policy + +## Report a Vulnerability + +If you have information about a security issue or vulnerability with an **Intel branded product or technology**, please send an e-mail to [secure@intel.com](mailto:secure@intel.com). Encrypt sensitive information using our [PGP public key](https://www.intel.com/content/www/us/en/security-center/pgp-public-key.html). + +Please provide as much information as possible, including: + +- The products and versions affected +- Detailed description of the vulnerability +- Information on known exploits + +A member of the Intel Product Security Team will review your e-mail and contact you to collaborate on resolving the issue. For more information on how Intel works to resolve security issues, see: + +- [Vulnerability handling guidelines](https://www.intel.com/content/www/us/en/security-center/vulnerability-handling-guidelines.html) + +For issues related to Intel's external web presence (Intel.com and related subdomains), please contact [Intel's External Security Research team](mailto:external.security.research@intel.com). + +## Intel's Bug Bounty Program + +Intel Corporation believes that working with skilled security researchers across the globe is a crucial part of identifying and mitigating security vulnerabilities in Intel products. + +Like other major technology companies, Intel incentivizes security researchers to report security vulnerabilities in Intel products to us to enable a coordinated response. To encourage closer collaboration with the security research community on these kinds of issues, Intel created its Bug Bounty Program. + +If you believe you've found a security vulnerability in an Intel product or technology, we encourage you to notify us through our program and work with us to mitigate and to coordinate disclosure of the vulnerability. + +[Read full details.](https://www.intel.com/content/www/us/en/security-center/bug-bounty-program.html) + +## Need product support? + +The [secure@intel.com](mailto:secure@intel.com) e-mail address should only be used for reporting security issues. + +If you... + +- Have questions about the security features of an Intel product +- Require technical support +- Want product updates or patches + +Please visit [Support & Downloads](https://www.intel.com/content/www/us/en/support.html).