From 287e4f9b7b5c0ebdbbe0c7e307678177ff269a44 Mon Sep 17 00:00:00 2001 From: Tomasz Leman Date: Mon, 13 Jan 2025 17:32:01 +0100 Subject: [PATCH 0001/1821] audio: chain_dma: fix incorrect format specifier for error codes This patch corrects the format specifier used for printing error codes in the chain_dma.c file. The error codes are signed integers, but the format specifier used was `%u`, which is for unsigned integers. This caused negative error codes to be printed incorrectly as large positive values. The format specifier has been changed to `%d` to correctly print signed integers. This is a cosmetic change that ensures error codes are accurately represented in the logs, aiding in debugging and analysis. Signed-off-by: Tomasz Leman --- src/audio/chain_dma.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/audio/chain_dma.c b/src/audio/chain_dma.c index 41282fd24eeb..cd19f5d677eb 100644 --- a/src/audio/chain_dma.c +++ b/src/audio/chain_dma.c @@ -187,13 +187,13 @@ static enum task_state chain_task_run(void *data) break; case -EPIPE: tr_warn(&chain_dma_tr, "chain_task_run(): dma_get_status() link xrun occurred," - " ret = %u", ret); + " ret = %d", ret); #if CONFIG_XRUN_NOTIFICATIONS_ENABLE handle_xrun(cd); #endif break; default: - tr_err(&chain_dma_tr, "chain_task_run(): dma_get_status() error, ret = %u", ret); + tr_err(&chain_dma_tr, "chain_task_run(): dma_get_status() error, ret = %d", ret); return SOF_TASK_STATE_COMPLETED; } @@ -204,7 +204,7 @@ static enum task_state chain_task_run(void *data) /* Host DMA does not report xruns. All error values will be treated as critical. */ ret = dma_get_status(cd->chan_host->dma->z_dev, cd->chan_host->index, &stat); if (ret < 0) { - tr_err(&chain_dma_tr, "chain_task_run(): dma_get_status() error, ret = %u", ret); + tr_err(&chain_dma_tr, "chain_task_run(): dma_get_status() error, ret = %d", ret); return SOF_TASK_STATE_COMPLETED; } @@ -223,14 +223,14 @@ static enum task_state chain_task_run(void *data) ret = dma_reload(cd->chan_host->dma->z_dev, cd->chan_host->index, 0, 0, increment); if (ret < 0) { tr_err(&chain_dma_tr, - "chain_task_run(): dma_reload() host error, ret = %u", ret); + "chain_task_run(): dma_reload() host error, ret = %d", ret); return SOF_TASK_STATE_COMPLETED; } ret = dma_reload(cd->chan_link->dma->z_dev, cd->chan_link->index, 0, 0, increment); if (ret < 0) { tr_err(&chain_dma_tr, - "chain_task_run(): dma_reload() link error, ret = %u", ret); + "chain_task_run(): dma_reload() link error, ret = %d", ret); return SOF_TASK_STATE_COMPLETED; } } else { @@ -248,7 +248,7 @@ static enum task_state chain_task_run(void *data) half_buff_size); if (ret < 0) { tr_err(&chain_dma_tr, - "chain_task_run(): dma_reload() link error, ret = %u", + "chain_task_run(): dma_reload() link error, ret = %d", ret); return SOF_TASK_STATE_COMPLETED; } @@ -264,7 +264,7 @@ static enum task_state chain_task_run(void *data) 0, 0, transferred); if (ret < 0) { tr_err(&chain_dma_tr, - "chain_task_run(): dma_reload() host error, ret = %u", ret); + "chain_task_run(): dma_reload() host error, ret = %d", ret); return SOF_TASK_STATE_COMPLETED; } @@ -274,7 +274,7 @@ static enum task_state chain_task_run(void *data) 0, 0, half_buff_size); if (ret < 0) { tr_err(&chain_dma_tr, "chain_task_run(): dma_reload() " - "link error, ret = %u", ret); + "link error, ret = %d", ret); return SOF_TASK_STATE_COMPLETED; } } From 753f0443026c78a9a51b70ffb9d3454a78a0f598 Mon Sep 17 00:00:00 2001 From: "hailong.fan" Date: Wed, 25 Dec 2024 19:55:37 +0800 Subject: [PATCH 0002/1821] platform: mediatek: add xtensa headers for mt8196 Add xtensa headers for mediatek mt8196 platform. Signed-off-by: hailong.fan --- .../include/arch/xtensa/config/core-isa.h | 831 ++++++++++++++++++ .../include/arch/xtensa/config/core-matmap.h | 101 +++ .../mt8196/include/arch/xtensa/config/defs.h | 41 + .../mt8196/include/arch/xtensa/config/key.h | 18 + .../include/arch/xtensa/config/secure.h | 47 + .../include/arch/xtensa/config/specreg.h | 112 +++ .../include/arch/xtensa/config/system.h | 293 ++++++ .../include/arch/xtensa/config/tie-asm.h | 362 ++++++++ .../mt8196/include/arch/xtensa/config/tie.h | 220 +++++ 9 files changed, 2025 insertions(+) create mode 100644 src/platform/mt8196/include/arch/xtensa/config/core-isa.h create mode 100644 src/platform/mt8196/include/arch/xtensa/config/core-matmap.h create mode 100644 src/platform/mt8196/include/arch/xtensa/config/defs.h create mode 100644 src/platform/mt8196/include/arch/xtensa/config/key.h create mode 100644 src/platform/mt8196/include/arch/xtensa/config/secure.h create mode 100644 src/platform/mt8196/include/arch/xtensa/config/specreg.h create mode 100644 src/platform/mt8196/include/arch/xtensa/config/system.h create mode 100644 src/platform/mt8196/include/arch/xtensa/config/tie-asm.h create mode 100644 src/platform/mt8196/include/arch/xtensa/config/tie.h diff --git a/src/platform/mt8196/include/arch/xtensa/config/core-isa.h b/src/platform/mt8196/include/arch/xtensa/config/core-isa.h new file mode 100644 index 000000000000..b0d7ed6a7c67 --- /dev/null +++ b/src/platform/mt8196/include/arch/xtensa/config/core-isa.h @@ -0,0 +1,831 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa + * processor CORE configuration + * + * See , which includes this file, for more details. + */ + +/* Xtensa processor core configuration information. + * + * Customer ID=7578; Build=0xa69ab; Copyright (c) 1999-2023 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef XTENSA_CORE_CONFIGURATION_H_ +#define XTENSA_CORE_CONFIGURATION_H_ + +/**************************************************************************** + * Parameters Useful for Any Code, USER or PRIVILEGED + **************************************************************************** + */ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + +/*---------------------------------------------------------------------- + * ISA + *---------------------------------------------------------------------- + */ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 16 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_EXCLUSIVE 1 /* L32EX/S32EX instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ +#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ +#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ +#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ +#define XCHAL_HAVE_LX 1 /* LX core */ +#define XCHAL_HAVE_NX 0 /* NX core (starting RH) */ +#define XCHAL_HAVE_RNX 0 /* RNX core (starting RJ) */ + +#define XCHAL_HAVE_SUPERGATHER 0 /* SuperGather */ + +#define XCHAL_HAVE_FUSION 0 /* Fusion */ +#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ +#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ +#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ +#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ +#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ +#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ +#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ +#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ +#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ +#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ +#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI5 1 /* HiFi5 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI5_NN_MAC 1 /* HiFi5 Audio Engine NN-MAC option */ + +/* HiFi5 Audio Engine Single--Precision VFPU option */ +#define XCHAL_HAVE_HIFI5_VFPU 1 +#define XCHAL_HAVE_HIFI5_HP_VFPU 1 /* HiFi5 Audio Engine Half-Precision VFPU option */ +#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4_VFPU 1 /* HiFi4 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3 1 /* HiFi3 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3_VFPU 1 /* HiFi3 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI1 0 /* HiFi1 */ +#define XCHAL_HAVE_HIFI1_VFPU 0 /* HiFi1 VFPU option */ +/* HiFi1 Low-latency MAC/FMA option */ +#define XCHAL_HAVE_HIFI1_LOW_LATENCY_MAC_FMA 0 +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ +#define XCHAL_HAVE_HIFI_MINI 0 + +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ +#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_USER_SPFPU 1 /* user SP floating-point pkg */ +#define XCHAL_HAVE_FP 1 /* single prec floating point */ +#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */ +#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */ +#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ +#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */ +#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ +#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ +#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ +#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ +#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ + +#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ +#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ + +#define XCHAL_HAVE_FUSIONG 0 /* FusionG */ +#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */ +#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */ +#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */ +#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */ +#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ + +#define XCHAL_HAVE_FUSIONJ 0 /* FusionJ */ +#define XCHAL_HAVE_FUSIONJ6 0 /* FusionJ6 */ +#define XCHAL_HAVE_FUSIONJ_SP_VFPU 0 /* sp_vfpu option on FusionJ */ +#define XCHAL_HAVE_FUSIONJ_DP_VFPU 0 /* dp_vfpu option on FusionJ */ +#define XCHAL_FUSIONJ_SIMD32 0 /* simd32 for FusionJ */ + +#define XCHAL_HAVE_PDX 0 /* PDX-LX */ +#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */ +#define XCHAL_HAVE_PDX4 0 /* PDX4-LX */ +#define XCHAL_HAVE_PDX8 0 /* PDX8-LX */ +#define XCHAL_HAVE_PDX16 0 /* PDX16-LX */ +#define XCHAL_HAVE_PDXNX 0 /* PDX-NX */ + +#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ +#define XCHAL_HAVE_BALL 0 +#define XCHAL_HAVE_BALLAP 0 +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_CONNX_B10 0 /* ConnX B10 pkg*/ +#define XCHAL_HAVE_CONNX_B20 0 /* ConnX B20 pkg*/ + +/* Double-precision Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_DP_VFPU 0 +/* Double-precision Vector Floating-point option on FP Machine*/ +#define XCHAL_HAVE_CONNX_B_DPX_VFPU 0 +/* Single-precision Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_SP_VFPU 0 +/* Single-precision Extended Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_SPX_VFPU 0 +/* Half-precision Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_HP_VFPU 0 +/* Half-precision Extended Vector Floating-point option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_HPX_VFPU 0 +/* 32-bit vector MAC (real and complex), FIR & FFT option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_32B_MAC 0 +#define XCHAL_HAVE_CONNX_B_VITERBI 0 /* Viterbi option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_TURBO 0 /* Turbo option on ConnX B10 & B20 */ +#define XCHAL_HAVE_CONNX_B_LDPC 0 /* LDPC option on ConnX B10 & B20 */ +#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ +#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ +#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ +#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */ +#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ + +#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */ +#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ +#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, Q6, Q7 or Q8 */ +#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */ +#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */ +#define XCHAL_HAVE_VISION_DP_VFPU 0 /* dp_vfpu option on Vision Q7/Q8 */ +#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6/Q6/Q7 */ +#define XCHAL_HAVE_VISION_SP_VFPU_2XFMAC 0 /* sp_vfpu_2xfma option on Vision Q7 */ +#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6/Q6 */ +#define XCHAL_HAVE_VISION_HP_VFPU_2XFMAC 0 /* hp_vfpu_2xfma option on Vision Q7 */ + +#define XCHAL_HAVE_VISIONC 0 /* Vision C */ + +#define XCHAL_HAVE_XNNE 0 /* XNNE */ + +/*---------------------------------------------------------------------- + * MISC + *---------------------------------------------------------------------- + */ + +#define XCHAL_NUM_LOADSTORE_UNITS 2 /* load/store units */ +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 32 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 16 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 16 /* data width in bytes */ + +/* d-side pipeline delay (1 = 5-stage, 2 = 7-stage) */ +#define XCHAL_DATA_PIPE_DELAY 2 +#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ +#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ +#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ +#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ + +#define XCHAL_UNIFIED_LOADSTORE 0 + +#define XCHAL_SW_VERSION 1411000 /* sw version of this header */ +#define XCHAL_SW_VERSION_MAJOR 14000 /* major ver# of sw */ +#define XCHAL_SW_VERSION_MINOR 11 /* minor ver# of sw */ +#define XCHAL_SW_VERSION_MICRO 0 /* micro ver# of sw */ +#define XCHAL_SW_MINOR_VERSION 1411000 /* with zeroed micro */ +#define XCHAL_SW_MICRO_VERSION 1411000 + +/* alphanum core name (CoreID) set in the Xtensa Processor Generator */ +#define XCHAL_CORE_ID "HiFi5_MPU_lock_2023_11" + +#define XCHAL_BUILD_UNIQUE_ID 0x000A69AB /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC003B286 /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x2A09D04B /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX7.1.8" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2810 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 8 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION_MICRO 0 /* subdot ver# of targeted hw */ +/* major*100+(major<2810 ? minor : minor*10+micro) */ +#define XCHAL_HW_VERSION 281080 +#define XCHAL_HW_REL_LX7 1 +#define XCHAL_HW_REL_LX7_1 1 +#define XCHAL_HW_REL_LX7_1_8 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2810 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 8 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MICRO 0 /* micro v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 281080 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2810 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 8 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MICRO 0 /* micro v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 281080 /* latest targeted hw */ + +/* Config is enabled for functional safety: */ +#define XCHAL_HAVE_FUNC_SAFETY 0 + +/* Config is enabled for secure operation: */ +#define XCHAL_HAVE_SECURE 0 + +#define XCHAL_HAVE_APB 0 + +/*---------------------------------------------------------------------- + * CACHE + *---------------------------------------------------------------------- + */ + +#define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 7 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 7 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 65536 /* I-cache size in bytes or 0 */ +#define XCHAL_ICACHE_SIZE_LOG2 16 +#define XCHAL_DCACHE_SIZE 131072 /* D-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE_LOG2 17 + +#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ +#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ + +#define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ +#define XCHAL_HAVE_PREFETCH_L1 1 /* prefetch to L1 cache */ +#define XCHAL_PREFETCH_CASTOUT_LINES 2 /* dcache pref. castout bufsz */ +#define XCHAL_PREFETCH_ENTRIES 16 /* cache prefetch entries */ +#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ +#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ +#define XCHAL_HAVE_CME_DOWNGRADES 0 +#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ +#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ +#define XCHAL_HAVE_ICACHE_DYN_WAYS 1 /* Icache dynamic way support */ +#define XCHAL_HAVE_DCACHE_DYN_WAYS 1 /* Dcache dynamic way support */ +#define XCHAL_HAVE_ICACHE_DYN_ENABLE 1 /* Icache enabled via MEMCTL */ +#define XCHAL_HAVE_DCACHE_DYN_ENABLE 1 /* Dcache enabled via MEMCTL */ + +#define XCHAL_L1SCACHE_SIZE 0 +#define XCHAL_L1SCACHE_SIZE_LOG2 0 +#define XCHAL_L1SCACHE_WAYS 1 +#define XCHAL_L1SCACHE_WAYS_LOG2 0 +#define XCHAL_L1SCACHE_ACCESS_SIZE 0 +#define XCHAL_L1SCACHE_BANKS 1 + +#define XCHAL_L1VCACHE_SIZE 0 + +#define XCHAL_HAVE_L2 0 /* NX L2 cache controller */ +#define XCHAL_HAVE_L2_CACHE 0 +#define XCHAL_NUM_CORES_IN_CLUSTER 0 + +/* PRID_ID macros are for internal use only ... subject to removal */ +#define PRID_ID_SHIFT 0 +#define PRID_ID_BITS 4 +#define PRID_ID_MASK 0x0000000F + +/* This one is a form of caching, though not architecturally visible: */ +#define XCHAL_HAVE_BRANCH_PREDICTION 0 /* branch [target] prediction */ + +/**************************************************************************** + * Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + * CACHE + *---------------------------------------------------------------------- + */ + +#define XCHAL_HAVE_PIF 1 /* any outbound bus present */ + +#define XCHAL_HAVE_AXI 1 /* AXI bus */ +#define XCHAL_HAVE_AXI_ECC 1 /* ECC on AXI bus */ +#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ + +#define XCHAL_HAVE_PIF_WR_RESP 1 /* pif write response */ +#define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 7 +#define XCHAL_DCACHE_SETWIDTH 8 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 4 +#define XCHAL_ICACHE_WAYS_LOG2 2 +#define XCHAL_DCACHE_WAYS 4 +#define XCHAL_DCACHE_WAYS_LOG2 2 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 1 +#define XCHAL_DCACHE_LINE_LOCKABLE 1 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 +#define XCHAL_ICACHE_ECC_WIDTH 4 +#define XCHAL_DCACHE_ECC_WIDTH 1 + +/* Cache access size in bytes (affects operation of SICW instruction): */ +#define XCHAL_ICACHE_ACCESS_SIZE 16 +#define XCHAL_DCACHE_ACCESS_SIZE 16 + +#define XCHAL_DCACHE_BANKS 2 /* number of banks */ + +/* The number of Cache lines associated with a single cache tag */ +#define XCHAL_DCACHE_LINES_PER_TAG_LOG2 0 + +/* Number of encoded cache attr bits (see for decoded bits): */ + +/* Extended memory attributes supported. */ +#define XCHAL_HAVE_EXT_CA 0 + +/*---------------------------------------------------------------------- + * INTERNAL I/D RAM/ROMs and XLMI + *---------------------------------------------------------------------- + */ +#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ +#define XCHAL_HAVE_IRAMCFG 0 /* IRAMxCFG register present */ +#define XCHAL_HAVE_DRAMCFG 0 /* DRAMxCFG register present */ + +/* Instruction RAM 0: */ +#define XCHAL_INSTRAM0_VADDR 0x3FFF0000 /* virtual address */ +#define XCHAL_INSTRAM0_PADDR 0x3FFF0000 /* physical address */ +#define XCHAL_INSTRAM0_SIZE 262144 /* size in bytes */ +#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_HAVE_INSTRAM0 1 +#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* Data RAM 0: */ +#define XCHAL_DATARAM0_VADDR 0x3FFE8000 /* virtual address */ +#define XCHAL_DATARAM0_PADDR 0x3FFE8000 /* physical address */ +#define XCHAL_DATARAM0_SIZE 65536 /* size in bytes */ +#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM0_BANKS 2 /* number of banks */ +#define XCHAL_HAVE_DATARAM0 1 +#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* Data RAM 1: */ +#define XCHAL_DATARAM1_VADDR 0x3FFE9000 /* virtual address */ +#define XCHAL_DATARAM1_PADDR 0x3FFE9000 /* physical address */ +#define XCHAL_DATARAM1_SIZE 131072 /* size in bytes */ +#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM1_BANKS 2 /* number of banks */ +#define XCHAL_HAVE_DATARAM1 1 +#define XCHAL_DATARAM1_HAVE_IDMA 0 /* idma supported by this local memory */ + +#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ + +/*---------------------------------------------------------------------- + * IDMA + *---------------------------------------------------------------------- + */ + +#define XCHAL_HAVE_IDMA 0 + +/*---------------------------------------------------------------------- + * INTERRUPTS and TIMERS + *---------------------------------------------------------------------- + */ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */ +/* number of interrupt levels (not including level zero) */ +#define XCHAL_NUM_INTLEVELS 5 +#define XCHAL_INTERRUPT_RANGE 32 /* range of interrupt numbers */ + +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0x040000FF +#define XCHAL_INTLEVEL2_MASK 0xA800FF00 +#define XCHAL_INTLEVEL3_MASK 0x518F0000 +#define XCHAL_INTLEVEL4_MASK 0x00700000 +#define XCHAL_INTLEVEL5_MASK 0x00000000 +#define XCHAL_INTLEVEL6_MASK 0x02000000 +#define XCHAL_INTLEVEL7_MASK 0x00000000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x040000FF +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0xAC00FFFF +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0xFD8FFFFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0xFDFFFFFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFDFFFFFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFFFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 1 +#define XCHAL_INT2_LEVEL 1 +#define XCHAL_INT3_LEVEL 1 +#define XCHAL_INT4_LEVEL 1 +#define XCHAL_INT5_LEVEL 1 +#define XCHAL_INT6_LEVEL 1 +#define XCHAL_INT7_LEVEL 1 +#define XCHAL_INT8_LEVEL 2 +#define XCHAL_INT9_LEVEL 2 +#define XCHAL_INT10_LEVEL 2 +#define XCHAL_INT11_LEVEL 2 +#define XCHAL_INT12_LEVEL 2 +#define XCHAL_INT13_LEVEL 2 +#define XCHAL_INT14_LEVEL 2 +#define XCHAL_INT15_LEVEL 2 +#define XCHAL_INT16_LEVEL 3 +#define XCHAL_INT17_LEVEL 3 +#define XCHAL_INT18_LEVEL 3 +#define XCHAL_INT19_LEVEL 3 +#define XCHAL_INT20_LEVEL 4 +#define XCHAL_INT21_LEVEL 4 +#define XCHAL_INT22_LEVEL 4 +#define XCHAL_INT23_LEVEL 3 +#define XCHAL_INT24_LEVEL 3 +#define XCHAL_INT25_LEVEL 6 +#define XCHAL_INT26_LEVEL 1 +#define XCHAL_INT27_LEVEL 2 +#define XCHAL_INT28_LEVEL 3 +#define XCHAL_INT29_LEVEL 2 +#define XCHAL_INT30_LEVEL 3 +#define XCHAL_INT31_LEVEL 2 +#define XCHAL_DEBUGLEVEL 5 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +/* NMI "level" (for use with EXCSAVE/EPS/EPC_n, RFI n) */ +#define XCHAL_NMILEVEL 6 + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT25_TYPE XTHAL_INTTYPE_NMI +#define XCHAL_INT26_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT27_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT28_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT29_TYPE XTHAL_INTTYPE_PROFILING +#define XCHAL_INT30_TYPE XTHAL_INTTYPE_WRITE_ERROR +#define XCHAL_INT31_TYPE XTHAL_INTTYPE_SOFTWARE + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x007FFFFF +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x01800000 +#define XCHAL_INTTYPE_MASK_NMI 0x02000000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x80000000 +#define XCHAL_INTTYPE_MASK_TIMER 0x1C000000 +#define XCHAL_INTTYPE_MASK_ETIE 0x00000000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x40000000 +#define XCHAL_INTTYPE_MASK_DBG_REQUEST 0x00000000 +#define XCHAL_INTTYPE_MASK_BREAKIN 0x00000000 +#define XCHAL_INTTYPE_MASK_TRAX 0x00000000 +#define XCHAL_INTTYPE_MASK_PROFILING 0x20000000 +#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000 +#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_L2_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_L2_STATUS 0x00000000 +#define XCHAL_INTTYPE_MASK_COR_ECC_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_WWDT 0x00000000 +#define XCHAL_INTTYPE_MASK_FXLK 0x00000000 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 26 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 27 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT 28 /* CCOMPARE2 */ +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 25 /* non-maskable interrupt */ +#define XCHAL_WRITE_ERROR_INTERRUPT 30 +#define XCHAL_PROFILING_INTERRUPT 29 + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +#define XCHAL_INTLEVEL6_NUM 25 +/* (There are many interrupts each at level(s) 1, 2, 3, 4.) */ + +/* + * External interrupt mapping. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ +#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ +#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ +#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ +#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ +#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ +#define XCHAL_EXTINT6_NUM 6 /* (intlevel 1) */ +#define XCHAL_EXTINT7_NUM 7 /* (intlevel 1) */ +#define XCHAL_EXTINT8_NUM 8 /* (intlevel 2) */ +#define XCHAL_EXTINT9_NUM 9 /* (intlevel 2) */ +#define XCHAL_EXTINT10_NUM 10 /* (intlevel 2) */ +#define XCHAL_EXTINT11_NUM 11 /* (intlevel 2) */ +#define XCHAL_EXTINT12_NUM 12 /* (intlevel 2) */ +#define XCHAL_EXTINT13_NUM 13 /* (intlevel 2) */ +#define XCHAL_EXTINT14_NUM 14 /* (intlevel 2) */ +#define XCHAL_EXTINT15_NUM 15 /* (intlevel 2) */ +#define XCHAL_EXTINT16_NUM 16 /* (intlevel 3) */ +#define XCHAL_EXTINT17_NUM 17 /* (intlevel 3) */ +#define XCHAL_EXTINT18_NUM 18 /* (intlevel 3) */ +#define XCHAL_EXTINT19_NUM 19 /* (intlevel 3) */ +#define XCHAL_EXTINT20_NUM 20 /* (intlevel 4) */ +#define XCHAL_EXTINT21_NUM 21 /* (intlevel 4) */ +#define XCHAL_EXTINT22_NUM 22 /* (intlevel 4) */ +#define XCHAL_EXTINT23_NUM 23 /* (intlevel 3) */ +#define XCHAL_EXTINT24_NUM 24 /* (intlevel 3) */ +#define XCHAL_EXTINT25_NUM 25 /* (intlevel 6) */ +/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ +#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ +#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ +#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ +#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ +#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ +#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ +#define XCHAL_INT6_EXTNUM 6 /* (intlevel 1) */ +#define XCHAL_INT7_EXTNUM 7 /* (intlevel 1) */ +#define XCHAL_INT8_EXTNUM 8 /* (intlevel 2) */ +#define XCHAL_INT9_EXTNUM 9 /* (intlevel 2) */ +#define XCHAL_INT10_EXTNUM 10 /* (intlevel 2) */ +#define XCHAL_INT11_EXTNUM 11 /* (intlevel 2) */ +#define XCHAL_INT12_EXTNUM 12 /* (intlevel 2) */ +#define XCHAL_INT13_EXTNUM 13 /* (intlevel 2) */ +#define XCHAL_INT14_EXTNUM 14 /* (intlevel 2) */ +#define XCHAL_INT15_EXTNUM 15 /* (intlevel 2) */ +#define XCHAL_INT16_EXTNUM 16 /* (intlevel 3) */ +#define XCHAL_INT17_EXTNUM 17 /* (intlevel 3) */ +#define XCHAL_INT18_EXTNUM 18 /* (intlevel 3) */ +#define XCHAL_INT19_EXTNUM 19 /* (intlevel 3) */ +#define XCHAL_INT20_EXTNUM 20 /* (intlevel 4) */ +#define XCHAL_INT21_EXTNUM 21 /* (intlevel 4) */ +#define XCHAL_INT22_EXTNUM 22 /* (intlevel 4) */ +#define XCHAL_INT23_EXTNUM 23 /* (intlevel 3) */ +#define XCHAL_INT24_EXTNUM 24 /* (intlevel 3) */ +#define XCHAL_INT25_EXTNUM 25 /* (intlevel 6) */ + +#define XCHAL_HAVE_ISB 0 /* No ISB */ +#define XCHAL_ISB_VADDR 0 /* N/A */ +#define XCHAL_HAVE_ITB 0 /* No ITB */ +#define XCHAL_ITB_VADDR 0 /* N/A */ + +#define XCHAL_HAVE_KSL 0 /* Kernel Stack Limit */ +#define XCHAL_HAVE_ISL 0 /* Interrupt Stack Limit */ +#define XCHAL_HAVE_PSL 0 /* Pageable Stack Limit */ + +/*---------------------------------------------------------------------- + * EXCEPTIONS and VECTORS + *---------------------------------------------------------------------- + */ + +/* Xtensa Exception Architecture + * number: 1 == XEA1 (until T1050) + * 2 == XEA2 (LX) + * 3 == XEA3 (NX) + * 0 == XEA5 (RNX) + */ +#define XCHAL_XEA_VERSION 2 +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEA3 0 /* Exception Architecture 3 */ +#define XCHAL_HAVE_XEA5 0 /* Exception Architecture 5 */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_IMPRECISE_EXCEPTIONS 0 /* imprecise exception option */ +#define XCHAL_EXCCAUSE_NUM 64 /* Number of exceptions */ +#define XCHAL_HAVE_HALT 0 /* halt architecture option */ +#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0x4e100400 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x4e100400 +#define XCHAL_RESET_VECBASE_OVERLAP 0 /* UNUSED */ + +#define XCHAL_RESET_VECTOR0_VADDR 0x4e100000 +#define XCHAL_RESET_VECTOR0_PADDR 0x4e100000 +#define XCHAL_RESET_VECTOR1_VADDR 0x4e100680 +#define XCHAL_RESET_VECTOR1_PADDR 0x4e100680 +#define XCHAL_RESET_VECTOR_VADDR XCHAL_RESET_VECTOR1_VADDR +#define XCHAL_RESET_VECTOR_PADDR XCHAL_RESET_VECTOR1_PADDR +#define XCHAL_USER_VECOFS 0x0000023C +#define XCHAL_USER_VECTOR_VADDR 0x4e10063C +#define XCHAL_USER_VECTOR_PADDR 0x4e10063C +#define XCHAL_KERNEL_VECOFS 0x0000021C +#define XCHAL_KERNEL_VECTOR_VADDR 0x4e10061C +#define XCHAL_KERNEL_VECTOR_PADDR 0x4e10061C +#define XCHAL_DOUBLEEXC_VECOFS 0x0000025C +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x4e10065C +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x4e10065C +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0x4e100400 +#define XCHAL_WINDOW_VECTORS_PADDR 0x4e100400 +#define XCHAL_INTLEVEL2_VECOFS 0x0000017C +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x4e10057C +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x4e10057C +#define XCHAL_INTLEVEL3_VECOFS 0x0000019C +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x4e10059C +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x4e10059C +#define XCHAL_INTLEVEL4_VECOFS 0x000001BC +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x4e1005BC +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x4e1005BC +#define XCHAL_INTLEVEL5_VECOFS 0x000001DC +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x4e1005DC +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x4e1005DC +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL5_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL5_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL5_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x000001FC +#define XCHAL_NMI_VECTOR_VADDR 0x4e1005FC +#define XCHAL_NMI_VECTOR_PADDR 0x4e1005FC +#define XCHAL_INTLEVEL6_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL6_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL6_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR + +/*---------------------------------------------------------------------- + * DEBUG MODULE + *---------------------------------------------------------------------- + */ + +/* Misc */ +#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ +#define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */ +#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ + +/* On-Chip Debug (OCD) */ +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ +#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ + +/* TRAX (in core) */ +#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ +#define XCHAL_TRAX_MEM_SIZE 4096 /* TRAX memory size in bytes */ +#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ +#define XCHAL_TRAX_ATB_WIDTH 32 /* ATB width (bits), 0=no ATB */ +#define XCHAL_TRAX_TIME_WIDTH 64 /* timestamp bitwidth, 0=none */ + +/* Perf counters */ +#define XCHAL_NUM_PERF_COUNTERS 8 /* performance counters */ + +/*---------------------------------------------------------------------- + * MMU + *---------------------------------------------------------------------- + */ + +/* See core-matmap.h header file for more details. */ +#define XCHAL_HAVE_TLBS 0 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */ +#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +/* full MMU (with page table [autorefill] and protection) usable for an MMU-based OS */ +#define XCHAL_HAVE_PTP_MMU 0 + +/* If none of the above last 5 are set, it's a custom TLB configuration. */ + +#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ + +/*---------------------------------------------------------------------- + * MPU + *---------------------------------------------------------------------- + */ +#define XCHAL_HAVE_MPU 1 +#define XCHAL_MPU_ENTRIES 32 +#define XCHAL_MPU_LOCK 1 + +/* MPU requires alignment of entries to background map */ +#define XCHAL_MPU_ALIGN_REQ 1 +#define XCHAL_MPU_BACKGROUND_ENTRIES 2 /* number of entries in bg map*/ +#define XCHAL_MPU_BG_CACHEADRDIS 0xFF /* default CACHEADRDIS for bg */ + +#define XCHAL_MPU_ALIGN_BITS 7 +#define XCHAL_MPU_ALIGN 128 + +/*----------------------------------------------------------------------- + * CSR Parity + *------------------------------------------------------------------------ + */ +#define XCHAL_HAVE_CSR_PARITY 0 + + +/*---------------------------------------------------------------------- + * FLEX-LOCK + *------------------------------------------------------------------------ + */ + +#define XCHAL_HAVE_FXLK 0 + +/*---------------------------------------------------------------------- + * WWDT (Windowed Watchdog Timer) + *------------------------------------------------------------------------ + */ +#define XCHAL_HAVE_WWDT 0 +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + +#endif /* XTENSA_CORE_CONFIGURATION_H_ */ + diff --git a/src/platform/mt8196/include/arch/xtensa/config/core-matmap.h b/src/platform/mt8196/include/arch/xtensa/config/core-matmap.h new file mode 100644 index 000000000000..a35a16752f8b --- /dev/null +++ b/src/platform/mt8196/include/arch/xtensa/config/core-matmap.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * xtensa/config/core-matmap.h -- Memory access and translation mapping + * parameters (CHAL) of the Xtensa processor core configuration. + * + * If you are using Xtensa Tools, see (which includes + * this file) for more details. + * + * In the Xtensa processor products released to date, all parameters + * defined in this file are derivable (at least in theory) from + * information contained in the core-isa.h header file. + * In particular, the following core configuration parameters are relevant: + * XCHAL_HAVE_CACHEATTR + * XCHAL_HAVE_MIMIC_CACHEATTR + * XCHAL_HAVE_XLT_CACHEATTR + * XCHAL_HAVE_PTP_MMU + * XCHAL_ITLB_ARF_ENTRIES_LOG2 + * XCHAL_DTLB_ARF_ENTRIES_LOG2 + * XCHAL_DCACHE_IS_WRITEBACK + * XCHAL_ICACHE_SIZE (presence of I-cache) + * XCHAL_DCACHE_SIZE (presence of D-cache) + * XCHAL_HW_VERSION_MAJOR + * XCHAL_HW_VERSION_MINOR + */ + +/* Customer ID=7578; Build=0xa69ab; Copyright (c) 1999-2023 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef XTENSA_CONFIG_CORE_MATMAP_H +#define XTENSA_CONFIG_CORE_MATMAP_H + +/*---------------------------------------------------------------------- + * CACHE (MEMORY ACCESS) ATTRIBUTES + *---------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------- + * MPU + *---------------------------------------------------------------------- + */ + +/* Mappings for legacy constants where appropriate */ + +#define XCHAL_CA_WRITEBACK (XTHAL_MEM_WRITEBACK | XTHAL_AR_RWXrwx) + +#define XCHAL_CA_WRITEBACK_NOALLOC (XTHAL_MEM_WRITEBACK_NOALLOC | XTHAL_AR_RWXrwx) + +#define XCHAL_CA_WRITETHRU (XTHAL_MEM_WRITETHRU | XTHAL_AR_RWXrwx) + +#define XCHAL_CA_ILLEGAL (XTHAL_AR_NONE | XTHAL_MEM_DEVICE) +#define XCHAL_CA_BYPASS (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE) +#define XCHAL_CA_BYPASSBUF (XTHAL_AR_RWXrwx | XTHAL_MEM_DEVICE |\ +XTHAL_MEM_BUFFERABLE) +#define XCHAL_CA_BYPASS_RX (XTHAL_AR_RX | XTHAL_MEM_DEVICE) +#define XCHAL_CA_BYPASS_RW (XTHAL_AR_RW | XTHAL_MEM_DEVICE) +#define XCHAL_CA_BYPASS_R (XTHAL_AR_R | XTHAL_MEM_DEVICE) +#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 1 + +/* + * Contents of MPU background map. + * NOTE: caller must define the XCHAL_MPU_BGMAP() macro (not defined here + * but specified below) before expanding the XCHAL_MPU_BACKGROUND_MAP(s) macro. + * + * XCHAL_MPU_BGMAP(s, vaddr_start, vaddr_last, rights, memtype, x...) + * + * s = passed from XCHAL_MPU_BACKGROUND_MAP(s), eg. to select how to expand + * vaddr_start = first byte of region (always 0 for first entry) + * vaddr_end = last byte of region (always 0xFFFFFFFF for last entry) + * rights = access rights + * memtype = memory type + * x = reserved for future use (0 until then) + */ +/* parasoft-begin-suppress MISRA2012-RULE-20_7 "Macro use model requires s to not be in ()" */ +#define XCHAL_MPU_BACKGROUND_MAP(s) (\ +XCHAL_MPU_BGMAP(s, 0x00000000, 0x7fffffff, 7, 6, 0) \ +XCHAL_MPU_BGMAP(s, 0x80000000, 0xffffffff, 7, 6, 0) \) +/* parasoft-end-suppress MISRA2012-RULE-20_7 "Macro use model requires s to not be in ()" */ + +/* end */ + +#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/ + diff --git a/src/platform/mt8196/include/arch/xtensa/config/defs.h b/src/platform/mt8196/include/arch/xtensa/config/defs.h new file mode 100644 index 000000000000..18ee59f671b3 --- /dev/null +++ b/src/platform/mt8196/include/arch/xtensa/config/defs.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* Definitions for Xtensa instructions, types, and protos. */ + +/* Customer ID = 7578; Build = 0xa69ab; Copyright (c) 2003-2004 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* NOTE: This file exists only for backward compatibility with T1050 + * and earlier Xtensa releases. It includes only a subset of the + * available header files. + */ + +#ifndef _XTENSA_BASE_HEADER +#define _XTENSA_BASE_HEADER + +#ifdef __XTENSA__ + +#include +#include +#include + +#endif /* __XTENSA__ */ +#endif /* !_XTENSA_BASE_HEADER */ diff --git a/src/platform/mt8196/include/arch/xtensa/config/key.h b/src/platform/mt8196/include/arch/xtensa/config/key.h new file mode 100644 index 000000000000..61a1fa79ed1c --- /dev/null +++ b/src/platform/mt8196/include/arch/xtensa/config/key.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Customer ID = 7578; Build = 0xa69ab; Copyright (c) 2020-2021 by Cadence Design Systems. Inc. + * ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Cadence Design Systems Inc. + */ + +#ifndef TENSILICA_CONFIG_KEY +#define TENSILICA_CONFIG_KEY 1 + +#include + +#endif + diff --git a/src/platform/mt8196/include/arch/xtensa/config/secure.h b/src/platform/mt8196/include/arch/xtensa/config/secure.h new file mode 100644 index 000000000000..8d46c3eb0257 --- /dev/null +++ b/src/platform/mt8196/include/arch/xtensa/config/secure.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* Secure Mode defines. */ + +/* Customer ID = 7578; Build = 0xa69ab; Copyright (c) 2020 Cadence Design Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef XTENSA_SECURE_H +#define XTENSA_SECURE_H + +/* SRAM */ +#define XCHAL_HAVE_SECURE_SRAM 0 + +/* INSTRAM0 */ +#define XCHAL_HAVE_SECURE_INSTRAM0 0 + +/* DATARAM1 */ +#define XCHAL_HAVE_SECURE_DATARAM1 0 + +/* DATARAM0 */ +#define XCHAL_HAVE_SECURE_DATARAM0 0 + +/* Array of all secure regions' start/size */ +#define XCHAL_SECURE_MEM_LIST \ +{ \ +} + +#endif /* XTENSA_SECURE_H */ + diff --git a/src/platform/mt8196/include/arch/xtensa/config/specreg.h b/src/platform/mt8196/include/arch/xtensa/config/specreg.h new file mode 100644 index 000000000000..e2ef5d4dd469 --- /dev/null +++ b/src/platform/mt8196/include/arch/xtensa/config/specreg.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Xtensa Special Register symbolic names + */ + +/* Id: + * //depot/rel/Homewood/ib.11/Xtensa/SWConfig/hal/specreg.h.tpp#1 + */ + +/* Customer ID = 7578; Build = 0xa69ab; Copyright (c) 1998-2002 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef XTENSA_SPECREG_H +#define XTENSA_SPECREG_H + +/* Include these special register bitfield definitions, for historical reasons: */ +#include + +/* Special registers: */ +#define LBEG 0 +#define LEND 1 +#define LCOUNT 2 +#define SAR 3 +#define BR 4 +#define PREFCTL 40 +#define WINDOWBASE 72 +#define WINDOWSTART 73 +#define MPUENB 90 +#define ERACCESS 95 +#define IBREAKENABLE 96 +#define MEMCTL 97 +#define CACHEADRDIS 98 +#define DDR 104 +#define IBREAKA_0 128 +#define IBREAKA_1 129 +#define DBREAKA_0 144 +#define DBREAKA_1 145 +#define DBREAKC_0 160 +#define DBREAKC_1 161 +#define EPC_1 177 +#define EPC_2 178 +#define EPC_3 179 +#define EPC_4 180 +#define EPC_5 181 +#define EPC_6 182 +#define DEPC 192 +#define EPS_2 194 +#define EPS_3 195 +#define EPS_4 196 +#define EPS_5 197 +#define EPS_6 198 +#define EXCSAVE_1 209 +#define EXCSAVE_2 210 +#define EXCSAVE_3 211 +#define EXCSAVE_4 212 +#define EXCSAVE_5 213 +#define EXCSAVE_6 214 +#define CPENABLE 224 +#define INTERRUPT 226 +#define INTCLEAR 227 +#define INTENABLE 228 +#define PS 230 +#define VECBASE 231 +#define EXCCAUSE 232 +#define DEBUGCAUSE 233 +#define CCOUNT 234 +#define PRID 235 +#define ICOUNT 236 +#define ICOUNTLEVEL 237 +#define EXCVADDR 238 +#define CCOMPARE_0 240 +#define CCOMPARE_1 241 +#define CCOMPARE_2 242 +#define MISC_REG_0 244 +#define MISC_REG_1 245 +#define MISC_REG_2 246 +#define MISC_REG_3 247 + +/* Special cases (bases of special register series): */ +#define IBREAKA 128 +#define DBREAKA 144 +#define DBREAKC 160 +#define EPC 176 +#define EPS 192 +#define EXCSAVE 208 +#define CCOMPARE 240 + +/* Special names for read-only and write-only interrupt registers: */ +#define INTREAD 226 +#define INTSET 226 + +#endif /* XTENSA_SPECREG_H */ + diff --git a/src/platform/mt8196/include/arch/xtensa/config/system.h b/src/platform/mt8196/include/arch/xtensa/config/system.h new file mode 100644 index 000000000000..77b6a105f71f --- /dev/null +++ b/src/platform/mt8196/include/arch/xtensa/config/system.h @@ -0,0 +1,293 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration + * + * NOTE: The location and contents of this file are highly subject to change. + * + * Source for configuration-independent binaries (which link in a + * configuration-specific HAL library) must NEVER include this file. + * The HAL itself has historically included this file in some instances, + * but this is not appropriate either, because the HAL is meant to be + * core-specific but system independent. + */ + +/* Customer ID = 7578; Build = 0xa69ab; Copyright (c) 2000-2010 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef XTENSA_CONFIG_SYSTEM_H +#define XTENSA_CONFIG_SYSTEM_H + +/*---------------------------------------------------------------------- + * CONFIGURED SOFTWARE OPTIONS + *---------------------------------------------------------------------- + */ + +/* (sw-only option, whether software uses absolute literals) */ +#define XSHAL_USE_ABSOLUTE_LITERALS 0 +/* Set if there is some memory that allows both code and literals. */ +#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 + +/* (sw-only option, selected ABI) */ +#define XSHAL_ABI XTHAL_ABI_WINDOWED +/* The above maps to one of the following constants: */ +#define XTHAL_ABI_WINDOWED 0 +#define XTHAL_ABI_CALL0 1 + +/* (sw-only option, selected C library) */ +#define XSHAL_CLIB XTHAL_CLIB_XCLIB +/* The above maps to one of the following constants: */ +#define XTHAL_CLIB_NEWLIB 0 +#define XTHAL_CLIB_UCLIBC 1 +#define XTHAL_CLIB_XCLIB 2 + +#define XSHAL_USE_FLOATING_POINT 1 + +#define XSHAL_FLOATING_POINT_ABI 1 + +/* SW workarounds enabled for HW errata: */ + +/*---------------------------------------------------------------------- + * DEVICE ADDRESSES + *---------------------------------------------------------------------- + */ + +/* + * Strange place to find these, but the configuration GUI + * allows moving these around to account for various core + * configurations. Specific boards (and their BSP software) + * will have specific meanings for these components. + */ + +/* I/O Block areas: */ +#define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000 +#define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000 +#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 + +#define XSHAL_IOBLOCK_BYPASS_VADDR 0x90000000 +#define XSHAL_IOBLOCK_BYPASS_PADDR 0x90000000 +#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000 + +/* System ROM: */ + +/* System RAM: */ +#define XSHAL_RAM_VADDR 0x40000000 +#define XSHAL_RAM_PADDR 0x40000000 +#define XSHAL_RAM_VSIZE 0x80000000 +#define XSHAL_RAM_PSIZE 0x80000000 +#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE +/* Largest available area (free of vectors): */ +#define XSHAL_RAM_AVAIL_VADDR 0x50000000 +#define XSHAL_RAM_AVAIL_VSIZE 0x80000000 + +/* + * Shadow system RAM (same device as system RAM, at different address). + * (Emulation boards need this for the SONIC Ethernet driver + * when data caches are configured for writeback mode.) + * NOTE: on full MMU configs, this points to the BYPASS virtual address + * of system RAM, ie. is the same as XSHAL_RAM_* except that virtual + * addresses are viewed through the BYPASS static map rather than + * the CACHED static map. + */ +#define XSHAL_RAM_BYPASS_VADDR 0x20000000 +#define XSHAL_RAM_BYPASS_PADDR 0x20000000 +#define XSHAL_RAM_BYPASS_PSIZE 0x20000000 + +/* Alternate system RAM (different device than system RAM): */ + +/* Some available location in which to place devices in a simulation (eg. XTMP): */ +#define XSHAL_SIMIO_CACHED_VADDR 0x20000000 +#define XSHAL_SIMIO_BYPASS_VADDR 0x20000000 +#define XSHAL_SIMIO_PADDR 0x20000000 +#define XSHAL_SIMIO_SIZE 0x20000000 + +/*---------------------------------------------------------------------- + * For use by reference testbench exit and diagnostic routines. + *---------------------------------------------------------------------- + */ +#define XSHAL_MAGIC_EXIT 0xdeeeb400 +#define XSHAL_STL_INFO_LOCATION 0xfffffffc + +/*---------------------------------------------------------------------- + * DEVICE-ADDRESS DEPENDENT... + * + * Values written to CACHEATTR special register (or its equivalent) + * to enable and disable caches in various modes. + *---------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------- + * BACKWARD COMPATIBILITY ... + *---------------------------------------------------------------------- + */ + +/* + * NOTE: the following two macros are DEPRECATED. Use the latter + * board-specific macros instead, which are specially tuned for the + * particular target environments' memory maps. + */ +/* disable caches in bypass mode */ +#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS +/* default setting to enable caches (no writeback!) */ +#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT + +/*---------------------------------------------------------------------- + * GENERIC + *---------------------------------------------------------------------- + */ + +/* For the following, a 512MB region is used if it contains a system (PIF) RAM, + * system (PIF) ROM, local memory, or XLMI. + */ + +/* These set any unused 512MB region to cache-BYPASS attribute: */ +/* enable caches in write-back mode */ +#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x24444422 +/* enable caches in write-allocate mode */ +#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x21111122 +/* enable caches in write-through mode */ +#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x21111122 +/* disable caches in bypass mode */ +#define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 +/* default setting to enable caches */ +#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK + +/* These set any unused 512MB region to ILLEGAL attribute: */ +/* enable caches in write-back mode */ +#define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xF44444FF +/* enable caches in write-allocate mode */ +#define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xF11111FF +/* enable caches in write-through mode */ +#define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xF11111FF +/* disable caches in bypass mode */ +#define XSHAL_STRICT_CACHEATTR_BYPASS 0xF22222FF +/* default setting to enable caches */ +#define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK + +/* These set the first 512MB, if unused, to ILLEGAL attribute to help catch + * NULL-pointer dereference bugs; all other unused 512MB regions are set + * to cache-BYPASS attribute: + */ +/* enable caches in write-back mode */ +#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2444442F +/* enable caches in write-allocate mode */ +#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2111112F +/* enable caches in write-through mode */ +#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2111112F +/* disable caches in bypass mode */ +#define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F +/* default setting to enable caches */ +#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK + +/*---------------------------------------------------------------------- + *ISS (Instruction Set Simulator) SPECIFIC ... + *---------------------------------------------------------------------- + */ + +/* For now, ISS defaults to the TRAPNULL settings: */ +#define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK +#define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC +#define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU +#define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS +#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK + +#define XSHAL_ISS_PIPE_REGIONS 0 +#define XSHAL_ISS_SDRAM_REGIONS 0 + +/*---------------------------------------------------------------------- + * XT2000 BOARD SPECIFIC ... + *---------------------------------------------------------------------- + */ + +/* For the following, a 512MB region is used if it contains any system RAM, + * system ROM, local memory, XLMI, or other XT2000 board device or memory. + * Regions containing devices are forced to cache-BYPASS mode regardless + * of whether the macro is _WRITEBACK vs. _BYPASS etc. + */ + +/* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */ +/* enable caches in write-back mode */ +#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xF442442F +/* enable caches in write-allocate mode */ +#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xF112112F +/* enable caches in write-through mode */ +#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xF112112F +/* disable caches in bypass mode */ +#define XSHAL_XT2000_CACHEATTR_BYPASS 0xF222222F +/* default setting to enable caches */ +#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK + +#define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */ +#define XSHAL_XT2000_SDRAM_REGIONS 0x00000024 /* BusInt SDRAM regions */ + +/*---------------------------------------------------------------------- + * VECTOR INFO AND SIZES + *---------------------------------------------------------------------- + */ + +#define XSHAL_VECTORS_PACKED 0 /* UNUSED */ +#define XSHAL_STATIC_VECTOR_SELECT 1 +#define XSHAL_RESET_VECTOR_VADDR 0x4e100680 +#define XSHAL_RESET_VECTOR_PADDR 0x4e100680 + +/* + * Sizes allocated to vectors by the system (memory map) configuration. + * These sizes are constrained by core configuration (eg. one vector's + * code cannot overflow into another vector) but are dependent on the + * system or board (or LSP) memory map configuration. + * + * Whether or not each vector happens to be in a system ROM is also + * a system configuration matter, sometimes useful, included here also: + */ +#define XSHAL_RESET_VECTOR_SIZE 0x000002E0 +#define XSHAL_RESET_VECTOR_ISROM 0 +#define XSHAL_USER_VECTOR_SIZE 0x0000001C +#define XSHAL_USER_VECTOR_ISROM 0 +/* for backward compatibility */ +#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE +/* for backward compatibility */ +#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE +#define XSHAL_KERNEL_VECTOR_SIZE 0x0000001C +#define XSHAL_KERNEL_VECTOR_ISROM 0 +/* for backward compatibility */ +#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE +/* for backward compatibility */ +#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE +#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x0000001C +#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0 +#define XSHAL_WINDOW_VECTORS_SIZE 0x00000178 +#define XSHAL_WINDOW_VECTORS_ISROM 0 +#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x0000001C +#define XSHAL_INTLEVEL2_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x0000001C +#define XSHAL_INTLEVEL3_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x0000001C +#define XSHAL_INTLEVEL4_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL5_VECTOR_SIZE 0x0000001C +#define XSHAL_INTLEVEL5_VECTOR_ISROM 0 +#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL5_VECTOR_SIZE +#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL5_VECTOR_ISROM +#define XSHAL_NMI_VECTOR_SIZE 0x0000001C +#define XSHAL_NMI_VECTOR_ISROM 0 +#define XSHAL_INTLEVEL6_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE + +#endif /*XTENSA_CONFIG_SYSTEM_H*/ + diff --git a/src/platform/mt8196/include/arch/xtensa/config/tie-asm.h b/src/platform/mt8196/include/arch/xtensa/config/tie-asm.h new file mode 100644 index 000000000000..ebef0818d327 --- /dev/null +++ b/src/platform/mt8196/include/arch/xtensa/config/tie-asm.h @@ -0,0 +1,362 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE + * + * NOTE: This header file is not meant to be included directly. + */ + +/* This header file contains assembly-language definitions (assembly + * macros, etc.) for this specific Xtensa processor's TIE extensions + * and options. It is customized to this Xtensa processor configuration. + * + * Customer ID = 7578; Build = 0xa69ab; Copyright (c) 1999-2023 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _XTENSA_CORE_TIE_ASM_H +#define _XTENSA_CORE_TIE_ASM_H + +#include + +/* Selection parameter values for save-area save/restore macros: */ +/* Option vs. TIE: */ +#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ +#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ +#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ +/* Whether used automatically by compiler: */ +#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ +#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ +#define XTHAL_SAS_ANYCC 0x000C /* both of the above */ +/* ABI handling across function calls: */ +#define XTHAL_SAS_CALR 0x0010 /* caller-saved */ +#define XTHAL_SAS_CALE 0x0020 /* callee-saved */ +#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ +#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ +/* Misc */ +#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ +#define XTHAL_SAS3(optie, ccuse, abi) (((optie) & XTHAL_SAS_ANYOT) \ +| ((ccuse) & XTHAL_SAS_ANYCC) \ +| ((abi) & XTHAL_SAS_ANYABI)) + +/* + * Macro to store all non-coprocessor (extra) custom TIE and optional state + * (not including zero-overhead loop registers). + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 4 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters: + * continue If macro invoked as part of a larger store sequence, set to 1 + * if this is not the first in the sequence. Defaults to 0. + * ofs Offset from start of larger sequence (from value of first ptr + * in sequence) at which to store. Defaults to next available space + * (or 0 if is 0). + * select Select what category(ies) of registers to store, as a bitmask + * (see XTHAL_SAS_xxx constants). Defaults to all registers. + * alloc Select what category(ies) of registers to allocate; if any + * category is selected here that is not in , space for + * the corresponding registers is skipped without doing any load. + */ +.macro xchal_ncp_load ptr at1 at2 at3 at4 continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0 +xchal_sa_start \continue, \ofs +// Optional global registers used by default by the compiler: +.ifeq(XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) +xchal_sa_align \ptr, 0, 1016, 4, 4 +l32i \at1, \ptr, .Lxchal_ofs_ + 0 +wur.threadptr \at1 // threadptr option +.set .Lxchal_ofs_, .Lxchal_ofs_ + 4 +.elseif((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 +xchal_sa_align \ptr, 0, 1016, 4, 4 +.set .Lxchal_ofs_, .Lxchal_ofs_ + 4 +.endif +// Optional caller-saved registers not used by default by the compiler: +.ifeq(XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) +xchal_sa_align \ptr, 0, 1016, 4, 4 +l32i \at1, \ptr, .Lxchal_ofs_ + 0 +wsr.br \at1 // boolean option +.set .Lxchal_ofs_, .Lxchal_ofs_ + 4 +.elseif((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 +xchal_sa_align \ptr, 0, 1016, 4, 4 +.set .Lxchal_ofs_, .Lxchal_ofs_ + 4 +.endif +.endm // xchal_ncp_load + +#define XCHAL_NCP_NUM_ATMPS 1 + +/* + * Macro to store the state of TIE coprocessor AudioEngineLX. + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 16 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters are the same as for xchal_ncp_store. + */ +#define xchal_cp_AudioEngineLX_store xchal_cp1_store +.macro xchal_cp1_store ptr at1 at2 at3 at4 continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0 +xchal_sa_start \continue, \ofs +// Custom caller-saved registers not used by default by the compiler: +.ifeq(XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) +xchal_sa_align \ptr, 0, 0, 16, 16 +ae_s64.i aed0, \ptr, .Lxchal_ofs_ + 56 +addi.a \ptr, \ptr, 64 +ae_s64.i aed1, \ptr, .Lxchal_ofs_ + 0 +ae_s64.i aed2, \ptr, .Lxchal_ofs_ + 8 +ae_s64.i aed3, \ptr, .Lxchal_ofs_ + 16 +ae_s64.i aed4, \ptr, .Lxchal_ofs_ + 24 +ae_s64.i aed5, \ptr, .Lxchal_ofs_ + 32 +ae_s64.i aed6, \ptr, .Lxchal_ofs_ + 40 +ae_s64.i aed7, \ptr, .Lxchal_ofs_ + 48 +ae_s64.i aed8, \ptr, .Lxchal_ofs_ + 56 +addi.a \ptr, \ptr, 64 +ae_s64.i aed9, \ptr, .Lxchal_ofs_ + 0 +ae_s64.i aed10, \ptr, .Lxchal_ofs_ + 8 +ae_s64.i aed11, \ptr, .Lxchal_ofs_ + 16 +ae_s64.i aed12, \ptr, .Lxchal_ofs_ + 24 +ae_s64.i aed13, \ptr, .Lxchal_ofs_ + 32 +ae_s64.i aed14, \ptr, .Lxchal_ofs_ + 40 +ae_s64.i aed15, \ptr, .Lxchal_ofs_ + 48 +ae_s64.i aed16, \ptr, .Lxchal_ofs_ + 56 +addi.a \ptr, \ptr, 64 +ae_s64.i aed17, \ptr, .Lxchal_ofs_ + 0 +ae_s64.i aed18, \ptr, .Lxchal_ofs_ + 8 +ae_s64.i aed19, \ptr, .Lxchal_ofs_ + 16 +ae_s64.i aed20, \ptr, .Lxchal_ofs_ + 24 +ae_s64.i aed21, \ptr, .Lxchal_ofs_ + 32 +ae_s64.i aed22, \ptr, .Lxchal_ofs_ + 40 +ae_s64.i aed23, \ptr, .Lxchal_ofs_ + 48 +ae_s64.i aed24, \ptr, .Lxchal_ofs_ + 56 +addi.a \ptr, \ptr, 64 +ae_s64.i aed25, \ptr, .Lxchal_ofs_ + 0 +ae_s64.i aed26, \ptr, .Lxchal_ofs_ + 8 +ae_s64.i aed27, \ptr, .Lxchal_ofs_ + 16 +ae_s64.i aed28, \ptr, .Lxchal_ofs_ + 24 +ae_s64.i aed29, \ptr, .Lxchal_ofs_ + 32 +ae_s64.i aed30, \ptr, .Lxchal_ofs_ + 40 +ae_s64.i aed31, \ptr, .Lxchal_ofs_ + 48 +ae_movae \at1, aep0 +s8i \at1, \ptr, .Lxchal_ofs_ + 56 +ae_movae \at1, aep1 +s8i \at1, \ptr, .Lxchal_ofs_ + 57 +ae_movae \at1, aep2 +s8i \at1, \ptr, .Lxchal_ofs_ + 58 +ae_movae \at1, aep3 +s8i \at1, \ptr, .Lxchal_ofs_ + 59 +addi.a \ptr, \ptr, 64 +ae_salign128.i u0, \ptr, .Lxchal_ofs_ + 0 +ae_salign128.i u1, \ptr, .Lxchal_ofs_ + 16 +ae_salign128.i u2, \ptr, .Lxchal_ofs_ + 32 +ae_salign128.i u3, \ptr, .Lxchal_ofs_ + 48 +addi.a \ptr, \ptr, -320 +ae_movdrzbvc aed0 // ureg AE_ZBIASV8C +ae_s64.i aed0, \ptr, .Lxchal_ofs_ + 0 + 0 +ae_movvfcrfsr aed0 // ureg FCR_FSR +ae_s64.i aed0, \ptr, .Lxchal_ofs_ + 8 + 0 +rur.ae_ovf_sar \at1 // ureg 240 +s32i \at1, \ptr, .Lxchal_ofs_ + 16 +rur.ae_bithead \at1 // ureg 241 +s32i \at1, \ptr, .Lxchal_ofs_ + 20 +rur.ae_ts_fts_bu_bp \at1 // ureg 242 +s32i \at1, \ptr, .Lxchal_ofs_ + 24 +rur.ae_cw_sd_no \at1 // ureg 243 +s32i \at1, \ptr, .Lxchal_ofs_ + 28 +rur.ae_cbegin0 \at1 // ureg 246 +s32i \at1, \ptr, .Lxchal_ofs_ + 32 +rur.ae_cend0 \at1 // ureg 247 +s32i \at1, \ptr, .Lxchal_ofs_ + 36 +rur.ae_cbegin1 \at1 // ureg 248 +s32i \at1, \ptr, .Lxchal_ofs_ + 40 +rur.ae_cend1 \at1 // ureg 249 +s32i \at1, \ptr, .Lxchal_ofs_ + 44 +rur.ae_cbegin2 \at1 // ureg 250 +s32i \at1, \ptr, .Lxchal_ofs_ + 48 +rur.ae_cend2 \at1 // ureg 251 +s32i \at1, \ptr, .Lxchal_ofs_ + 52 +.set .Lxchal_ofs_, .Lxchal_ofs_ + 384 +.elseif((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 +xchal_sa_align \ptr, 0, 0, 16, 16 +.set .Lxchal_ofs_, .Lxchal_ofs_ + 384 +.endif +.endm // xchal_cp1_store + +/* + * Macro to load the state of TIE coprocessor AudioEngineLX. + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 16 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters are the same as for xchal_ncp_load. + */ +#define xchal_cp_AudioEngineLX_load xchal_cp1_load +.macro xchal_cp1_load ptr at1 at2 at3 at4 continue = 0 ofs = -1 select = XTHAL_SAS_ALL alloc = 0 +xchal_sa_start \continue, \ofs +// Custom caller-saved registers not used by default by the compiler: +.ifeq(XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) +xchal_sa_align \ptr, 0, 0, 16, 16 +ae_l64.i aed0, \ptr, .Lxchal_ofs_ + 0 + 0 // ureg AE_ZBIASV8C +ae_movzbvcdr aed0 +ae_l64.i aed0, \ptr, .Lxchal_ofs_ + 8 + 0 // ureg FCR_FSR +ae_movfcrfsrv aed0 +l32i \at1, \ptr, .Lxchal_ofs_ + 16 +wur.ae_ovf_sar \at1 // ureg 240 +l32i \at1, \ptr, .Lxchal_ofs_ + 20 +wur.ae_bithead \at1 // ureg 241 +l32i \at1, \ptr, .Lxchal_ofs_ + 24 +wur.ae_ts_fts_bu_bp \at1 // ureg 242 +l32i \at1, \ptr, .Lxchal_ofs_ + 28 +wur.ae_cw_sd_no \at1 // ureg 243 +l32i \at1, \ptr, .Lxchal_ofs_ + 32 +wur.ae_cbegin0 \at1 // ureg 246 +l32i \at1, \ptr, .Lxchal_ofs_ + 36 +wur.ae_cend0 \at1 // ureg 247 +l32i \at1, \ptr, .Lxchal_ofs_ + 40 +wur.ae_cbegin1 \at1 // ureg 248 +l32i \at1, \ptr, .Lxchal_ofs_ + 44 +wur.ae_cend1 \at1 // ureg 249 +l32i \at1, \ptr, .Lxchal_ofs_ + 48 +wur.ae_cbegin2 \at1 // ureg 250 +l32i \at1, \ptr, .Lxchal_ofs_ + 52 +wur.ae_cend2 \at1 // ureg 251 +ae_l64.i aed0, \ptr, .Lxchal_ofs_ + 56 +addi.a \ptr, \ptr, 64 +ae_l64.i aed1, \ptr, .Lxchal_ofs_ + 0 +ae_l64.i aed2, \ptr, .Lxchal_ofs_ + 8 +ae_l64.i aed3, \ptr, .Lxchal_ofs_ + 16 +ae_l64.i aed4, \ptr, .Lxchal_ofs_ + 24 +ae_l64.i aed5, \ptr, .Lxchal_ofs_ + 32 +ae_l64.i aed6, \ptr, .Lxchal_ofs_ + 40 +ae_l64.i aed7, \ptr, .Lxchal_ofs_ + 48 +ae_l64.i aed8, \ptr, .Lxchal_ofs_ + 56 +addi.a \ptr, \ptr, 64 +ae_l64.i aed9, \ptr, .Lxchal_ofs_ + 0 +ae_l64.i aed10, \ptr, .Lxchal_ofs_ + 8 +ae_l64.i aed11, \ptr, .Lxchal_ofs_ + 16 +ae_l64.i aed12, \ptr, .Lxchal_ofs_ + 24 +ae_l64.i aed13, \ptr, .Lxchal_ofs_ + 32 +ae_l64.i aed14, \ptr, .Lxchal_ofs_ + 40 +ae_l64.i aed15, \ptr, .Lxchal_ofs_ + 48 +ae_l64.i aed16, \ptr, .Lxchal_ofs_ + 56 +addi.a \ptr, \ptr, 64 +ae_l64.i aed17, \ptr, .Lxchal_ofs_ + 0 +ae_l64.i aed18, \ptr, .Lxchal_ofs_ + 8 +ae_l64.i aed19, \ptr, .Lxchal_ofs_ + 16 +ae_l64.i aed20, \ptr, .Lxchal_ofs_ + 24 +ae_l64.i aed21, \ptr, .Lxchal_ofs_ + 32 +ae_l64.i aed22, \ptr, .Lxchal_ofs_ + 40 +ae_l64.i aed23, \ptr, .Lxchal_ofs_ + 48 +ae_l64.i aed24, \ptr, .Lxchal_ofs_ + 56 +addi.a \ptr, \ptr, 64 +ae_l64.i aed25, \ptr, .Lxchal_ofs_ + 0 +ae_l64.i aed26, \ptr, .Lxchal_ofs_ + 8 +ae_l64.i aed27, \ptr, .Lxchal_ofs_ + 16 +ae_l64.i aed28, \ptr, .Lxchal_ofs_ + 24 +ae_l64.i aed29, \ptr, .Lxchal_ofs_ + 32 +ae_l64.i aed30, \ptr, .Lxchal_ofs_ + 40 +ae_l64.i aed31, \ptr, .Lxchal_ofs_ + 48 +addi.a \ptr, \ptr, 56 +l8ui \at1, \ptr, .Lxchal_ofs_ + 0 +ae_movea aep0, \at1 +l8ui \at1, \ptr, .Lxchal_ofs_ + 1 +ae_movea aep1, \at1 +l8ui \at1, \ptr, .Lxchal_ofs_ + 2 +ae_movea aep2, \at1 +l8ui \at1, \ptr, .Lxchal_ofs_ + 3 +ae_movea aep3, \at1 +addi.a \ptr, \ptr, 8 +ae_lalign128.i u0, \ptr, .Lxchal_ofs_ + 0 +ae_lalign128.i u1, \ptr, .Lxchal_ofs_ + 16 +ae_lalign128.i u2, \ptr, .Lxchal_ofs_ + 32 +ae_lalign128.i u3, \ptr, .Lxchal_ofs_ + 48 +.set .Lxchal_pofs_, .Lxchal_pofs_ + 320 +.set .Lxchal_ofs_, .Lxchal_ofs_ + 64 +.elseif((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 +xchal_sa_align \ptr, 0, 0, 16, 16 +.set .Lxchal_ofs_, .Lxchal_ofs_ + 384 +.endif +.endm // xchal_cp1_load + +#define XCHAL_CP1_NUM_ATMPS 1 +#define XCHAL_SA_NUM_ATMPS 1 + +/* Empty macros for unconfigured coprocessors: */ +.macro xchal_cp0_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm +.macro xchal_cp0_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm +.macro xchal_cp2_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm +.macro xchal_cp2_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm +.macro xchal_cp3_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm +.macro xchal_cp3_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm +.macro xchal_cp4_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm +.macro xchal_cp4_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm +.macro xchal_cp5_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm +.macro xchal_cp5_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm +.macro xchal_cp6_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm +.macro xchal_cp6_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm +.macro xchal_cp7_store p a b c d continue = 0 ofs = -1 select = -1 ; .endm +.macro xchal_cp7_load p a b c d continue = 0 ofs = -1 select = -1 ; .endm + +#endif /*_XTENSA_CORE_TIE_ASM_H*/ + diff --git a/src/platform/mt8196/include/arch/xtensa/config/tie.h b/src/platform/mt8196/include/arch/xtensa/config/tie.h new file mode 100644 index 000000000000..517d79faab47 --- /dev/null +++ b/src/platform/mt8196/include/arch/xtensa/config/tie.h @@ -0,0 +1,220 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration + * + * NOTE: This header file is not meant to be included directly. + */ + +/* This header file describes this specific Xtensa processor's TIE extensions + * that extend basic Xtensa core functionality. It is customized to this + * Xtensa processor configuration. + * + * Customer ID = 7578; Build = 0xa69ab; Copyright (c) 1999-2023 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef XTENSA_CORE_TIE_H +#define XTENSA_CORE_TIE_H + +/* parasoft-begin-suppress ALL "This file not MISRA checked." */ + +#define XCHAL_CP_NUM UINT32_C(1) /* number of coprocessors */ +#define XCHAL_CP_MAX UINT32_C(2) /* max CP ID + 1 (0 if none) */ +#define XCHAL_CP_MASK UINT32_C(0x02) /* bitmask of all CPs by ID */ +#define XCHAL_CP_PORT_MASK UINT32_C(0x00) /* bitmask of only port CPs */ + +/* Basic parameters of each coprocessor: */ +#define XCHAL_CP1_NAME "audio_engine_lx" +#define XCHAL_CP1_IDENT audio_engine_lx +#define XCHAL_CP1_SA_SIZE UINT32_C(384) /* size of state save area */ +#define XCHAL_CP1_SA_ALIGN UINT32_C(16) /* min alignment of save area */ +#define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */ + +/* Filler info for unassigned coprocessors, to simplify arrays etc: */ +#define XCHAL_CP0_SA_SIZE UINT32_C(0) +#define XCHAL_CP0_SA_ALIGN UINT32_C(1) +#define XCHAL_CP2_SA_SIZE UINT32_C(0) +#define XCHAL_CP2_SA_ALIGN UINT32_C(1) +#define XCHAL_CP3_SA_SIZE UINT32_C(0) +#define XCHAL_CP3_SA_ALIGN UINT32_C(1) +#define XCHAL_CP4_SA_SIZE UINT32_C(0) +#define XCHAL_CP4_SA_ALIGN UINT32_C(1) +#define XCHAL_CP5_SA_SIZE UINT32_C(0) +#define XCHAL_CP5_SA_ALIGN UINT32_C(1) +#define XCHAL_CP6_SA_SIZE UINT32_C(0) +#define XCHAL_CP6_SA_ALIGN UINT32_C(1) +#define XCHAL_CP7_SA_SIZE UINT32_C(0) +#define XCHAL_CP7_SA_ALIGN UINT32_C(1) + +/* Save area for non-coprocessor optional and custom (TIE) state: */ +#define XCHAL_NCP_SA_SIZE UINT32_C(8) +#define XCHAL_NCP_SA_ALIGN UINT32_C(4) + +/* Total save area for optional and custom state (NCP + CPn): */ +#define XCHAL_TOTAL_SA_SIZE UINT32_C(400) /* with 16-byte align padding */ +#define XCHAL_TOTAL_SA_ALIGN UINT32_C(16) /* actual minimum alignment */ + +/* + * Detailed contents of save areas. + * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) + * before expanding the XCHAL_xxx_SA_LIST() macros. + * + * XCHAL_SA_REG(s, ccused, abikind, kind, opt, name, galign, align, asize, + * dbnum, base, regnum, bitsz, gapsz, reset, x...) + * + * s = passed from XCHAL_*_LIST(s), eg. to select how to expand + * ccused = set if used by compiler without special options or code + * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) + * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) + * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) + * name = lowercase reg name (no quotes) + * galign = group byte alignment (power of 2) (galign >= align) + * align = register byte alignment (power of 2) + * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) + * (not including any pad bytes required to galign this or next reg) + * dbnum = unique target number f/debug (see ) + * base = reg shortname w/o index (or sr = special, ur = TIE user reg) + * regnum = reg index in regfile, or special/TIE-user reg number + * bitsz = number of significant bits (regfile width, or ur/sr mask bits) + * gapsz = intervening bits, if bitsz bits not stored contiguously + * (padsz = pad bits at end [TIE regfile] or at msbits [ur, sr] of asize) + * reset = register reset value (or 0 if undefined at reset) + * x = reserved for future use (0 until then) + * + * To filter out certain registers, e.g. to expand only the non-global + * registers used by the compiler, you can do something like this: + * + * #define XCHAL_SA_REG(s, ccused, p...) SELCC##ccused(p) + * #define SELCC0(p...) + * #define SELCC1(abikind, p...) SELAK##abikind(p) + * #define SELAK0(p...) REG(p) + * #define SELAK1(p...) REG(p) + * #define SELAK2(p...) + * #define REG(kind, tie, name, galn, aln, asz, csz, dbnum, base, rnum, bsz, rst, x...) \ + * ...what you want to expand... + */ + +#define XCHAL_NCP_SA_NUM 2 +#define XCHAL_NCP_SA_LIST(s) (\ +XCHAL_SA_REG(s, 1, 2, 1, 1, threadptr, 4, 4, 4, 0x03E7, ur, 231, 32, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 0, 1, br, 4, 4, 4, 0x0204, sr, 4, 16, 0, 0, 0)) + +#define XCHAL_CP0_SA_NUM 0 +#define XCHAL_CP0_SA_LIST(s) /* empty */ + +#define XCHAL_CP1_SA_NUM 52 +#define XCHAL_CP1_SA_LIST(s) (\ +XCHAL_SA_REG(s, 0, 0, 1, 0, ae_zbiasv8c, 16, 8, 8, 0x1029, ur, -1, 16, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 1, 0, fcr_fsr, 8, 8, 8, 0x102A, ur, -1, 7, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 1, 0, ae_ovf_sar, 4, 4, 4, 0x03F0, ur, 240, 15, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 1, 0, ae_bithead, 4, 4, 4, 0x03F1, ur, 241, 32, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 1, 0, ae_ts_fts_bu_bp, 4, 4, 4, 0x03F2, ur, 242, 16, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 1, 0, ae_cw_sd_no, 4, 4, 4, 0x03F3, ur, 243, 29, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 1, 0, ae_cbegin0, 4, 4, 4, 0x03F6, ur, 246, 32, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 1, 0, ae_cend0, 4, 4, 4, 0x03F7, ur, 247, 32, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 1, 0, ae_cbegin1, 4, 4, 4, 0x03F8, ur, 248, 32, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 1, 0, ae_cend1, 4, 4, 4, 0x03F9, ur, 249, 32, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 1, 0, ae_cbegin2, 4, 4, 4, 0x03FA, ur, 250, 32, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 1, 0, ae_cend2, 4, 4, 4, 0x03FB, ur, 251, 32, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed0, 8, 8, 8, 0x1000, aed, 0, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed1, 8, 8, 8, 0x1001, aed, 1, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed2, 8, 8, 8, 0x1002, aed, 2, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed3, 8, 8, 8, 0x1003, aed, 3, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed4, 8, 8, 8, 0x1004, aed, 4, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed5, 8, 8, 8, 0x1005, aed, 5, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed6, 8, 8, 8, 0x1006, aed, 6, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed7, 8, 8, 8, 0x1007, aed, 7, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed8, 8, 8, 8, 0x1008, aed, 8, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed9, 8, 8, 8, 0x1009, aed, 9, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed10, 8, 8, 8, 0x100A, aed, 10, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed11, 8, 8, 8, 0x100B, aed, 11, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed12, 8, 8, 8, 0x100C, aed, 12, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed13, 8, 8, 8, 0x100D, aed, 13, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed14, 8, 8, 8, 0x100E, aed, 14, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed15, 8, 8, 8, 0x100F, aed, 15, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed16, 8, 8, 8, 0x1010, aed, 16, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed17, 8, 8, 8, 0x1011, aed, 17, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed18, 8, 8, 8, 0x1012, aed, 18, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed19, 8, 8, 8, 0x1013, aed, 19, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed20, 8, 8, 8, 0x1014, aed, 20, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed21, 8, 8, 8, 0x1015, aed, 21, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed22, 8, 8, 8, 0x1016, aed, 22, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed23, 8, 8, 8, 0x1017, aed, 23, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed24, 8, 8, 8, 0x1018, aed, 24, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed25, 8, 8, 8, 0x1019, aed, 25, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed26, 8, 8, 8, 0x101A, aed, 26, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed27, 8, 8, 8, 0x101B, aed, 27, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed28, 8, 8, 8, 0x101C, aed, 28, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed29, 8, 8, 8, 0x101D, aed, 29, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed30, 8, 8, 8, 0x101E, aed, 30, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aed31, 8, 8, 8, 0x101F, aed, 31, 64, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aep0, 1, 1, 1, 0x1024, aep, 0, 8, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aep1, 1, 1, 1, 0x1025, aep, 1, 8, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aep2, 1, 1, 1, 0x1026, aep, 2, 8, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, aep3, 1, 1, 1, 0x1027, aep, 3, 8, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, u0, 16, 16, 16, 0x1020, u, 0, 128, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, u1, 16, 16, 16, 0x1021, u, 1, 128, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, u2, 16, 16, 16, 0x1022, u, 2, 128, 0, 0, 0) \ +XCHAL_SA_REG(s, 0, 0, 2, 0, u3, 16, 16, 16, 0x1023, u, 3, 128, 0, 0, 0)) + +#define XCHAL_CP2_SA_NUM 0 +#define XCHAL_CP2_SA_LIST(s) /* empty */ + +#define XCHAL_CP3_SA_NUM 0 +#define XCHAL_CP3_SA_LIST(s) /* empty */ + +#define XCHAL_CP4_SA_NUM 0 +#define XCHAL_CP4_SA_LIST(s) /* empty */ + +#define XCHAL_CP5_SA_NUM 0 +#define XCHAL_CP5_SA_LIST(s) /* empty */ + +#define XCHAL_CP6_SA_NUM 0 +#define XCHAL_CP6_SA_LIST(s) /* empty */ + +#define XCHAL_CP7_SA_NUM 0 +#define XCHAL_CP7_SA_LIST(s) /* empty */ + +/* Byte length of instruction from its first nibble (op0 field), per FLIX. */ +#define XCHAL_OP0_FORMAT_LENGTHS (3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16) +/* Byte length of instruction from its first byte, per FLIX. */ +#define XCHAL_BYTE0_FORMAT_LENGTHS (\ +3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \ +3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \ +3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \ +3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \ +3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \ +3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \ +3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \ +3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \ +3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \ +3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \ +3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \ +3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \ +3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \ +3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \ +3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \ +3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 8, 16, \) + +/* parasoft-end-suppress ALL "This file not MISRA checked." */ + +#endif /* XTENSA_CORE_TIE_H */ + From 7bd1bbb893694827d28f971ef0b983113f990c47 Mon Sep 17 00:00:00 2001 From: "hailong.fan" Date: Wed, 25 Dec 2024 20:11:21 +0800 Subject: [PATCH 0003/1821] platform: mediatek: add mt8196 memory layout and register definitions Add memory layout and register address for mediatek mt8196 [Cache] I-Cache: 64KB, 4-way Associativity D-Cache: 128KB, 4-way Associativity [Memory] Dram: ADSP can access DRAM shared with CPU L2TCM: 768KB ADSP SRAM POOL Signed-off-by: hailong.fan --- .../include/platform/drivers/mt_reg_base.h | 147 +++++++++++ .../mt8196/include/platform/lib/memory.h | 228 ++++++++++++++++++ 2 files changed, 375 insertions(+) create mode 100644 src/platform/mt8196/include/platform/drivers/mt_reg_base.h create mode 100644 src/platform/mt8196/include/platform/lib/memory.h diff --git a/src/platform/mt8196/include/platform/drivers/mt_reg_base.h b/src/platform/mt8196/include/platform/drivers/mt_reg_base.h new file mode 100644 index 000000000000..21605116506b --- /dev/null +++ b/src/platform/mt8196/include/platform/drivers/mt_reg_base.h @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + * + */ + +#ifndef MT_REG_BASE_H +#define MT_REG_BASE_H + +#define MTK_DSP_CFGREG_BASE 0x1A000000 /* DSP Register base */ +#define MTK_DSP_CFGREG_SIZE 0x1000 +#define MTK_ADSP_CFGREG_SW_RSTN (MTK_DSP_CFGREG_BASE + 0x0000) +#define MTK_ADSP_HIFI_IO_CONFIG (MTK_DSP_CFGREG_BASE + 0x000c) +#define MTK_ADSP_IRQ_STATUS (MTK_DSP_CFGREG_BASE + 0x0010) +#define MTK_ADSP_SW_INT_SET (MTK_DSP_CFGREG_BASE + 0x0018) +#define MTK_ADSP_SW_INT_CLR (MTK_DSP_CFGREG_BASE + 0x001c) +#define MTK_ADSP_SW_INT_32A (MTK_DSP_CFGREG_BASE + 0x0020) +#define MTK_ADSP_IRQ_MASK (MTK_DSP_CFGREG_BASE + 0x0030) +#define MTK_ADSP_GENERAL_IRQ_SET (MTK_DSP_CFGREG_BASE + 0x0034) +#define MTK_ADSP_GENERAL_IRQ_CLR (MTK_DSP_CFGREG_BASE + 0x0038) +#define MTK_ADSP_DVFSRC_STATE (MTK_DSP_CFGREG_BASE + 0x003c) +#define MTK_ADSP_DVFSRC_REQ (MTK_DSP_CFGREG_BASE + 0x0040) +//todo +#define MTK_ADSP_DDREN_REQ_0 (MTK_DSP_CFGREG_BASE + 0x0044) +#define MTK_ADSP_SPM_ACK (MTK_DSP_CFGREG_BASE + 0x004c) +#define MTK_ADSP_IRQ_EN (MTK_DSP_CFGREG_BASE + 0x0050) +#define MTK_ADSP_IRQ_POL_FIX (MTK_DSP_CFGREG_BASE + 0x0054) +#define MTK_ADSP_SPM_WAKEUPSRC_CORE0 (MTK_DSP_CFGREG_BASE + 0x005c) +#define MTK_ADSP_SEMAPHORE (MTK_DSP_CFGREG_BASE + 0x0064) +#define MTK_ADSP_DBG_SEL (MTK_DSP_CFGREG_BASE + 0x0074) +#define MTK_ADSP_DBG_INFO (MTK_DSP_CFGREG_BASE + 0x0078) +#define MTK_ADSP_WDT_CON_C0 (MTK_DSP_CFGREG_BASE + 0x007c) +#define MTK_ADSP_WDT_INIT_VALUE_C0 (MTK_DSP_CFGREG_BASE + 0x0080) +#define MTK_ADSP_WDT_CNT_C0 (MTK_DSP_CFGREG_BASE + 0x0084) +#define MTK_ADSP_WAKEUPSRC_MASK_C0 (MTK_DSP_CFGREG_BASE + 0x00a0) +#define MTK_ADSP_WAKEUPSRC_IRQ_C0 (MTK_DSP_CFGREG_BASE + 0x00a4) +#define MTK_ADSP2SPM_MBOX (MTK_DSP_CFGREG_BASE + 0x00bc) +#define MTK_SPM2ADSP_MBOX (MTK_DSP_CFGREG_BASE + 0x00c0) + +/* intc */ +#define MTK_ADSP_INTC_BASE (MTK_DSP_CFGREG_BASE + 0x14000) + +#define INTC_IRQ_RAW_STA0 (MTK_ADSP_INTC_BASE + 0x000) +#define INTC_IRQ_STA0 (MTK_ADSP_INTC_BASE + 0x008) +#define INTC_IRQ_STA1 (MTK_ADSP_INTC_BASE + 0x00c) +#define INTC_IRQ_EN0 (MTK_ADSP_INTC_BASE + 0x010) +#define INTC_IRQ_POL0 (MTK_ADSP_INTC_BASE + 0x018) +#define INTC_IRQ_WAKE_EN0 (MTK_ADSP_INTC_BASE + 0x020) +#define INTC_IRQ_STAGE1_EN0 (MTK_ADSP_INTC_BASE + 0x030) +#define INTC_IRQ_GRP0_0 (MTK_ADSP_INTC_BASE + 0x040) +#define INTC_IRQ_GRP0_STA0 (MTK_ADSP_INTC_BASE + 0x0C0) +#define INTC_GRP_IRQ_OUT_STA (MTK_ADSP_INTC_BASE + 0x140) + +//todo +#define MTK_GPR_RW_REG0 (MTK_DSP_CFGREG_BASE + 0x0440) +#define MTK_GPR_RW_REG1 (MTK_DSP_CFGREG_BASE + 0x0444) +#define MTK_GPR_RW_REG2 (MTK_DSP_CFGREG_BASE + 0x0448) +#define MTK_GPR_RW_REG3 (MTK_DSP_CFGREG_BASE + 0x044c) +#define MTK_GPR_RW_REG4 (MTK_DSP_CFGREG_BASE + 0x0450) +#define MTK_GPR_RW_REG5 (MTK_DSP_CFGREG_BASE + 0x0454) +#define MTK_GPR_RW_REG6 (MTK_DSP_CFGREG_BASE + 0x0458) +#define MTK_GPR_RW_REG7 (MTK_DSP_CFGREG_BASE + 0x045c) +#define MTK_GPR_RW_REG8 (MTK_DSP_CFGREG_BASE + 0x0460) +#define MTK_GPR_RW_REG9 (MTK_DSP_CFGREG_BASE + 0x0464) +#define MTK_GPR_RW_REG10 (MTK_DSP_CFGREG_BASE + 0x0468) +#define MTK_GPR_RW_REG11 (MTK_DSP_CFGREG_BASE + 0x046c) +#define MTK_GPR_RW_REG12 (MTK_DSP_CFGREG_BASE + 0x0470) +#define MTK_GPR_RW_REG13 (MTK_DSP_CFGREG_BASE + 0x0474) +#define MTK_GPR_RW_REG14 (MTK_DSP_CFGREG_BASE + 0x0478) +#define MTK_GPR_RW_REG15 (MTK_DSP_CFGREG_BASE + 0x047c) +#define MTK_GPR_RW_REG16 (MTK_DSP_CFGREG_BASE + 0x0480) +#define MTK_GPR_RW_REG17 (MTK_DSP_CFGREG_BASE + 0x0484) +#define MTK_GPR_RW_REG18 (MTK_DSP_CFGREG_BASE + 0x0488) +#define MTK_GPR_RW_REG19 (MTK_DSP_CFGREG_BASE + 0x048c) +#define MTK_GPR_RW_REG20 (MTK_DSP_CFGREG_BASE + 0x0490) +#define MTK_GPR_RW_REG21 (MTK_DSP_CFGREG_BASE + 0x0494) +#define MTK_GPR_RW_REG22 (MTK_DSP_CFGREG_BASE + 0x0498) +#define MTK_GPR_RW_REG23 (MTK_DSP_CFGREG_BASE + 0x049c) +#define MTK_GPR_RW_REG24 (MTK_DSP_CFGREG_BASE + 0x04a0) +#define MTK_GPR_RW_REG25 (MTK_DSP_CFGREG_BASE + 0x04a4) +#define MTK_GPR_RW_REG26 (MTK_DSP_CFGREG_BASE + 0x04a8) +#define MTK_GPR_RW_REG27 (MTK_DSP_CFGREG_BASE + 0x04ac) +/* use for tickless status */ +#define MTK_GPR_RW_REG28 (MTK_DSP_CFGREG_BASE + 0x04b0) +#define MTK_GPR_RW_REG29 (MTK_DSP_CFGREG_BASE + 0x04b4) + +#define MTK_ADSP_IRQ_OUT_MASK (MTK_DSP_CFGREG_BASE + 0x0500) + +#define MTK_DSP_CKCTRL_BASE (MTK_DSP_CFGREG_BASE + 0x1000) +#define MTK_DSP_CKCTRL_SIZE 0x1000 + +//todo +#define MTK_DSP_OS_TIMER_BASE (MTK_DSP_CFGREG_BASE + 0xB000) +#define MTK_DSP_OS_TIMER_SIZE 0x1000 + +#define MTK_DSP_UART0_BASE (MTK_DSP_CFGREG_BASE + 0xD000) +#define MTK_DSP_UART0_SIZE 0x1000 +#define MTK_DSP_BT_UART_BASE (MTK_DSP_CFGREG_BASE + 0xE000) +#define MTK_DSP_BT_UART_SIZE 0x1000 + +#define MTK_DSP_BUS_BASE (MTK_DSP_CFGREG_BASE + 0xF000) +#define MTK_DSP_BUS_SIZE 0x1000 + +#define MTK_DSP_SECURE_BASE (MTK_DSP_CFGREG_BASE + 0x345000) +#define MTK_MBOX_IRQ_IN (MTK_DSP_SECURE_BASE + 0x70) + +#define MTK_REG_TOPCKGEN_BASE 0x10000000 +#define MTK_REG_TOPCKGEN_SIZE 0x1000 +#define MTK_CLK_CFG_UPDATE1 (MTK_REG_TOPCKGEN_BASE + 0x0008) +#define MTK_CLK_CFG_13_STA (MTK_REG_TOPCKGEN_BASE + 0x00E0) +#define MTK_CLK_CFG_13_SET (MTK_REG_TOPCKGEN_BASE + 0x00E4) +#define MTK_CLK_CFG_13_CLR (MTK_REG_TOPCKGEN_BASE + 0x00E8) +#define MTK_ADSP_CK_UPDATE (0x1 << 23) +#define MTK_ADSP_SEL_BASE (16) + +//todo +#define MTK_CLK_CFG_UPDATE2 (MTK_REG_TOPCKGEN_BASE + 0x000C) +#define MTK_CLK_CFG_17 (MTK_REG_TOPCKGEN_BASE + 0x0EC) +#define MTK_CLK_CFG_17_SET (MTK_REG_TOPCKGEN_BASE + 0x0F0) +#define MTK_CLK_CFG_17_CLR (MTK_REG_TOPCKGEN_BASE + 0x0F4) +#define MTK_CLK_CFG_17_CLR (MTK_REG_TOPCKGEN_BASE + 0x0F4) + +//todo, pll base? +#define MTK_REG_APMIXDSYS_BASE 0x10000800 +#define MTK_REG_APMIXDSYS_SIZE 0x1000 + +//todo +#define MTK_PLLEN_ALL_EN (MTK_REG_APMIXDSYS_BASE + 0x0080) +#define MTK_PLLEN_ALL_SET (MTK_REG_APMIXDSYS_BASE + 0x0084) +#define MTK_PLLEN_ALL_CLR (MTK_REG_APMIXDSYS_BASE + 0x0088) +#define MTK_ADSPPLL_CON0 (MTK_REG_APMIXDSYS_BASE + 0x028c) +#define MTK_ADSPPLL_CON1 (MTK_REG_APMIXDSYS_BASE + 0x0290) +#define MTK_PLL_ADSP_EN_BIT (0x1 << 3) + + +/* MBOX registers */ +#define MTK_ADSP_MBOX_BASE (MTK_DSP_CFGREG_BASE + 0x350000) +#define MTK_ADSP_MBOX_REG_BASE(x) (MTK_ADSP_MBOX_BASE + (0x10000 * (x))) +#define MTK_ADSP_MBOX_REG_SIZE (0x50000) +#define MTK_ADSP_MBOX_IN_CMD(x) (MTK_ADSP_MBOX_REG_BASE(x) + 0x100) +#define MTK_ADSP_MBOX_IN_CMD_CLR(x) (MTK_ADSP_MBOX_REG_BASE(x) + 0x108) +#define MTK_ADSP_MBOX_OUT_CMD(x) (MTK_ADSP_MBOX_REG_BASE(x) + 0x104) +#define MTK_ADSP_MBOX_OUT_CMD_CLR(x) (MTK_ADSP_MBOX_REG_BASE(x) + 0x10c) + +#endif /* MT_REG_BASE_H */ diff --git a/src/platform/mt8196/include/platform/lib/memory.h b/src/platform/mt8196/include/platform/lib/memory.h new file mode 100644 index 000000000000..f6d8bd521208 --- /dev/null +++ b/src/platform/mt8196/include/platform/lib/memory.h @@ -0,0 +1,228 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + */ + +#ifdef __SOF_LIB_MEMORY_H__ + +#ifndef __PLATFORM_LIB_MEMORY_H__ +#define __PLATFORM_LIB_MEMORY_H__ + +#include + +/* data cache line alignment */ +#define PLATFORM_DCACHE_ALIGN sizeof(void *) + +/* physical DSP addresses */ +#define SRAM_BASE 0x4e100000 +#define SRAM_SIZE 0x80000 + +/* reset vector + rodata + module_init + text + data + bss */ +#define SOF_DATA_SIZE 0x80000 +#define VECTOR_SIZE 0x700 +#define SRAM_START (SRAM_BASE + VECTOR_SIZE) + +#define DRAM_BASE 0x90000000 +#define DRAM0_SIZE 0x500000 +#define MAILBOX_BASE (DRAM_BASE + DRAM0_SIZE) +#define DSP_SYS_SIZE 0xA00000 + +#define UUID_ENTRY_ELF_BASE (SRAM_BASE + SOF_DATA_SIZE) +#define UUID_ENTRY_ELF_SIZE 0x6000 + +#define LOG_ENTRY_ELF_BASE (UUID_ENTRY_ELF_BASE + UUID_ENTRY_ELF_SIZE) +#define LOG_ENTRY_ELF_SIZE 0x20000 +#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE) +#define EXT_MANIFEST_ELF_SIZE (SRAM_BASE + SRAM_SIZE - EXT_MANIFEST_ELF_BASE) + +/* + * The Memory Layout on MT8189 are organised like this :- + * + * +--------------------------------------------------------------------------+ + * | Offset | Region | Size | + * +---------------------+----------------+-----------------------------------+ + * | SRAM_START | RO Data | SOF_DATA_SIZE | + * | | text | | + * | | Data | | + * | | BSS | | + * +---------------------+----------------+-----------------------------------+ + * | fw_ready | + * +---------------------+----------------+-----------------------------------+ + * | static_uuid | + * +---------------------+----------------+-----------------------------------+ + * | static_log | + * +---------------------+----------------+-----------------------------------+ + * | fw_metadata | + * +---------------------+----------------+-----------------------------------+ + * + * +---------------------+----------------+-----------------------------------+ + * | SOF_DRAM_BASE | | SOF_DRAM_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SOF_STACK_END | Stack | SOF_STACK_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SOF_STACK_BASE | | | + * +---------------------+----------------+-----------------------------------+ + * | MAILBOX_BASE | | SOF_MAILBOX_SIZE | + * +---------------------+----------------+-----------------------------------+ + */ + +#define SRAM_OUTBOX_BASE MAILBOX_BASE +#define SRAM_OUTBOX_SIZE 0x1000 +#define SRAM_OUTBOX_OFFSET 0 + +#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE) +#define SRAM_INBOX_SIZE 0x1000 +#define SRAM_INBOX_OFFSET SRAM_OUTBOX_SIZE + +#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) +#define SRAM_DEBUG_SIZE 0x800 +#define SRAM_DEBUG_OFFSET (SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE) + +#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) +#define SRAM_EXCEPT_SIZE 0x800 +#define SRAM_EXCEPT_OFFSET (SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE) + +#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) +#define SRAM_STREAM_SIZE 0x1000 +#define SRAM_STREAM_OFFSET (SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE) + +#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) +#define SRAM_TRACE_SIZE 0x1000 +#define SRAM_TRACE_OFFSET (SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE) + +/*4K + 4K +2K + 2K + 4K + 4K = 20KB*/ +#define SOF_MAILBOX_SIZE \ + (SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE + SRAM_DEBUG_SIZE + \ + SRAM_EXCEPT_SIZE + SRAM_STREAM_SIZE + SRAM_TRACE_SIZE) + +/* SOF image on DRAM */ +#define SOF_DRAM_BASE DRAM_BASE +#define SOF_DRAM_SIZE 0x100000 + +/* Heap section sizes for module pool */ +#define HEAP_RT_COUNT8 0 +#define HEAP_RT_COUNT16 48 +#define HEAP_RT_COUNT32 48 +#define HEAP_RT_COUNT64 32 +#define HEAP_RT_COUNT128 32 +#define HEAP_RT_COUNT256 32 +#define HEAP_RT_COUNT512 32 +#define HEAP_RT_COUNT1024 4 +#define HEAP_RT_COUNT2048 2 +#define HEAP_RT_COUNT4096 2 + +/* Heap section sizes for system runtime heap */ +#define HEAP_SYS_RT_COUNT64 128 +#define HEAP_SYS_RT_COUNT512 16 +#define HEAP_SYS_RT_COUNT1024 8 + +/* Heap configuration */ + +#define HEAP_SYSTEM_BASE (SOF_DRAM_BASE + SOF_DRAM_SIZE) +#define HEAP_SYSTEM_SIZE 0x6000 + +#define HEAP_SYS_RUNTIME_BASE (HEAP_SYSTEM_BASE + HEAP_SYSTEM_SIZE) +/*24KB*/ +#define HEAP_SYS_RUNTIME_SIZE \ + (HEAP_SYS_RT_COUNT64 * 64 + HEAP_SYS_RT_COUNT512 * 512 + \ + HEAP_SYS_RT_COUNT1024 * 1024) + +#define HEAP_RUNTIME_BASE (HEAP_SYS_RUNTIME_BASE + HEAP_SYS_RUNTIME_SIZE) +/*48*(16 +32) + 32*(64 128+256) + 4*(512+1024) + 1*2048 = 24832 = 24.25KB*/ +#define HEAP_RUNTIME_SIZE \ + (HEAP_RT_COUNT8 * 8 + HEAP_RT_COUNT16 * 16 + \ + HEAP_RT_COUNT32 * 32 + HEAP_RT_COUNT64 * 64 + \ + HEAP_RT_COUNT128 * 128 + HEAP_RT_COUNT256 * 256 + \ + HEAP_RT_COUNT512 * 512 + HEAP_RT_COUNT1024 * 1024 + \ + HEAP_RT_COUNT2048 * 2048 + HEAP_RT_COUNT4096 * 4096) + +#define HEAP_BUFFER_BASE (HEAP_RUNTIME_BASE + HEAP_RUNTIME_SIZE) +#define HEAP_BUFFER_SIZE \ + (DRAM0_SIZE - SOF_DRAM_SIZE - HEAP_RUNTIME_SIZE - SOF_STACK_TOTAL_SIZE - \ + HEAP_SYS_RUNTIME_SIZE - HEAP_SYSTEM_SIZE) + +#define HEAP_BUFFER_BLOCK_SIZE 0x100 +#define HEAP_BUFFER_COUNT (HEAP_BUFFER_SIZE / HEAP_BUFFER_BLOCK_SIZE) + +#define PLATFORM_HEAP_SYSTEM 1 /* one per core */ +#define PLATFORM_HEAP_SYSTEM_RUNTIME 1 /* one per core */ +#define PLATFORM_HEAP_RUNTIME 1 +#define PLATFORM_HEAP_BUFFER 1 + +/* Stack configuration */ +#define SOF_STACK_SIZE (CONFIG_SOF_STACK_SIZE) +#define SOF_STACK_TOTAL_SIZE SOF_STACK_SIZE /*4KB*/ +#define SOF_STACK_BASE (DRAM_BASE + DRAM0_SIZE) +#define SOF_STACK_END (SOF_STACK_BASE - SOF_STACK_TOTAL_SIZE) + +/* Vector and literal sizes - not in core-isa.h */ +#define SOF_MEM_VECT_LIT_SIZE 0x4 +#define SOF_MEM_VECT_TEXT_SIZE 0x1c +#define SOF_MEM_VECT_SIZE (SOF_MEM_VECT_TEXT_SIZE + SOF_MEM_VECT_LIT_SIZE) + +#define SOF_MEM_RESET_TEXT_SIZE 0x2e0 +#define SOF_MEM_RESET_LIT_SIZE 0x120 +#define SOF_MEM_VECBASE_LIT_SIZE 0x178 + +#define SOF_MEM_RO_SIZE 0x8 + +#define HEAP_BUF_ALIGNMENT DCACHE_LINE_SIZE + +/** \brief EDF task's default stack size in bytes. */ +#define PLATFORM_TASK_DEFAULT_STACK_SIZE 3072 + +#if !defined(__ASSEMBLER__) && !defined(LINKER) + +struct sof; + +/** + * \brief Data shared between different cores. + * Does nothing, since mt8186 doesn't support SMP. + */ +#define SHARED_DATA + +void platform_init_memmap(struct sof *sof); + +static inline void *platform_shared_get(void *ptr, int bytes) +{ + return ptr; +} + +#define uncache_to_cache(address) address +#define cache_to_uncache(address) address +#define cache_to_uncache_init(address) address +#define is_uncached(address) 0 + +/** + * \brief Function for keeping shared data synchronized. + * It's used after usage of data shared by different cores. + * Such data is either statically marked with SHARED_DATA + * or dynamically allocated with SOF_MEM_FLAG_SHARED flag. + * Does nothing, since mt8186 doesn't support SMP. + */ + +static inline void *platform_rfree_prepare(void *ptr) +{ + return ptr; +} + +#endif + +#define host_to_local(addr) (addr) +#define local_to_host(addr) (addr) + +#endif /* __PLATFORM_LIB_MEMORY_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/memory.h" + +#endif /* __SOF_LIB_MEMORY_H__ */ From fe82f080c17346cbc1754573349882ef8c8d8541 Mon Sep 17 00:00:00 2001 From: "hailong.fan" Date: Thu, 26 Dec 2024 09:39:04 +0800 Subject: [PATCH 0004/1821] platform: mediatek: Add support for mt8196 platform mt8196 plaform integrates a single-core HIFI5 DSP. The DSP does not have DVFS scenario. When the system is in an active state, the DSP clock is 800MHz(0.75v). When the system enters a low power scenario, the DSP is in WFI state, and the clock is 26MHz. The DSP core and DMA in DSP subsys both can access DRAM directly. Signed-off-by: hailong.fan --- src/platform/mt8196/CMakeLists.txt | 7 + .../mt8196/include/platform/drivers/idc.h | 33 ++ .../mt8196/include/platform/drivers/intc.h | 186 ++++++ .../include/platform/drivers/interrupt.h | 72 +++ .../include/platform/drivers/mt_reg_base.h | 32 - .../mt8196/include/platform/drivers/timer.h | 47 ++ .../mt8196/include/platform/lib/clk.h | 33 ++ .../mt8196/include/platform/lib/cpu.h | 22 + .../mt8196/include/platform/lib/dai.h | 19 + .../mt8196/include/platform/lib/dma.h | 30 + .../mt8196/include/platform/lib/mailbox.h | 77 +++ .../mt8196/include/platform/lib/pm_runtime.h | 66 +++ .../mt8196/include/platform/platform.h | 91 +++ .../mt8196/include/platform/trace/trace.h | 26 + src/platform/mt8196/lib/CMakeLists.txt | 7 + src/platform/mt8196/lib/clk.c | 58 ++ src/platform/mt8196/lib/dma.c | 45 ++ src/platform/mt8196/lib/memory.c | 101 ++++ src/platform/mt8196/mt8196.x.in | 554 ++++++++++++++++++ src/platform/mt8196/platform.c | 212 +++++++ 20 files changed, 1686 insertions(+), 32 deletions(-) create mode 100644 src/platform/mt8196/CMakeLists.txt create mode 100644 src/platform/mt8196/include/platform/drivers/idc.h create mode 100644 src/platform/mt8196/include/platform/drivers/intc.h create mode 100644 src/platform/mt8196/include/platform/drivers/interrupt.h create mode 100644 src/platform/mt8196/include/platform/drivers/timer.h create mode 100644 src/platform/mt8196/include/platform/lib/clk.h create mode 100644 src/platform/mt8196/include/platform/lib/cpu.h create mode 100644 src/platform/mt8196/include/platform/lib/dai.h create mode 100644 src/platform/mt8196/include/platform/lib/dma.h create mode 100644 src/platform/mt8196/include/platform/lib/mailbox.h create mode 100644 src/platform/mt8196/include/platform/lib/pm_runtime.h create mode 100644 src/platform/mt8196/include/platform/platform.h create mode 100644 src/platform/mt8196/include/platform/trace/trace.h create mode 100644 src/platform/mt8196/lib/CMakeLists.txt create mode 100644 src/platform/mt8196/lib/clk.c create mode 100644 src/platform/mt8196/lib/dma.c create mode 100644 src/platform/mt8196/lib/memory.c create mode 100644 src/platform/mt8196/mt8196.x.in create mode 100644 src/platform/mt8196/platform.c diff --git a/src/platform/mt8196/CMakeLists.txt b/src/platform/mt8196/CMakeLists.txt new file mode 100644 index 000000000000..911878ab3c0d --- /dev/null +++ b/src/platform/mt8196/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: BSD-3-Clause + +add_subdirectory(lib) + +add_local_sources(sof platform.c) +target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/mt8196/include/arch) +target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/mt8196/include/platform) diff --git a/src/platform/mt8196/include/platform/drivers/idc.h b/src/platform/mt8196/include/platform/drivers/idc.h new file mode 100644 index 000000000000..8ad311b1471b --- /dev/null +++ b/src/platform/mt8196/include/platform/drivers/idc.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + */ + +#if defined(__XTOS_RTOS_IDC_H__) || defined(__ZEPHYR_RTOS_IDC_H__) + +#ifndef __PLATFORM_DRIVERS_IDC_H__ +#define __PLATFORM_DRIVERS_IDC_H__ + +#include + +struct idc_msg; + +static inline int idc_send_msg(struct idc_msg *msg, uint32_t mode) +{ + return 0; +} + +static inline int idc_init(void) +{ + return 0; +} + +#endif /* __PLATFORM_DRIVERS_IDC_H__ */ + +#else + +#error "This file shouldn't be included from outside of Zephyr/XTOS's rtos/idc.h" + +#endif diff --git a/src/platform/mt8196/include/platform/drivers/intc.h b/src/platform/mt8196/include/platform/drivers/intc.h new file mode 100644 index 000000000000..be741ae6e484 --- /dev/null +++ b/src/platform/mt8196/include/platform/drivers/intc.h @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + */ +#ifndef MTK_INTC_H +#define MTK_INTC_H + +#include +#include +#include + +enum IRQn_Type { + CCU_IRQn = 0, + SCP_IRQn = 1, + SPM_IRQn = 2, + PCIE_IRQn = 3, + INFRA_HANG_IRQn = 4, + PERI_TIMEOUT_IRQn = 5, + MBOX_C0_IRQn = 6, + MBOX_C1_IRQn = 7, + TIMER0_IRQn = 8, + TIMER1_IRQn = 9, + IPC_C0_IRQn = 10, + IPC_C1_IRQn = 11, + IPC1_RSV_IRQn = 12, + C2C_SW_C0_IRQn = 13, + C2C_SW_C1_IRQn = 14, + UART_IRQn = 15, + UART_BT_IRQn = 16, + LATENCY_MON_IRQn = 17, + BUS_TRACKER_IRQn = 18, + USB0_IRQn = 19, + USB1_IRQn = 20, + SCPVOW_IRQn = 21, + CCIF3_C0_IRQn = 22, + CCIF3_C1_IRQn = 23, + PWR_CTRL_IRQn = 24, + DMA_C0_IRQn = 25, + DMA_C1_IRQn = 26, // no use as gdma only has one set + AXI_DMA0_IRQn = 27, + AXI_DMA1_IRQn = 28, + AUDIO_C0_IRQn = 29, + AUDIO_C1_IRQn = 30, + HIFI5_WDT_C0_IRQn = 31, + HIFI5_WDT_C1_IRQn = 32, + APU_MBOX_C0_IRQn = 33, + APU_MBOX_C1_IRQn = 34, + TIMER2_IRQn = 35, + PWR_ON_C0_IRQ = 36, + PWR_ON_C1_IRQ = 37, + WAKEUP_SRC_C0_IRQn = 38, + WAKEUP_SRC_C1_IRQn = 39, + WDT_IRQn = 40, + CONNSYS1_IRQn = 41, // BTCVSD + CONNSYS3_IRQn = 42, // BLEISO + CONNSYS4_IRQn = 43, // ISOCH, bt2dsp_isoch_irq_mask + CONNSYS2_IRQn = 44, // A2DP + IPIC_IRQn = 45, + AXI_DMA2_IRQn = 46, + AXI_DMA3_IRQn = 47, + APSRC_DDREN_IRQn = 48, + LAT_MON_EMI_IRQn = 49, + LAT_MON_INFRA_IRQn = 50, + DEVAPC_VIO_IRQn = 51, + AO_INFRA_HANG_IRQn = 52, + BUS_TRA_EMI_IRQn = 53, + BUS_TRA_INFRA_IRQn = 54, + L2SRAM_VIO_IRQn = 55, + L2SRAM_SETERR_IRQn = 56, + PCIERC_GRP2_IRQn = 57, + PCIERC_GRP3_IRQn = 58, + IRQ_MAX_CHANNEL = 59, + NO_IRQ = 0xFFFFFFFFU, // -1 +}; + +#define INTC_GRP_LEN 2 +#define INTC_GRP_GAP 3 // size of group = 2 words = 8 bytes +#define WORD_LEN 32 +#define INTC_WORD(irq) ((irq) >> 5) +#define INTC_BIT(irq) (1 << ((irq) & 0x1F)) +#define INTC_WORD_OFS(word) ((word) << 2) +#ifndef INTC_GROUP_OFS +#define INTC_GROUP_OFS(grp) ((grp) << INTC_GRP_GAP) +#endif + +// #define INTC_IRQ_RAW_STA(word) (INTC_IRQ_RAW_STA0 + INTC_WORD_OFS(word)) +#define INTC_IRQ_STA(word) (INTC_IRQ_STA0 + INTC_WORD_OFS(word)) +#define INTC_IRQ_EN(word) (INTC_IRQ_EN0 + INTC_WORD_OFS(word)) +#define INTC_IRQ_WAKE_EN(word) (INTC_IRQ_WAKE_EN0 + INTC_WORD_OFS(word)) +#define INTC_IRQ_STAGE1_EN(word) (INTC_IRQ_STAGE1_EN0 + INTC_WORD_OFS(word)) +#define INTC_IRQ_POL(word) (INTC_IRQ_POL0 + INTC_WORD_OFS(word)) +#define INTC_IRQ_GRP(grp, word) (INTC_IRQ_GRP0_0 + INTC_GROUP_OFS(grp)\ + + INTC_WORD_OFS(word)) +#define INTC_IRQ_GRP_STA(grp, word) (INTC_IRQ_GRP0_STA0 + INTC_GROUP_OFS(grp)\ + + INTC_WORD_OFS(word)) + +/* intc group level */ +#define INTC_GRP0_LEVEL XCHAL_INT0_LEVEL +#define INTC_GRP1_LEVEL XCHAL_INT1_LEVEL +#define INTC_GRP2_LEVEL XCHAL_INT2_LEVEL +#define INTC_GRP3_LEVEL XCHAL_INT3_LEVEL +#define INTC_GRP4_LEVEL XCHAL_INT4_LEVEL +#define INTC_GRP5_LEVEL XCHAL_INT5_LEVEL +#define INTC_GRP6_LEVEL XCHAL_INT7_LEVEL +#define INTC_GRP7_LEVEL XCHAL_INT8_LEVEL +#define INTC_GRP8_LEVEL XCHAL_INT9_LEVEL +#define INTC_GRP9_LEVEL XCHAL_INT10_LEVEL +#define INTC_GRP10_LEVEL XCHAL_INT11_LEVEL +#define INTC_GRP11_LEVEL XCHAL_INT16_LEVEL +#define INTC_GRP12_LEVEL XCHAL_INT17_LEVEL +#define INTC_GRP13_LEVEL XCHAL_INT18_LEVEL +#define INTC_GRP14_LEVEL XCHAL_INT20_LEVEL +#define INTC_GRP15_LEVEL XCHAL_INT21_LEVEL + + +enum INTC_GROUP { + INTC_GRP0 = 0, + INTC_GRP1, + INTC_GRP2, + INTC_GRP3, + INTC_GRP4, + INTC_GRP5, + INTC_GRP6, + INTC_GRP7, + INTC_GRP8, + INTC_GRP9, + INTC_GRP10, + INTC_GRP11, + INTC_GRP12, + INTC_GRP13, + INTC_GRP14, + INTC_GRP15, + INTC_GRP_NUM, + NO_GRP, +}; + +enum INTC_POL { + INTC_POL_HIGH = 0x0, + INTC_POL_LOW = 0x1, + INTC_POL_NUM, +}; + +struct intc_irq_desc_t { + uint8_t id; + uint8_t group; + uint8_t pol; +}; + +struct intc_desc_t { + uint32_t int_en[INTC_GRP_LEN]; + uint32_t grp_irqs[INTC_GRP_NUM][INTC_GRP_LEN]; + struct intc_irq_desc_t irqs[IRQ_MAX_CHANNEL]; +}; + +struct intc_irq_config { + uint32_t int_en[INTC_GRP_LEN]; +}; + +struct intc_grp_config { + uint32_t grp_irq[INTC_GRP_NUM][INTC_GRP_LEN]; +}; + +struct intc_coreoff_wake_en_config { + uint32_t wake_en[INTC_GRP_LEN]; +}; + +struct intc_sleep_wake_en_config { + uint32_t wake_en[INTC_GRP_LEN]; +}; + +extern const unsigned char grp_pri[INTC_GRP_NUM]; +extern const uint8_t irq2grp_map[IRQ_MAX_CHANNEL]; +extern const uint8_t grp2hifi_irq_map[INTC_GRP_NUM]; +void intc_init(void); + +#ifdef CFG_TICKLESS_SUPPORT +extern struct intc_sleep_wake_en_config sleep_wakeup_src_en; +#endif +#ifdef CFG_CORE_OFF_SUPPORT +extern struct intc_coreoff_wake_en_config coreoff_wakeup_src_en; +#endif + +#endif /* INTC_H */ + diff --git a/src/platform/mt8196/include/platform/drivers/interrupt.h b/src/platform/mt8196/include/platform/drivers/interrupt.h new file mode 100644 index 000000000000..71048100df8c --- /dev/null +++ b/src/platform/mt8196/include/platform/drivers/interrupt.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + */ + +#ifdef __SOF_DRIVERS_INTERRUPT_H__ + +#ifndef __PLATFORM_DRIVERS_INTERRUPT_H__ +#define __PLATFORM_DRIVERS_INTERRUPT_H__ + +#include +#include +#include + +#define PLATFORM_IRQ_HW_NUM XCHAL_NUM_INTERRUPTS +#define PLATFORM_IRQ_FIRST_CHILD PLATFORM_IRQ_HW_NUM +#define PLATFORM_IRQ_CHILDREN 32 + +/* MTK_ADSP_IRQ_MASK */ +#define MTK_DSP_OUT_IRQ_MASK 0x3FF + +#define HIFI_IRQ_MAX_CHANNEL 26 + +#define DEFALUT_WAKEUP_SRC_MASK_BIT 0x001A5E13 +#define DEFAULT_WAKEUP_SRC_EN0_BIT 0xA046B550 +#define DEFAULT_WAKEUP_SRC_EN1_BIT 0x00002148 + +#define MTK_DSP_IRQ_MBOX_C0 2 +#define MTK_DSP_IRQ_OSTIMER32_C0 1 +#define IPC0_IRQn IPC_C0_IRQn +#define C2C_SW_IRQn C2C_SW_C0_IRQn +#define CCIF3_IRQn CCIF3_C0_IRQn +#define DMA_IRQn DMA_C0_IRQn +#define AUDIO_IRQn AUDIO_C0_IRQn +#define HIFI5_WDT_IRQn HIFI5_WDT_C0_IRQn +#define APU_MBOX_IRQn APU_MBOX_C0_IRQn +#define PWR_ON_CORE_IRQn PWR_ON_C0_IRQ +#define WAKEUP_SRC_IRQn WAKEUP_SRC_C0_IRQn +#define AXI_DMA_CH0_IRQn AXI_DMA0_IRQn +#define AXI_DMA_CH1_IRQn AXI_DMA2_IRQn + +/* following interrupts are HiFi internal interrupts */ +#define MTK_DSP_IRQ_NMI 25 +#define MTK_DSP_IRQ_PROFILING 29 +#define MTK_DSP_IRQ_WERR 30 +#define MTK_DSP_IRQ_SW 31 +#define MTK_MAX_IRQ_NUM 59 + +/* grouped mailbox IRQ */ +#define MTK_DSP_IRQ_MBOX0 59 +#define MTK_DSP_IRQ_MBOX1 60 +#define MTK_DSP_IRQ_MBOX2 61 +#define MTK_DSP_IRQ_MBOX3 62 +#define MTK_DSP_IRQ_MBOX4 63 + +#define MTK_DSP_MBOX_MASK 0xF + +int mtk_irq_group_id(uint32_t irq); +void intc_irq_unmask(enum IRQn_Type irq); +void intc_irq_mask(enum IRQn_Type irq); +int intc_irq_enable(enum IRQn_Type irq); +int intc_irq_disable(enum IRQn_Type irq); + +#endif /* __PLATFORM_DRIVERS_INTERRUPT_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/drivers/interrupt.h" + +#endif /* __SOF_DRIVERS_INTERRUPT_H__ */ diff --git a/src/platform/mt8196/include/platform/drivers/mt_reg_base.h b/src/platform/mt8196/include/platform/drivers/mt_reg_base.h index 21605116506b..bb990270512e 100644 --- a/src/platform/mt8196/include/platform/drivers/mt_reg_base.h +++ b/src/platform/mt8196/include/platform/drivers/mt_reg_base.h @@ -22,7 +22,6 @@ #define MTK_ADSP_GENERAL_IRQ_CLR (MTK_DSP_CFGREG_BASE + 0x0038) #define MTK_ADSP_DVFSRC_STATE (MTK_DSP_CFGREG_BASE + 0x003c) #define MTK_ADSP_DVFSRC_REQ (MTK_DSP_CFGREG_BASE + 0x0040) -//todo #define MTK_ADSP_DDREN_REQ_0 (MTK_DSP_CFGREG_BASE + 0x0044) #define MTK_ADSP_SPM_ACK (MTK_DSP_CFGREG_BASE + 0x004c) #define MTK_ADSP_IRQ_EN (MTK_DSP_CFGREG_BASE + 0x0050) @@ -53,7 +52,6 @@ #define INTC_IRQ_GRP0_STA0 (MTK_ADSP_INTC_BASE + 0x0C0) #define INTC_GRP_IRQ_OUT_STA (MTK_ADSP_INTC_BASE + 0x140) -//todo #define MTK_GPR_RW_REG0 (MTK_DSP_CFGREG_BASE + 0x0440) #define MTK_GPR_RW_REG1 (MTK_DSP_CFGREG_BASE + 0x0444) #define MTK_GPR_RW_REG2 (MTK_DSP_CFGREG_BASE + 0x0448) @@ -91,7 +89,6 @@ #define MTK_DSP_CKCTRL_BASE (MTK_DSP_CFGREG_BASE + 0x1000) #define MTK_DSP_CKCTRL_SIZE 0x1000 -//todo #define MTK_DSP_OS_TIMER_BASE (MTK_DSP_CFGREG_BASE + 0xB000) #define MTK_DSP_OS_TIMER_SIZE 0x1000 @@ -106,35 +103,6 @@ #define MTK_DSP_SECURE_BASE (MTK_DSP_CFGREG_BASE + 0x345000) #define MTK_MBOX_IRQ_IN (MTK_DSP_SECURE_BASE + 0x70) -#define MTK_REG_TOPCKGEN_BASE 0x10000000 -#define MTK_REG_TOPCKGEN_SIZE 0x1000 -#define MTK_CLK_CFG_UPDATE1 (MTK_REG_TOPCKGEN_BASE + 0x0008) -#define MTK_CLK_CFG_13_STA (MTK_REG_TOPCKGEN_BASE + 0x00E0) -#define MTK_CLK_CFG_13_SET (MTK_REG_TOPCKGEN_BASE + 0x00E4) -#define MTK_CLK_CFG_13_CLR (MTK_REG_TOPCKGEN_BASE + 0x00E8) -#define MTK_ADSP_CK_UPDATE (0x1 << 23) -#define MTK_ADSP_SEL_BASE (16) - -//todo -#define MTK_CLK_CFG_UPDATE2 (MTK_REG_TOPCKGEN_BASE + 0x000C) -#define MTK_CLK_CFG_17 (MTK_REG_TOPCKGEN_BASE + 0x0EC) -#define MTK_CLK_CFG_17_SET (MTK_REG_TOPCKGEN_BASE + 0x0F0) -#define MTK_CLK_CFG_17_CLR (MTK_REG_TOPCKGEN_BASE + 0x0F4) -#define MTK_CLK_CFG_17_CLR (MTK_REG_TOPCKGEN_BASE + 0x0F4) - -//todo, pll base? -#define MTK_REG_APMIXDSYS_BASE 0x10000800 -#define MTK_REG_APMIXDSYS_SIZE 0x1000 - -//todo -#define MTK_PLLEN_ALL_EN (MTK_REG_APMIXDSYS_BASE + 0x0080) -#define MTK_PLLEN_ALL_SET (MTK_REG_APMIXDSYS_BASE + 0x0084) -#define MTK_PLLEN_ALL_CLR (MTK_REG_APMIXDSYS_BASE + 0x0088) -#define MTK_ADSPPLL_CON0 (MTK_REG_APMIXDSYS_BASE + 0x028c) -#define MTK_ADSPPLL_CON1 (MTK_REG_APMIXDSYS_BASE + 0x0290) -#define MTK_PLL_ADSP_EN_BIT (0x1 << 3) - - /* MBOX registers */ #define MTK_ADSP_MBOX_BASE (MTK_DSP_CFGREG_BASE + 0x350000) #define MTK_ADSP_MBOX_REG_BASE(x) (MTK_ADSP_MBOX_BASE + (0x10000 * (x))) diff --git a/src/platform/mt8196/include/platform/drivers/timer.h b/src/platform/mt8196/include/platform/drivers/timer.h new file mode 100644 index 000000000000..8aeacca52981 --- /dev/null +++ b/src/platform/mt8196/include/platform/drivers/timer.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + */ + +#ifndef __PLATFORM_DRIVERS_TIMER_H__ +#define __PLATFORM_DRIVERS_TIMER_H__ + +#include +#include + +/*-------timer:ostimer0-------*/ +enum ostimer { + OSTIMER0 = 0, + OSTIMER1, + OSTIMER2, + OSTIMER3, + NR_TMRS +}; + +#define MTK_TIMER_CON(n) (MTK_DSP_OS_TIMER_BASE + 0x0 + 0x10 * (n)) +#define MTK_TIMER_RST_VAL(n) (MTK_DSP_OS_TIMER_BASE + 0x4 + 0x10 * (n)) +#define MTK_TIMER_CUR_VAL(n) (MTK_DSP_OS_TIMER_BASE + 0x8 + 0x10 * (n)) +#define MTK_TIMER_IRQ_ACK(n) (MTK_DSP_OS_TIMER_BASE + 0xC + 0x10 * (n)) + +#define MTK_TIMER_ENABLE_BIT BIT(0) +#define MTK_TIMER_IRQ_ENABLE BIT(0) +#define MTK_TIMER_IRQ_STA BIT(4) +#define MTK_TIMER_IRQ_CLEAR BIT(5) + +#define MTK_TIMER_CLKSRC_BIT (BIT(4) | BIT(5)) +#define MTK_TIMER_CLK_SRC_CLK_26M 0 +#define MTK_TIMER_CLK_SRC_BCLK BIT(5) +#define MTK_TIMER_CLK_SRC_PCLK (BIT(4) | BIT(5)) + +/*-------platform_timer: 64 bit systimer-------*/ +#define MTK_OSTIMER_CON (MTK_DSP_OS_TIMER_BASE + 0x80) +#define MTK_OSTIMER_CUR_L (MTK_DSP_OS_TIMER_BASE + 0x8C) +#define MTK_OSTIMER_CUR_H (MTK_DSP_OS_TIMER_BASE + 0x90) +#define MTK_OSTIMER_TVAL (MTK_DSP_OS_TIMER_BASE + 0x94) +#define MTK_OSTIMER_IRQ_ACK (MTK_DSP_OS_TIMER_BASE + 0x98) + +#define MTK_OSTIMER_EN_BIT BIT(0) + +#endif /* __PLATFORM_DRIVERS_TIMER_H__ */ diff --git a/src/platform/mt8196/include/platform/lib/clk.h b/src/platform/mt8196/include/platform/lib/clk.h new file mode 100644 index 000000000000..f4f311948fb4 --- /dev/null +++ b/src/platform/mt8196/include/platform/lib/clk.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + */ + +#ifdef __SOF_LIB_CLK_H__ + +#ifndef __PLATFORM_LIB_CLK_H__ +#define __PLATFORM_LIB_CLK_H__ + +#include + +struct sof; + +#define CPU_DEFAULT_IDX 0 + +#define CLK_CPU(x) (x) +#define CLK_DEFAULT_CPU_HZ 26000000 +#define CLK_MAX_CPU_HZ 800000000 +#define NUM_CLOCKS 1 +#define NUM_CPU_FREQ 2 + +void platform_clock_init(struct sof *sof); + +#endif /* __PLATFORM_LIB_CLK_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/clk.h" + +#endif /* __SOF_LIB_CLK_H__ */ diff --git a/src/platform/mt8196/include/platform/lib/cpu.h b/src/platform/mt8196/include/platform/lib/cpu.h new file mode 100644 index 000000000000..f99974213c2f --- /dev/null +++ b/src/platform/mt8196/include/platform/lib/cpu.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + */ + +#ifdef __SOF_LIB_CPU_H__ + +#ifndef __PLATFORM_LIB_CPU_H__ +#define __PLATFORM_LIB_CPU_H__ + +/** \brief Id of primary DSP core */ +#define PLATFORM_PRIMARY_CORE_ID 0 + +#endif /* __PLATFORM_LIB_CPU_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/cpu.h" + +#endif /* __SOF_LIB_CPU_H__ */ diff --git a/src/platform/mt8196/include/platform/lib/dai.h b/src/platform/mt8196/include/platform/lib/dai.h new file mode 100644 index 000000000000..e56a35d5ccc1 --- /dev/null +++ b/src/platform/mt8196/include/platform/lib/dai.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + */ + +#ifdef __SOF_LIB_DAI_H__ + +#ifndef __PLATFORM_LIB_DAI_H__ +#define __PLATFORM_LIB_DAI_H__ + +#endif /* __PLATFORM_LIB_DAI_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/dai.h" + +#endif /* __SOF_LIB_DAI_H__ */ diff --git a/src/platform/mt8196/include/platform/lib/dma.h b/src/platform/mt8196/include/platform/lib/dma.h new file mode 100644 index 000000000000..419f160cbfd9 --- /dev/null +++ b/src/platform/mt8196/include/platform/lib/dma.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + */ + +#ifdef __SOF_LIB_DMA_H__ + +#ifndef __PLATFORM_LIB_DMA_H__ +#define __PLATFORM_LIB_DMA_H__ + +#define PLATFORM_NUM_DMACS 2 + +/* max number of supported DMA channels */ +#define PLATFORM_MAX_DMA_CHAN 32 + +#define DMA_ID_AFE_MEMIF 0 +#define DMA_ID_HOST 1 + +#define dma_chan_irq(dma, chan) dma_irq(dma) +#define dma_chan_irq_name(dma, chan) dma_irq_name(dma) + +#endif /* __PLATFORM_LIB_DMA_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/dma.h" + +#endif /* __SOF_LIB_DMA_H__ */ diff --git a/src/platform/mt8196/include/platform/lib/mailbox.h b/src/platform/mt8196/include/platform/lib/mailbox.h new file mode 100644 index 000000000000..04896aaa3ee5 --- /dev/null +++ b/src/platform/mt8196/include/platform/lib/mailbox.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + */ + +#ifdef __SOF_LIB_MAILBOX_H__ + +#ifndef __PLATFORM_LIB_MAILBOX_H__ +#define __PLATFORM_LIB_MAILBOX_H__ + +#include +#include +#include +#include + +/* + * The Window Region on MT8186 SRAM is organised like this :- + * +--------------------------------------------------------------------------+ + * | Offset | Region | Size | + * +---------------------+----------------+-----------------------------------+ + * | SRAM_OUTBOX_BASE | Outbox | SRAM_MAILBOX_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SRAM_INBOX_BASE | Inbox | SRAM_INBOX_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SRAM_DEBUG_BASE | Debug data | SRAM_DEBUG_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SRAM_EXCEPT_BASE | Except | SRAM_EXCEPT_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SRAM_STREAM_BASE | Stream | SRAM_STREAM_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SRAM_TRACE_BASE | Trace Buffer | SRAM_TRACE_SIZE | + * +---------------------+----------------+-----------------------------------+ + */ + +#define MAILBOX_DSPBOX_SIZE SRAM_OUTBOX_SIZE +#define MAILBOX_DSPBOX_BASE SRAM_OUTBOX_BASE +#define MAILBOX_DSPBOX_OFFSET SRAM_OUTBOX_OFFSET + +#define MAILBOX_HOSTBOX_SIZE SRAM_INBOX_SIZE +#define MAILBOX_HOSTBOX_BASE SRAM_INBOX_BASE +#define MAILBOX_HOSTBOX_OFFSET SRAM_INBOX_OFFSET + +#define MAILBOX_DEBUG_SIZE SRAM_DEBUG_SIZE +#define MAILBOX_DEBUG_BASE SRAM_DEBUG_BASE +#define MAILBOX_DEBUG_OFFSET SRAM_DEBUG_OFFSET + +#define MAILBOX_EXCEPTION_SIZE SRAM_EXCEPT_SIZE +#define MAILBOX_EXCEPTION_BASE SRAM_EXCEPT_BASE +#define MAILBOX_EXCEPTION_OFFSET SRAM_EXCEPT_OFFSET + +#define MAILBOX_STREAM_SIZE SRAM_STREAM_SIZE +#define MAILBOX_STREAM_BASE SRAM_STREAM_BASE +#define MAILBOX_STREAM_OFFSET SRAM_STREAM_OFFSET + +#define MAILBOX_TRACE_SIZE SRAM_TRACE_SIZE +#define MAILBOX_TRACE_BASE SRAM_TRACE_BASE +#define MAILBOX_TRACE_OFFSET SRAM_TRACE_OFFSET + +#define ADSP_IPI_OP_REQ 0x1 +#define ADSP_IPI_OP_RSP 0x2 +void trigger_irq_to_host_req(void); +void trigger_irq_to_host_rsp(void); + +static inline void mailbox_sw_reg_write(size_t offset, uint32_t src) +{ + io_reg_write(MAILBOX_DEBUG_BASE + offset, src); +} + +#endif /* __PLATFORM_LIB_MAILBOX_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/mailbox.h" + +#endif /* __SOF_LIB_MAILBOX_H__ */ diff --git a/src/platform/mt8196/include/platform/lib/pm_runtime.h b/src/platform/mt8196/include/platform/lib/pm_runtime.h new file mode 100644 index 000000000000..7d6213823fd6 --- /dev/null +++ b/src/platform/mt8196/include/platform/lib/pm_runtime.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + */ + +#ifdef __SOF_LIB_PM_RUNTIME_H__ + +#ifndef __PLATFORM_LIB_PM_RUNTIME_H__ +#define __PLATFORM_LIB_PM_RUNTIME_H__ + +#include + +struct pm_runtime_data; + +/** + * \brief Initializes platform specific runtime power management. + * \param[in,out] prd Runtime power management data. + */ +static inline void platform_pm_runtime_init(struct pm_runtime_data *prd) +{ +} + +/** + * \brief Retrieves platform specific power management resource. + * + * \param[in] context Type of power management context. + * \param[in] index The index of the device. + * \param[in] flags The flags, set of RPM_... + */ +static inline void platform_pm_runtime_get(uint32_t context, uint32_t index, uint32_t flags) +{ +} + +/** + * \brief Releases platform specific power management resource. + * + * \param[in] context Type of power management context. + * \param[in] index The index of the device. + * \param[in] flags The flags, set of RPM_... + */ +static inline void platform_pm_runtime_put(uint32_t context, uint32_t index, uint32_t flags) +{ +} + +static inline void platform_pm_runtime_enable(uint32_t context, uint32_t index) +{ +} + +static inline void platform_pm_runtime_disable(uint32_t context, uint32_t index) +{ +} + +static inline bool platform_pm_runtime_is_active(uint32_t context, uint32_t index) +{ + return false; +} + +#endif /* __PLATFORM_LIB_PM_RUNTIME_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/pm_runtime.h" + +#endif /* __SOF_LIB_PM_RUNTIME_H__ */ diff --git a/src/platform/mt8196/include/platform/platform.h b/src/platform/mt8196/include/platform/platform.h new file mode 100644 index 000000000000..60becc79ded7 --- /dev/null +++ b/src/platform/mt8196/include/platform/platform.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + */ + +#ifdef __SOF_PLATFORM_H__ + +#ifndef __PLATFORM_PLATFORM_H__ +#define __PLATFORM_PLATFORM_H__ + +#if !defined(__ASSEMBLER__) && !defined(LINKER) + +#include +#include +#include + +struct ll_schedule_domain; +struct timer; + +#define PLATFORM_DEFAULT_CLOCK CLK_CPU(0) +#define LPSRAM_SIZE 16384 + +/* IPC Interrupt */ +#define PLATFORM_IPC_INTERRUPT MTK_DSP_IRQ_MAILBOX +#define PLATFORM_IPC_INTERRUPT_NAME NULL + +/* Host page size */ +#define HOST_PAGE_SIZE 4096 +#define PLATFORM_PAGE_TABLE_SIZE 256 + +/* pipeline IRQ */ +#define PLATFORM_SCHEDULE_IRQ MTK_DSP_IRQ_SW +#define PLATFORM_SCHEDULE_IRQ_NAME NULL + +/* Platform stream capabilities */ +#define PLATFORM_MAX_CHANNELS 4 +#define PLATFORM_MAX_STREAMS 5 + +/* local buffer size of DMA tracing */ +#define DMA_TRACE_LOCAL_SIZE HOST_PAGE_SIZE + +/* trace bytes flushed during panic */ +#define DMA_FLUSH_TRACE_SIZE (MAILBOX_TRACE_SIZE >> 2) + +/* the interval of DMA trace copying */ +#define DMA_TRACE_PERIOD 500000 + +/* + * the interval of reschedule DMA trace copying in special case like half + * fullness of local DMA trace buffer + */ +#define DMA_TRACE_RESCHEDULE_TIME 100 + +/* DSP default delay in cycles */ +#define PLATFORM_DEFAULT_DELAY 12 + +#define SRAM_REG_FW_STATUS 0x4 + +/* Platform defined panic code */ +static inline void platform_panic(uint32_t p) +{ + /* Store the error code in the debug box so the + * application processor can pick it up. Takes up 4 bytes + * from the debug box. + */ + mailbox_sw_reg_write(SRAM_REG_FW_STATUS, p); + + /* Notify application processor */ + trigger_irq_to_host_req(); +} + +/** + * \brief Platform specific CPU entering idle. + * May be power-optimized using platform specific capabilities. + * @param level Interrupt level. + */ +void platform_wait_for_interrupt(int level); + +extern intptr_t _module_init_start; +extern intptr_t _module_init_end; +#endif + +#endif /* __PLATFORM_PLATFORM_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/platform.h" + +#endif /* __SOF_PLATFORM_H__ */ diff --git a/src/platform/mt8196/include/platform/trace/trace.h b/src/platform/mt8196/include/platform/trace/trace.h new file mode 100644 index 000000000000..ede2259cf192 --- /dev/null +++ b/src/platform/mt8196/include/platform/trace/trace.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + */ + +#ifdef __SOF_TRACE_TRACE_H__ + +#ifndef __PLATFORM_TRACE_TRACE_H__ +#define __PLATFORM_TRACE_TRACE_H__ + +#include +#include +#include +#include + +#define platform_trace_point(__x) + +#endif /* __PLATFORM_TRACE_TRACE_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/trace/trace.h" + +#endif /* __SOF_TRACE_TRACE_H__ */ diff --git a/src/platform/mt8196/lib/CMakeLists.txt b/src/platform/mt8196/lib/CMakeLists.txt new file mode 100644 index 000000000000..63d0f657cbd0 --- /dev/null +++ b/src/platform/mt8196/lib/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: BSD-3-Clause + +add_local_sources(sof + clk.c + dma.c + memory.c +) diff --git a/src/platform/mt8196/lib/clk.c b/src/platform/mt8196/lib/clk.c new file mode 100644 index 000000000000..69af725dec73 --- /dev/null +++ b/src/platform/mt8196/lib/clk.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +SOF_DEFINE_REG_UUID(clkdrv_mt8196); + +DECLARE_TR_CTX(clkdrv_tr, SOF_UUID(clkdrv_mt8196_uuid), LOG_LEVEL_INFO); + +/* default voltage is 0.75V */ +const struct freq_table platform_cpu_freq[] = { + { 26000000, 26000}, + { 800000000, 26000}, +}; + +STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ, + invalid_number_of_cpu_frequencies); + +static SHARED_DATA struct clock_info platform_clocks_info[NUM_CLOCKS]; + +void platform_clock_init(struct sof *sof) +{ + int i; + + tr_dbg(&clkdrv_tr, "clock init\n"); + sof->clocks = platform_shared_get(platform_clocks_info, sizeof(platform_clocks_info)); + + /* When the system is in an active state, the DSP clock operates at 800MHz (0.75V). + * In a low power scenario, the DSP enters WFI state, and the clock reduces to 26MHz. + * The clock selection is controlled by the host, and we do not allow SOF to change + * the ADSP frequency. + */ + for (i = 0; i < CONFIG_CORE_COUNT; i++) { + sof->clocks[i] = (struct clock_info){ + .freqs_num = NUM_CPU_FREQ, + .freqs = platform_cpu_freq, + .default_freq_idx = CPU_DEFAULT_IDX, + .current_freq_idx = CPU_DEFAULT_IDX, + .notification_id = NOTIFIER_ID_CPU_FREQ, + .notification_mask = NOTIFIER_TARGET_CORE_MASK(i), + .set_freq = NULL, + }; + } +} diff --git a/src/platform/mt8196/lib/dma.c b/src/platform/mt8196/lib/dma.c new file mode 100644 index 000000000000..daa22f46a9f3 --- /dev/null +++ b/src/platform/mt8196/lib/dma.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + */ + +#include +#include +#include +#include +#include +#include + +extern const struct dma_ops dummy_dma_ops; + +static SHARED_DATA struct dma dma[PLATFORM_NUM_DMACS] = { +{ + .plat_data = { + .id = DMA_ID_HOST, + .dir = DMA_DIR_HMEM_TO_LMEM | DMA_DIR_LMEM_TO_HMEM, + .devs = DMA_DEV_HOST, + .channels = 16, + }, + .ops = &dummy_dma_ops, +}, +}; + +static const struct dma_info lib_dma = { + .dma_array = cache_to_uncache_init((struct dma *)dma), + .num_dmas = ARRAY_SIZE(dma) +}; + +int dmac_init(struct sof *sof) +{ + int i; + + /* early lock initialization for ref counting */ + for (i = 0; i < ARRAY_SIZE(dma); i++) + k_spinlock_init(&dma[i].lock); + + sof->dma_info = &lib_dma; + + return 0; +} diff --git a/src/platform/mt8196/lib/memory.c b/src/platform/mt8196/lib/memory.c new file mode 100644 index 000000000000..dca28790d741 --- /dev/null +++ b/src/platform/mt8196/lib/memory.c @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + */ + +#include +#include +#include +#include +#include + +/* Heap blocks for system runtime */ +static SHARED_DATA struct block_hdr sys_rt_block64[HEAP_SYS_RT_COUNT64]; +static SHARED_DATA struct block_hdr sys_rt_block512[HEAP_SYS_RT_COUNT512]; +static SHARED_DATA struct block_hdr sys_rt_block1024[HEAP_SYS_RT_COUNT1024]; + +/* Heap memory for system runtime */ +static SHARED_DATA struct block_map sys_rt_heap_map[] = { + BLOCK_DEF(64, HEAP_SYS_RT_COUNT64, sys_rt_block64), + BLOCK_DEF(512, HEAP_SYS_RT_COUNT512, sys_rt_block512), + BLOCK_DEF(1024, HEAP_SYS_RT_COUNT1024, sys_rt_block1024), +}; + +/* Heap blocks for modules */ +static SHARED_DATA struct block_hdr mod_block16[HEAP_RT_COUNT16]; +static SHARED_DATA struct block_hdr mod_block32[HEAP_RT_COUNT32]; +static SHARED_DATA struct block_hdr mod_block64[HEAP_RT_COUNT64]; +static SHARED_DATA struct block_hdr mod_block128[HEAP_RT_COUNT128]; +static SHARED_DATA struct block_hdr mod_block256[HEAP_RT_COUNT256]; +static SHARED_DATA struct block_hdr mod_block512[HEAP_RT_COUNT512]; +static SHARED_DATA struct block_hdr mod_block1024[HEAP_RT_COUNT1024]; +static SHARED_DATA struct block_hdr mod_block2048[HEAP_RT_COUNT2048]; +static SHARED_DATA struct block_hdr mod_block4096[HEAP_RT_COUNT4096]; + +/* Heap memory map for modules */ +static SHARED_DATA struct block_map rt_heap_map[] = { + BLOCK_DEF(16, HEAP_RT_COUNT16, mod_block16), + BLOCK_DEF(32, HEAP_RT_COUNT32, mod_block32), + BLOCK_DEF(64, HEAP_RT_COUNT64, mod_block64), + BLOCK_DEF(128, HEAP_RT_COUNT128, mod_block128), + BLOCK_DEF(256, HEAP_RT_COUNT256, mod_block256), + BLOCK_DEF(512, HEAP_RT_COUNT512, mod_block512), + BLOCK_DEF(1024, HEAP_RT_COUNT1024, mod_block1024), + BLOCK_DEF(2048, HEAP_RT_COUNT2048, mod_block2048), + BLOCK_DEF(4096, HEAP_RT_COUNT4096, mod_block4096), +}; + +/* Heap blocks for buffers */ +static SHARED_DATA struct block_hdr buf_block[HEAP_BUFFER_COUNT]; + +/* Heap memory map for buffers */ +static SHARED_DATA struct block_map buf_heap_map[] = { + BLOCK_DEF(HEAP_BUFFER_BLOCK_SIZE, HEAP_BUFFER_COUNT, buf_block), +}; + +static SHARED_DATA struct mm memmap = { + .system[0] = { + .heap = HEAP_SYSTEM_BASE, + .size = HEAP_SYSTEM_SIZE, + .info = {.free = HEAP_SYSTEM_SIZE,}, + .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE | + SOF_MEM_CAPS_DMA, + }, + .system_runtime[0] = { + .blocks = ARRAY_SIZE(sys_rt_heap_map), + .map = sys_rt_heap_map, + .heap = HEAP_SYS_RUNTIME_BASE, + .size = HEAP_SYS_RUNTIME_SIZE, + .info = {.free = HEAP_SYS_RUNTIME_SIZE,}, + .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE | + SOF_MEM_CAPS_DMA, + }, + .runtime[0] = { + .blocks = ARRAY_SIZE(rt_heap_map), + .map = rt_heap_map, + .heap = HEAP_RUNTIME_BASE, + .size = HEAP_RUNTIME_SIZE, + .info = {.free = HEAP_RUNTIME_SIZE,}, + .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE | + SOF_MEM_CAPS_DMA, + }, + .buffer[0] = { + .blocks = ARRAY_SIZE(buf_heap_map), + .map = buf_heap_map, + .heap = HEAP_BUFFER_BASE, + .size = HEAP_BUFFER_SIZE, + .info = {.free = HEAP_BUFFER_SIZE,}, + .caps = SOF_MEM_CAPS_RAM | SOF_MEM_CAPS_CACHE | + SOF_MEM_CAPS_DMA, + }, + .total = {.free = HEAP_SYSTEM_SIZE + HEAP_SYS_RUNTIME_SIZE + + HEAP_RUNTIME_SIZE + HEAP_BUFFER_SIZE,}, +}; + +void platform_init_memmap(struct sof *sof) +{ + /* memmap has been initialized statically as a part of .data */ + sof->memory_map = platform_shared_get(&memmap, sizeof(memmap)); +} diff --git a/src/platform/mt8196/mt8196.x.in b/src/platform/mt8196/mt8196.x.in new file mode 100644 index 000000000000..939779d8f120 --- /dev/null +++ b/src/platform/mt8196/mt8196.x.in @@ -0,0 +1,554 @@ +/* + * Linker Script for mt8196 MediaTek + * + * This script is run through the GNU C preprocessor to align the memory + * offsets with headers. + * + * Use spaces for formatting as cpp ignore tab sizes. + */ + + +#include +#include + +#if CONFIG_MEDIATEK_DRAM_IMAGE +#define IMAGE_LOC sof_dram +#else +#define IMAGE_LOC sof_sram +#endif + +OUTPUT_ARCH(xtensa) + +MEMORY +{ + vector_reset_text : + org = XCHAL_RESET_VECTOR0_PADDR, + len = SOF_MEM_RESET_TEXT_SIZE + vector_reset_lit : + org = XCHAL_RESET_VECTOR0_PADDR + SOF_MEM_RESET_TEXT_SIZE, + len = SOF_MEM_RESET_LIT_SIZE + vector_base_text : + org = XCHAL_VECBASE_RESET_PADDR, + len = SOF_MEM_VECBASE_LIT_SIZE + vector_int2_lit : + org = XCHAL_INTLEVEL2_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_int2_text : + org = XCHAL_INTLEVEL2_VECTOR_PADDR, + len = SOF_MEM_VECT_TEXT_SIZE + vector_int3_lit : + org = XCHAL_INTLEVEL3_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_int3_text : + org = XCHAL_INTLEVEL3_VECTOR_PADDR, + len = SOF_MEM_VECT_TEXT_SIZE + vector_int4_lit : + org = XCHAL_INTLEVEL4_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_int4_text : + org = XCHAL_INTLEVEL4_VECTOR_PADDR, + len = SOF_MEM_VECT_TEXT_SIZE + vector_int5_lit : + org = XCHAL_INTLEVEL5_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_int5_text : + org = XCHAL_INTLEVEL5_VECTOR_PADDR, + len = SOF_MEM_VECT_TEXT_SIZE + vector_kernel_lit : + org = XCHAL_KERNEL_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_kernel_text : + org = XCHAL_KERNEL_VECTOR_PADDR, + len = SOF_MEM_VECT_TEXT_SIZE + vector_user_lit : + org = XCHAL_USER_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_user_text : + org = XCHAL_USER_VECTOR_PADDR, + len = SOF_MEM_VECT_TEXT_SIZE + vector_double_lit : + org = XCHAL_DOUBLEEXC_VECTOR_PADDR - SOF_MEM_VECT_LIT_SIZE, + len = SOF_MEM_VECT_LIT_SIZE + vector_double_text : + org = XCHAL_DOUBLEEXC_VECTOR_PADDR, + len = SOF_MEM_VECT_TEXT_SIZE + sof_sram : + org = SRAM_START, + len = SRAM_SIZE + sof_dram : + org = SOF_DRAM_BASE, + len = SOF_DRAM_SIZE + system_heap : + org = HEAP_SYSTEM_BASE, + len = HEAP_SYSTEM_SIZE + system_runtime_heap : + org = HEAP_SYS_RUNTIME_BASE, + len = HEAP_SYS_RUNTIME_SIZE + runtime_heap : + org = HEAP_RUNTIME_BASE, + len = HEAP_RUNTIME_SIZE + buffer_heap : + org = HEAP_BUFFER_BASE, + len = HEAP_BUFFER_SIZE + sof_stack : + org = SOF_STACK_END, + len = SOF_STACK_BASE - SOF_STACK_END + static_uuid_entries_seg (!ari) : + org = UUID_ENTRY_ELF_BASE, + len = UUID_ENTRY_ELF_SIZE + static_log_entries_seg (!ari) : + org = LOG_ENTRY_ELF_BASE, + len = LOG_ENTRY_ELF_SIZE + fw_metadata_seg (!ari) : + org = EXT_MANIFEST_ELF_BASE, + len = EXT_MANIFEST_ELF_SIZE +} + +PHDRS +{ + vector_reset_text_phdr PT_LOAD; + vector_reset_lit_phdr PT_LOAD; + vector_base_text_phdr PT_LOAD; + vector_base_lit_phdr PT_LOAD; + vector_int2_text_phdr PT_LOAD; + vector_int2_lit_phdr PT_LOAD; + vector_int3_text_phdr PT_LOAD; + vector_int3_lit_phdr PT_LOAD; + vector_int4_text_phdr PT_LOAD; + vector_int4_lit_phdr PT_LOAD; + vector_int5_text_phdr PT_LOAD; + vector_int5_lit_phdr PT_LOAD; + vector_kernel_text_phdr PT_LOAD; + vector_kernel_lit_phdr PT_LOAD; + vector_user_text_phdr PT_LOAD; + vector_user_lit_phdr PT_LOAD; + vector_double_text_phdr PT_LOAD; + vector_double_lit_phdr PT_LOAD; + sof_sram_phdr PT_LOAD; + system_heap_phdr PT_LOAD; + system_runtime_heap_phdr PT_LOAD; + runtime_heap_phdr PT_LOAD; + buffer_heap_phdr PT_LOAD; + sof_stack_phdr PT_LOAD; + static_uuid_entries_phdr PT_NOTE; + static_log_entries_phdr PT_NOTE; + metadata_entries_phdr PT_NOTE; +} + +/* Default entry point: */ +ENTRY(_ResetVector) +_rom_store_table = 0; + +/* ABI0 does not use Window base */ +PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR); + +/* Various memory-map dependent cache attribute settings: */ +_memmap_cacheattr_wb_base = 0x00000404; +_memmap_cacheattr_wt_base = 0x00000404; +_memmap_cacheattr_bp_base = 0x00000404; +_memmap_cacheattr_unused_mask = 0xFFFFF0FF; +_memmap_cacheattr_wb_trapnull = 0x44444444; +_memmap_cacheattr_wba_trapnull = 0x44444444; +_memmap_cacheattr_wbna_trapnull = 0x44444444; +_memmap_cacheattr_wt_trapnull = 0x44444444; +_memmap_cacheattr_bp_trapnull = 0x44444444; +_memmap_cacheattr_wb_strict = 0x00000404; +_memmap_cacheattr_wt_strict = 0x00000404; +_memmap_cacheattr_bp_strict = 0x00000404; +_memmap_cacheattr_wb_allvalid = 0x44444444; +_memmap_cacheattr_wt_allvalid = 0x44444444; +_memmap_cacheattr_bp_allvalid = 0x44444444; +PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); + +_EXT_MAN_ALIGN_ = 16; +EXTERN(ext_man_fw_ver) + +SECTIONS +{ + .ResetVector.text : ALIGN(4) + { + _ResetVector_text_start = ABSOLUTE(.); + KEEP (*(.ResetVector.text)) + _ResetVector_text_end = ABSOLUTE(.); + } >vector_reset_text :vector_reset_text_phdr + + .ResetVector.literal : ALIGN(4) + { + _ResetVector_literal_start = ABSOLUTE(.); + *(.ResetVector.literal) + _ResetVector_literal_end = ABSOLUTE(.); + } >vector_reset_lit :vector_reset_lit_phdr + + .WindowVectors.text : ALIGN(4) + { + _WindowVectors_text_start = ABSOLUTE(.); + KEEP (*(.WindowVectors.text)) + _WindowVectors_text_end = ABSOLUTE(.); + } >vector_base_text :vector_base_text_phdr + + .Level2InterruptVector.literal : ALIGN(4) + { + _Level2InterruptVector_literal_start = ABSOLUTE(.); + *(.Level2InterruptVector.literal) + _Level2InterruptVector_literal_end = ABSOLUTE(.); + } >vector_int2_lit :vector_int2_lit_phdr + + .Level2InterruptVector.text : ALIGN(4) + { + _Level2InterruptVector_text_start = ABSOLUTE(.); + KEEP (*(.Level2InterruptVector.text)) + _Level2InterruptVector_text_end = ABSOLUTE(.); + } >vector_int2_text :vector_int2_text_phdr + + .Level3InterruptVector.literal : ALIGN(4) + { + _Level3InterruptVector_literal_start = ABSOLUTE(.); + *(.Level3InterruptVector.literal) + _Level3InterruptVector_literal_end = ABSOLUTE(.); + } >vector_int3_lit :vector_int3_lit_phdr + + .Level3InterruptVector.text : ALIGN(4) + { + _Level3InterruptVector_text_start = ABSOLUTE(.); + KEEP (*(.Level3InterruptVector.text)) + _Level3InterruptVector_text_end = ABSOLUTE(.); + } >vector_int3_text :vector_int3_text_phdr + + .Level4InterruptVector.literal : ALIGN(4) + { + _Level4InterruptVector_literal_start = ABSOLUTE(.); + *(.Level4InterruptVector.literal) + _Level4InterruptVector_literal_end = ABSOLUTE(.); + } >vector_int4_lit :vector_int4_lit_phdr + + .Level4InterruptVector.text : ALIGN(4) + { + _Level4InterruptVector_text_start = ABSOLUTE(.); + KEEP (*(.Level4InterruptVector.text)) + _Level4InterruptVector_text_end = ABSOLUTE(.); + } >vector_int4_text :vector_int4_text_phdr + + .DebugExceptionVector.literal : ALIGN(4) + { + _DebugExceptionVector_literal_start = ABSOLUTE(.); + *(.DebugExceptionVector.literal) + _DebugExceptionVector_literal_end = ABSOLUTE(.); + } >vector_int5_lit :vector_int5_lit_phdr + + .DebugExceptionVector.text : ALIGN(4) + { + _DebugExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.DebugExceptionVector.text)) + _DebugExceptionVector_text_end = ABSOLUTE(.); + } >vector_int5_text :vector_int5_text_phdr + + .NMIExceptionVector.literal : ALIGN(4) + { + _NMIExceptionVector_literal_start = ABSOLUTE(.); + *(.NMIExceptionVector.literal) + _NMIExceptionVector_literal_end = ABSOLUTE(.); + } >vector_int5_lit :vector_int5_lit_phdr + + .NMIExceptionVector.text : ALIGN(4) + { + _NMIExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.NMIExceptionVector.text)) + _NMIExceptionVector_text_end = ABSOLUTE(.); + } >vector_int5_text :vector_int5_text_phdr + + .KernelExceptionVector.literal : ALIGN(4) + { + _KernelExceptionVector_literal_start = ABSOLUTE(.); + *(.KernelExceptionVector.literal) + _KernelExceptionVector_literal_end = ABSOLUTE(.); + } >vector_kernel_lit :vector_kernel_lit_phdr + + .KernelExceptionVector.text : ALIGN(4) + { + _KernelExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.KernelExceptionVector.text)) + _KernelExceptionVector_text_end = ABSOLUTE(.); + } >vector_kernel_text :vector_kernel_text_phdr + + .UserExceptionVector.literal : ALIGN(4) + { + _UserExceptionVector_literal_start = ABSOLUTE(.); + *(.UserExceptionVector.literal) + _UserExceptionVector_literal_end = ABSOLUTE(.); + } >vector_user_lit :vector_user_lit_phdr + + .UserExceptionVector.text : ALIGN(4) + { + _UserExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.UserExceptionVector.text)) + _UserExceptionVector_text_end = ABSOLUTE(.); + } >vector_user_text :vector_user_text_phdr + + .DoubleExceptionVector.literal : ALIGN(4) + { + _DoubleExceptionVector_literal_start = ABSOLUTE(.); + *(.DoubleExceptionVector.literal) + _DoubleExceptionVector_literal_end = ABSOLUTE(.); + } >vector_double_lit :vector_double_lit_phdr + + .DoubleExceptionVector.text : ALIGN(4) + { + _DoubleExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.DoubleExceptionVector.text)) + _DoubleExceptionVector_text_end = ABSOLUTE(.); + } >vector_double_text :vector_double_text_phdr + + .fw_ready : ALIGN(4) + { + KEEP (*(.fw_ready)) + KEEP (*(.fw_ready_metadata)) + } >IMAGE_LOC :sof_sram_phdr + + .rodata : ALIGN(4) + { + _rodata_start = ABSOLUTE(.); + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); + KEEP (*(.xt_except_table)) + KEEP (*(.gcc_except_table)) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + KEEP (*(.eh_frame)) + /* C++ constructor and destructor tables, properly ordered: */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + . = ALIGN(4); /* this table MUST be 4-byte aligned */ + _bss_table_start = ABSOLUTE(.); + LONG(_bss_start) + LONG(_bss_end) + _bss_table_end = ABSOLUTE(.); + _rodata_end = ABSOLUTE(.); + } >IMAGE_LOC :sof_sram_phdr + + .module_init : ALIGN(4) + { + _module_init_start = ABSOLUTE(.); + *(*.initcall) + _module_init_end = ABSOLUTE(.); + } >IMAGE_LOC :sof_sram_phdr + + .text : ALIGN(4) + { + _stext = .; + _text_start = ABSOLUTE(.); + *(.entry.text) + *(.init.literal) + KEEP(*(.init)) + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.fini.literal) + KEEP(*(.fini)) + *(.gnu.version) + _text_end = ABSOLUTE(.); + _etext = .; + } >IMAGE_LOC :sof_sram_phdr + + .reset.rodata : ALIGN(4) + { + _reset_rodata_start = ABSOLUTE(.); + *(.reset.rodata) + _reset_rodata_end = ABSOLUTE(.); + } >IMAGE_LOC :sof_sram_phdr + + + .data : ALIGN(4) + { + _data_start = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + KEEP(*(.gnu.linkonce.d.*personality*)) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + KEEP(*(.jcr)) + _trace_ctx_start = ABSOLUTE(.); + *(.trace_ctx) + _trace_ctx_end = ABSOLUTE(.); + _data_end = ABSOLUTE(.); + } >IMAGE_LOC :sof_sram_phdr + + .lit4 : ALIGN(4) + { + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + } >IMAGE_LOC :sof_sram_phdr + + .bss (NOLOAD) : ALIGN(8) + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + _bss_end = ABSOLUTE(.); + } >IMAGE_LOC :sof_sram_phdr + + /* stack */ + _end = SOF_STACK_END; + PROVIDE(end = SOF_STACK_END); + _stack_sentry = SOF_STACK_END; + __stack = SOF_STACK_BASE; + + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_ranges 0 : { *(.debug_ranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .xt.insn 0 : + { + KEEP (*(.xt.insn)) + KEEP (*(.gnu.linkonce.x.*)) + } + .xt.prop 0 : + { + KEEP (*(.xt.prop)) + KEEP (*(.xt.prop.*)) + KEEP (*(.gnu.linkonce.prop.*)) + } + .xt.lit 0 : + { + KEEP (*(.xt.lit)) + KEEP (*(.xt.lit.*)) + KEEP (*(.gnu.linkonce.p.*)) + } + .xt.profile_range 0 : + { + KEEP (*(.xt.profile_range)) + KEEP (*(.gnu.linkonce.profile_range.*)) + } + .xt.profile_ranges 0 : + { + KEEP (*(.xt.profile_ranges)) + KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) + } + .xt.profile_files 0 : + { + KEEP (*(.xt.profile_files)) + KEEP (*(.gnu.linkonce.xt.profile_files.*)) + } + + .xtensa.info 0 : + { + *(.xtensa.info) + } + + .comment 0 : + { + KEEP(*(.comment)) + } + + .note.GNU-stack 0 : + { + *(.note.GNU-stack) + } + + .system_heap (NOLOAD) : ALIGN(8) + { + . = ALIGN (32); + _system_heap_start = ABSOLUTE(.); + . = . + HEAP_SYSTEM_SIZE; + _system_heap_end = ABSOLUTE(.); + } >system_heap :system_heap_phdr + + .system_runtime_heap (NOLOAD) : ALIGN(8) + { + . = ALIGN (HEAP_BUF_ALIGNMENT); + _system_runtime_heap_start = ABSOLUTE(.); + . = . + HEAP_SYS_RUNTIME_SIZE; + _system_runtime_heap_end = ABSOLUTE(.); + } >system_runtime_heap :system_runtime_heap_phdr + + .runtime_heap (NOLOAD) : ALIGN(8) + { + . = ALIGN (32); + _runtime_heap_start = ABSOLUTE(.); + . = . + HEAP_RUNTIME_SIZE; + _runtime_heap_end = ABSOLUTE(.); + } >runtime_heap :runtime_heap_phdr + + .buffer_heap (NOLOAD) : ALIGN(8) + { + . = ALIGN (HEAP_BUF_ALIGNMENT); + _buffer_heap_start = ABSOLUTE(.); + . = . + HEAP_BUFFER_SIZE; + _buffer_heap_end = ABSOLUTE(.); + } >buffer_heap :buffer_heap_phdr + + .sof_stack (NOLOAD) : ALIGN(8) + { + . = ALIGN (4096); + _sof_stack_start = ABSOLUTE(.); + . = . + SOF_STACK_TOTAL_SIZE; + _sof_stack_end = ABSOLUTE(.); + } >sof_stack :sof_stack_phdr + + .static_uuid_entries (COPY) : ALIGN(1024) + { + *(*.static_uuids) + } > static_uuid_entries_seg :static_uuid_entries_phdr + + .static_log_entries (COPY) : ALIGN(1024) + { + *(*.static_log*) + } > static_log_entries_seg :static_log_entries_phdr + + .fw_metadata (COPY) : ALIGN(1024) + { + KEEP (*(.fw_metadata)) + . = ALIGN(_EXT_MAN_ALIGN_); + } >fw_metadata_seg :metadata_entries_phdr +} diff --git a/src/platform/mt8196/platform.c b/src/platform/mt8196/platform.c new file mode 100644 index 000000000000..714d5ac8961d --- /dev/null +++ b/src/platform/mt8196/platform.c @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct sof; + +static const struct sof_ipc_fw_ready ready + __section(".fw_ready") = { + .hdr = { + .cmd = SOF_IPC_FW_READY, + .size = sizeof(struct sof_ipc_fw_ready), + }, + /* dspbox is for DSP initiated IPC, hostbox is for host initiated IPC */ + .version = { + .hdr.size = sizeof(struct sof_ipc_fw_version), + .micro = SOF_MICRO, + .minor = SOF_MINOR, + .major = SOF_MAJOR, + .tag = SOF_TAG, + .abi_version = SOF_ABI_VERSION, + .src_hash = SOF_SRC_HASH, + }, + .flags = DEBUG_SET_FW_READY_FLAGS, +}; + +#define NUM_MTK_WINDOWS 6 + +const struct ext_man_windows xsram_window + __aligned(EXT_MAN_ALIGN) __section(".fw_metadata") __unused = { + .hdr = { + .type = EXT_MAN_ELEM_WINDOW, + .elem_size = ALIGN_UP_COMPILE(sizeof(struct ext_man_windows), EXT_MAN_ALIGN), + }, + .window = { + .ext_hdr = { + .hdr.cmd = SOF_IPC_FW_READY, + .hdr.size = sizeof(struct sof_ipc_window), + .type = SOF_IPC_EXT_WINDOW, + }, + .num_windows = NUM_MTK_WINDOWS, + .window = { + { + .type = SOF_IPC_REGION_UPBOX, + .id = 0, /* map to host window 0 */ + .flags = 0, + .size = MAILBOX_DSPBOX_SIZE, + .offset = MAILBOX_DSPBOX_OFFSET, + }, + { + .type = SOF_IPC_REGION_DOWNBOX, + .id = 0, /* map to host window 0 */ + .flags = 0, + .size = MAILBOX_HOSTBOX_SIZE, + .offset = MAILBOX_HOSTBOX_OFFSET, + }, + { + .type = SOF_IPC_REGION_DEBUG, + .id = 0, /* map to host window 0 */ + .flags = 0, + .size = MAILBOX_DEBUG_SIZE, + .offset = MAILBOX_DEBUG_OFFSET, + }, + { + .type = SOF_IPC_REGION_TRACE, + .id = 0, /* map to host window 0 */ + .flags = 0, + .size = MAILBOX_TRACE_SIZE, + .offset = MAILBOX_TRACE_OFFSET, + }, + { + .type = SOF_IPC_REGION_STREAM, + .id = 0, /* map to host window 0 */ + .flags = 0, + .size = MAILBOX_STREAM_SIZE, + .offset = MAILBOX_STREAM_OFFSET, + }, + { + .type = SOF_IPC_REGION_EXCEPTION, + .id = 0, /* map to host window 0 */ + .flags = 0, + .size = MAILBOX_EXCEPTION_SIZE, + .offset = MAILBOX_EXCEPTION_OFFSET, + }, + }, + } +}; + +static SHARED_DATA struct timer timer_shared = { + .id = OSTIMER0, + .irq = MTK_DSP_IRQ_OSTIMER32_C0, +}; + +/* Override the default MPU setup. This table matches the memory map + * of the 'sample_controller' core and will need to be modified for + * other cores. + * NOTE: This table sets up all of external memory as shared uncached. + * For best results, edit the LSP memory map to create a separate + * section in shared memory, place all sections that need to be uncached + * into that section, and only map that section uncached. See README + * for more details. + */ +const struct xthal_MPU_entry __xt_mpu_init_table[] __section(".ResetVector.text") = { + XTHAL_MPU_ENTRY(0x00000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_DEVICE), // infra + XTHAL_MPU_ENTRY(0x10000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_DEVICE), // infra + XTHAL_MPU_ENTRY(0x1a000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_DEVICE), // cfg + XTHAL_MPU_ENTRY(0x1a110000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_DEVICE), // audio + XTHAL_MPU_ENTRY(0x4e100000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK), // sram + XTHAL_MPU_ENTRY(0x4e180000, 1, XTHAL_AR_NONE, XTHAL_MEM_DEVICE), // unused + XTHAL_MPU_ENTRY(0x90000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK_NOALLOC), // dram + XTHAL_MPU_ENTRY(0x90500000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_NON_CACHEABLE), // dram + XTHAL_MPU_ENTRY(0x91100000, 1, XTHAL_AR_NONE, XTHAL_MEM_DEVICE), // unused +}; + +const unsigned int __xt_mpu_init_table_size __section(".ResetVector.text") = + ARRAY_SIZE(__xt_mpu_init_table); + +int platform_boot_complete(uint32_t boot_message) +{ + mailbox_dspbox_write(0, &ready, sizeof(ready)); + /* now interrupt host to tell it we are done booting */ + trigger_irq_to_host_req(); + + return 0; +} + +int platform_init(struct sof *sof) +{ + int ret; + + sof->platform_timer = platform_shared_get(&timer_shared, sizeof(timer_shared)); + sof->cpu_timers = sof->platform_timer; + platform_interrupt_init(); + platform_clock_init(sof); + + scheduler_init_edf(); + + /* init low latency domains and schedulers */ + sof->platform_timer_domain = timer_domain_init(sof->platform_timer, PLATFORM_DEFAULT_CLOCK); + scheduler_init_ll(sof->platform_timer_domain); + platform_timer_start(sof->platform_timer); + sa_init(sof, CONFIG_SYSTICK_PERIOD); + + /* init DMA */ + ret = dmac_init(sof); + if (ret < 0) + return -ENODEV; + + /* Init platform domain */ + sof->platform_dma_domain = dma_multi_chan_domain_init(&sof->dma_info->dma_array[0], 1, + PLATFORM_DEFAULT_CLOCK, false); + + scheduler_init_ll(sof->platform_dma_domain); + + /* initialize the host IPC mechanisms */ + ipc_init(sof); + +#if CONFIG_TRACE + /* Initialize DMA for Trace*/ + trace_point(TRACE_BOOT_PLATFORM_DMA_TRACE); + dma_trace_init_complete(sof->dmat); +#endif + + /* show heap status */ + heap_trace_all(1); + + return 0; +} + +int platform_context_save(struct sof *sof) +{ + clock_set_freq(CLK_CPU(cpu_get_id()), CLK_DEFAULT_CPU_HZ); + return 0; +} + +void platform_wait_for_interrupt(int level) +{ + arch_wait_for_interrupt(level); +} + From ed4c32326fbdb82f49ae90b8f33bd142cee27ac0 Mon Sep 17 00:00:00 2001 From: "hailong.fan" Date: Thu, 26 Dec 2024 09:45:41 +0800 Subject: [PATCH 0005/1821] drivers: mediatek: Add drivers for mt8196 Add interrupt, timer and ipc driver for mt8196. Signed-off-by: hailong.fan --- src/drivers/mediatek/mt8196/CMakeLists.txt | 4 + src/drivers/mediatek/mt8196/intc.c | 133 ++++++++++++ src/drivers/mediatek/mt8196/intc_map.c | 104 ++++++++++ src/drivers/mediatek/mt8196/interrupt.c | 228 +++++++++++++++++++++ src/drivers/mediatek/mt8196/ipc.c | 187 +++++++++++++++++ src/drivers/mediatek/mt8196/timer.c | 220 ++++++++++++++++++++ 6 files changed, 876 insertions(+) create mode 100644 src/drivers/mediatek/mt8196/CMakeLists.txt create mode 100644 src/drivers/mediatek/mt8196/intc.c create mode 100644 src/drivers/mediatek/mt8196/intc_map.c create mode 100644 src/drivers/mediatek/mt8196/interrupt.c create mode 100644 src/drivers/mediatek/mt8196/ipc.c create mode 100644 src/drivers/mediatek/mt8196/timer.c diff --git a/src/drivers/mediatek/mt8196/CMakeLists.txt b/src/drivers/mediatek/mt8196/CMakeLists.txt new file mode 100644 index 000000000000..0d5d85f72215 --- /dev/null +++ b/src/drivers/mediatek/mt8196/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: BSD-3-Clause + +add_local_sources(sof interrupt.c intc.c intc_map.c ipc.c timer.c) + diff --git a/src/drivers/mediatek/mt8196/intc.c b/src/drivers/mediatek/mt8196/intc.c new file mode 100644 index 000000000000..ded339be8b90 --- /dev/null +++ b/src/drivers/mediatek/mt8196/intc.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +SOF_DEFINE_REG_UUID(intc_mt8196); +DECLARE_TR_CTX(intc_tr, SOF_UUID(intc_mt8196_uuid), LOG_LEVEL_INFO); + +static struct intc_desc_t intc_desc; + +void intc_init(void) +{ + uint32_t word, group, irq; + + for (group = 0; group < INTC_GRP_NUM; group++) { + for (word = 0; word < INTC_GRP_LEN; word++) + intc_desc.grp_irqs[group][word] = 0x0; + } + + for (word = 0; word < INTC_GRP_LEN; word++) + intc_desc.int_en[word] = 0x0; + + for (irq = 0; irq < IRQ_MAX_CHANNEL; irq++) { + intc_desc.irqs[irq].id = irq; + intc_desc.irqs[irq].group = irq2grp_map[irq]; + intc_desc.irqs[irq].pol = INTC_POL_LOW; + } + + for (word = 0; word < INTC_GRP_LEN; word++) { + io_reg_write(INTC_IRQ_EN(word), 0x0); + io_reg_write(INTC_IRQ_WAKE_EN(word), 0x0); + io_reg_write(INTC_IRQ_STAGE1_EN(word), 0x0); + io_reg_write(INTC_IRQ_POL(word), 0xFFFFFFFF); + } + + for (group = 0; group < INTC_GRP_NUM; group++) { + for (word = 0; word < INTC_GRP_LEN; word++) + io_reg_write(INTC_IRQ_GRP(group, word), 0x0); + } +} + +void intc_irq_unmask(enum IRQn_Type irq) +{ + uint32_t word, group; + + if (irq < IRQ_MAX_CHANNEL && intc_desc.irqs[irq].group < INTC_GRP_NUM) { + word = INTC_WORD(irq); + group = intc_desc.irqs[irq].group; + io_reg_update_bits(INTC_IRQ_EN(word), INTC_BIT(irq), INTC_BIT(irq)); + } else { + tr_err(&intc_tr, "Invalid INTC interrupt %d", irq); + } +} + +void intc_irq_mask(enum IRQn_Type irq) +{ + uint32_t word; + + if (irq < IRQ_MAX_CHANNEL) { + word = INTC_WORD(irq); + io_reg_update_bits(INTC_IRQ_EN(word), INTC_BIT(irq), 0); + } else { + tr_err(&intc_tr, "Invalid INTC interrupt %d", irq); + } +} + +int intc_irq_enable(enum IRQn_Type irq) +{ + uint32_t word, irq_b, group, pol; + int ret; + + if (irq < IRQ_MAX_CHANNEL && intc_desc.irqs[irq].group < INTC_GRP_NUM && + intc_desc.irqs[irq].pol < INTC_POL_NUM) { + word = INTC_WORD(irq); + irq_b = INTC_BIT(irq); + group = intc_desc.irqs[irq].group; + pol = intc_desc.irqs[irq].pol; + + intc_desc.int_en[word] |= irq_b; + intc_desc.grp_irqs[group][word] |= irq_b; + io_reg_update_bits(INTC_IRQ_EN(word), irq_b, 0); + if (pol == INTC_POL_HIGH) + io_reg_update_bits(INTC_IRQ_POL(word), irq_b, 0); + else + io_reg_update_bits(INTC_IRQ_POL(word), irq_b, irq_b); + + io_reg_update_bits(INTC_IRQ_GRP(group, word), irq_b, irq_b); + io_reg_update_bits(INTC_IRQ_EN(word), irq_b, irq_b); + + ret = 1; + } else { + tr_err(&intc_tr, "Invalid INTC interrupt %d", irq); + ret = 0; + } + + return ret; +} + +int intc_irq_disable(enum IRQn_Type irq) +{ + uint32_t word, irq_b, group; + int ret; + + if (irq < IRQ_MAX_CHANNEL && intc_desc.irqs[irq].group < INTC_GRP_NUM) { + word = INTC_WORD(irq); + irq_b = INTC_BIT(irq); + group = intc_desc.irqs[irq].group; + + intc_desc.int_en[word] &= ~irq_b; + intc_desc.grp_irqs[group][word] &= ~irq_b; + io_reg_update_bits(INTC_IRQ_EN(word), irq_b, 0); + io_reg_update_bits(INTC_IRQ_GRP(group, word), irq_b, 0); + + ret = 1; + } else { + tr_err(&intc_tr, "INTC fail to disable irq %u\n", irq); + ret = 0; + } + + return ret; +} + diff --git a/src/drivers/mediatek/mt8196/intc_map.c b/src/drivers/mediatek/mt8196/intc_map.c new file mode 100644 index 000000000000..2c3fcbba965d --- /dev/null +++ b/src/drivers/mediatek/mt8196/intc_map.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +const unsigned char grp_pri[INTC_GRP_NUM] = { + INTC_GRP0_LEVEL, INTC_GRP1_LEVEL, INTC_GRP2_LEVEL, INTC_GRP3_LEVEL, + INTC_GRP4_LEVEL, INTC_GRP5_LEVEL, INTC_GRP6_LEVEL, INTC_GRP7_LEVEL, + INTC_GRP8_LEVEL, INTC_GRP9_LEVEL, INTC_GRP10_LEVEL, INTC_GRP11_LEVEL, + INTC_GRP12_LEVEL, INTC_GRP13_LEVEL, INTC_GRP14_LEVEL, INTC_GRP15_LEVEL, +}; + +const uint8_t irq2grp_map[IRQ_MAX_CHANNEL] = { + [CCU_IRQn] = INTC_GRP1, + [SCP_IRQn] = INTC_GRP1, + [SPM_IRQn] = INTC_GRP1, + [PCIE_IRQn] = INTC_GRP1, + [INFRA_HANG_IRQn] = INTC_GRP1, + [PERI_TIMEOUT_IRQn] = INTC_GRP1, + [MBOX_C0_IRQn] = INTC_GRP2, + [MBOX_C1_IRQn] = INTC_GRP2, + [TIMER0_IRQn] = INTC_GRP1, + [TIMER1_IRQn] = INTC_GRP1, + [IPC_C0_IRQn] = INTC_GRP1, + [IPC_C1_IRQn] = INTC_GRP1, + [IPC1_RSV_IRQn] = INTC_GRP1, + [C2C_SW_C0_IRQn] = INTC_GRP1, + [C2C_SW_C1_IRQn] = INTC_GRP1, + [UART_IRQn] = INTC_GRP12, + [UART_BT_IRQn] = INTC_GRP12, + [LATENCY_MON_IRQn] = INTC_GRP11, + [BUS_TRACKER_IRQn] = INTC_GRP13, + [USB0_IRQn] = INTC_GRP8, + [USB1_IRQn] = INTC_GRP8, + [SCPVOW_IRQn] = NO_GRP, + [CCIF3_C0_IRQn] = INTC_GRP8, + [CCIF3_C1_IRQn] = INTC_GRP8, + [PWR_CTRL_IRQn] = NO_GRP, + [DMA_C0_IRQn] = INTC_GRP10, + [DMA_C1_IRQn] = NO_GRP, + [AXI_DMA0_IRQn] = INTC_GRP9, + [AXI_DMA1_IRQn] = NO_GRP, + [AUDIO_C0_IRQn] = INTC_GRP10, + [AUDIO_C1_IRQn] = INTC_GRP10, + [HIFI5_WDT_C0_IRQn] = INTC_GRP13, + [HIFI5_WDT_C1_IRQn] = INTC_GRP13, + [APU_MBOX_C0_IRQn] = INTC_GRP0, + [APU_MBOX_C1_IRQn] = INTC_GRP0, + [TIMER2_IRQn] = INTC_GRP13, + [PWR_ON_C0_IRQ] = INTC_GRP13, + [PWR_ON_C1_IRQ] = INTC_GRP13, + [WAKEUP_SRC_C0_IRQn] = INTC_GRP13, + [WAKEUP_SRC_C1_IRQn] = INTC_GRP13, + [WDT_IRQn] = NO_GRP, + [CONNSYS1_IRQn] = INTC_GRP3, + [CONNSYS3_IRQn] = INTC_GRP3, + [CONNSYS4_IRQn] = INTC_GRP3, + [CONNSYS2_IRQn] = INTC_GRP3, + [IPIC_IRQn] = INTC_GRP1, + [AXI_DMA2_IRQn] = INTC_GRP9, + [AXI_DMA3_IRQn] = NO_GRP, + [APSRC_DDREN_IRQn] = INTC_GRP4, + [LAT_MON_EMI_IRQn] = INTC_GRP11, + [LAT_MON_INFRA_IRQn] = INTC_GRP11, + [DEVAPC_VIO_IRQn] = INTC_GRP11, + [AO_INFRA_HANG_IRQn] = NO_GRP, + [BUS_TRA_EMI_IRQn] = INTC_GRP13, + [BUS_TRA_INFRA_IRQn] = INTC_GRP13, + [L2SRAM_VIO_IRQn] = INTC_GRP11, + [L2SRAM_SETERR_IRQn] = INTC_GRP11, + [PCIERC_GRP2_IRQn] = INTC_GRP8, + [PCIERC_GRP3_IRQn] = INTC_GRP8, +}; + +const uint8_t grp2hifi_irq_map[INTC_GRP_NUM] = { + [INTC_GRP0] = 0, + [INTC_GRP1] = 1, + [INTC_GRP2] = 2, + [INTC_GRP3] = 3, + [INTC_GRP4] = 4, + [INTC_GRP5] = 5, + [INTC_GRP6] = 7, + [INTC_GRP7] = 8, + [INTC_GRP8] = 9, + [INTC_GRP9] = 10, + [INTC_GRP10] = 11, + [INTC_GRP11] = 16, + [INTC_GRP12] = 17, + [INTC_GRP13] = 18, + [INTC_GRP14] = 20, + [INTC_GRP15] = 21, +}; diff --git a/src/drivers/mediatek/mt8196/interrupt.c b/src/drivers/mediatek/mt8196/interrupt.c new file mode 100644 index 000000000000..d329544cb5ae --- /dev/null +++ b/src/drivers/mediatek/mt8196/interrupt.c @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PENDING_IRQ_INDEX_MAX 32 + +SOF_DEFINE_REG_UUID(irq_mt8196); + +DECLARE_TR_CTX(int_tr, SOF_UUID(irq_mt8196_uuid), LOG_LEVEL_INFO); + +static void mtk_irq_init(void) +{ + intc_init(); +} + +static void mtk_irq_mask(struct irq_desc *desc, uint32_t irq, unsigned int core) +{ + if (!desc) { + if (irq >= 0 && irq < IRQ_MAX_CHANNEL) + intc_irq_disable(irq); + else + tr_err(&int_tr, "Invalid interrupt num%d", irq); + } else { + switch (desc->irq) { + case MTK_DSP_IRQ_MBOX_C0: + intc_irq_disable(6); + break; + default: + tr_err(&int_tr, "Invalid interrupt %d", desc->irq); + return; + } + } +} + +static void mtk_irq_unmask(struct irq_desc *desc, uint32_t irq, unsigned int core) +{ + if (!desc) { + if (irq >= 0 && irq < IRQ_MAX_CHANNEL) + intc_irq_enable(irq); + else + tr_err(&int_tr, "Invalid interrupt num%d", irq); + } else { + switch (desc->irq) { + case MTK_DSP_IRQ_MBOX_C0: + intc_irq_enable(6); + break; + default: + tr_err(&int_tr, "Invalid interrupt %d", desc->irq); + return; + } + } +} + +static uint32_t mtk_irq_group_pending_status(uint32_t irq) +{ + uint32_t irq_status = 0; + + if (irq == MTK_DSP_IRQ_MBOX_C0 && + (io_reg_read(INTC_IRQ_STA0) & BIT(6))) { + irq_status = io_reg_read(MTK_MBOX_IRQ_IN) & MTK_DSP_MBOX_MASK; + } + + return irq_status; +} + +static uint32_t mtk_get_pending_index(uint32_t current, uint32_t *next) +{ + uint32_t index; + + if (current == 0) + return PENDING_IRQ_INDEX_MAX; + + /* ffs returns one plus the index of the least significant 1-bit of input int */ + index = ffs(current) - 1; + + /* remove the handling index from current pending status */ + *next = current & ~(1ull << index); + + return index; +} + +static inline void mtk_handle_group_pending_irq(struct irq_cascade_desc *cascade, + uint32_t line_index, uint32_t status) +{ + int core = cpu_get_id(); + struct list_item *clist; + struct irq_desc *child = NULL; + uint32_t idx; + uint32_t next_status; + bool handled; + k_spinlock_key_t key; + + idx = mtk_get_pending_index(status, &next_status); + while (idx < PENDING_IRQ_INDEX_MAX) { + handled = false; + + key = k_spin_lock(&cascade->lock); + list_for_item(clist, &cascade->child[idx].list) { + child = container_of(clist, struct irq_desc, irq_list); + + if (child->handler && (child->cpu_mask & 1 << core)) { + child->handler(child->handler_arg); + handled = true; + } + } + k_spin_unlock(&cascade->lock, key); + + if (!handled) { + tr_err(&int_tr, "Not handle irq %u in group %u", + idx, line_index); + } + + idx = mtk_get_pending_index(next_status, &next_status); + } +} + +static inline void mtk_irq_group_handler(void *data, uint32_t line_index) +{ + struct irq_desc *parent = data; + struct irq_cascade_desc *cascade = + container_of(parent, struct irq_cascade_desc, desc); + uint32_t status; + + status = mtk_irq_group_pending_status(line_index); + if (status) + mtk_handle_group_pending_irq(cascade, line_index, status); + else + tr_err(&int_tr, "No pending irq in group %d", line_index); +} + +#define DEFINE_IRQ_HANDLER(n) \ + static void irqhandler_##n(void *arg) \ + { \ + mtk_irq_group_handler(arg, n); \ + } + +DEFINE_IRQ_HANDLER(2) + +static const char mtk_irq_mailbox[] = "mtk_irq_mailbox"; + +static const struct irq_cascade_ops irq_ops = { + .mask = mtk_irq_mask, + .unmask = mtk_irq_unmask, +}; + +static const struct irq_cascade_tmpl dsp_irq[] = { + { + .name = mtk_irq_mailbox, + .irq = MTK_DSP_IRQ_MBOX_C0, + .handler = irqhandler_2, + .ops = &irq_ops, + .global_mask = false, + }, +}; + +int mtk_irq_group_id(uint32_t in_irq) +{ + if (in_irq >= MTK_MAX_IRQ_NUM) + in_irq -= MTK_MAX_IRQ_NUM; + + return interrupt_get_irq(in_irq, dsp_irq[0].name); +} + +void platform_interrupt_init(void) +{ + int i; + + mtk_irq_init(); + for (i = 0; i < ARRAY_SIZE(dsp_irq); i++) + interrupt_cascade_register(dsp_irq + i); +} + +void platform_interrupt_set(uint32_t irq) +{ + if (interrupt_is_dsp_direct(irq)) + arch_interrupt_set(irq); +} + +void platform_interrupt_clear(uint32_t irq, uint32_t mask) +{ + if (interrupt_is_dsp_direct(irq)) + arch_interrupt_clear(irq); +} + +uint32_t platform_interrupt_get_enabled(void) +{ + return 0; +} + +void interrupt_mask(uint32_t irq, unsigned int cpu) +{ + struct irq_cascade_desc *cascade = interrupt_get_parent(irq); + + if (cascade && cascade->ops->mask) + cascade->ops->mask(&cascade->desc, irq - cascade->irq_base, + cpu); + else + mtk_irq_mask(NULL, irq, 0); +} + +void interrupt_unmask(uint32_t irq, unsigned int cpu) +{ + struct irq_cascade_desc *cascade = interrupt_get_parent(irq); + + if (cascade && cascade->ops->unmask) + cascade->ops->unmask(&cascade->desc, irq - cascade->irq_base, + cpu); + else + mtk_irq_unmask(NULL, irq, 0); +} diff --git a/src/drivers/mediatek/mt8196/ipc.c b/src/drivers/mediatek/mt8196/ipc.c new file mode 100644 index 000000000000..cb47e25c1dd0 --- /dev/null +++ b/src/drivers/mediatek/mt8196/ipc.c @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IPC_DSPMBOX_DSP_RSP 0 +#define IPC_DSPMBOX_DSP_REQ 1 + +SOF_DEFINE_REG_UUID(ipc_task_mt8196); + +static struct ipc *local_ipc; + +struct ipc_data { + struct ipc_data_host_buffer dh_buffer; +}; + +static void mbox0_handler(void *args) +{ + uint32_t op = io_reg_read(MTK_ADSP_MBOX_IN_CMD(0)); + + /* clear interrupt */ + io_reg_write(MTK_ADSP_MBOX_IN_CMD_CLR(0), op); + ipc_schedule_process(local_ipc); +} + +static void mbox1_handler(void *args) +{ + uint32_t op = io_reg_read(MTK_ADSP_MBOX_IN_CMD(1)); + + /* clear interrupt */ + io_reg_write(MTK_ADSP_MBOX_IN_CMD_CLR(1), op); + local_ipc->is_notification_pending = false; +} + +void trigger_irq_to_host_rsp(void) +{ + io_reg_write(MTK_ADSP_MBOX_OUT_CMD(0), ADSP_IPI_OP_RSP); +} + +void trigger_irq_to_host_req(void) +{ + io_reg_write(MTK_ADSP_MBOX_OUT_CMD(1), ADSP_IPI_OP_REQ); +} + +enum task_state ipc_platform_do_cmd(struct ipc *ipc) +{ + struct ipc_cmd_hdr *hdr; + + hdr = mailbox_validate(); + ipc_cmd(hdr); + + return SOF_TASK_STATE_COMPLETED; +} + +void ipc_platform_complete_cmd(struct ipc *ipc) +{ + trigger_irq_to_host_rsp(); + while (ipc->pm_prepare_D3) + wait_for_interrupt(0); +} + +int ipc_platform_send_msg(const struct ipc_msg *msg) +{ + struct ipc *ipc = ipc_get(); + + if (ipc->is_notification_pending) + return -EBUSY; + + /* now send the message */ + mailbox_dspbox_write(0, msg->tx_data, msg->tx_size); + + ipc->is_notification_pending = true; + + /* now interrupt host to tell it we have sent a message */ + trigger_irq_to_host_req(); + return 0; +} + +void ipc_platform_send_msg_direct(const struct ipc_msg *msg) +{ + /* TODO: add support */ +} + +#if CONFIG_HOST_PTABLE +struct ipc_data_host_buffer *ipc_platform_get_host_buffer(struct ipc *ipc) +{ + struct ipc_data *iipc = ipc_get_drvdata(ipc); + + return &iipc->dh_buffer; +} +#endif + +int platform_ipc_init(struct ipc *ipc) +{ + int mbox_irq0, mbox_irq1; + int ret; + +#if CONFIG_HOST_PTABLE + struct ipc_data *iipc; + + iipc = rzalloc(SOF_MEM_ZONE_SYS, 0, SOF_MEM_CAPS_RAM, sizeof(*iipc)); + ipc_set_drvdata(ipc, iipc); +#else + ipc_set_drvdata(ipc, NULL); +#endif + + local_ipc = ipc; + + /* schedule */ + schedule_task_init_edf(&ipc->ipc_task, SOF_UUID(ipc_task_mt8196_uuid), + &ipc_task_ops, ipc, 0, 0); + +#if CONFIG_HOST_PTABLE + /* allocate page table buffer */ + iipc->dh_buffer.page_table = + rzalloc(SOF_MEM_ZONE_SYS, 0, SOF_MEM_CAPS_RAM, PLATFORM_PAGE_TABLE_SIZE); + + iipc->dh_buffer.dmac = dma_get(DMA_DIR_HMEM_TO_LMEM, 0, DMA_DEV_HOST, DMA_ACCESS_SHARED); + if (!iipc->dh_buffer.dmac) { + tr_err(&ipc_tr, "Unable to find DMA for host page table"); + sof_panic(SOF_IPC_PANIC_IPC); + } +#endif + + /* + * AP req -- mbox0 --> DSP + * AP <-- mbox0 -- DSP rsp + * AP <-- mbox1 -- DSP req + * AP rsp -- mbox1 --> DSP + */ + mbox_irq0 = mtk_irq_group_id(MTK_DSP_IRQ_MBOX0); + if (mbox_irq0 < 0) { + tr_err(&ipc_tr, "Invalid ipc mbox 0 IRQ:%d", mbox_irq0); + sof_panic(SOF_IPC_PANIC_IPC); + } + + mbox_irq1 = mtk_irq_group_id(MTK_DSP_IRQ_MBOX1); + if (mbox_irq1 < 0) { + tr_err(&ipc_tr, "Invalid ipc mbox 1 IRQ:%d", mbox_irq1); + sof_panic(SOF_IPC_PANIC_IPC); + } + + ret = interrupt_register(mbox_irq0, mbox0_handler, ipc); + if (ret < 0) { + tr_err(&ipc_tr, "Unable to register ipc mbox 0 IRQ"); + sof_panic(SOF_IPC_PANIC_IPC); + } + + ret = interrupt_register(mbox_irq1, mbox1_handler, ipc); + if (ret < 0) { + tr_err(&ipc_tr, "Unable to register ipc mbox 1 IRQ"); + sof_panic(SOF_IPC_PANIC_IPC); + } + + interrupt_enable(mbox_irq0, ipc); + interrupt_enable(mbox_irq1, ipc); + + return 0; +} diff --git a/src/drivers/mediatek/mt8196/timer.c b/src/drivers/mediatek/mt8196/timer.c new file mode 100644 index 000000000000..211cd45fe19d --- /dev/null +++ b/src/drivers/mediatek/mt8196/timer.c @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright(c) 2024 MediaTek. All rights reserved. + * + * Author: Hailong Fan + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void platform_timer_start(struct timer *timer) +{ + /* set 26m clksrc */ + io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_ENABLE_BIT, 0); + io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_CLKSRC_BIT, + MTK_TIMER_CLK_SRC_CLK_26M); + + /* enable timer */ + io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_ENABLE_BIT, + MTK_TIMER_ENABLE_BIT); + + /* enable system boot time timer */ + io_reg_update_bits(MTK_OSTIMER_CON, MTK_OSTIMER_EN_BIT, + MTK_OSTIMER_EN_BIT); +} + +void platform_timer_stop(struct timer *timer) +{ + if (timer->id > NR_TMRS) + return; + + io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_ENABLE_BIT, 0); + io_reg_update_bits(MTK_TIMER_IRQ_ACK(timer->id), MTK_TIMER_IRQ_ENABLE, 0); +} + +/* IRQs off in arch_timer_get_system() */ +uint64_t platform_timer_get_atomic(struct timer *timer) +{ + return platform_timer_get(timer); +} + +int64_t platform_timer_set(struct timer *timer, uint64_t ticks) +{ + uint64_t time; + uint32_t flags; + uint32_t low, high; + uint32_t ticks_set; + + if (timer->id > NR_TMRS) + return -EINVAL; + + flags = arch_interrupt_global_disable(); + + low = io_reg_read(MTK_OSTIMER_CUR_L); + high = io_reg_read(MTK_OSTIMER_CUR_H); + + /* ostimer 13M counter to 26M interrupt */ + time = (((uint64_t)high << 32) | low) << 1; + + ticks_set = (ticks > time) ? ticks - time : UINT64_MAX - time + ticks; + + timer->hitimeout = ticks >> 32; + timer->lowtimeout = ticks_set; + + /* disable timer before config it */ + io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_ENABLE_BIT, 0); + + /* set 26m clksrc */ + io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_CLKSRC_BIT, + MTK_TIMER_CLK_SRC_CLK_26M); + /* timer reset value */ + io_reg_write(MTK_TIMER_RST_VAL(timer->id), ticks_set); + + /* clear and enable irq */ + io_reg_update_bits(MTK_TIMER_IRQ_ACK(timer->id), MTK_TIMER_IRQ_CLEAR, + MTK_TIMER_IRQ_CLEAR); + io_reg_update_bits(MTK_TIMER_IRQ_ACK(timer->id), MTK_TIMER_IRQ_ENABLE, + MTK_TIMER_IRQ_ENABLE); + + /* enable timer */ + io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_ENABLE_BIT, + MTK_TIMER_ENABLE_BIT); + + arch_interrupt_global_enable(flags); + + return ticks; +} + +void platform_timer_clear(struct timer *timer) +{ + if (timer->id > NR_TMRS) + return; + + io_reg_update_bits(MTK_TIMER_IRQ_ACK(timer->id), MTK_TIMER_IRQ_CLEAR, + MTK_TIMER_IRQ_CLEAR); +} + +uint64_t platform_timer_get(struct timer *timer) +{ + uint64_t time; + uint32_t low; + uint32_t high0; + uint32_t high1; + + if (timer->id > NR_TMRS) + return -EINVAL; + + /* 64bit reads are non atomic on xtensa so we must + * read a stable value where there is no bit 32 flipping. + */ + do { + high0 = io_reg_read(MTK_OSTIMER_CUR_H); + low = io_reg_read(MTK_OSTIMER_CUR_L); + high1 = io_reg_read(MTK_OSTIMER_CUR_H); + + /* worst case is we perform this twice so 6 * 32b clock reads */ + } while (high0 != high1); + + /* convert 13M ostimer counter value to 26M */ + time = (((uint64_t)high0 << 32) | low) << 1; + + return time; +} + +/* get timestamp for host stream DMA position */ +void platform_host_timestamp(struct comp_dev *host, struct sof_ipc_stream_posn *posn) +{ + int err; + + /* get host position */ + err = comp_position(host, posn); + if (err == 0) + posn->flags |= SOF_TIME_HOST_VALID | SOF_TIME_HOST_64; +} + +/* get timestamp for DAI stream DMA position */ +void platform_dai_timestamp(struct comp_dev *dai, + struct sof_ipc_stream_posn *posn) +{ + int err; + + /* get DAI position */ + err = comp_position(dai, posn); + if (err == 0) + posn->flags |= SOF_TIME_DAI_VALID; + + posn->wallclock = timer_get_system(timer_get()) - posn->wallclock; + posn->flags |= SOF_TIME_WALL_VALID | SOF_TIME_WALL_64; +} + +/* get current wallclock for componnent */ +void platform_dai_wallclock(struct comp_dev *dai, uint64_t *wallclock) +{ + *wallclock = platform_timer_get(timer_get()); +} + +static void platform_timer_handler(void *arg) +{ + struct timer *timer = arg; + + io_reg_update_bits(MTK_TIMER_IRQ_ACK(timer->id), MTK_TIMER_IRQ_CLEAR, + MTK_TIMER_IRQ_CLEAR); + + io_reg_update_bits(MTK_TIMER_CON(timer->id), MTK_TIMER_ENABLE_BIT, 0); + + io_reg_update_bits(MTK_TIMER_IRQ_ACK(timer->id), MTK_TIMER_IRQ_ENABLE, 0); + + timer->handler(timer->data); +} + +static int platform_timer_register(struct timer *timer, void (*handler)(void *arg), void *arg) +{ + timer->handler = handler; + timer->data = arg; + timer->hitime = 0; + timer->hitimeout = 0; + + return interrupt_register(timer->irq, platform_timer_handler, timer); +} + +int timer_register(struct timer *timer, void(*handler)(void *arg), void *arg) +{ + switch (timer->id) { + case OSTIMER0: + case OSTIMER1: + case OSTIMER2: + case OSTIMER3: + return platform_timer_register(timer, handler, arg); + default: + return -EINVAL; + } +} + +void timer_unregister(struct timer *timer, void *arg) +{ + interrupt_unregister(timer->irq, arg); +} + +void timer_enable(struct timer *timer, void *arg, int core) +{ + /* enable timer interrupt */ + interrupt_enable(timer->irq, arg); + + interrupt_unmask(8, cpu_get_id()); +} + +void timer_disable(struct timer *timer, void *arg, int core) +{ + /* enable timer interrupt */ + interrupt_disable(timer->irq, arg); + interrupt_mask(8, cpu_get_id()); +} From e468f214c759ccecea35b573a4fe4e1e65dd9f0a Mon Sep 17 00:00:00 2001 From: "hailong.fan" Date: Thu, 26 Dec 2024 09:48:49 +0800 Subject: [PATCH 0006/1821] config: Add default config for mt8196 Add default config for mt8196 platform. Signed-off-by: hailong.fan --- src/arch/xtensa/configs/mt8196_defconfig | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 src/arch/xtensa/configs/mt8196_defconfig diff --git a/src/arch/xtensa/configs/mt8196_defconfig b/src/arch/xtensa/configs/mt8196_defconfig new file mode 100644 index 000000000000..1d9fffedfbd2 --- /dev/null +++ b/src/arch/xtensa/configs/mt8196_defconfig @@ -0,0 +1,15 @@ +CONFIG_MT8196=y +CONFIG_CORE_COUNT=1 +CONFIG_COMP_VOLUME=y +CONFIG_COMP_SRC=n +CONFIG_COMP_FIR=n +CONFIG_COMP_IIR=n +CONFIG_COMP_DCBLOCK=n +CONFIG_COMP_TDFB=n +CONFIG_COMP_TONE=n +CONFIG_COMP_MIXER=n +CONFIG_COMP_MUX=n +CONFIG_COMP_KPB=n +CONFIG_COMP_SEL=n +CONFIG_COMP_ASRC=n +CONFIG_DEBUG=y From 42e5c21caab6574e5e90b8608dcdf4bf5eb91eb1 Mon Sep 17 00:00:00 2001 From: "hailong.fan" Date: Thu, 26 Dec 2024 09:52:43 +0800 Subject: [PATCH 0007/1821] platform: Add build support for mediatek mt8196 platform Add CMakefile for mediatek mt8196 platform to build. Signed-off-by: hailong.fan --- scripts/docker_build/sof_builder/Dockerfile | 1 + scripts/set_xtensa_params.sh | 8 ++++++-- scripts/xtensa-build-all.sh | 2 +- src/arch/xtensa/CMakeLists.txt | 4 +++- src/drivers/mediatek/CMakeLists.txt | 3 +++ src/platform/CMakeLists.txt | 2 ++ src/platform/Kconfig | 22 +++++++++++++++++++++ uuid-registry.txt | 5 +++++ 8 files changed, 43 insertions(+), 4 deletions(-) diff --git a/scripts/docker_build/sof_builder/Dockerfile b/scripts/docker_build/sof_builder/Dockerfile index 90c082e4a173..843b5a448663 100644 --- a/scripts/docker_build/sof_builder/Dockerfile +++ b/scripts/docker_build/sof_builder/Dockerfile @@ -117,6 +117,7 @@ ENV PATH="/home/sof/work/xtensa-imx8ulp-elf/bin:${PATH}" ENV PATH="/home/sof/work/xtensa-mt8186-elf/bin:${PATH}" ENV PATH="/home/sof/work/xtensa-mt8195-elf/bin:${PATH}" ENV PATH="/home/sof/work/xtensa-mt8188-elf/bin:${PATH}" +ENV PATH="/home/sof/work/xtensa-mt8196-elf/bin:${PATH}" ARG NEWLIB_REPO=https://github.com/jcmvbkbc/newlib-xtensa.git RUN cd "$HOME" && \ diff --git a/scripts/set_xtensa_params.sh b/scripts/set_xtensa_params.sh index 622e30ddfbe0..e7af75d037fd 100644 --- a/scripts/set_xtensa_params.sh +++ b/scripts/set_xtensa_params.sh @@ -135,7 +135,11 @@ case "$platform" in HOST="xtensa-mt8195-elf" TOOLCHAIN_VER="RI-2019.1-linux" ;; - + mt8196) + XTENSA_CORE="HiFi5_MPU_lock_2023_11" + HOST="xtensa-mt8196-elf" + TOOLCHAIN_VER="RI-2023.11-linux" + ;; *) >&2 printf 'Unknown xtensa platform=%s\n' "$platform" return 1 @@ -144,7 +148,7 @@ esac # Pre-zephyr "XTOS" build, testbench,... case "$platform" in - mtl|lnl|ptl|acp_7_0) + mtl|lnl|ptl|acp_7_0|mt8196) SOF_CC_BASE='clang';; *) SOF_CC_BASE='xcc';; diff --git a/scripts/xtensa-build-all.sh b/scripts/xtensa-build-all.sh index a7d83c9fbd3e..ffcdafe450a0 100755 --- a/scripts/xtensa-build-all.sh +++ b/scripts/xtensa-build-all.sh @@ -18,7 +18,7 @@ DEFAULT_PLATFORMS=( SUPPORTED_PLATFORMS=( "${DEFAULT_PLATFORMS[@]}" ) # Container work is in progress -SUPPORTED_PLATFORMS+=( acp_6_3 acp_7_0 ) +SUPPORTED_PLATFORMS+=( acp_6_3 acp_7_0 mt8196) BUILD_ROM=no BUILD_DEBUG=no diff --git a/src/arch/xtensa/CMakeLists.txt b/src/arch/xtensa/CMakeLists.txt index e8478444b66e..0bc510e22330 100644 --- a/src/arch/xtensa/CMakeLists.txt +++ b/src/arch/xtensa/CMakeLists.txt @@ -26,6 +26,8 @@ elseif(CONFIG_MT8188) set(platform_folder mt8188) elseif(CONFIG_MT8195) set(platform_folder mt8195) +elseif(CONFIG_MT8196) + set(platform_folder mt8196) else() message(FATAL_ERROR "Platform not defined, check your Kconfiguration?") endif() @@ -477,7 +479,7 @@ set(UNSIGNED_RI imx8 imx8x imx8m imx8ulp) # AMD list(APPEND UNSIGNED_RI rn rmb vangogh acp_6_3 acp_7_0) # MediaTek -list(APPEND UNSIGNED_RI mt8186 mt8188 mt8195) +list(APPEND UNSIGNED_RI mt8186 mt8188 mt8195 mt8196) if(${fw_name} IN_LIST UNSIGNED_RI) # mere copy add_custom_command(OUTPUT reproducible.ri diff --git a/src/drivers/mediatek/CMakeLists.txt b/src/drivers/mediatek/CMakeLists.txt index f1090111e5d6..0dfbebbccf19 100644 --- a/src/drivers/mediatek/CMakeLists.txt +++ b/src/drivers/mediatek/CMakeLists.txt @@ -7,3 +7,6 @@ endif() if(CONFIG_MT8186 OR CONFIG_MT8188) add_subdirectory(mt818x) endif() +if(CONFIG_MT8196) + add_subdirectory(mt8196) +endif() diff --git a/src/platform/CMakeLists.txt b/src/platform/CMakeLists.txt index 8006b8b3caf8..56ff5b94c21f 100644 --- a/src/platform/CMakeLists.txt +++ b/src/platform/CMakeLists.txt @@ -21,4 +21,6 @@ elseif(CONFIG_MT8188) add_subdirectory(mt8188) elseif(CONFIG_MT8195) add_subdirectory(mt8195) +elseif(CONFIG_MT8196) + add_subdirectory(mt8196) endif() diff --git a/src/platform/Kconfig b/src/platform/Kconfig index 46f53b10e808..2ebc868e627a 100644 --- a/src/platform/Kconfig +++ b/src/platform/Kconfig @@ -282,6 +282,27 @@ config MTK help Select if your target is a Mediatek DSP. Builds Zephyr firmware. +config MT8196 + bool "Build for MTK MT8196" + select XT_INTERRUPT_LEVEL_1 + select XT_INTERRUPT_LEVEL_2 + select XT_INTERRUPT_LEVEL_3 + select XT_INTERRUPT_LEVEL_4 + select DUMMY_DMA + select HOST_PTABLE + select XT_WAITI_DELAY + select MEDIATEK + select XTENSA_EXCLUSIVE + select SCHEDULE_DMA_MULTI_CHANNEL + help + This configuration enables support for the MediaTek MT8196 platform. + It includes necessary interrupt levels, DMA support, and other + platform-specific features required for the proper functioning of + the MT8196 SoC. Enabling this option will ensure that the build + system includes all relevant drivers and configurations for MT8196. + + Select this option if your target platform is MT8196-compatible. + endchoice config MAX_CORE_COUNT @@ -485,6 +506,7 @@ config RIMAGE_SIGNING_SCHEMA default "mt8186" if MT8186 default "mt8188" if MT8188 default "mt8195" if MT8195 + default "mt8196" if MT8196 default "" help Signing schema name used by rimage to decide how to build final binary diff --git a/uuid-registry.txt b/uuid-registry.txt index bbf92ecd2ec2..0015543b7aa7 100644 --- a/uuid-registry.txt +++ b/uuid-registry.txt @@ -46,6 +46,7 @@ ec290e95-4a20-47eb-bbffd9c888431831 chmap 53863428-9a72-44df-af0ffe45ea2348ba clkdrv_mt8186 19d4e680-4479-48cc-af869f63d8b0098b clkdrv_mt8188 23b12fd5-c2a9-41a8-a2b3231ab7dcdc70 clkdrv_mt8195 +e87bf747-e574-4362-bf2cc015d2859dd9 clkdrv_mt8196 8890ea76-0df9-44ae-87e6994f4c15e9fa clock 7c42ce8b-0108-43d0-913756d660478c5f component 9ba00c83-ca12-4a83-943c1fa2e82f9dda copier @@ -82,15 +83,18 @@ a5dacb0e-88dc-415c-a1b53e8df77f1976 idc_cmd_task b90f5a4e-5537-4375-a1df95485472ff9e idc_task 696ae2bc-2877-11eb-adc10242ac120002 igo_nr fa00558c-d653-4851-a03ab21f125a9524 interrupt +2f520e85-49ba-4284-90d83def24af313b intc_mt8196 be60f97d-78df-4796-a0ee435cb56b720a ipc a814a1ca-0b83-466c-95872f35ff8d12e8 ipcgw 389c9186-5a7d-4ad1-a02ca02ecdadfb33 ipc_task 49be8ff3-71a3-4456-bb7e4723f2e5730c ipc_task_amd a3fe3bf2-39a4-4fc3-b3418a96e0a26759 ipc_task_mt818x +caef4bd7-7a2e-4039-9b061f5ff9ec3899 ipc_task_mt8196 6c8f0d53-ff77-4ca1-b825c0c4e1b0d322 ipc_task_posix 1862d39a-3a84-4d64-8c91dce1dfc122db irq 6533d0eb-b785-4709-84f5347c81720189 irq_acp d2e3f730-df39-42ee-81a839bfb4d024c2 irq_mt818x +7eb28333-f08f-436f-bbbd764ac21fc2f1 irq_mt8196 eba8d51f-7827-47b5-82eede6e7743af67 keyword d8218443-5ff3-4a4c-b3886cfe07b9562e kpb a8a0cb32-4a77-4db1-85c753d7ee07bce6 kpb4 @@ -135,6 +139,7 @@ d7f6712d-131c-45a7-82ed6aa9dc2291ea pm_runtime cf90d851-68a2-4987-a2de85aed0c8531c sgen_mt8186 99316bd9-07b9-4665-81796e048d67cb45 sgen_mt8188 9eb1a55b-fc20-4442-96131ff1023be493 sgen_mt8195 +bcf54c06-5702-4a60-ac4abb509123c649 sgen_mt8196 dabe8814-47e8-11ed-a58bb309974fecce shmread e2b6031c-47e8-11ed-07a97f801b6efa6c shmwrite 167a961e-8ae4-11ea-89f1000c29ce1635 smart_amp_test From 9b55f480262f04d7f65cf109ebe8b17aedbac898 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 14 Jan 2025 10:51:07 +0100 Subject: [PATCH 0008/1821] rimage: raise maximum number of modules Of course, 32 modules must be enough forever, until it isn't. With waves we've hit the limit. Let's raise it to 48, because that certainly will be enough forever. Signed-off-by: Guennadi Liakhovetski --- tools/rimage/src/include/rimage/cavs/cavs_ext_manifest.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/rimage/src/include/rimage/cavs/cavs_ext_manifest.h b/tools/rimage/src/include/rimage/cavs/cavs_ext_manifest.h index 4002f37fddb1..e135dbbfc191 100644 --- a/tools/rimage/src/include/rimage/cavs/cavs_ext_manifest.h +++ b/tools/rimage/src/include/rimage/cavs/cavs_ext_manifest.h @@ -27,7 +27,7 @@ #define EXTENDED_MANIFEST_VERSION_MAJOR 0x0001 #define EXTENDED_MANIFEST_VERSION_MINOR 0x0000 -#define FW_MAX_EXT_MODULE_NUM 32 +#define FW_MAX_EXT_MODULE_NUM 48 struct uuid_t { uint32_t d0; From b95fc72685b5f99adb1a70b48b72f8738b1bec13 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Tue, 14 Jan 2025 08:08:32 +0100 Subject: [PATCH 0009/1821] waves: add support for IPC4 compilation, including as LLEXT With this waves can be built as a part of IPC4 configuration - either linked into the base image or as a LLEXT module. Signed-off-by: Guennadi Liakhovetski --- src/audio/module_adapter/Kconfig | 3 ++- .../module/waves/llext/CMakeLists.txt | 11 ++++++++ .../module/waves/llext/llext.toml.h | 6 +++++ src/audio/module_adapter/module/waves/waves.c | 26 ++++++++++++++++++- .../module_adapter/module/waves/waves.toml | 24 +++++++++++++++++ tools/rimage/config/mtl.toml.h | 4 +++ zephyr/CMakeLists.txt | 19 +++++++++----- 7 files changed, 84 insertions(+), 9 deletions(-) create mode 100644 src/audio/module_adapter/module/waves/llext/CMakeLists.txt create mode 100644 src/audio/module_adapter/module/waves/llext/llext.toml.h create mode 100644 src/audio/module_adapter/module/waves/waves.toml diff --git a/src/audio/module_adapter/Kconfig b/src/audio/module_adapter/Kconfig index fb646a7f47e6..36c87aa69090 100644 --- a/src/audio/module_adapter/Kconfig +++ b/src/audio/module_adapter/Kconfig @@ -174,8 +174,9 @@ endif # Cadence files specific to PASSTHROUGH base codecs. config WAVES_CODEC - bool "Waves codec" + tristate "Waves codec" select WAVES_CODEC_STUB if COMP_STUBS + default m if LIBRARY_DEFAULT_MODULAR default n help Select to include Waves codec. Waves codec implements MaxxEffect API. diff --git a/src/audio/module_adapter/module/waves/llext/CMakeLists.txt b/src/audio/module_adapter/module/waves/llext/CMakeLists.txt new file mode 100644 index 000000000000..63104b8d71a0 --- /dev/null +++ b/src/audio/module_adapter/module/waves/llext/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Intel Corporation. +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_WAVES_CODEC_STUB) +sof_llext_build("waves" + SOURCES ../waves.c + ../maxx_stub.c +) +else() +message(FATAL_ERROR "Add library linking support in src/audio/module_adapter/module/waves/llext/CMakeLists.txt") +endif() diff --git a/src/audio/module_adapter/module/waves/llext/llext.toml.h b/src/audio/module_adapter/module/waves/llext/llext.toml.h new file mode 100644 index 000000000000..af98b94af57d --- /dev/null +++ b/src/audio/module_adapter/module/waves/llext/llext.toml.h @@ -0,0 +1,6 @@ +#include +#define LOAD_TYPE "2" +#include "../waves.toml" + +[module] +count = __COUNTER__ diff --git a/src/audio/module_adapter/module/waves/waves.c b/src/audio/module_adapter/module/waves/waves.c index 8ea54c8e21ed..4f606fd594dd 100644 --- a/src/audio/module_adapter/module/waves/waves.c +++ b/src/audio/module_adapter/module/waves/waves.c @@ -19,7 +19,9 @@ #define NUM_IO_STREAMS (1) SOF_DEFINE_REG_UUID(waves); + DECLARE_TR_CTX(waves_tr, SOF_UUID(waves_uuid), LOG_LEVEL_INFO); +LOG_MODULE_REGISTER(waves, CONFIG_SOF_LOG_LEVEL); struct waves_codec_data { uint32_t sample_rate; @@ -248,7 +250,8 @@ static int waves_effect_check(struct comp_dev *dev) /* different interleaving is not supported */ if (audio_stream_get_buffer_fmt(src_fmt) != audio_stream_get_buffer_fmt(snk_fmt)) { - comp_err(dev, "waves_effect_check() source %d sink %d buffer format mismatch"); + comp_err(dev, "waves_effect_check() source %d sink %d buffer format mismatch", + audio_stream_get_buffer_fmt(src_fmt), audio_stream_get_buffer_fmt(snk_fmt)); return -EINVAL; } @@ -896,3 +899,24 @@ static const struct module_interface waves_interface = { DECLARE_MODULE_ADAPTER(waves_interface, waves_uuid, waves_tr); SOF_MODULE_INIT(waves, sys_comp_module_waves_interface_init); + +#if CONFIG_WAVES_CODEC_MODULE && CONFIG_WAVES_CODEC_STUB +/* modular: llext dynamic link */ + +#include +#include +#include + +/* d944281a-afe9-4695-a043-d7f62b89538e */ +#define UUID_WAVES_CODEC 0x1A, 0x28, 0x44, 0xD9, 0xE9, 0xAF, 0x95, 0x46, \ + 0xA0, 0x43, 0xD7, 0xF6, 0x2B, 0x89, 0x53, 0x8E + +SOF_LLEXT_MOD_ENTRY(waves, &waves_interface); + +static const struct sof_man_module_manifest mod_manifest __section(".module") __used = + SOF_LLEXT_MODULE_MANIFEST("WAVES", waves_llext_entry, + 7, UUID_WAVES_CODEC, 8); + +SOF_LLEXT_BUILDINFO; + +#endif diff --git a/src/audio/module_adapter/module/waves/waves.toml b/src/audio/module_adapter/module/waves/waves.toml new file mode 100644 index 000000000000..5e81fb4b05d6 --- /dev/null +++ b/src/audio/module_adapter/module/waves/waves.toml @@ -0,0 +1,24 @@ +#ifndef LOAD_TYPE +#define LOAD_TYPE "0" +#endif + + REM # waves module config + [[module.entry]] + name = "WAVES" + uuid = "D944281A-AFE9-4695-A043-D7F62B89538E" + affinity_mask = "0x1" + instance_count = "4" + domain_types = "0" + load_type = LOAD_TYPE + module_type = "13" + auto_start = "0" + sched_caps = [1, 0x00008000] + + REM # pin = [dir, type, sample rate, size, container, channel-cfg] + pin = [0, 0, 0xfeef, 0xf, 0xf, 0x45ff, + 1, 0, 0xfeef, 0xf, 0xf, 0x1ff] + + REM # mod_cfg [PAR_0 PAR_1 PAR_2 PAR_3 IS_BYTES CPS IBS OBS MOD_FLAGS CPC OBLS] + mod_cfg = [0, 0, 0, 0, 4096, 1000000, 128, 128, 0, 0, 0] + + index = __COUNTER__ diff --git a/tools/rimage/config/mtl.toml.h b/tools/rimage/config/mtl.toml.h index eb61190b96fc..90b468efba18 100644 --- a/tools/rimage/config/mtl.toml.h +++ b/tools/rimage/config/mtl.toml.h @@ -134,6 +134,10 @@ #include