3939
4040void common_hal_nativeio_spi_construct (nativeio_spi_obj_t * self ,
4141 const mcu_pin_obj_t * clock , const mcu_pin_obj_t * mosi ,
42- const mcu_pin_obj_t * miso , uint32_t baudrate ) {
42+ const mcu_pin_obj_t * miso ) {
4343 struct spi_config config_spi_master ;
4444 spi_get_config_defaults (& config_spi_master );
4545
@@ -67,9 +67,10 @@ void common_hal_nativeio_spi_construct(nativeio_spi_obj_t *self,
6767 mosi_pad = mosi -> sercom [j ].pad ;
6868 if (miso_none ) {
6969 sercom = potential_sercom ;
70+ break ;
7071 }
7172 } else {
72- break ;
73+ continue ;
7374 }
7475 }
7576 if (!miso_none ) {
@@ -130,8 +131,6 @@ void common_hal_nativeio_spi_construct(nativeio_spi_obj_t *self,
130131 * pinmuxes [miso_pad ] = miso_pinmux ;
131132 }
132133
133- config_spi_master .mode_specific .master .baudrate = baudrate ;
134-
135134 spi_init (& self -> spi_master_instance , sercom , & config_spi_master );
136135
137136 spi_enable (& self -> spi_master_instance );
@@ -141,8 +140,64 @@ void common_hal_nativeio_spi_deinit(nativeio_spi_obj_t *self) {
141140 spi_disable (& self -> spi_master_instance );
142141}
143142
143+ bool common_hal_nativeio_spi_configure (nativeio_spi_obj_t * self ,
144+ uint32_t baudrate , uint8_t polarity , uint8_t phase , uint8_t bits ) {
145+ // TODO(tannewt): Check baudrate first before changing it.
146+ enum status_code status = spi_set_baudrate (& self -> spi_master_instance , baudrate );
147+ if (status != STATUS_OK ) {
148+ return false;
149+ }
150+
151+ SercomSpi * const spi_module = & (self -> spi_master_instance .hw -> SPI );
152+ // If the settings are already what we want then don't reset them.
153+ if (spi_module -> CTRLA .bit .CPHA == phase &&
154+ spi_module -> CTRLA .bit .CPOL == polarity &&
155+ spi_module -> CTRLB .bit .CHSIZE == (bits - 8 )) {
156+ return true;
157+ }
158+
159+ spi_disable (& self -> spi_master_instance );
160+ while (spi_is_syncing (& self -> spi_master_instance )) {
161+ /* Wait until the synchronization is complete */
162+ }
163+
164+ spi_module -> CTRLA .bit .CPHA = phase ;
165+ spi_module -> CTRLA .bit .CPOL = polarity ;
166+ spi_module -> CTRLB .bit .CHSIZE = bits - 8 ;
167+
168+ while (spi_is_syncing (& self -> spi_master_instance )) {
169+ /* Wait until the synchronization is complete */
170+ }
171+
172+ /* Enable the module */
173+ spi_enable (& self -> spi_master_instance );
174+
175+ while (spi_is_syncing (& self -> spi_master_instance )) {
176+ /* Wait until the synchronization is complete */
177+ }
178+
179+ return true;
180+ }
181+
182+ bool common_hal_nativeio_spi_try_lock (nativeio_spi_obj_t * self ) {
183+ self -> has_lock = spi_lock (& self -> spi_master_instance ) == STATUS_OK ;
184+ return self -> has_lock ;
185+ }
186+
187+ bool common_hal_nativeio_spi_has_lock (nativeio_spi_obj_t * self ) {
188+ return self -> has_lock ;
189+ }
190+
191+ void common_hal_nativeio_spi_unlock (nativeio_spi_obj_t * self ) {
192+ self -> has_lock = false;
193+ spi_unlock (& self -> spi_master_instance );
194+ }
195+
144196bool common_hal_nativeio_spi_write (nativeio_spi_obj_t * self ,
145197 const uint8_t * data , size_t len ) {
198+ if (len == 0 ) {
199+ return true;
200+ }
146201 enum status_code status = spi_write_buffer_wait (
147202 & self -> spi_master_instance ,
148203 data ,
@@ -152,6 +207,9 @@ bool common_hal_nativeio_spi_write(nativeio_spi_obj_t *self,
152207
153208bool common_hal_nativeio_spi_read (nativeio_spi_obj_t * self ,
154209 uint8_t * data , size_t len ) {
210+ if (len == 0 ) {
211+ return true;
212+ }
155213 enum status_code status = spi_read_buffer_wait (
156214 & self -> spi_master_instance ,
157215 data ,
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