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kscharlundkscharlund
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Merge branch 'develop' into read-can-fd-msg-64
2 parents ccab928 + 9ab5e35 commit 0a31628

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‎can/__init__.py‎

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@@ -37,6 +37,7 @@ class CanError(IOError):
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from .interfaces import VALID_INTERFACES
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from . import interface
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from .interface import Bus, detect_available_configs
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from .bit_timing import BitTiming
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from .broadcastmanager import (
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CyclicSendTaskABC,

‎can/bit_timing.py‎

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from typing import Union
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class BitTiming:
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"""Representation of a bit timing configuration.
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The class can be constructed in various ways, depending on the information
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available or the capabilities of the interfaces that need to be supported.
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The preferred way is using bitrate, CAN clock frequency, TSEG1, TSEG2, SJW::
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can.BitTiming(bitrate=1000000, f_clock=8000000, tseg1=5, tseg2=1, sjw=1)
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If the clock frequency is unknown it may be omitted but some interfaces may
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require it.
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Alternatively the BRP can be given instead of bitrate and clock frequency but this
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will limit the number of supported interfaces.
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It is also possible specify BTR registers directly,
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but will not work for all interfaces::
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can.BitTiming(btr0=0x00, btr1=0x14)
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"""
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sync_seg = 1
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def __init__(
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self,
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bitrate: int = None,
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f_clock: int = None,
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brp: int = None,
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tseg1: int = None,
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tseg2: int = None,
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sjw: int = None,
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nof_samples: int = 1,
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btr0: int = None,
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btr1: int = None,
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):
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"""
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:param int bitrate:
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Bitrate in bits/s.
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:param int f_clock:
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The CAN system clock frequency in Hz.
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Usually the oscillator frequency divided by 2.
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:param int brp:
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Bit Rate Prescaler. Prefer to use bitrate and f_clock instead.
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:param int tseg1:
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Time segment 1, that is, the number of quanta from (but not including)
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the Sync Segment to the sampling point.
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:param int tseg2:
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Time segment 2, that is, the number of quanta from the sampling
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point to the end of the bit.
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:param int sjw:
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The Synchronization Jump Width. Decides the maximum number of time quanta
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that the controller can resynchronize every bit.
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:param int nof_samples:
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Either 1 or 3. Some CAN controllers can also sample each bit three times.
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In this case, the bit will be sampled three quanta in a row,
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with the last sample being taken in the edge between TSEG1 and TSEG2.
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Three samples should only be used for relatively slow baudrates.
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:param int btr0:
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The BTR0 register value used by many CAN controllers.
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:param int btr1:
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The BTR1 register value used by many CAN controllers.
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"""
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self._bitrate = bitrate
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self._brp = brp
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self._sjw = sjw
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self._tseg1 = tseg1
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self._tseg2 = tseg2
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self._nof_samples = nof_samples
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self._f_clock = f_clock
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if btr0 is not None:
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self._brp = (btr0 & 0x3F) + 1
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self._sjw = (btr0 >> 6) + 1
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if btr1 is not None:
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self._tseg1 = (btr1 & 0xF) + 1
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self._tseg2 = ((btr1 >> 4) & 0x7) + 1
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self._nof_samples = 3 if btr1 & 0x80 else 1
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if nof_samples not in (1, 3):
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raise ValueError("nof_samples must be 1 or 3")
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@property
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def nbt(self) -> int:
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"""Nominal Bit Time."""
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return self.sync_seg + self.tseg1 + self.tseg2
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@property
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def bitrate(self) -> Union[int, float]:
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"""Bitrate in bits/s."""
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if self._bitrate:
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return self._bitrate
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if self._f_clock and self._brp:
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return self._f_clock / (self._brp * self.nbt)
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raise ValueError("bitrate must be specified")
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@property
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def brp(self) -> int:
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"""Bit Rate Prescaler."""
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if self._brp:
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return self._brp
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if self._f_clock and self._bitrate:
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return round(self._f_clock / (self._bitrate * self.nbt))
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raise ValueError("Either bitrate and f_clock or brp must be specified")
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@property
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def sjw(self) -> int:
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"""Synchronization Jump Width."""
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if not self._sjw:
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raise ValueError("sjw must be specified")
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return self._sjw
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@property
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def tseg1(self) -> int:
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"""Time segment 1.
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The number of quanta from (but not including) the Sync Segment to the sampling point.
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"""
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if not self._tseg1:
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raise ValueError("tseg1 must be specified")
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return self._tseg1
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@property
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def tseg2(self) -> int:
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"""Time segment 2.
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The number of quanta from the sampling point to the end of the bit.
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"""
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if not self._tseg2:
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raise ValueError("tseg2 must be specified")
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return self._tseg2
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@property
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def nof_samples(self) -> int:
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"""Number of samples (1 or 3)."""
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if not self._nof_samples:
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raise ValueError("nof_samples must be specified")
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return self._nof_samples
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@property
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def f_clock(self) -> int:
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"""The CAN system clock frequency in Hz.
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Usually the oscillator frequency divided by 2.
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"""
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if not self._f_clock:
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raise ValueError("f_clock must be specified")
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return self._f_clock
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@property
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def sample_point(self) -> float:
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"""Sample point in percent."""
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return 100.0 * (self.nbt - self.tseg2) / self.nbt
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@property
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def btr0(self) -> int:
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sjw = self.sjw
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brp = self.brp
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if brp < 1 or brp > 64:
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raise ValueError("brp must be 1 - 64")
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if sjw < 1 or sjw > 4:
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raise ValueError("sjw must be 1 - 4")
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return (sjw - 1) << 6 | brp - 1
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@property
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def btr1(self) -> int:
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sam = 1 if self.nof_samples == 3 else 0
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tseg1 = self.tseg1
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tseg2 = self.tseg2
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if tseg1 < 1 or tseg1 > 16:
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raise ValueError("tseg1 must be 1 - 16")
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if tseg2 < 1 or tseg2 > 8:
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raise ValueError("tseg2 must be 1 - 8")
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return sam << 7 | (tseg2 - 1) << 4 | tseg1 - 1
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def __str__(self) -> str:
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segments = []
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try:
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segments.append(f"{self.bitrate} bits/s")
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except ValueError:
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pass
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try:
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segments.append(f"sample point: {self.sample_point:.2f}%")
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except ValueError:
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pass
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try:
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segments.append(f"BRP: {self.brp}")
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except ValueError:
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pass
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try:
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segments.append(f"TSEG1: {self.tseg1}")
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except ValueError:
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pass
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try:
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segments.append(f"TSEG2: {self.tseg2}")
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except ValueError:
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pass
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try:
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segments.append(f"SJW: {self.sjw}")
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except ValueError:
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pass
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try:
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segments.append(f"BTR: {self.btr0:02X}{self.btr1:02X}h")
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except ValueError:
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pass
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return ", ".join(segments)
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def __repr__(self) -> str:
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kwargs = {}
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if self._f_clock:
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kwargs["f_clock"] = self._f_clock
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if self._bitrate:
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kwargs["bitrate"] = self._bitrate
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if self._brp:
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kwargs["brp"] = self._brp
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if self._tseg1:
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kwargs["tseg1"] = self._tseg1
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if self._tseg2:
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kwargs["tseg2"] = self._tseg2
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if self._sjw:
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kwargs["sjw"] = self._sjw
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if self._nof_samples != 1:
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kwargs["nof_samples"] = self._nof_samples
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args = ", ".join(f"{key}={value}" for key, value in kwargs.items())
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return f"can.BitTiming({args})"

‎can/interfaces/__init__.py‎

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"slcan": ("can.interfaces.slcan", "slcanBus"),
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"canalystii": ("can.interfaces.canalystii", "CANalystIIBus"),
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"systec": ("can.interfaces.systec", "UcanBus"),
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"seeedstudio": ("can.interfaces.seeedstudio", "SeeedBus"),
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}
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BACKENDS.update(

‎can/interfaces/seeedstudio/__init__.py‎

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# coding: utf-8
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"""
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"""
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from can.interfaces.seeedstudio.seeedstudio import SeeedBus

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