Skip to content

Commit 3cfd125

Browse files
tannergoodingtannergooding
authored
Updating the managed baselines to x86-64-v2 and armv8-a + lse (dotnet#118101)
* Updating the managed baselines to x86-64-v2 and armv8.1-a * Fix parens on MacOS * Fix a check that's necessary for 64-bit * Don't require FEAT_LSE on Linux * Remove the legacy encoding for pextrw * Fix a pre-initialization smoke test to account for Popcnt now being pre-initialized * Update the R2R baseline to differ from the NAOT baseline * Have the preinitialization smoke test use an ISA that is opportunistic with the new baseline * Don't target x86-64-v3 for OSX to avoid negatively impacting Apple Silicon * Ensure the RCPC2 check is done last so methods aren't marked as using it unnecessarily * Ensure containment for Ssse3.Shuffle still works * Ensure AVX only hardware doesn't assert during lowering * Don't run the JittedMethodsCountingTest if the default target is disabled
1 parent d342502 commit 3cfd125

48 files changed

Lines changed: 1153 additions & 2668 deletions

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

‎docs/design/coreclr/botr/vectors-and-intrinsics.md‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -40,8 +40,8 @@ For AOT compilation, the situation is far more complex. This is due to the follo
4040

4141
## Crossgen2 model of hardware intrinsic usage
4242
There are 2 sets of instruction sets known to the compiler.
43-
- The baseline instruction set which defaults to (Sse, Sse2), but may be adjusted via compiler option.
44-
- The optimistic instruction set which defaults to (Sse3, Ssse3, Sse41, Sse42, Popcnt, Pclmulqdq, and Lzcnt).
43+
- The baseline instruction set which defaults to x86-64-v2 (SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, and POPCNT), but may be adjusted via compiler option.
44+
- The optimistic instruction set which defaults to (AES, GFNI, SHA, WAITPKG, and X86SERIALIZE).
4545

4646
Code will be compiled using the optimistic instruction set to drive compilation, but any use of an instruction set beyond the baseline instruction set will be recorded, as will any attempt to use an instruction set beyond the optimistic set if that attempted use has a semantic effect. If the baseline instruction set includes `Avx2` then the size and characteristics of of `Vector<T>` is known. Any other decisions about ABI may also be encoded. For instance, it is likely that the ABI of `Vector256<T>` and `Vector512<T>` will vary based on the presence/absence of `Avx` support.
4747

‎eng/pipelines/common/templates/runtimes/run-test-job.yml‎

Lines changed: 8 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -359,74 +359,31 @@ jobs:
359359
- jitstress_random_2
360360
${{ if in(parameters.testGroup, 'jitstress-isas-arm') }}:
361361
scenarios:
362-
- jitstress_isas_incompletehwintrinsic
363362
- jitstress_isas_nohwintrinsic
364-
- jitstress_isas_nohwintrinsic_nosimd
365-
- jitstress_isas_nosimd
366363
${{ if in(parameters.testGroup, 'jitstress-isas-x86') }}:
367364
scenarios:
368-
- jitstress_isas_incompletehwintrinsic
369365
- jitstress_isas_nohwintrinsic
370-
- jitstress_isas_nohwintrinsic_nosimd
371-
- jitstress_isas_nosimd
372366
- jitstress_isas_x86_evex
373-
- jitstress_isas_x86_noaes
374367
- jitstress_isas_x86_noavx
375368
- jitstress_isas_x86_noavx2
376369
- jitstress_isas_x86_noavx512
377-
- jitstress_isas_x86_nobmi1
378-
- jitstress_isas_x86_nobmi2
379-
- jitstress_isas_x86_nofma
380-
- jitstress_isas_x86_nohwintrinsic
381-
- jitstress_isas_x86_nolzcnt
382-
- jitstress_isas_x86_nopclmulqdq
383-
- jitstress_isas_x86_nopopcnt
384-
- jitstress_isas_x86_nosse
385-
- jitstress_isas_x86_nosse2
386-
- jitstress_isas_x86_nosse3
387-
- jitstress_isas_x86_nosse3_4
388-
- jitstress_isas_x86_nosse41
389-
- jitstress_isas_x86_nosse42
390-
- jitstress_isas_x86_nossse3
391370
- jitstress_isas_x86_vectort128
392371
- jitstress_isas_x86_vectort512
393372
- jitstress_isas_x86_noavx512_vectort128
394-
- jitstress_isas_1_x86_noaes
373+
- jitstress_isas_1_x86_evex
395374
- jitstress_isas_1_x86_noavx
396375
- jitstress_isas_1_x86_noavx2
397376
- jitstress_isas_1_x86_noavx512
398-
- jitstress_isas_1_x86_nobmi1
399-
- jitstress_isas_1_x86_nobmi2
400-
- jitstress_isas_1_x86_nofma
401-
- jitstress_isas_1_x86_nohwintrinsic
402-
- jitstress_isas_1_x86_nolzcnt
403-
- jitstress_isas_1_x86_nopclmulqdq
404-
- jitstress_isas_1_x86_nopopcnt
405-
- jitstress_isas_1_x86_nosse
406-
- jitstress_isas_1_x86_nosse2
407-
- jitstress_isas_1_x86_nosse3
408-
- jitstress_isas_1_x86_nosse3_4
409-
- jitstress_isas_1_x86_nosse41
410-
- jitstress_isas_1_x86_nosse42
411-
- jitstress_isas_1_x86_nossse3
412-
- jitstress_isas_2_x86_noaes
377+
- jitstress_isas_1_x86_vectort128
378+
- jitstress_isas_1_x86_vectort512
379+
- jitstress_isas_1_x86_noavx512_vectort128
380+
- jitstress_isas_2_x86_evex
413381
- jitstress_isas_2_x86_noavx
414382
- jitstress_isas_2_x86_noavx2
415383
- jitstress_isas_2_x86_noavx512
416-
- jitstress_isas_2_x86_nobmi1
417-
- jitstress_isas_2_x86_nobmi2
418-
- jitstress_isas_2_x86_nofma
419-
- jitstress_isas_2_x86_nohwintrinsic
420-
- jitstress_isas_2_x86_nolzcnt
421-
- jitstress_isas_2_x86_nopclmulqdq
422-
- jitstress_isas_2_x86_nopopcnt
423-
- jitstress_isas_2_x86_nosse
424-
- jitstress_isas_2_x86_nosse2
425-
- jitstress_isas_2_x86_nosse3
426-
- jitstress_isas_2_x86_nosse3_4
427-
- jitstress_isas_2_x86_nosse41
428-
- jitstress_isas_2_x86_nosse42
429-
- jitstress_isas_2_x86_nossse3
384+
- jitstress_isas_2_x86_vectort128
385+
- jitstress_isas_2_x86_vectort512
386+
- jitstress_isas_2_x86_noavx512_vectort128
430387
${{ if in(parameters.testGroup, 'jitstress-isas-avx512') }}:
431388
scenarios:
432389
- jitstress_isas_x86_evex

‎src/coreclr/inc/clrconfigvalues.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -670,7 +670,6 @@ RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableHWIntrinsic, W("EnableHWIntri
670670
#endif // defined(TARGET_LOONGARCH64)
671671

672672
#if defined(TARGET_AMD64) || defined(TARGET_X86)
673-
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableSSE42, W("EnableSSE42"), 1, "Allows SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, and dependent hardware intrinsics to be disabled")
674673
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX, W("EnableAVX"), 1, "Allows AVX and dependent hardware intrinsics to be disabled")
675674
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX2, W("EnableAVX2"), 1, "Allows AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE and dependent hardware intrinsics to be disabled")
676675
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX512, W("EnableAVX512"), 1, "Allows AVX512 F+BW+CD+DQ+VL and depdendent hardware intrinsics to be disabled")

0 commit comments

Comments
 (0)