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Merge branch 'next/dt' into next/multiplatform
* next/dt: (182 commits) ARM: tegra: Add Avionic Design Tamonten Evaluation Carrier support ARM: tegra: Add Avionic Design Medcom-Wide support ARM: tegra: Add Avionic Design Plutux support ARM: tegra: Add Avionic Design Tamonten support ARM: tegra: dts: Add pwm label ARM: dt: tegra: whistler: configure power off ARM: mxs: m28evk: Disable OCOTP OUI loading ARM: imx6q: use pll2_pfd2_396m as the enfc_sel's parent ARM: dts: imx6q-sabrelite: add usbotg pinctrl support ARM: dts: imx23-olinuxino: Add USB host support ARM: dts: imx6q-sabrelite: add usbmisc device ARM: dts: mx23: Add USB resources ARM: dts: mxs: Add ethernetX to macX aliases ARM: msm: Remove non-DT targets from 8960 ARM: msm: Add DT support for 8960 ARM: msm: Move io mapping prototypes to common.h ARM: msm: Rename board-msm8x60 to signify its DT only status ARM: msm: Make 8660 a DT only target ARM: msm: Move 8660 to DT timer ARM: msm: Add DT support to msm_timer ...
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‎Documentation/devicetree/bindings/arm/mrvl/tauros2.txt‎

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* Marvell Tauros2 Cache
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Required properties:
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- compatible : Should be "marvell,tauros2-cache".
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- marvell,tauros2-cache-features : Specify the features supported for the
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tauros2 cache.
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The features including
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CACHE_TAUROS2_PREFETCH_ON (1 << 0)
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CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1)
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The definition can be found at
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arch/arm/include/asm/hardware/cache-tauros2.h
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Example:
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L2: l2-cache {
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compatible = "marvell,tauros2-cache";
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marvell,tauros2-cache-features = <0x3>;
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};

‎Documentation/devicetree/bindings/arm/msm/timer.txt‎

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* MSM Timer
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Properties:
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- compatible : Should at least contain "qcom,msm-timer". More specific
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properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general
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purpose timer and a debug timer respectively.
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- interrupts : Interrupt indicating a match event.
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- reg : Specifies the base address of the timer registers. The second region
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specifies an optional register used to configure the clock divider.
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- clock-frequency : The frequency of the timer in Hz.
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Optional:
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- cpu-offset : per-cpu offset used when the timer is accessed without the
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CPU remapping facilities. The offset is cpu-offset * cpu-nr.
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Example:
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timer@200a004 {
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compatible = "qcom,msm-gpt", "qcom,msm-timer";
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interrupts = <1 2 0x301>;
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reg = <0x0200a004 0x10>;
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clock-frequency = <32768>;
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cpu-offset = <0x40000>;
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};
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timer@200a024 {
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compatible = "qcom,msm-dgt", "qcom,msm-timer";
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interrupts = <1 3 0x301>;
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reg = <0x0200a024 0x10>,
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<0x0200a034 0x4>;
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clock-frequency = <6750000>;
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cpu-offset = <0x40000>;
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};

‎Documentation/devicetree/bindings/arm/omap/omap.txt‎

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- OMAP3 BeagleBoard : Low cost community board
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compatible = "ti,omap3-beagle", "ti,omap3"
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- OMAP3 Tobi with Overo : Commercial expansion board with daughter board
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compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3"
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- OMAP4 SDP : Software Developement Board
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compatible = "ti,omap4-sdp", "ti,omap4430"
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‎Documentation/devicetree/bindings/clock/imx23-clock.txt‎

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* Clock bindings for Freescale i.MX23
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Required properties:
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- compatible: Should be "fsl,imx23-clkctrl"
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- reg: Address and length of the register set
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- #clock-cells: Should be <1>
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. The following is a full list of i.MX23
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clocks and IDs.
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Clock ID
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------------------
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ref_xtal 0
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pll 1
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ref_cpu 2
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ref_emi 3
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ref_pix 4
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ref_io 5
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saif_sel 6
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lcdif_sel 7
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gpmi_sel 8
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ssp_sel 9
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emi_sel 10
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cpu 11
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etm_sel 12
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cpu_pll 13
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cpu_xtal 14
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hbus 15
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xbus 16
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lcdif_div 17
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ssp_div 18
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gpmi_div 19
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emi_pll 20
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emi_xtal 21
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etm_div 22
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saif_div 23
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clk32k_div 24
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rtc 25
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adc 26
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spdif_div 27
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clk32k 28
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dri 29
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pwm 30
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filt 31
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uart 32
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ssp 33
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gpmi 34
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spdif 35
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emi 36
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saif 37
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lcdif 38
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etm 39
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usb 40
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usb_pwr 41
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Examples:
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clks: clkctrl@80040000 {
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compatible = "fsl,imx23-clkctrl";
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reg = <0x80040000 0x2000>;
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#clock-cells = <1>;
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clock-output-names =
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...
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"uart", /* 32 */
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...
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"end_of_list";
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};
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auart0: serial@8006c000 {
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compatible = "fsl,imx23-auart";
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reg = <0x8006c000 0x2000>;
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interrupts = <24 25 23>;
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clocks = <&clks 32>;
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status = "disabled";
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};

‎Documentation/devicetree/bindings/clock/imx28-clock.txt‎

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* Clock bindings for Freescale i.MX28
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Required properties:
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- compatible: Should be "fsl,imx28-clkctrl"
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- reg: Address and length of the register set
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- #clock-cells: Should be <1>
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. The following is a full list of i.MX28
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clocks and IDs.
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Clock ID
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------------------
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ref_xtal 0
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pll0 1
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pll1 2
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pll2 3
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ref_cpu 4
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ref_emi 5
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ref_io0 6
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ref_io1 7
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ref_pix 8
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ref_hsadc 9
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ref_gpmi 10
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saif0_sel 11
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saif1_sel 12
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gpmi_sel 13
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ssp0_sel 14
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ssp1_sel 15
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ssp2_sel 16
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ssp3_sel 17
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emi_sel 18
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etm_sel 19
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lcdif_sel 20
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cpu 21
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ptp_sel 22
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cpu_pll 23
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cpu_xtal 24
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hbus 25
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xbus 26
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ssp0_div 27
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ssp1_div 28
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ssp2_div 29
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ssp3_div 30
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gpmi_div 31
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emi_pll 32
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emi_xtal 33
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lcdif_div 34
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etm_div 35
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ptp 36
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saif0_div 37
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saif1_div 38
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clk32k_div 39
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rtc 40
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lradc 41
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spdif_div 42
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clk32k 43
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pwm 44
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uart 45
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ssp0 46
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ssp1 47
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ssp2 48
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ssp3 49
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gpmi 50
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spdif 51
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emi 52
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saif0 53
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saif1 54
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lcdif 55
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etm 56
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fec 57
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can0 58
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can1 59
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usb0 60
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usb1 61
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usb0_pwr 62
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usb1_pwr 63
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enet_out 64
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Examples:
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clks: clkctrl@80040000 {
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compatible = "fsl,imx28-clkctrl";
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reg = <0x80040000 0x2000>;
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#clock-cells = <1>;
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clock-output-names =
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...
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"uart", /* 45 */
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...
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"end_of_list";
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};
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auart0: serial@8006a000 {
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compatible = "fsl,imx28-auart", "fsl,imx23-auart";
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reg = <0x8006a000 0x2000>;
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interrupts = <112 70 71>;
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clocks = <&clks 45>;
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status = "disabled";
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};

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