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dhalbertdhalbert
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atmel-samd working
1 parent a0721fc commit d628d2a

7 files changed

Lines changed: 349 additions & 23 deletions

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‎ports/atmel-samd/bindings/samd/Clock.c‎

Lines changed: 260 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -163,3 +163,263 @@ const mp_obj_type_t samd_clock_type = {
163163
.print = samd_clock_print,
164164
.locals_dict = (mp_obj_t)&samd_clock_locals_dict,
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};
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#ifdef SAMD21
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#ifdef SAMD21_EXPOSE_ALL_CLOCKS
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CLOCK_SOURCE(XOSC);
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CLOCK_SOURCE(GCLKIN);
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CLOCK_SOURCE(GCLKGEN1);
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CLOCK_SOURCE(OSCULP32K);
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#endif
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CLOCK_SOURCE(OSC32K);
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CLOCK_SOURCE(XOSC32K);
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#ifdef SAMD21_EXPOSE_ALL_CLOCKS
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CLOCK_SOURCE(OSC8M);
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CLOCK_SOURCE(DFLL48M);
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CLOCK_SOURCE(DPLL96M);
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182+
CLOCK_GCLK_(SYSCTRL, DFLL48);
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CLOCK_GCLK_(SYSCTRL, FDPLL);
184+
CLOCK_GCLK_(SYSCTRL, FDPLL32K);
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CLOCK_GCLK(WDT);
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#endif
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CLOCK_GCLK(RTC);
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#ifdef SAMD21_EXPOSE_ALL_CLOCKS
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CLOCK_GCLK(EIC);
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CLOCK_GCLK(USB);
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CLOCK_GCLK_(EVSYS, 0);
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CLOCK_GCLK_(EVSYS, 1);
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CLOCK_GCLK_(EVSYS, 2);
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CLOCK_GCLK_(EVSYS, 3);
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CLOCK_GCLK_(EVSYS, 4);
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CLOCK_GCLK_(EVSYS, 5);
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CLOCK_GCLK_(EVSYS, 6);
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CLOCK_GCLK_(EVSYS, 7);
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CLOCK_GCLK_(EVSYS, 8);
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CLOCK_GCLK_(EVSYS, 9);
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CLOCK_GCLK_(EVSYS, 10);
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CLOCK_GCLK_(EVSYS, 11);
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CLOCK(SERCOMx_SLOW, 1, 19);
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CLOCK_GCLK_(SERCOM0, CORE);
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CLOCK_GCLK_(SERCOM1, CORE);
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CLOCK_GCLK_(SERCOM2, CORE);
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CLOCK_GCLK_(SERCOM3, CORE);
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CLOCK_GCLK_(SERCOM4, CORE);
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CLOCK_GCLK_(SERCOM5, CORE);
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CLOCK(TCC0_TCC1, 1, 26);
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CLOCK(TCC2_TCC3, 1, 27);
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CLOCK(TC4_TC5, 1, 28);
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CLOCK(TC6_TC7, 1, 29);
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CLOCK_GCLK(ADC);
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CLOCK_GCLK_(AC, DIG);
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CLOCK_GCLK_(AC, ANA);
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CLOCK_GCLK(DAC);
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CLOCK_GCLK(PTC);
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CLOCK_GCLK_(I2S, 0);
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CLOCK_GCLK_(I2S, 1);
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CLOCK(SYSTICK, 2, 0);
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#endif
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STATIC const mp_rom_map_elem_t samd_clock_global_dict_table[] = {
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#ifdef SAMD21_EXPOSE_ALL_CLOCKS
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CLOCK_ENTRY(XOSC),
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CLOCK_ENTRY(GCLKIN),
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CLOCK_ENTRY(GCLKGEN1),
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CLOCK_ENTRY(OSCULP32K),
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#endif
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CLOCK_ENTRY(OSC32K),
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CLOCK_ENTRY(XOSC32K),
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#ifdef SAMD21_EXPOSE_ALL_CLOCKS
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CLOCK_ENTRY(OSC8M),
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CLOCK_ENTRY(DFLL48M),
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CLOCK_ENTRY(DPLL96M),
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CLOCK_ENTRY_(SYSCTRL, DFLL48),
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CLOCK_ENTRY_(SYSCTRL, FDPLL),
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CLOCK_ENTRY_(SYSCTRL, FDPLL32K),
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CLOCK_ENTRY(WDT),
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#endif
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CLOCK_ENTRY(RTC),
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#ifdef SAMD21_EXPOSE_ALL_CLOCKS
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CLOCK_ENTRY(EIC),
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CLOCK_ENTRY(USB),
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CLOCK_ENTRY_(EVSYS, 0),
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CLOCK_ENTRY_(EVSYS, 1),
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CLOCK_ENTRY_(EVSYS, 2),
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CLOCK_ENTRY_(EVSYS, 3),
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CLOCK_ENTRY_(EVSYS, 4),
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CLOCK_ENTRY_(EVSYS, 5),
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CLOCK_ENTRY_(EVSYS, 6),
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CLOCK_ENTRY_(EVSYS, 7),
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CLOCK_ENTRY_(EVSYS, 8),
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CLOCK_ENTRY_(EVSYS, 9),
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CLOCK_ENTRY_(EVSYS, 10),
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CLOCK_ENTRY_(EVSYS, 11),
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CLOCK_ENTRY(SERCOMx_SLOW),
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CLOCK_ENTRY_(SERCOM0, CORE),
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CLOCK_ENTRY_(SERCOM1, CORE),
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CLOCK_ENTRY_(SERCOM2, CORE),
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CLOCK_ENTRY_(SERCOM3, CORE),
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CLOCK_ENTRY_(SERCOM4, CORE),
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CLOCK_ENTRY_(SERCOM5, CORE),
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CLOCK_ENTRY(TCC0_TCC1),
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CLOCK_ENTRY(TCC2_TCC3),
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CLOCK_ENTRY(TC4_TC5),
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CLOCK_ENTRY(TC6_TC7),
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CLOCK_ENTRY(ADC),
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CLOCK_ENTRY_(AC, DIG),
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CLOCK_ENTRY_(AC, ANA),
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CLOCK_ENTRY(DAC),
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CLOCK_ENTRY(PTC),
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CLOCK_ENTRY_(I2S, 0),
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CLOCK_ENTRY_(I2S, 1),
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CLOCK_ENTRY(SYSTICK),
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#endif
280+
};
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MP_DEFINE_CONST_DICT(samd_clock_globals, samd_clock_global_dict_table);
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#endif // SAMD21
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#ifdef SAMD51
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#include <instance/can0.h>
290+
#include <instance/can1.h>
291+
#include <instance/i2s.h>
292+
#include <instance/sdhc1.h>
293+
#include <instance/sercom6.h>
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#include <instance/sercom7.h>
295+
#include <instance/tcc4.h>
296+
297+
CLOCK_SOURCE(XOSC0);
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CLOCK_SOURCE(XOSC1);
299+
CLOCK_SOURCE(GCLKIN);
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CLOCK_SOURCE(GCLKGEN1);
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CLOCK_SOURCE(OSCULP32K);
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CLOCK_SOURCE(XOSC32K);
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CLOCK_SOURCE(DFLL);
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CLOCK_SOURCE(DPLL0);
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CLOCK_SOURCE(DPLL1);
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CLOCK_GCLK_(OSCCTRL, DFLL48);
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CLOCK_GCLK_(OSCCTRL, FDPLL0);
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CLOCK_GCLK_(OSCCTRL, FDPLL1);
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CLOCK_GCLK_(OSCCTRL, FDPLL032K); // GCLK_OSCCTRL_FDPLL1_32K, GCLK_SDHC0_SLOW, GCLK_SDHC1_SLOW, GCLK_SERCOM[0..7]_SLOW
311+
CLOCK_GCLK(EIC);
312+
CLOCK_GCLK_(FREQM, MSR);
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// 6: GCLK_FREQM_REF
314+
CLOCK_GCLK_(SERCOM0, CORE);
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CLOCK_GCLK_(SERCOM1, CORE);
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CLOCK(TC0_TC1, 1, 9);
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CLOCK_GCLK(USB);
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CLOCK_GCLK_(EVSYS, 0);
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CLOCK_GCLK_(EVSYS, 1);
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CLOCK_GCLK_(EVSYS, 2);
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CLOCK_GCLK_(EVSYS, 3);
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CLOCK_GCLK_(EVSYS, 4);
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CLOCK_GCLK_(EVSYS, 5);
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CLOCK_GCLK_(EVSYS, 6);
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CLOCK_GCLK_(EVSYS, 7);
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CLOCK_GCLK_(EVSYS, 8);
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CLOCK_GCLK_(EVSYS, 9);
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CLOCK_GCLK_(EVSYS, 10);
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CLOCK_GCLK_(EVSYS, 11);
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CLOCK_GCLK_(SERCOM2, CORE);
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CLOCK_GCLK_(SERCOM3, CORE);
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CLOCK(TCC0_TCC1, 1, 25);
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CLOCK(TC2_TC3, 1, 26);
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CLOCK_GCLK(CAN0);
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CLOCK_GCLK(CAN1);
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CLOCK(TCC2_TCC3, 1, 29);
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CLOCK(TC4_TC5, 1, 30);
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// CLOCK_GCLK(PDEC);
339+
// CLOCK_GCLK(AC);
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// CLOCK_GCLK(CCL);
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CLOCK_GCLK_(SERCOM4, CORE);
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CLOCK_GCLK_(SERCOM5, CORE);
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CLOCK_GCLK_(SERCOM6, CORE);
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CLOCK_GCLK_(SERCOM7, CORE);
345+
CLOCK_GCLK(TCC4);
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CLOCK(TC6_TC7, 1, 39);
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CLOCK_GCLK(ADC0);
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CLOCK_GCLK(ADC1);
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CLOCK_GCLK(DAC);
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CLOCK_GCLK_(I2S, 0);
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CLOCK_GCLK_(I2S, 1);
352+
// CLOCK_GCLK(SDHC0);
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// CLOCK_GCLK(SDHC1);
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// 47: GCLK_CM4_TRACE
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CLOCK(SYSTICK, 2, 0);
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CLOCK(CPU, 2, 1);
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CLOCK(RTC, 2, 2);
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STATIC const mp_rom_map_elem_t samd_clock_global_dict_table[] = {
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CLOCK_ENTRY(XOSC0),
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CLOCK_ENTRY(XOSC1),
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CLOCK_ENTRY(GCLKIN),
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CLOCK_ENTRY(GCLKGEN1),
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CLOCK_ENTRY(OSCULP32K),
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CLOCK_ENTRY(XOSC32K),
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CLOCK_ENTRY(DFLL),
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CLOCK_ENTRY(DPLL0),
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CLOCK_ENTRY(DPLL1),
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CLOCK_ENTRY_(OSCCTRL, DFLL48),
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CLOCK_ENTRY_(OSCCTRL, FDPLL0),
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CLOCK_ENTRY_(OSCCTRL, FDPLL1),
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CLOCK_ENTRY_(OSCCTRL, FDPLL032K),
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CLOCK_ENTRY(EIC),
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CLOCK_ENTRY_(FREQM, MSR),
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CLOCK_ENTRY_(SERCOM0, CORE),
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CLOCK_ENTRY_(SERCOM1, CORE),
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CLOCK_ENTRY(TC0_TC1),
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CLOCK_ENTRY(USB),
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CLOCK_ENTRY_(EVSYS, 0),
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CLOCK_ENTRY_(EVSYS, 1),
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CLOCK_ENTRY_(EVSYS, 2),
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CLOCK_ENTRY_(EVSYS, 3),
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CLOCK_ENTRY_(EVSYS, 4),
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CLOCK_ENTRY_(EVSYS, 5),
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CLOCK_ENTRY_(EVSYS, 6),
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CLOCK_ENTRY_(EVSYS, 7),
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CLOCK_ENTRY_(EVSYS, 8),
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CLOCK_ENTRY_(EVSYS, 9),
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CLOCK_ENTRY_(EVSYS, 10),
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CLOCK_ENTRY_(EVSYS, 11),
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CLOCK_ENTRY_(SERCOM2, CORE),
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CLOCK_ENTRY_(SERCOM3, CORE),
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CLOCK_ENTRY(TCC0_TCC1),
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CLOCK_ENTRY(TC2_TC3),
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CLOCK_ENTRY(CAN0),
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CLOCK_ENTRY(CAN1),
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CLOCK_ENTRY(TCC2_TCC3),
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CLOCK_ENTRY(TC4_TC5),
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// CLOCK_ENTRY(PDEC),
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// CLOCK_ENTRY(AC),
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// CLOCK_ENTRY(CCL),
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CLOCK_ENTRY_(SERCOM4, CORE),
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CLOCK_ENTRY_(SERCOM5, CORE),
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CLOCK_ENTRY_(SERCOM6, CORE),
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CLOCK_ENTRY_(SERCOM7, CORE),
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CLOCK_ENTRY(TCC4),
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CLOCK_ENTRY(TC6_TC7),
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CLOCK_ENTRY(ADC0),
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CLOCK_ENTRY(ADC1),
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CLOCK_ENTRY(DAC),
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CLOCK_ENTRY_(I2S, 0),
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CLOCK_ENTRY_(I2S, 1),
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// CLOCK_ENTRY(SDHC0),
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// CLOCK_ENTRY(SDHC1),
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CLOCK_ENTRY(SYSTICK),
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CLOCK_ENTRY(CPU),
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CLOCK_ENTRY(RTC),
422+
};
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MP_DEFINE_CONST_DICT(samd_clock_globals, samd_clock_global_dict_table);
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#endif // SAMD51

‎ports/atmel-samd/common-hal/frequencyio/FrequencyIn.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -213,7 +213,7 @@ void frequencyin_samd51_start_dpll() {
213213
// Will also enable the Lock Bypass due to low-frequency sources causing DPLL unlocks
214214
// as outlined in the Errata (1.12.1)
215215
OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0) | OSCCTRL_DPLLRATIO_LDR(2999);
216-
if (board_has_crystal()) { // we can use XOSC32K directly as the source
216+
if (BOARD_HAS_CRYSTAL) { // we can use XOSC32K directly as the source
217217
OSC32KCTRL->XOSC32K.bit.EN32K = 1;
218218
OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK(1) |
219219
OSCCTRL_DPLLCTRLB_LBYPASS;

‎ports/atmel-samd/mpconfigport.h‎

Lines changed: 30 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -30,28 +30,16 @@
3030
// Definitions for which SAMD chip we're using.
3131
#include "include/sam.h"
3232

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////////////////////////////////////////////////////////////////////////////////////////////////////
35+
#ifdef SAMD21
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3337
#if INTERNAL_FLASH_FILESYSTEM
3438
#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (64*1024)
3539
#else
3640
#define CIRCUITPY_INTERNAL_FLASH_FILESYSTEM_SIZE (0)
3741
#endif
3842

39-
#ifndef CALIBRATE_CRYSTALLESS
40-
#define CALIBRATE_CRYSTALLESS (0)
41-
#endif
42-
43-
// if CALIBRATE_CRYSTALLESS is requested, make room for storing
44-
// calibration data generated from external USB.
45-
#ifndef CIRCUITPY_INTERNAL_CONFIG_SIZE
46-
#if CALIBRATE_CRYSTALLESS
47-
#define CIRCUITPY_INTERNAL_CONFIG_SIZE (256)
48-
#else
49-
#define CIRCUITPY_INTERNAL_CONFIG_SIZE (0)
50-
#endif
51-
#endif
52-
53-
#ifdef SAMD21
54-
5543
// HMCRAMC0_SIZE is defined in the ASF4 include files for each SAMD21 chip.
5644
#define RAM_SIZE HMCRAMC0_SIZE
5745
#define BOOTLOADER_SIZE (8*1024)
@@ -84,6 +72,8 @@
8472

8573
#endif // SAMD21
8674

75+
////////////////////////////////////////////////////////////////////////////////////////////////////
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8777
#ifdef SAMD51
8878

8979
#ifndef CIRCUITPY_INTERNAL_NVM_SIZE
@@ -110,13 +100,37 @@
110100
#define MICROPY_PY_BUILTINS_NOTIMPLEMENTED (1)
111101
#define MICROPY_PY_COLLECTIONS_ORDEREDDICT (1)
112102
#define MICROPY_PY_FUNCTION_ATTRS (1)
103+
// MICROPY_PY_UJSON depends on MICROPY_PY_IO
113104
#define MICROPY_PY_IO (1)
114105
#define MICROPY_PY_UJSON (1)
115106
#define MICROPY_PY_REVERSE_SPECIAL_METHODS (1)
116107
// MICROPY_PY_UERRNO_LIST - Use the default
117108

118109
#endif // SAMD51
119110

111+
////////////////////////////////////////////////////////////////////////////////////////////////////
112+
113+
// This also includes mpconfigboard.h.
114+
#include "py/circuitpy_mpconfig.h"
115+
116+
#ifndef CALIBRATE_CRYSTALLESS
117+
#define CALIBRATE_CRYSTALLESS (0)
118+
#endif
119+
120+
#ifndef BOARD_HAS_CRYSTAL
121+
#define BOARD_HAS_CRYSTAL (0)
122+
#endif
123+
124+
// if CALIBRATE_CRYSTALLESS is requested, make room for storing
125+
// calibration data generated from external USB.
126+
#ifndef CIRCUITPY_INTERNAL_CONFIG_SIZE
127+
#if CALIBRATE_CRYSTALLESS
128+
#define CIRCUITPY_INTERNAL_CONFIG_SIZE (NVMCTRL_ROW_SIZE) // 256
129+
#else
130+
#define CIRCUITPY_INTERNAL_CONFIG_SIZE (0)
131+
#endif
132+
#endif
133+
120134
// Flash layout, starting at 0x00000000
121135
//
122136
// bootloader (8 or 16kB)
@@ -155,8 +169,6 @@
155169

156170
#include "peripherals/samd/dma.h"
157171

158-
#include "py/circuitpy_mpconfig.h"
159-
160172
#define MICROPY_PORT_ROOT_POINTERS \
161173
CIRCUITPY_COMMON_ROOT_POINTERS \
162174
mp_obj_t playing_audio[AUDIO_DMA_CHANNEL_COUNT];

‎ports/atmel-samd/peripherals‎

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