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py/emitnative: Simplify binary op emitter, no need to check inplace ops.
1 parent a3afa8c commit c59fc14

1 file changed

Lines changed: 17 additions & 16 deletions

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‎py/emitnative.c‎

Lines changed: 17 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1825,18 +1825,20 @@ STATIC void emit_native_binary_op(emit_t *emit, mp_binary_op_t op) {
18251825
vtype_kind_t vtype_lhs = peek_vtype(emit, 1);
18261826
vtype_kind_t vtype_rhs = peek_vtype(emit, 0);
18271827
if (vtype_lhs == VTYPE_INT && vtype_rhs == VTYPE_INT) {
1828+
// for integers, inplace and normal ops are equivalent, so use just normal ops
1829+
if (MP_BINARY_OP_INPLACE_OR <= op && op <= MP_BINARY_OP_INPLACE_POWER) {
1830+
op += MP_BINARY_OP_OR - MP_BINARY_OP_INPLACE_OR;
1831+
}
1832+
18281833
#if N_X64 || N_X86
18291834
// special cases for x86 and shifting
1830-
if (op == MP_BINARY_OP_LSHIFT
1831-
|| op == MP_BINARY_OP_INPLACE_LSHIFT
1832-
|| op == MP_BINARY_OP_RSHIFT
1833-
|| op == MP_BINARY_OP_INPLACE_RSHIFT) {
1835+
if (op == MP_BINARY_OP_LSHIFT || op == MP_BINARY_OP_RSHIFT) {
18341836
#if N_X64
18351837
emit_pre_pop_reg_reg(emit, &vtype_rhs, ASM_X64_REG_RCX, &vtype_lhs, REG_RET);
18361838
#else
18371839
emit_pre_pop_reg_reg(emit, &vtype_rhs, ASM_X86_REG_ECX, &vtype_lhs, REG_RET);
18381840
#endif
1839-
if (op == MP_BINARY_OP_LSHIFT || op == MP_BINARY_OP_INPLACE_LSHIFT) {
1841+
if (op == MP_BINARY_OP_LSHIFT) {
18401842
ASM_LSL_REG(emit->as, REG_RET);
18411843
} else {
18421844
ASM_ASR_REG(emit->as, REG_RET);
@@ -1847,10 +1849,9 @@ STATIC void emit_native_binary_op(emit_t *emit, mp_binary_op_t op) {
18471849
#endif
18481850

18491851
// special cases for floor-divide and module because we dispatch to helper functions
1850-
if (op == MP_BINARY_OP_FLOOR_DIVIDE || op == MP_BINARY_OP_INPLACE_FLOOR_DIVIDE
1851-
|| op == MP_BINARY_OP_MODULO || op == MP_BINARY_OP_INPLACE_MODULO) {
1852+
if (op == MP_BINARY_OP_FLOOR_DIVIDE || op == MP_BINARY_OP_MODULO) {
18521853
emit_pre_pop_reg_reg(emit, &vtype_rhs, REG_ARG_2, &vtype_lhs, REG_ARG_1);
1853-
if (op == MP_BINARY_OP_FLOOR_DIVIDE || op == MP_BINARY_OP_INPLACE_FLOOR_DIVIDE) {
1854+
if (op == MP_BINARY_OP_FLOOR_DIVIDE) {
18541855
emit_call(emit, MP_F_SMALL_INT_FLOOR_DIVIDE);
18551856
} else {
18561857
emit_call(emit, MP_F_SMALL_INT_MODULO);
@@ -1865,29 +1866,29 @@ STATIC void emit_native_binary_op(emit_t *emit, mp_binary_op_t op) {
18651866
if (0) {
18661867
// dummy
18671868
#if !(N_X64 || N_X86)
1868-
} else if (op == MP_BINARY_OP_LSHIFT || op == MP_BINARY_OP_INPLACE_LSHIFT) {
1869+
} else if (op == MP_BINARY_OP_LSHIFT) {
18691870
ASM_LSL_REG_REG(emit->as, REG_ARG_2, reg_rhs);
18701871
emit_post_push_reg(emit, VTYPE_INT, REG_ARG_2);
1871-
} else if (op == MP_BINARY_OP_RSHIFT || op == MP_BINARY_OP_INPLACE_RSHIFT) {
1872+
} else if (op == MP_BINARY_OP_RSHIFT) {
18721873
ASM_ASR_REG_REG(emit->as, REG_ARG_2, reg_rhs);
18731874
emit_post_push_reg(emit, VTYPE_INT, REG_ARG_2);
18741875
#endif
1875-
} else if (op == MP_BINARY_OP_OR || op == MP_BINARY_OP_INPLACE_OR) {
1876+
} else if (op == MP_BINARY_OP_OR) {
18761877
ASM_OR_REG_REG(emit->as, REG_ARG_2, reg_rhs);
18771878
emit_post_push_reg(emit, VTYPE_INT, REG_ARG_2);
1878-
} else if (op == MP_BINARY_OP_XOR || op == MP_BINARY_OP_INPLACE_XOR) {
1879+
} else if (op == MP_BINARY_OP_XOR) {
18791880
ASM_XOR_REG_REG(emit->as, REG_ARG_2, reg_rhs);
18801881
emit_post_push_reg(emit, VTYPE_INT, REG_ARG_2);
1881-
} else if (op == MP_BINARY_OP_AND || op == MP_BINARY_OP_INPLACE_AND) {
1882+
} else if (op == MP_BINARY_OP_AND) {
18821883
ASM_AND_REG_REG(emit->as, REG_ARG_2, reg_rhs);
18831884
emit_post_push_reg(emit, VTYPE_INT, REG_ARG_2);
1884-
} else if (op == MP_BINARY_OP_ADD || op == MP_BINARY_OP_INPLACE_ADD) {
1885+
} else if (op == MP_BINARY_OP_ADD) {
18851886
ASM_ADD_REG_REG(emit->as, REG_ARG_2, reg_rhs);
18861887
emit_post_push_reg(emit, VTYPE_INT, REG_ARG_2);
1887-
} else if (op == MP_BINARY_OP_SUBTRACT || op == MP_BINARY_OP_INPLACE_SUBTRACT) {
1888+
} else if (op == MP_BINARY_OP_SUBTRACT) {
18881889
ASM_SUB_REG_REG(emit->as, REG_ARG_2, reg_rhs);
18891890
emit_post_push_reg(emit, VTYPE_INT, REG_ARG_2);
1890-
} else if (op == MP_BINARY_OP_MULTIPLY || op == MP_BINARY_OP_INPLACE_MULTIPLY) {
1891+
} else if (op == MP_BINARY_OP_MULTIPLY) {
18911892
ASM_MUL_REG_REG(emit->as, REG_ARG_2, reg_rhs);
18921893
emit_post_push_reg(emit, VTYPE_INT, REG_ARG_2);
18931894
} else if (MP_BINARY_OP_LESS <= op && op <= MP_BINARY_OP_NOT_EQUAL) {

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