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jeplerjepler
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_canio: Minimal implementation for SAM E5x MCUs
Tested & working: * Send standard packets * Receive standard packets (1 FIFO, no filter) Interoperation between SAM E54 Xplained running this tree and MicroPython running on STM32F405 Feather with an external transceiver was also tested. Many other aspects of a full implementation are not yet present, such as error detection and recovery.
1 parent e7a213a commit a2e1867

30 files changed

Lines changed: 2190 additions & 3 deletions

‎main.c‎

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@@ -81,6 +81,10 @@
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#include "supervisor/shared/bluetooth.h"
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#endif
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#if CIRCUITPY_CANIO
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#include "common-hal/_canio/CAN.h"
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#endif
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void do_str(const char *src, mp_parse_input_kind_t input_kind) {
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mp_lexer_t *lex = mp_lexer_new_from_str_len(MP_QSTR__lt_stdin_gt_, src, strlen(src), 0);
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if (lex == NULL) {
@@ -226,6 +230,10 @@ void cleanup_after_vm(supervisor_allocation* heap) {
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free_memory(heap);
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supervisor_move_memory();
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#ifdef CIRCUITPY_CANIO
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common_hal_canio_reset();
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#endif
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reset_port();
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#if CIRCUITPY_BOARD
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reset_board_busses();

‎ports/atmel-samd/Makefile‎

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@@ -393,6 +393,10 @@ SRC_QSTR += $(HEADER_BUILD)/sdiodata.h
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$(HEADER_BUILD)/sdiodata.h: tools/mksdiodata.py | $(HEADER_BUILD)
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$(Q)$(PYTHON3) $< > $@
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SRC_QSTR += $(HEADER_BUILD)/candata.h
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$(HEADER_BUILD)/candata.h: tools/mkcandata.py | $(HEADER_BUILD)
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$(Q)$(PYTHON3) $< > $@
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SRC_QSTR += $(SRC_C) $(SRC_SUPERVISOR) $(SRC_COMMON_HAL_EXPANDED) $(SRC_SHARED_MODULE_EXPANDED)
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# Sources that only hold QSTRs after pre-processing.
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SRC_QSTR_PREPROCESSOR += peripherals/samd/$(PERIPHERALS_CHIP_FAMILY)/clocks.c

‎ports/atmel-samd/asf4_conf/same54/peripheral_clk_config.h‎

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@@ -1165,6 +1165,88 @@
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#define CONF_SDHC1_SLOW_FREQUENCY 12000000
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#endif
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// <h> CAN Clock Settings
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// <y> CAN Clock source
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
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// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
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// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
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// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
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// <i> Select the clock source for CAN.
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// <id> sdhc_gclk_selection
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#ifndef CONF_GCLK_CAN0_SRC
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#define CONF_GCLK_CAN0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#endif
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/**
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* \def CAN FREQUENCY
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* \brief CAN's Clock frequency
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*/
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#ifndef CONF_CAN0_FREQUENCY
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#define CONF_CAN0_FREQUENCY 120000000
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#endif
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// <h> CAN Clock Settings
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// <y> CAN Clock source
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
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// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
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// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
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// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
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// <i> Select the clock source for CAN.
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// <id> sdhc_gclk_selection
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#ifndef CONF_GCLK_CAN1_SRC
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#define CONF_GCLK_CAN1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#endif
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/**
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* \def CAN FREQUENCY
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* \brief CAN's Clock frequency
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*/
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#ifndef CONF_CAN1_FREQUENCY
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#define CONF_CAN1_FREQUENCY 120000000
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#endif
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// <<< end of configuration section >>>
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#endif // PERIPHERAL_CLK_CONFIG_H

‎ports/atmel-samd/boards/common.template.ld‎

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@@ -51,6 +51,7 @@ SECTIONS
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{
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. = ALIGN(4);
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_srelocate = .; /* create a global symbol at data start; used by startup code in order to initialize the .data section in RAM */
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. = ALIGN(4);
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*(.ramfunc)
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*(.ramfunc*)
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*(.data) /* .data sections */
@@ -61,11 +62,15 @@ SECTIONS
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} >RAM
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/* Uninitialized data section */
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.bss :
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.bss (NOLOAD) :
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{
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. = ALIGN(4);
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_sbss = .;
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_szero = .; /* define a global symbol at bss start; used by startup code */
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/* Data accessed by the CAN peripheral must be in the first 64kB RAM */
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_scanram = .;
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*(.canram)
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_ecanram = .;
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*(.bss)
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*(.bss*)
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*(COMMON)

‎ports/atmel-samd/boards/same54_xplained/mpconfigboard.mk‎

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@@ -12,3 +12,4 @@ EXTERNAL_FLASH_DEVICES = "N25Q256A"
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LONGINT_IMPL = MPZ
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CIRCUITPY_SDIOIO = 1
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CIRCUITPY_CANIO = 1

‎ports/atmel-samd/boards/same54_xplained/pins.c‎

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@@ -48,8 +48,9 @@ STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
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{ MP_OBJ_NEW_QSTR(MP_QSTR_QT), MP_ROM_PTR(&pin_PA16) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_CANRX), MP_ROM_PTR(&pin_PB12) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_CANTX), MP_ROM_PTR(&pin_PB13) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_CAN_RX), MP_ROM_PTR(&pin_PB13) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_CAN_TX), MP_ROM_PTR(&pin_PB12) },
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{ MP_OBJ_NEW_QSTR(MP_QSTR_CAN_STANDBY), MP_ROM_PTR(&pin_PC13) },
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// EXT1 header
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{ MP_OBJ_NEW_QSTR(MP_QSTR_PB04), MP_ROM_PTR(&pin_PB04) },

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