Skip to content

Commit a2b18b7

Browse files
committed
Fix loops and comma style.
1 parent eb2b418 commit a2b18b7

3 files changed

Lines changed: 12 additions & 12 deletions

File tree

ports/atmel-samd/common-hal/pulseio/PWMOut.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -156,7 +156,7 @@ void common_hal_pulseio_pwmout_construct(pulseio_pwmout_obj_t* self,
156156
direction = 1;
157157
start = 0;
158158
}
159-
for (uint8_t i = start; i >= 0 && i < NUM_TIMERS_PER_PIN && timer == NULL; i += direction) {
159+
for (int8_t i = start; i >= 0 && i < NUM_TIMERS_PER_PIN && timer == NULL; i += direction) {
160160
const pin_timer_t* t = &pin->timer[i];
161161
if ((!t->is_tc && t->index >= TCC_INST_NUM) ||
162162
(t->is_tc && t->index >= TC_INST_NUM)) {

ports/atmel-samd/common-hal/pulseio/PulseOut.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -98,7 +98,7 @@ void common_hal_pulseio_pulseout_construct(pulseio_pulseout_obj_t* self,
9898
if (refcount == 0) {
9999
// Find a spare timer.
100100
Tc *tc = NULL;
101-
uint8_t index = TC_INST_NUM - 1;
101+
int8_t index = TC_INST_NUM - 1;
102102
for (; index >= 0; index--) {
103103
if (tc_insts[index]->COUNT16.CTRLA.bit.ENABLE == 0) {
104104
tc = tc_insts[index];

ports/atmel-samd/timers.c

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -46,10 +46,10 @@ const uint8_t tc_gclk_ids[TC_INST_NUM] = {TC3_GCLK_ID,
4646
TC4_GCLK_ID,
4747
TC5_GCLK_ID,
4848
#ifdef TC6_GCLK_ID
49-
, TC6_GCLK_ID
49+
TC6_GCLK_ID,
5050
#endif
5151
#ifdef TC7_GCLK_ID
52-
, TC7_GCLK_ID
52+
TC7_GCLK_ID,
5353
#endif
5454
};
5555
const uint8_t tcc_gclk_ids[3] = {TCC0_GCLK_ID, TCC1_GCLK_ID, TCC2_GCLK_ID};
@@ -59,18 +59,18 @@ const uint8_t tcc_cc_num[5] = {6, 4, 3, 2, 2};
5959
const uint8_t tc_gclk_ids[TC_INST_NUM] = {TC0_GCLK_ID,
6060
TC1_GCLK_ID,
6161
TC2_GCLK_ID,
62-
TC3_GCLK_ID
62+
TC3_GCLK_ID,
6363
#ifdef TC4_GCLK_ID
64-
, TC4_GCLK_ID
64+
TC4_GCLK_ID,
6565
#endif
6666
#ifdef TC5_GCLK_ID
67-
, TC5_GCLK_ID
67+
TC5_GCLK_ID,
6868
#endif
6969
#ifdef TC6_GCLK_ID
70-
, TC6_GCLK_ID
70+
TC6_GCLK_ID,
7171
#endif
7272
#ifdef TC7_GCLK_ID
73-
, TC7_GCLK_ID
73+
TC7_GCLK_ID,
7474
#endif
7575
};
7676
const uint8_t tcc_gclk_ids[5] = {TCC0_GCLK_ID, TCC1_GCLK_ID, TCC2_GCLK_ID, TCC3_GCLK_ID,
@@ -91,12 +91,12 @@ IRQn_Type const tc_irq[TC_INST_NUM] = {
9191
#endif
9292
TC3_IRQn,
9393
TC4_IRQn,
94-
TC5_IRQn
94+
TC5_IRQn,
9595
#ifdef TC6
96-
, TC6_IRQn
96+
TC6_IRQn,
9797
#endif
9898
#ifdef TC7
99-
, TC7_IRQn
99+
TC7_IRQn,
100100
#endif
101101
};
102102

0 commit comments

Comments
 (0)