py/asmxtensa.h: Explicitly cast args to 32-bits so left-shift is legal.

dpgeorge · dpgeorge · commit a25aa2bcc334 · 2017-02-08T10:48:51.000+11:00
For archs that have 16-bit pointers, the asmxtensa.h file can give compiler
warnings about left-shift being greater than the width of the type (due to
the inline functions in this header file).  Explicitly casting the
constants to uint32_t stops these warnings.
diff --git a/py/asmxtensa.h b/py/asmxtensa.h
@@ -73,19 +73,19 @@
 
 // macros for encoding instructions (little endian versions)
 #define ASM_XTENSA_ENCODE_RRR(op0, op1, op2, r, s, t) \
-    (((op2) << 20) | ((op1) << 16) | ((r) << 12) | ((s) << 8) | ((t) << 4) | (op0))
+    ((((uint32_t)op2) << 20) | (((uint32_t)op1) << 16) | ((r) << 12) | ((s) << 8) | ((t) << 4) | (op0))
 #define ASM_XTENSA_ENCODE_RRI4(op0, op1, r, s, t, imm4) \
     (((imm4) << 20) | ((op1) << 16) | ((r) << 12) | ((s) << 8) | ((t) << 4) | (op0))
 #define ASM_XTENSA_ENCODE_RRI8(op0, r, s, t, imm8) \
-    (((imm8) << 16) | ((r) << 12) | ((s) << 8) | ((t) << 4) | (op0))
+    ((((uint32_t)imm8) << 16) | ((r) << 12) | ((s) << 8) | ((t) << 4) | (op0))
 #define ASM_XTENSA_ENCODE_RI16(op0, t, imm16) \
     (((imm16) << 8) | ((t) << 4) | (op0))
 #define ASM_XTENSA_ENCODE_RSR(op0, op1, op2, rs, t) \
     (((op2) << 20) | ((op1) << 16) | ((rs) << 8) | ((t) << 4) | (op0))
 #define ASM_XTENSA_ENCODE_CALL(op0, n, offset) \
     (((offset) << 6) | ((n) << 4) | (op0))
 #define ASM_XTENSA_ENCODE_CALLX(op0, op1, op2, r, s, m, n) \
-    (((op2) << 20) | ((op1) << 16) | ((r) << 12) | ((s) << 8) | ((m) << 6) | ((n) << 4) | (op0))
+    ((((uint32_t)op2) << 20) | (((uint32_t)op1) << 16) | ((r) << 12) | ((s) << 8) | ((m) << 6) | ((n) << 4) | (op0))
 #define ASM_XTENSA_ENCODE_BRI8(op0, r, s, m, n, imm8) \
     (((imm8) << 16) | ((r) << 12) | ((s) << 8) | ((m) << 6) | ((n) << 4) | (op0))
 #define ASM_XTENSA_ENCODE_BRI12(op0, s, m, n, imm12) \
