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ravotusdpgeorge
ravotus
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dpgeorge
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stmhal: Add address parameters to openocd config files.
Also make l4 config the default for STM32L476DISC board.
1 parent 50a2966 commit 0d75b0d

4 files changed

Lines changed: 15 additions & 13 deletions

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‎stmhal/Makefile‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -296,23 +296,24 @@ else
296296
$(Q)$(DFU_UTIL) -a 0 -d $(DEVICE) -D $<
297297
endif
298298

299+
FLASH_ADDR ?= 0x08000000
299300
TEXT_ADDR ?= 0x08020000
300301

301302
deploy-stlink: $(BUILD)/firmware.dfu
302303
$(ECHO) "Writing $(BUILD)/firmware0.bin to the board via ST-LINK"
303-
$(Q)$(STFLASH) write $(BUILD)/firmware0.bin 0x08000000
304+
$(Q)$(STFLASH) write $(BUILD)/firmware0.bin $(FLASH_ADDR)
304305
$(ECHO) "Writing $(BUILD)/firmware1.bin to the board via ST-LINK"
305306
$(Q)$(STFLASH) --reset write $(BUILD)/firmware1.bin $(TEXT_ADDR)
306307

307308
deploy-openocd: $(BUILD)/firmware.dfu
308309
$(ECHO) "Writing $(BUILD)/firmware{0,1}.bin to the board via ST-LINK using OpenOCD"
309-
$(Q)$(OPENOCD) -f $(OPENOCD_CONFIG) -c "stm_flash $(BUILD)/firmware0.bin $(BUILD)/firmware1.bin"
310+
$(Q)$(OPENOCD) -f $(OPENOCD_CONFIG) -c "stm_flash $(BUILD)/firmware0.bin $(FLASH_ADDR) $(BUILD)/firmware1.bin $(TEXT_ADDR)"
310311

311312
$(BUILD)/firmware.dfu: $(BUILD)/firmware.elf
312313
$(ECHO) "Create $@"
313314
$(Q)$(OBJCOPY) -O binary -j .isr_vector $^ $(BUILD)/firmware0.bin
314315
$(Q)$(OBJCOPY) -O binary -j .text -j .data $^ $(BUILD)/firmware1.bin
315-
$(Q)$(PYTHON) $(DFU) -b 0x08000000:$(BUILD)/firmware0.bin -b $(TEXT_ADDR):$(BUILD)/firmware1.bin $@
316+
$(Q)$(PYTHON) $(DFU) -b $(FLASH_ADDR):$(BUILD)/firmware0.bin -b $(TEXT_ADDR):$(BUILD)/firmware1.bin $@
316317

317318
$(BUILD)/firmware.hex: $(BUILD)/firmware.elf
318319
$(ECHO) "Create $@"

‎stmhal/boards/STM32L476DISC/mpconfigboard.mk‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,3 +3,4 @@ CMSIS_MCU = STM32L476xx
33
AF_FILE = boards/stm32l476_af.csv
44
LD_FILE = boards/stm32l476xg.ld
55
TEXT_ADDR = 0x08004000
6+
OPENOCD_CONFIG = boards/openocd_stm32l4.cfg

‎stmhal/boards/openocd_stm32f4.cfg‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -17,17 +17,17 @@ source [find target/stm32f4x.cfg]
1717
reset_config srst_only
1818
init
1919

20-
proc stm_flash { BIN0 BIN1 } {
20+
proc stm_flash { BIN0 ADDR0 BIN1 ADDR1 } {
2121
reset halt
2222
sleep 100
2323
wait_halt 2
24-
flash write_image erase $BIN0 0x08000000
24+
flash write_image erase $BIN0 $ADDR0
2525
sleep 100
26-
verify_image $BIN0 0x08000000
26+
verify_image $BIN0 $ADDR0
2727
sleep 100
28-
flash write_image erase $BIN1 0x08020000
28+
flash write_image erase $BIN1 $ADDR1
2929
sleep 100
30-
verify_image $BIN1 0x08020000
30+
verify_image $BIN1 $ADDR1
3131
sleep 100
3232
reset run
3333
shutdown

‎stmhal/boards/openocd_stm32l4.cfg‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -17,17 +17,17 @@ source [find target/stm32l4x.cfg]
1717
reset_config srst_only
1818
init
1919

20-
proc stm_flash { BIN0 BIN1 } {
20+
proc stm_flash { BIN0 ADDR0 BIN1 ADDR1 } {
2121
reset halt
2222
sleep 100
2323
wait_halt 2
24-
flash write_image erase $BIN0 0x08000000
24+
flash write_image erase $BIN0 $ADDR0
2525
sleep 100
26-
verify_image $BIN0 0x08000000
26+
verify_image $BIN0 $ADDR0
2727
sleep 100
28-
flash write_image erase $BIN1 0x08004000
28+
flash write_image erase $BIN1 $ADDR1
2929
sleep 100
30-
verify_image $BIN1 0x08004000
30+
verify_image $BIN1 $ADDR1
3131
sleep 100
3232
reset run
3333
shutdown

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