3131
3232 / * reconfigure L2 cache aux control reg * /
3333 ldr r0 , = 0xC0 | / * tag RAM * / \
34- 0x4 | / * data RAM * / \
35- 1 << 24 | / * disable write allocate delay * / \
36- 1 << 23 | / * disable write allocate combine * / \
37- 1 << 22 / * disable write allocate * /
34+ 0x4 | / * data RAM * / \
35+ 1 << 24 | / * disable write allocate delay * / \
36+ 1 << 23 | / * disable write allocate combine * / \
37+ 1 << 22 / * disable write allocate * /
3838
3939#if defined(CONFIG_MX51)
4040 ldr r3 , [ r4 , #ROM_SI_REV ]
@@ -290,20 +290,20 @@ setup_pll_func:
290290
291291 setup_pll PLL1_BASE_ADDR , 800
292292
293- setup_pll PLL3_BASE_ADDR, 400
293+ setup_pll PLL3_BASE_ADDR, 400
294294
295- /* Switch peripheral to PLL3 * /
296- ldr r0, =CCM_BASE_ADDR
297- ldr r1, = 0x00015154
298- str r1 , [ r0 , #CLKCTL_CBCMR ]
299- ldr r1, = 0x02898945
300- str r1 , [ r0 , #CLKCTL_CBCDR ]
301- /* make sure change is effective * /
295+ /* Switch peripheral to PLL3 * /
296+ ldr r0, =CCM_BASE_ADDR
297+ ldr r1, = 0x00015154
298+ str r1 , [ r0 , #CLKCTL_CBCMR ]
299+ ldr r1, = 0x02898945
300+ str r1 , [ r0 , #CLKCTL_CBCDR ]
301+ /* make sure change is effective * /
3023021 : ldr r1 , [ r0 , #CLKCTL_CDHIPR ]
303- cmp r1 , # 0x0
304- bne 1b
303+ cmp r1 , # 0x0
304+ bne 1b
305305
306- setup_pll PLL2_BASE_ADDR, 400
306+ setup_pll PLL2_BASE_ADDR, 400
307307
308308 / * Switch peripheral to PLL2 * /
309309 ldr r0 , =CCM_BASE_ADDR
@@ -324,7 +324,7 @@ setup_pll_func:
324324 cmp r1 , # 0x0
325325 bne 1b
326326
327- setup_pll PLL3_BASE_ADDR, 216
327+ setup_pll PLL3_BASE_ADDR, 216
328328
329329 setup_pll PLL4_BASE_ADDR , 455
330330
@@ -358,13 +358,13 @@ setup_pll_func:
358358 str r1 , [ r0 , #CLKCTL_CCGR6 ]
359359 str r1 , [ r0 , #CLKCTL_CCGR7 ]
360360
361- mov r1 , # 0x00000
362- str r1 , [ r0 , #CLKCTL_CCDR ]
361+ mov r1 , # 0x00000
362+ str r1 , [ r0 , #CLKCTL_CCDR ]
363363
364- /* for cko - for ARM div by 8 * /
365- mov r1 , # 0x000A0000
366- add r1 , r1 , # 0x00000F0
367- str r1 , [ r0 , #CLKCTL_CCOSR ]
364+ /* for cko - for ARM div by 8 * /
365+ mov r1 , # 0x000A0000
366+ add r1 , r1 , # 0x00000F0
367+ str r1 , [ r0 , #CLKCTL_CCOSR ]
368368
369369#endif / * CONFIG_MX53 * /
370370.endm
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