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| 1 | +/* |
| 2 | + * (C) Copyright 2001 |
| 3 | + * Stäubli Faverges - <www.staubli.com> |
| 4 | + * Pierre AUBERT p.aubert@staubli.com |
| 5 | + * U-Boot port on RPXClassic LF (CLLF_BW31) board |
| 6 | + * |
| 7 | + * (C) Copyright 2000 |
| 8 | + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 9 | + * |
| 10 | + * See file CREDITS for list of people who contributed to this |
| 11 | + * project. |
| 12 | + * |
| 13 | + * This program is free software; you can redistribute it and/or |
| 14 | + * modify it under the terms of the GNU General Public License as |
| 15 | + * published by the Free Software Foundation; either version 2 of |
| 16 | + * the License, or (at your option) any later version. |
| 17 | + * |
| 18 | + * This program is distributed in the hope that it will be useful, |
| 19 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 21 | + * GNU General Public License for more details. |
| 22 | + * |
| 23 | + * You should have received a copy of the GNU General Public License |
| 24 | + * along with this program; if not, write to the Free Software |
| 25 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 26 | + * MA 02111-1307 USA |
| 27 | + */ |
| 28 | + |
| 29 | +#include <common.h> |
| 30 | +#include <i2c.h> |
| 31 | +#include <config.h> |
| 32 | +#include <mpc8xx.h> |
| 33 | + |
| 34 | +/* ------------------------------------------------------------------------- */ |
| 35 | + |
| 36 | +static long int dram_size (long int, long int *, long int); |
| 37 | +static unsigned char aschex_to_byte (unsigned char *cp); |
| 38 | + |
| 39 | +/* ------------------------------------------------------------------------- */ |
| 40 | + |
| 41 | +#define _NOT_USED_ 0xFFFFCC25 |
| 42 | + |
| 43 | +const uint sdram_table[] = |
| 44 | +{ |
| 45 | + /* |
| 46 | + * Single Read. (Offset 00h in UPMA RAM) |
| 47 | + */ |
| 48 | + 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08, |
| 49 | + 0x3FBFCC27, /* last */ |
| 50 | + _NOT_USED_, _NOT_USED_, _NOT_USED_, |
| 51 | + |
| 52 | + /* |
| 53 | + * Burst Read. (Offset 08h in UPMA RAM) |
| 54 | + */ |
| 55 | + 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88, |
| 56 | + 0x3FBFCC27, /* last */ |
| 57 | + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
| 58 | + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
| 59 | + _NOT_USED_, _NOT_USED_, _NOT_USED_, |
| 60 | + |
| 61 | + /* |
| 62 | + * Single Write. (Offset 18h in UPMA RAM) |
| 63 | + */ |
| 64 | + 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00, |
| 65 | + 0x3FFFCC27, /* last */ |
| 66 | + _NOT_USED_, _NOT_USED_, _NOT_USED_, |
| 67 | + |
| 68 | + /* |
| 69 | + * Burst Write. (Offset 20h in UPMA RAM) |
| 70 | + */ |
| 71 | + 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C, |
| 72 | + 0x0CFFCC00, 0x33FFCC27, /* last */ |
| 73 | + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
| 74 | + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
| 75 | + _NOT_USED_, _NOT_USED_, |
| 76 | + |
| 77 | + /* |
| 78 | + * Refresh. (Offset 30h in UPMA RAM) |
| 79 | + */ |
| 80 | + 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24, |
| 81 | + 0x3FFFCC27, /* last */ |
| 82 | + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
| 83 | + _NOT_USED_, _NOT_USED_, _NOT_USED_, |
| 84 | + |
| 85 | + /* |
| 86 | + * Exception. (Offset 3Ch in UPMA RAM) |
| 87 | + */ |
| 88 | + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ |
| 89 | +}; |
| 90 | + |
| 91 | +/* ------------------------------------------------------------------------- */ |
| 92 | + |
| 93 | + |
| 94 | +/* |
| 95 | + * Check Board Identity: |
| 96 | + */ |
| 97 | + |
| 98 | +int checkboard (void) |
| 99 | +{ |
| 100 | + puts ("Board: RPXClassic\n"); |
| 101 | + return (0); |
| 102 | +} |
| 103 | + |
| 104 | +/*----------------------------------------------------------------------------- |
| 105 | + * board_get_enetaddr -- Read the MAC Address in the I2C EEPROM |
| 106 | + *----------------------------------------------------------------------------- |
| 107 | + */ |
| 108 | +void board_get_enetaddr (uchar * enet) |
| 109 | +{ |
| 110 | + int i; |
| 111 | + char buff[256], *cp; |
| 112 | + |
| 113 | + /* Initialize I2C */ |
| 114 | + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); |
| 115 | + |
| 116 | + /* Read 256 bytes in EEPROM */ |
| 117 | + i2c_read (0x54, 0, 1, buff, 128); |
| 118 | + i2c_read (0x54, 128, 1, buff + 128, 128); |
| 119 | + |
| 120 | + /* Retrieve MAC address in buffer (key EA) */ |
| 121 | + for (cp = buff;;) { |
| 122 | + if (cp[0] == 'E' && cp[1] == 'A') { |
| 123 | + cp += 3; |
| 124 | + /* Read MAC address */ |
| 125 | + for (i = 0; i < 6; i++, cp += 2) { |
| 126 | + enet[i] = aschex_to_byte (cp); |
| 127 | + } |
| 128 | + } |
| 129 | + /* Scan to the end of the record */ |
| 130 | + while ((*cp != '\n') && (*cp != 0xff)) { |
| 131 | + cp++; |
| 132 | + } |
| 133 | + /* If the next character is a \n, 0 or ff, we are done. */ |
| 134 | + cp++; |
| 135 | + if ((*cp == '\n') || (*cp == 0) || (*cp == 0xff)) |
| 136 | + break; |
| 137 | + } |
| 138 | + |
| 139 | +#ifdef CONFIG_FEC_ENET |
| 140 | + /* The MAC address is the same as normal ethernet except the 3rd byte */ |
| 141 | + /* (See the E.P. Planet Core Overview manual */ |
| 142 | + enet[3] |= 0x80; |
| 143 | + |
| 144 | + /* Validate the fast ethernet tranceiver */ |
| 145 | + *((volatile uchar *) BCSR2) &= ~BCSR2_MIICTL; |
| 146 | + *((volatile uchar *) BCSR2) &= ~BCSR2_MIIPWRDWN; |
| 147 | + *((volatile uchar *) BCSR2) |= BCSR2_MIIRST; |
| 148 | + *((volatile uchar *) BCSR2) |= BCSR2_MIIPWRDWN; |
| 149 | +#endif |
| 150 | + |
| 151 | + printf ("MAC address = %02x:%02x:%02x:%02x:%02x:%02x\n", |
| 152 | + enet[0], enet[1], enet[2], enet[3], enet[4], enet[5]); |
| 153 | + |
| 154 | +} |
| 155 | + |
| 156 | +void rpxclassic_init (void) |
| 157 | +{ |
| 158 | + /* Enable NVRAM */ |
| 159 | + *((uchar *) BCSR0) |= BCSR0_ENNVRAM; |
| 160 | + |
| 161 | +} |
| 162 | + |
| 163 | +/* ------------------------------------------------------------------------- */ |
| 164 | + |
| 165 | +long int initdram (int board_type) |
| 166 | +{ |
| 167 | + volatile immap_t *immap = (immap_t *) CFG_IMMR; |
| 168 | + volatile memctl8xx_t *memctl = &immap->im_memctl; |
| 169 | + long int size10; |
| 170 | + |
| 171 | + upmconfig (UPMA, (uint *) sdram_table, |
| 172 | + sizeof (sdram_table) / sizeof (uint)); |
| 173 | + |
| 174 | + /* Refresh clock prescalar */ |
| 175 | + memctl->memc_mptpr = CFG_MPTPR; |
| 176 | + |
| 177 | + memctl->memc_mar = 0x00000000; |
| 178 | + |
| 179 | + /* Map controller banks 1 to the SDRAM bank */ |
| 180 | + memctl->memc_or1 = CFG_OR1_PRELIM; |
| 181 | + memctl->memc_br1 = CFG_BR1_PRELIM; |
| 182 | + |
| 183 | + memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ |
| 184 | + |
| 185 | + udelay (200); |
| 186 | + |
| 187 | + /* perform SDRAM initializsation sequence */ |
| 188 | + |
| 189 | + memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */ |
| 190 | + udelay (1); |
| 191 | + |
| 192 | + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ |
| 193 | + |
| 194 | + udelay (1000); |
| 195 | + |
| 196 | + /* Check Bank 0 Memory Size |
| 197 | + * try 10 column mode |
| 198 | + */ |
| 199 | + |
| 200 | + size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE_PRELIM, |
| 201 | + SDRAM_MAX_SIZE); |
| 202 | + |
| 203 | + return (size10); |
| 204 | +} |
| 205 | + |
| 206 | +/* ------------------------------------------------------------------------- */ |
| 207 | + |
| 208 | +/* |
| 209 | + * Check memory range for valid RAM. A simple memory test determines |
| 210 | + * the actually available RAM size between addresses `base' and |
| 211 | + * `base + maxsize'. Some (not all) hardware errors are detected: |
| 212 | + * - short between address lines |
| 213 | + * - short between data lines |
| 214 | + */ |
| 215 | + |
| 216 | +static long int dram_size (long int mamr_value, long int *base, long int maxsize) |
| 217 | +{ |
| 218 | + volatile immap_t *immap = (immap_t *) CFG_IMMR; |
| 219 | + volatile memctl8xx_t *memctl = &immap->im_memctl; |
| 220 | + volatile long int *addr; |
| 221 | + ulong cnt, val; |
| 222 | + ulong save[32]; /* to make test non-destructive */ |
| 223 | + unsigned char i = 0; |
| 224 | + |
| 225 | + memctl->memc_mamr = mamr_value; |
| 226 | + |
| 227 | + for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { |
| 228 | + addr = base + cnt; /* pointer arith! */ |
| 229 | + |
| 230 | + save[i++] = *addr; |
| 231 | + *addr = ~cnt; |
| 232 | + } |
| 233 | + |
| 234 | + /* write 0 to base address */ |
| 235 | + addr = base; |
| 236 | + save[i] = *addr; |
| 237 | + *addr = 0; |
| 238 | + |
| 239 | + /* check at base address */ |
| 240 | + if ((val = *addr) != 0) { |
| 241 | + *addr = save[i]; |
| 242 | + return (0); |
| 243 | + } |
| 244 | + |
| 245 | + for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { |
| 246 | + addr = base + cnt; /* pointer arith! */ |
| 247 | + |
| 248 | + val = *addr; |
| 249 | + *addr = save[--i]; |
| 250 | + |
| 251 | + if (val != (~cnt)) { |
| 252 | + return (cnt * sizeof (long)); |
| 253 | + } |
| 254 | + } |
| 255 | + return (maxsize); |
| 256 | +} |
| 257 | +static unsigned char aschex_to_byte (unsigned char *cp) |
| 258 | +{ |
| 259 | + u_char byte, c; |
| 260 | + |
| 261 | + c = *cp++; |
| 262 | + |
| 263 | + if ((c >= 'A') && (c <= 'F')) { |
| 264 | + c -= 'A'; |
| 265 | + c += 10; |
| 266 | + } else if ((c >= 'a') && (c <= 'f')) { |
| 267 | + c -= 'a'; |
| 268 | + c += 10; |
| 269 | + } else { |
| 270 | + c -= '0'; |
| 271 | + } |
| 272 | + |
| 273 | + byte = c * 16; |
| 274 | + |
| 275 | + c = *cp; |
| 276 | + |
| 277 | + if ((c >= 'A') && (c <= 'F')) { |
| 278 | + c -= 'A'; |
| 279 | + c += 10; |
| 280 | + } else if ((c >= 'a') && (c <= 'f')) { |
| 281 | + c -= 'a'; |
| 282 | + c += 10; |
| 283 | + } else { |
| 284 | + c -= '0'; |
| 285 | + } |
| 286 | + |
| 287 | + byte += c; |
| 288 | + |
| 289 | + return (byte); |
| 290 | +} |
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