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Merge patch series "SMBIOS improvements"
Raymond Mao <raymond.mao@linaro.org> says: Motivations for changes: Current SMBIOS library and command-line tool is not fully matching with the requirements: 1. Missing support for other mandatory types (u-boot#7, u-boot#9, u-boot#16, u-boot#17, u-boot#19). 2. Only a few platforms support SMBIOS node from the device tree. 3. Values of some fields are hardcoded in the library other than fetching from the device hardware. 4. Embedded data with dynamic length is not supported (E.g. Contained Object Handles in Type #2 and Contained Elements in Type #3) Changes: 1. Refactor the SMBIOS library and command-line tool to better align with the SMBIOS spec. 2. Create an arch-specific driver for all aarch64-based platforms to fetch SMBIOS private data from the device hardware (processor and cache). 3. Create a sysinfo driver to poppulate platform SMBIOS private data. 4. Add generic SMBIOS DTS file for arm64 platforms for those common strings and values which cannot be retrieved from the system registers. Vendors can create their own SMBIOS node using this as an example. For those boards without SMBIOS nodes, this DTS file can be included to have a generic SMBIOS information of the system. 5. Add support for Type u-boot#7 (Cache Information) and link its handles to Type #4. 6. To minimize size-growth for those platforms which have not sufficient ROM spaces or the platforms which don't need detailed SMBIOS information, new added fields are only being built when kconfig GENERATE_SMBIOS_TABLE_VERBOSE is selected. Once this patch is acceptted, subsequent patch sets will add other missing types (u-boot#9, u-boot#16, u-boot#17, u-boot#19). Tests: To test this with QEMU arm64, please follow the guide on dt_qemu.rst to get a merged DT to run with. ``` qemu-system-aarch64 -machine virt -machine dumpdtb=qemu.dtb cat <(dtc -I dtb qemu.dtb) <(dtc -I dtb ./dts/dt.dtb | grep -v /dts-v1/) \ | dtc - -o merged.dtb qemu-system-aarch64 -machine virt -nographic -bios u-boot.bin \ -dtb merged.dtb ``` Link: https://lore.kernel.org/r/20241206225438.13866-1-raymond.mao@linaro.org
2 parents e17be5a + 0af16b3 commit 079214e

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‎arch/arm/cpu/armv8/Makefile‎

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@@ -46,3 +46,5 @@ obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/
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obj-$(CONFIG_XEN) += xen/
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obj-$(CONFIG_ARMV8_CE_SHA1) += sha1_ce_glue.o sha1_ce_core.o
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obj-$(CONFIG_ARMV8_CE_SHA256) += sha256_ce_glue.o sha256_ce_core.o
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obj-$(CONFIG_SYSINFO_SMBIOS) += sysinfo.o

‎arch/arm/cpu/armv8/sysinfo.c‎

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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2024 Linaro Limited
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* Author: Raymond Mao <raymond.mao@linaro.org>
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*/
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#include <dm.h>
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#include <smbios_plat.h>
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#include <stdio.h>
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#include <sysinfo.h>
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union ccsidr_el1 {
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struct {
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u64 linesize:3;
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u64 associativity:10;
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u64 numsets:15;
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u64 unknown:4;
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u64 reserved:32;
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} no_ccidx;
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struct {
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u64 linesize:3;
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u64 associativity:21;
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u64 reserved1:8;
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u64 numsets:24;
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u64 reserved2:8;
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} ccidx_aarch64;
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struct {
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u64 linesize:3;
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u64 associativity:21;
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u64 reserved:8;
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u64 unallocated:32;
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} ccidx_aarch32;
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u64 data;
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};
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union midr_el1 {
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struct {
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u64 revision:4;
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u64 partnum:12;
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u64 architecture:4;
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u64 variant:4;
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u64 implementer:8;
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u64 reserved:32;
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} fields;
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u64 data;
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};
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enum {
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CACHE_NONE,
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CACHE_INST_ONLY,
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CACHE_DATA_ONLY,
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CACHE_INST_WITH_DATA,
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CACHE_UNIFIED,
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};
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enum {
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CACHE_ASSOC_DIRECT_MAPPED = 1,
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CACHE_ASSOC_2WAY = 2,
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CACHE_ASSOC_4WAY = 4,
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CACHE_ASSOC_8WAY = 8,
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CACHE_ASSOC_16WAY = 16,
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CACHE_ASSOC_12WAY = 12,
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CACHE_ASSOC_24WAY = 24,
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CACHE_ASSOC_32WAY = 32,
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CACHE_ASSOC_48WAY = 48,
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CACHE_ASSOC_64WAY = 64,
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CACHE_ASSOC_20WAY = 20,
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};
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enum {
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VENDOR_RESERVED = 0,
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VENDOR_ARM = 0x41,
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VENDOR_BROADCOM = 0x42,
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VENDOR_CAVIUM = 0x43,
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VENDOR_DEC = 0x44,
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VENDOR_FUJITSU = 0x46,
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VENDOR_INFINEON = 0x49,
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VENDOR_FREESCALE = 0x4d,
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VENDOR_NVIDIA = 0x4e,
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VENDOR_AMCC = 0x50,
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VENDOR_QUALCOMM = 0x51,
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VENDOR_MARVELL = 0x56,
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VENDOR_INTEL = 0x69,
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VENDOR_AMPERE = 0xc0,
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};
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/*
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* TODO:
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* To support ARMv8.3, we need to read "CCIDX, bits [23:20]" from
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* ID_AA64MMFR2_EL1 to get the format of CCSIDR_EL1:
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*
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* 0b0000 - 32-bit format implemented for all levels of the CCSIDR_EL1.
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* 0b0001 - 64-bit format implemented for all levels of the CCSIDR_EL1.
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*
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* Here we assume to use CCSIDR_EL1 in no CCIDX layout:
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* NumSets, bits [27:13]: (Number of sets in cache) - 1
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* Associativity, bits [12:3]: (Associativity of cache) - 1
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* LineSize, bits [2:0]: (Log2(Number of bytes in cache line)) - 4
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*/
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int sysinfo_get_cache_info(u8 level, struct cache_info *cinfo)
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{
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u64 clidr_el1;
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u32 csselr_el1;
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u32 num_sets;
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union ccsidr_el1 creg;
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int cache_type;
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sysinfo_cache_info_default(cinfo);
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/* Read CLIDR_EL1 */
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asm volatile("mrs %0, clidr_el1" : "=r" (clidr_el1));
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debug("CLIDR_EL1: 0x%llx\n", clidr_el1);
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cache_type = (clidr_el1 >> (3 * level)) & 0x7;
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if (cache_type == CACHE_NONE) /* level does not exist */
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return -1;
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switch (cache_type) {
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case CACHE_INST_ONLY:
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cinfo->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_INST;
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break;
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case CACHE_DATA_ONLY:
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cinfo->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_DATA;
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break;
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case CACHE_UNIFIED:
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cinfo->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_UNIFIED;
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break;
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case CACHE_INST_WITH_DATA:
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cinfo->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_OTHER;
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break;
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default:
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cinfo->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_UNKNOWN;
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break;
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}
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/* Select cache level */
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csselr_el1 = (level << 1);
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asm volatile("msr csselr_el1, %0" : : "r" (csselr_el1));
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/* Read CCSIDR_EL1 */
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asm volatile("mrs %0, ccsidr_el1" : "=r" (creg.data));
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debug("CCSIDR_EL1 (Level %d): 0x%llx\n", level + 1, creg.data);
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/* Extract cache size and associativity */
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cinfo->line_size = 1 << (creg.no_ccidx.linesize + 4);
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/* Map the associativity value */
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switch (creg.no_ccidx.associativity + 1) {
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case CACHE_ASSOC_DIRECT_MAPPED:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_DMAPPED;
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break;
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case CACHE_ASSOC_2WAY:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_2WAY;
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break;
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case CACHE_ASSOC_4WAY:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_4WAY;
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break;
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case CACHE_ASSOC_8WAY:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_8WAY;
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break;
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case CACHE_ASSOC_16WAY:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_16WAY;
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break;
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case CACHE_ASSOC_12WAY:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_12WAY;
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break;
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case CACHE_ASSOC_24WAY:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_24WAY;
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break;
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case CACHE_ASSOC_32WAY:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_32WAY;
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break;
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case CACHE_ASSOC_48WAY:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_48WAY;
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break;
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case CACHE_ASSOC_64WAY:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_64WAY;
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break;
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case CACHE_ASSOC_20WAY:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_20WAY;
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break;
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default:
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cinfo->associativity = SMBIOS_CACHE_ASSOC_UNKNOWN;
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break;
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}
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num_sets = creg.no_ccidx.numsets + 1;
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/* Size in KB */
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cinfo->max_size = (cinfo->associativity * num_sets * cinfo->line_size) /
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1024;
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debug("L%d Cache:\n", level + 1);
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debug("Number of bytes in cache line:%u\n", cinfo->line_size);
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debug("Associativity of cache:%u\n", cinfo->associativity);
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debug("Number of sets in cache:%u\n", num_sets);
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debug("Cache size in KB:%u\n", cinfo->max_size);
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cinfo->inst_size = cinfo->max_size;
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/*
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* Below fields with common values are placed under DT smbios node
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* socket-design, config
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* Other fields are typically specific to the implementation of the ARM
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* processor by the silicon vendor:
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* supp_sram_type, curr_sram_type, speed, err_corr_type
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*/
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return 0;
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}
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int sysinfo_get_processor_info(struct processor_info *pinfo)
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{
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u64 mpidr, core_count;
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union midr_el1 midr;
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/* Read the MIDR_EL1 register */
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asm volatile("mrs %0, MIDR_EL1" : "=r"(midr.data));
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/* Read the MPIDR_EL1 register */
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asm volatile("mrs %0, MPIDR_EL1" : "=r"(mpidr));
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debug("MIDR: 0x%016llx\n", midr.data);
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debug("MPIDR: 0x%016llx\n", mpidr);
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debug("CPU Implementer: 0x%02x\n", midr.fields.implementer);
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switch (midr.fields.implementer) {
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case VENDOR_ARM:
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pinfo->manufacturer = "ARM Limited";
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break;
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case VENDOR_BROADCOM:
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pinfo->manufacturer = "Broadcom Corporation";
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break;
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case VENDOR_CAVIUM:
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pinfo->manufacturer = "Cavium Inc";
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break;
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case VENDOR_DEC:
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pinfo->manufacturer = "Digital Equipment Corporation";
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break;
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case VENDOR_FUJITSU:
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pinfo->manufacturer = "Fujitsu Ltd";
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break;
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case VENDOR_INFINEON:
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pinfo->manufacturer = "Infineon Technologies AG";
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break;
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case VENDOR_FREESCALE:
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pinfo->manufacturer = "Freescale Semiconductor Inc";
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break;
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case VENDOR_NVIDIA:
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pinfo->manufacturer = "NVIDIA Corporation";
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break;
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case VENDOR_AMCC:
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pinfo->manufacturer =
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"Applied Micro Circuits Corporation";
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break;
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case VENDOR_QUALCOMM:
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pinfo->manufacturer = "Qualcomm Inc";
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break;
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case VENDOR_MARVELL:
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pinfo->manufacturer = "Marvell International Ltd";
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break;
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case VENDOR_INTEL:
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pinfo->manufacturer = "Intel Corporation";
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break;
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case VENDOR_AMPERE:
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pinfo->manufacturer = "Ampere Computing";
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break;
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default:
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pinfo->manufacturer = "Unknown";
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break;
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}
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debug("CPU part number: 0x%x\n", midr.fields.partnum);
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debug("CPU revision: 0x%x\n", midr.fields.revision);
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debug("CPU architecture: 0x%x\n", midr.fields.architecture);
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debug("CPU variant: 0x%x\n", midr.fields.variant);
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/* Extract number of cores */
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core_count = (mpidr >> 0) & 0xFF;
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pinfo->core_count = core_count + 1;
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debug("CPU Core Count: %d\n", pinfo->core_count);
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pinfo->core_enabled = pinfo->core_count;
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pinfo->characteristics = SMBIOS_PROCESSOR_64BIT |
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SMBIOS_PROCESSOR_ARM64_SOCID;
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if (pinfo->core_count > 1)
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pinfo->characteristics |= SMBIOS_PROCESSOR_MULTICORE;
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/*
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* Below fields with common values are placed under DT smbios node
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* version, processor-type, processor-status, upgrade, family2,
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* socket-design, serial, asset-tag, part-number
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*/
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return 0;
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}

‎arch/arm/dts/qemu-arm64.dts‎

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77

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/dts-v1/;
99

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#if defined(CONFIG_SYSINFO_SMBIOS) && !defined(QFW_SMBIOS)
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#include "smbios_generic.dtsi"
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#endif
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/ {
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};

‎arch/arm/dts/smbios_generic.dtsi‎

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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Default SMBIOS information for Arm64 platforms
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*
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* Copyright (c) 2024 Linaro Limited
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* Author: Raymond Mao <raymond.mao@linaro.org>
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*/
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#include <config.h>
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#include <smbios_def.h>
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/ {
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smbios {
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compatible = "u-boot,sysinfo-smbios";
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smbios {
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system {
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manufacturer = CONFIG_SYS_VENDOR;
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product = CONFIG_SYS_BOARD;
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version = "";
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serial = "";
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wakeup-type = <SMBIOS_WAKEUP_TYPE_UNKNOWN>;
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sku = "";
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family = "armv8";
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};
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baseboard {
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manufacturer = CONFIG_SYS_VENDOR;
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product = CONFIG_SYS_BOARD;
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version = "";
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serial = "";
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asset-tag = "";
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chassis-location = "";
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feature-flags = <SMBIOS_BOARD_FEAT_HOST_BOARD>;
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board-type = <SMBIOS_BOARD_TYPE_MOTHERBOARD>;
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};
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chassis {
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manufacturer = CONFIG_SYS_VENDOR;
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version = "";
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serial = "";
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asset-tag = "";
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chassis-type = <SMBIOS_ENCLOSURE_DESKTOP>;
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bootup-state = <SMBIOS_STATE_SAFE>;
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power-supply-state = <SMBIOS_STATE_SAFE>;
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thermal-state = <SMBIOS_STATE_SAFE>;
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security-status = <SMBIOS_SECURITY_NONE>;
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oem-defined = <SMBIOS_ENCLOSURE_OEM_UND>;
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height = <SMBIOS_ENCLOSURE_HEIGHT_UND>;
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number-of-power-cords = <SMBIOS_POWCORD_NUM_UND>;
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};
51+
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processor {
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version = "";
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processor-type = <SMBIOS_PROCESSOR_TYPE_CENTRAL>;
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processor-status = <SMBIOS_PROCESSOR_STATUS_ENABLED>;
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upgrade = <SMBIOS_PROCESSOR_UPGRADE_NONE>;
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family = <SMBIOS_PROCESSOR_FAMILY_EXT>;
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family2 = <SMBIOS_PROCESSOR_FAMILY_ARMV8>;
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socket-design = "";
60+
serial = "";
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asset-tag = "";
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part-number = "";
63+
};
64+
65+
cache {
66+
l1-cache {
67+
socket-design = "";
68+
config = <(SMBIOS_CACHE_LEVEL_1 |
69+
SMBIOS_CACHE_ENABLED |
70+
SMBIOS_CACHE_OP_WB)>;
71+
};
72+
73+
l2-cache {
74+
socket-design = "";
75+
config = <(SMBIOS_CACHE_LEVEL_2 |
76+
SMBIOS_CACHE_ENABLED |
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SMBIOS_CACHE_OP_WB)>;
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};
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};
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};
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};
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};

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