Merge pull request #3702 from corob-msft/docs/corob/mdl-210805-7

PRMerger15 · web-flow · commit cfb20603dcbd · 2021-08-06T09:24:36.000+05:30
Markdown quality fixes 7 of N
diff --git a/docs/dotnet/interoperability-with-other-dotnet-languages-cpp-cli.md b/docs/dotnet/interoperability-with-other-dotnet-languages-cpp-cli.md
@@ -57,9 +57,7 @@ public class MainClass {
 */
 ```
 
-### Example
-
-This Visual C++ program consumes the indexer.
+This C++/CLI program consumes the indexer.
 
 ```cpp
 // consume_cs_indexers_2.cpp
@@ -75,6 +73,8 @@ int main() {
 }
 ```
 
+The example produces this output:
+
 ```Output
 Element #0 = 21
 Element #1 = 0
diff --git a/docs/dotnet/managed-types-cpp-cli.md b/docs/dotnet/managed-types-cpp-cli.md
@@ -68,8 +68,6 @@ public value struct S {
 };
 ```
 
-### Example
-
 This sample is the client:
 
 ```cpp
@@ -95,7 +93,7 @@ int main() {
 }
 ```
 
-### Output
+The example produces this output:
 
 ```Output
 S.i = 5
diff --git a/docs/dotnet/reflection-cpp-cli.md b/docs/dotnet/reflection-cpp-cli.md
@@ -222,7 +222,7 @@ Compatible classes are then instantiated with the <xref:System.Activator.CreateI
 
 Note that the <xref:System.Reflection.Assembly.Load%2A> method does not accept assembly names that include the file extension. The main function in the application trims any provided extensions, so the following code example works in either case.
 
-### Example
+### Example app
 
 The following code defines the application that accepts plug-ins. An assembly name must be provided as the first argument. This assembly should contain at least one public <xref:System.Windows.Forms.Form> derived type.
 
@@ -268,7 +268,7 @@ int main() {
 }
 ```
 
-### Example
+### Example plug-ins
 
 The following code defines three classes derived from <xref:System.Windows.Forms.Form>. When the name of the resulting assembly name is passed to the executable in the previous listing, each of these three classes will be discovered and instantiated, despite the fact that they were all unknown to the hosting application at compile time.
 
diff --git a/docs/extensions/consuming-generics-cpp-cli.md b/docs/extensions/consuming-generics-cpp-cli.md
@@ -10,14 +10,10 @@ ms.assetid: e6330ef5-e907-432e-b527-7a22f5899639
 
 Generics authored in one .NET (or UWP) language may be used in other languages. Unlike templates, a generic in a compiled assembly still remains generic. Thus, one may instantiate the generic type in a different assembly and even in a different language than the assembly in which the generic type was defined.
 
-## Example: Generic class defined in C #
-
-### Description
+## Example: Generic class defined in C&#35;
 
 This example shows a generic class defined in C#.
 
-### Code
-
 ```csharp
 // consuming_generics_from_other_NET_languages.cs
 // compile with: /target:library
@@ -74,14 +70,10 @@ public class CircularList<ItemType> {
 }
 ```
 
-## Example: Consume assembly authored in C #
-
-### Description
+## Example: Consume assembly authored in C&#35;
 
 This example consumes the assembly authored in C#.
 
-### Code
-
 ```cpp
 // consuming_generics_from_other_NET_languages_2.cpp
 // compile with: /clr
@@ -101,6 +93,8 @@ int main() {
 }
 ```
 
+The example produces this output:
+
 ```Output
 90
 80
diff --git a/docs/extensions/override-cpp-component-extensions.md b/docs/extensions/override-cpp-component-extensions.md
@@ -34,7 +34,7 @@ struct X : public I1 {
 };
 ```
 
-### Example
+### Windows Runtime example
 
 The following code example shows that **override** can be used in Windows Runtime compilations.
 
@@ -54,7 +54,7 @@ ref struct X : public I1 {
 
 Compiler option: `/ZW`
 
-### Example
+### C++/CLI example
 
 The following code example shows that **override** can be used in common language runtime compilations.
 
diff --git a/docs/intrinsics/x64-amd64-intrinsics-list.md b/docs/intrinsics/x64-amd64-intrinsics-list.md
@@ -1027,7 +1027,7 @@ The following table lists the intrinsics available on x64 processors. The Techno
 | [`_mm256_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_round_ps) | AVX \[2] | immintrin.h | `__m256 _mm256_round_ps(__m256, int);` |
 | [`_mm256_rsqrt_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_rsqrt_ps) | AVX \[2] | immintrin.h | `__m256 _mm256_rsqrt_ps(__m256);` |
 | [`_mm256_sad_epu8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sad_epu8) | AVX2 \[2] | immintrin.h | `__m256i _mm256_sad_epu8(__m256i, __m256i);` |
-| [`_mm256_set_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set_epi16) | AVX \[2] | immintrin.h | `(__m256i _mm256_set_epi16(short ` |
+| [`_mm256_set_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set_epi16) | AVX \[2] | immintrin.h | `(__m256i _mm256_set_epi16(short, short, short, short, short, short, short, short, short, short, short, short, short, short, short, short);` |
 | [`_mm256_set_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set_epi32) | AVX \[2] | immintrin.h | `__m256i _mm256_set_epi32(int, int, int, int, int, int, int, int);` |
 | [`_mm256_set_epi64x`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set_epi64x) | AVX \[2] | immintrin.h | `__m256i _mm256_set_epi64x(long long, long long, long long, long long);` |
 | [`_mm256_set_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set_epi8) | AVX \[2] | immintrin.h | `__m256i _mm256_set_epi8(char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char);` |
@@ -1039,10 +1039,10 @@ The following table lists the intrinsics available on x64 processors. The Techno
 | [`_mm256_set1_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set1_epi8) | AVX \[2] | immintrin.h | `__m256i _mm256_set1_epi8(char);` |
 | [`_mm256_set1_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set1_pd) | AVX \[2] | immintrin.h | `__m256d _mm256_set1_pd(double);` |
 | [`_mm256_set1_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set1_ps) | AVX \[2] | immintrin.h | `__m256 _mm256_set1_ps(float);` |
-| [`_mm256_setr_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_epi16) | AVX \[2] | immintrin.h | `(__m256i _mm256_setr_epi16(short ` |
+| [`_mm256_setr_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_epi16) | AVX \[2] | immintrin.h | `(__m256i _mm256_setr_epi16(short, short, short, short, short, short, short, short, short, short, short, short, short, short, short, short);` |
 | [`_mm256_setr_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_epi32) | AVX \[2] | immintrin.h | `__m256i _mm256_setr_epi32(int, int, int, int, int, int, int, int);` |
 | [`_mm256_setr_epi64x`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_epi64x) | AVX \[2] | immintrin.h | `__m256i _mm256_setr_epi64x(long long, long long, long long, long long);` |
-| [`_mm256_setr_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_epi8) | AVX \[2] | immintrin.h | `(__m256i _mm256_setr_epi8(char ` |
+| [`_mm256_setr_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_epi8) | AVX \[2] | immintrin.h | `(__m256i _mm256_setr_epi8(char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char);` |
 | [`_mm256_setr_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_pd) | AVX \[2] | immintrin.h | `__m256d _mm256_setr_pd(double, double, double, double);` |
 | [`_mm256_setr_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_ps) | AVX \[2] | immintrin.h | `__m256 _mm256_setr_ps(float, float, float, float, float, float, float, float);` |
 | [`_mm256_setzero_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setzero_pd) | AVX \[2] | immintrin.h | `__m256d _mm256_setzero_pd(void);` |
diff --git a/docs/intrinsics/x86-intrinsics-list.md b/docs/intrinsics/x86-intrinsics-list.md
@@ -1121,7 +1121,7 @@ The following table lists the intrinsics available on x86 processors. The Techno
 | [`_mm256_round_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_round_ps) | AVX \[2] | immintrin.h | `__m256 _mm256_round_ps(__m256, int);` |
 | [`_mm256_rsqrt_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_rsqrt_ps) | AVX \[2] | immintrin.h | `__m256 _mm256_rsqrt_ps(__m256);` |
 | [`_mm256_sad_epu8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_sad_epu8) | AVX2 \[2] | immintrin.h | `__m256i _mm256_sad_epu8(__m256i, __m256i);` |
-| [`_mm256_set_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set_epi16) | AVX \[2] | immintrin.h | `(__m256i _mm256_set_epi16(short ` |
+| [`_mm256_set_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set_epi16) | AVX \[2] | immintrin.h | `(__m256i _mm256_set_epi16(short, short, short, short, short, short, short, short, short, short, short, short, short, short, short, short);` |
 | [`_mm256_set_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set_epi32) | AVX \[2] | immintrin.h | `__m256i _mm256_set_epi32(int, int, int, int, int, int, int, int);` |
 | [`_mm256_set_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set_epi8) | AVX \[2] | immintrin.h | `__m256i _mm256_set_epi8(char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char);` |
 | [`_mm256_set_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set_pd) | AVX \[2] | immintrin.h | `__m256d _mm256_set_pd(double, double, double, double);` |
@@ -1131,9 +1131,9 @@ The following table lists the intrinsics available on x86 processors. The Techno
 | [`_mm256_set1_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set1_epi8) | AVX \[2] | immintrin.h | `__m256i _mm256_set1_epi8(char);` |
 | [`_mm256_set1_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set1_pd) | AVX \[2] | immintrin.h | `__m256d _mm256_set1_pd(double);` |
 | [`_mm256_set1_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_set1_ps) | AVX \[2] | immintrin.h | `__m256 _mm256_set1_ps(float);` |
-| [`_mm256_setr_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_epi16) | AVX \[2] | immintrin.h | `(__m256i _mm256_setr_epi16(short ` |
+| [`_mm256_setr_epi16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_epi16) | AVX \[2] | immintrin.h | `(__m256i _mm256_setr_epi16(short, short, short, short, short, short, short, short, short, short, short, short, short, short, short, short);` |
 | [`_mm256_setr_epi32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_epi32) | AVX \[2] | immintrin.h | `__m256i _mm256_setr_epi32(int, int, int, int, int, int, int, int);` |
-| [`_mm256_setr_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_epi8) | AVX \[2] | immintrin.h | `(__m256i _mm256_setr_epi8(char ` |
+| [`_mm256_setr_epi8`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_epi8) | AVX \[2] | immintrin.h | `(__m256i _mm256_setr_epi8(char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char, char,);` |
 | [`_mm256_setr_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_pd) | AVX \[2] | immintrin.h | `__m256d _mm256_setr_pd(double, double, double, double);` |
 | [`_mm256_setr_ps`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setr_ps) | AVX \[2] | immintrin.h | `__m256 _mm256_setr_ps(float, float, float, float, float, float, float, float);` |
 | [`_mm256_setzero_pd`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_setzero_pd) | AVX \[2] | immintrin.h | `__m256d _mm256_setzero_pd(void);` |
@@ -1271,10 +1271,10 @@ The following table lists the intrinsics available on x86 processors. The Techno
 | [`__sidt`](sidt.md) |  | intrin.h | `void __sidt(void*);` |
 | `__slwpcb` | LWP \[1] | ammintrin.h | `void *__slwpcb(void);` |
 | `_stac` | SMAP | intrin.h | `void _stac(void);` |
-| [`_storebe_i16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_storebe_i16&expand=5141) | MOVBE | immintrin.h | `void _storebe_i16(void *, short); \[3] ` |
-| [`_storebe_i32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_storebe_i32&expand=5142) | MOVBE | immintrin.h | `void _storebe_i32(void *, int); \[3] ` |
-| `_store_be_u16` | MOVBE | immintrin.h | `void _store_be_u16(void *, unsigned short); \[3] ` |
-| `_store_be_u32` | MOVBE | immintrin.h | `void _store_be_u32(void *, unsigned int); \[3] ` |
+| [`_storebe_i16`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_storebe_i16&expand=5141) | MOVBE | immintrin.h | `void _storebe_i16(void *, short);` \[3] |
+| [`_storebe_i32`](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_storebe_i32&expand=5142) | MOVBE | immintrin.h | `void _storebe_i32(void *, int);` \[3] |
+| `_store_be_u16` | MOVBE | immintrin.h | `void _store_be_u16(void *, unsigned short);` \[3] |
+| `_store_be_u32` | MOVBE | immintrin.h | `void _store_be_u32(void *, unsigned int);` \[3] |
 | `_Store_HLERelease` | HLE \[2] | immintrin.h | `void _Store_HLERelease(long volatile *, long);` |
 | `_StorePointer_HLERelease` | HLE \[2] | immintrin.h | `void _StorePointer_HLERelease(void * volatile *, void *);` |
 | [`__stosb`](stosb.md) |  | intrin.h | `void __stosb(unsigned char *, unsigned char, size_t);` |
diff --git a/docs/linux/connect-to-your-remote-linux-computer.md b/docs/linux/connect-to-your-remote-linux-computer.md
@@ -199,15 +199,12 @@ The `rsync` command is used by both MSBuild-based Linux projects and CMake proje
 
 ![Screenshot showing a Headers Error.](media/port-forwarding-headers-error.png)
 
-
 `rsync` is also used by Visual Studio's CMake support to copy source files to the remote system. If you can't enable TCP port forwarding, you can use `sftp` as your remote copy sources method. `sftp` is often slower than `rsync`, but doesn't have a dependency on TCP port forwarding. You can manage your remote copy sources method with the `remoteCopySourcesMethod` property in the [CMake Settings Editor](../build/cmakesettings-reference.md#settings-for-cmake-linux). If TCP port forwarding is disabled on your remote system, you'll see an error in the CMake output window the first time it invokes `rsync`.
 
 ![Screenshot showing an Rsync Error.](media/port-forwarding-copy-error.png)
 
-
 `gdbserver` can be used for debugging on embedded devices. If you can't enable TCP port forwarding, then you must use `gdb` for all remote debugging scenarios. `gdb` is used by default when debugging projects on a remote system.
 
-
 Visual Studio's Linux support has a dependency on TCP port forwarding. Both `rsync` and `gdbserver` are affected if TCP port forwarding is disabled on your remote system. If this dependency impacts you, vote for this [suggestion ticket](https://developercommunity2.visualstudio.com/t/shDonshshtsh-shrelysh-s/840265?space=62) on Developer Community.
 
 ## Connect to WSL
diff --git a/docs/linux/connectionmanager-reference.md b/docs/linux/connectionmanager-reference.md
@@ -48,11 +48,11 @@ The functionality of ConnectionManager.exe is also available in Visual Studio. T
   
 - **`clean`**
 
-  Deletes header cache for connections that no longer exist. 
+  Deletes header cache for connections that no longer exist.
 
 - **`list`** \[**`--properties`**]
 
-  Displays information, IDs, and properties of all stored connections. 
+  Displays information, IDs, and properties of all stored connections.
 
 - **`help`**
 
@@ -64,7 +64,7 @@ The functionality of ConnectionManager.exe is also available in Visual Studio. T
   
 - **`update`** \[*default* \| *all* \| *connection_id* \| *user\@host* \[**`--port`** *port*]] \[**`--previous`**] [**`--fingerprint`**]
 
-  Added in Visual Studio 16.10. Updates the host key fingerprint of the specified connection(s). 
+  Added in Visual Studio 16.10. Updates the host key fingerprint of the specified connection(s).
 
 ### Options
 
@@ -91,7 +91,7 @@ The functionality of ConnectionManager.exe is also available in Visual Studio. T
 - **`-n`**, **`--dry-run`**
 
   Does a dry run of the command.
- 
+
 - **`--p`**
 
   Same as **`--password`**.
@@ -102,7 +102,7 @@ The functionality of ConnectionManager.exe is also available in Visual Studio. T
   
 - **`--previous`**
 
-  Indicates that the connection(s) will be read from the previous version of connection manager, updated, and written to the new version. 
+  Indicates that the connection(s) will be read from the previous version of connection manager, updated, and written to the new version.
   
 - **`--fingerprint`**
 
