@@ -139,17 +139,21 @@ void board_early_init(void) {
139139 // CLK_SRC_HFRC, CLK_SRC_HFXO or CLK_SRC_PLL
140140 .stby_clk_src = CLK_SRC_HFRC ,
141141 .stby_clk_freq = SCALED_FREQ_RC_STDBY_76_8_MHZ ,
142- // Disable all power domains.
143- .power_domains = 0 ,
144- // Add all memories
145- .memory_blocks = SERAM_MASK | SRAM0_MASK | SRAM1_MASK | MRAM_MASK | BACKUP4K_MASK |
146- SRAM6A_MASK | SRAM6B_MASK | SRAM7_1_MASK | SRAM7_2_MASK | SRAM7_3_MASK |
147- SRAM8_MASK | SRAM9_MASK | FWRAM_MASK ,
142+ // Disable all power domains except AON.
143+ .power_domains = PD_VBAT_AON_MASK ,
144+ // Keep SERAM, MRAM and backup SRAM on.
145+ // (SRAM0 also needs to stay on because it's used for .bss.sram0 which is zerod
146+ // by the runtime before the run profile is configured.)
147+ .memory_blocks = SERAM_MASK | SRAM0_MASK | MRAM_MASK | BACKUP4K_MASK ,
148+ // Gate the clocks of IP blocks.
149+ .ip_clock_gating = 0x3ffb ,
150+ // Gate PHY power (saves 0.5uA).
148151 .phy_pwr_gating = LDO_PHY_MASK | USB_PHY_MASK | MIPI_TX_DPHY_MASK | MIPI_RX_DPHY_MASK |
149152 MIPI_PLL_DPHY_MASK ,
150153 .vdd_ioflex_3V3 = IOFLEX_LEVEL_3V3 ,
151154 .vtor_address = SCB -> VTOR ,
152155 .vtor_address_ns = SCB -> VTOR ,
156+ // Configure wake-up sources.
153157 .ewic_cfg = EWIC_RTC_A ,
154158 .wakeup_events = WE_LPRTC ,
155159 };
@@ -165,6 +169,14 @@ void board_early_init(void) {
165169}
166170
167171MP_WEAK void board_enter_stop (void ) {
172+ // Let USB_D_SEL float, so it doesn't source 30uA through the 110k resistors to GND.
173+ mp_hal_pin_input (pin_USB_D_SEL );
174+
175+ #if MICROPY_HW_ENABLE_OSPI
176+ // SPI deep power down reduces deepsleep consumption by about 10uA at 3.3V.
177+ ospi_flash_sleep ();
178+ #endif
179+
168180 // Disable NPU interrupt
169181 NVIC_DisableIRQ (NPU_IRQ_NUMBER );
170182 NVIC_ClearPendingIRQ (NPU_IRQ_NUMBER );
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