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dpgeorgedpgeorge
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drivers/nrf24l01: Update to work on newer ports, using machine, utime.
Changes made are: - Use the time module in place of the pyb module for delays. - Use spi.read/spi.write instead of spi.send/spi.receive. - Drop some non-portable parameters to spi and pin initialization. Thanks to @deshipu for the original patch.
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Lines changed: 47 additions & 29 deletions

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‎drivers/nrf24l01/nrf24l01.py‎

Lines changed: 47 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
"""
33

44
from micropython import const
5-
import pyb
5+
import utime
66

77
# nRF24L01+ registers
88
CONFIG = const(0x00)
@@ -53,22 +53,24 @@ class NRF24L01:
5353
def __init__(self, spi, cs, ce, channel=46, payload_size=16):
5454
assert payload_size <= 32
5555

56-
# init the SPI bus and pins
57-
spi.init(spi.MASTER, baudrate=4000000, polarity=0, phase=0, firstbit=spi.MSB)
58-
cs.init(cs.OUT_PP, cs.PULL_NONE)
59-
ce.init(ce.OUT_PP, ce.PULL_NONE)
56+
self.buf = bytearray(1)
6057

6158
# store the pins
6259
self.spi = spi
6360
self.cs = cs
6461
self.ce = ce
6562

63+
# init the SPI bus and pins
64+
self.init_spi(4000000)
65+
cs.init(cs.OUT, value=1)
66+
ce.init(ce.OUT, value=0)
67+
6668
# reset everything
6769
self.ce.low()
6870
self.cs.high()
6971
self.payload_size = payload_size
7072
self.pipe0_read_addr = None
71-
pyb.delay(5)
73+
utime.sleep_ms(5)
7274

7375
# set address width to 5 bytes and check for device present
7476
self.reg_write(SETUP_AW, 0b11)
@@ -98,28 +100,44 @@ def __init__(self, spi, cs, ce, channel=46, payload_size=16):
98100
self.flush_rx()
99101
self.flush_tx()
100102

103+
def init_spi(self, baudrate):
104+
try:
105+
master = self.spi.MASTER
106+
except AttributeError:
107+
self.spi.init(baudrate=baudrate, polarity=0, phase=0)
108+
else:
109+
self.spi.init(master, baudrate=baudrate, polarity=0, phase=0)
110+
101111
def reg_read(self, reg):
102112
self.cs.low()
103-
self.spi.send_recv(reg)
104-
buf = self.spi.recv(1)
113+
self.spi.readinto(self.buf, reg)
114+
self.spi.readinto(self.buf)
115+
self.cs.high()
116+
return self.buf[0]
117+
118+
def reg_write_bytes(self, reg, buf):
119+
self.cs.low()
120+
self.spi.readinto(self.buf, 0x20 | reg)
121+
self.spi.write(buf)
105122
self.cs.high()
106-
return buf[0]
123+
return self.buf[0]
107124

108-
def reg_write(self, reg, buf):
125+
def reg_write(self, reg, value):
109126
self.cs.low()
110-
status = self.spi.send_recv(0x20 | reg)[0]
111-
self.spi.send(buf)
127+
self.spi.readinto(self.buf, 0x20 | reg)
128+
ret = self.buf[0]
129+
self.spi.readinto(self.buf, value)
112130
self.cs.high()
113-
return status
131+
return ret
114132

115133
def flush_rx(self):
116134
self.cs.low()
117-
self.spi.send(FLUSH_RX)
135+
self.spi.readinto(self.buf, FLUSH_RX)
118136
self.cs.high()
119137

120138
def flush_tx(self):
121139
self.cs.low()
122-
self.spi.send(FLUSH_TX)
140+
self.spi.readinto(self.buf, FLUSH_TX)
123141
self.cs.high()
124142

125143
# power is one of POWER_x defines; speed is one of SPEED_x defines
@@ -144,8 +162,8 @@ def set_channel(self, channel):
144162
# address should be a bytes object 5 bytes long
145163
def open_tx_pipe(self, address):
146164
assert len(address) == 5
147-
self.reg_write(RX_ADDR_P0, address)
148-
self.reg_write(TX_ADDR, address)
165+
self.reg_write_bytes(RX_ADDR_P0, address)
166+
self.reg_write_bytes(TX_ADDR, address)
149167
self.reg_write(RX_PW_P0, self.payload_size)
150168

151169
# address should be a bytes object 5 bytes long
@@ -157,7 +175,7 @@ def open_rx_pipe(self, pipe_id, address):
157175
if pipe_id == 0:
158176
self.pipe0_read_addr = address
159177
if pipe_id < 2:
160-
self.reg_write(RX_ADDR_P0 + pipe_id, address)
178+
self.reg_write_bytes(RX_ADDR_P0 + pipe_id, address)
161179
else:
162180
self.reg_write(RX_ADDR_P0 + pipe_id, address[0])
163181
self.reg_write(RX_PW_P0 + pipe_id, self.payload_size)
@@ -168,12 +186,12 @@ def start_listening(self):
168186
self.reg_write(STATUS, RX_DR | TX_DS | MAX_RT)
169187

170188
if self.pipe0_read_addr is not None:
171-
self.reg_write(RX_ADDR_P0, self.pipe0_read_addr)
189+
self.reg_write_bytes(RX_ADDR_P0, self.pipe0_read_addr)
172190

173191
self.flush_rx()
174192
self.flush_tx()
175193
self.ce.high()
176-
pyb.udelay(130)
194+
utime.sleep_us(130)
177195

178196
def stop_listening(self):
179197
self.ce.low()
@@ -187,8 +205,8 @@ def any(self):
187205
def recv(self):
188206
# get the data
189207
self.cs.low()
190-
self.spi.send(R_RX_PAYLOAD)
191-
buf = self.spi.recv(self.payload_size)
208+
self.spi.readinto(self.buf, R_RX_PAYLOAD)
209+
buf = self.spi.read(self.payload_size)
192210
self.cs.high()
193211
# clear RX ready flag
194212
self.reg_write(STATUS, RX_DR)
@@ -198,9 +216,9 @@ def recv(self):
198216
# blocking wait for tx complete
199217
def send(self, buf, timeout=500):
200218
send_nonblock = self.send_start(buf)
201-
start = pyb.millis()
219+
start = utime.ticks_ms()
202220
result = None
203-
while result is None and pyb.elapsed_millis(start) < timeout:
221+
while result is None and utime.ticks_diff(utime.ticks_ms(), start) < timeout:
204222
result = self.send_done() # 1 == success, 2 == fail
205223
if result == 2:
206224
raise OSError("send failed")
@@ -209,18 +227,18 @@ def send(self, buf, timeout=500):
209227
def send_start(self, buf):
210228
# power up
211229
self.reg_write(CONFIG, (self.reg_read(CONFIG) | PWR_UP) & ~PRIM_RX)
212-
pyb.udelay(150)
230+
utime.sleep_us(150)
213231
# send the data
214232
self.cs.low()
215-
self.spi.send(W_TX_PAYLOAD)
216-
self.spi.send(buf)
233+
self.spi.readinto(self.buf, W_TX_PAYLOAD)
234+
self.spi.write(buf)
217235
if len(buf) < self.payload_size:
218-
self.spi.send(b'\x00' * (self.payload_size - len(buf))) # pad out data
236+
self.spi.write(b'\x00' * (self.payload_size - len(buf))) # pad out data
219237
self.cs.high()
220238

221239
# enable the chip so it can send the data
222240
self.ce.high()
223-
pyb.udelay(15) # needs to be >10us
241+
utime.sleep_us(15) # needs to be >10us
224242
self.ce.low()
225243

226244
# returns None if send still in progress, 1 for success, 2 for fail

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