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tannewttannewt
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SPI tweaks for SD Cards:
* Always init SPI to 250k to start for SD cards. * Add ability to configure byte written during read. * Add ability to read and write to portions of buffers like existing I2C API.
1 parent 10fbe06 commit 370d1de

6 files changed

Lines changed: 88 additions & 23 deletions

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‎atmel-samd/boards/feather_m0_adalogger/pins.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ STATIC const mp_map_elem_t board_global_dict_table[] = {
66
{ MP_OBJ_NEW_QSTR(MP_QSTR_A2), (mp_obj_t)&pin_PB09 },
77
{ MP_OBJ_NEW_QSTR(MP_QSTR_A3), (mp_obj_t)&pin_PA04 },
88
{ MP_OBJ_NEW_QSTR(MP_QSTR_A4), (mp_obj_t)&pin_PA05 },
9-
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD), (mp_obj_t)&pin_PA08 },
9+
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_CS), (mp_obj_t)&pin_PA08 },
1010
{ MP_OBJ_NEW_QSTR(MP_QSTR_A5), (mp_obj_t)&pin_PB02 },
1111
{ MP_OBJ_NEW_QSTR(MP_QSTR_SCK), (mp_obj_t)&pin_PB11 },
1212
{ MP_OBJ_NEW_QSTR(MP_QSTR_MOSI), (mp_obj_t)&pin_PB10 },

‎atmel-samd/common-hal/nativeio/SPI.c‎

Lines changed: 12 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,11 @@ void common_hal_nativeio_spi_construct(nativeio_spi_obj_t *self,
135135
self->MISO_pin = miso->pin;
136136
}
137137

138+
// Always start at 250khz which is what SD cards need. They are sensitive to
139+
// SPI bus noise before they are put into SPI mode.
140+
self->current_baudrate = 250000;
141+
config_spi_master.mode_specific.master.baudrate = self->current_baudrate;
142+
138143
spi_init(&self->spi_master_instance, sercom, &config_spi_master);
139144

140145
spi_enable(&self->spi_master_instance);
@@ -150,9 +155,11 @@ void common_hal_nativeio_spi_deinit(nativeio_spi_obj_t *self) {
150155
bool common_hal_nativeio_spi_configure(nativeio_spi_obj_t *self,
151156
uint32_t baudrate, uint8_t polarity, uint8_t phase, uint8_t bits) {
152157
// TODO(tannewt): Check baudrate first before changing it.
153-
enum status_code status = spi_set_baudrate(&self->spi_master_instance, baudrate);
154-
if (status != STATUS_OK) {
155-
return false;
158+
if (baudrate != self->current_baudrate) {
159+
enum status_code status = spi_set_baudrate(&self->spi_master_instance, baudrate);
160+
if (status != STATUS_OK) {
161+
return false;
162+
}
156163
}
157164

158165
SercomSpi *const spi_module = &(self->spi_master_instance.hw->SPI);
@@ -213,14 +220,14 @@ bool common_hal_nativeio_spi_write(nativeio_spi_obj_t *self,
213220
}
214221

215222
bool common_hal_nativeio_spi_read(nativeio_spi_obj_t *self,
216-
uint8_t *data, size_t len) {
223+
uint8_t *data, size_t len, uint8_t write_value) {
217224
if (len == 0) {
218225
return true;
219226
}
220227
enum status_code status = spi_read_buffer_wait(
221228
&self->spi_master_instance,
222229
data,
223230
len,
224-
0);
231+
write_value);
225232
return status == STATUS_OK;
226233
}

‎atmel-samd/common-hal/nativeio/types.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -85,6 +85,7 @@ typedef struct {
8585
uint8_t clock_pin;
8686
uint8_t MOSI_pin;
8787
uint8_t MISO_pin;
88+
uint32_t current_baudrate;
8889
} nativeio_spi_obj_t;
8990

9091
typedef struct {

‎esp8266/common-hal/nativeio/SPI.c‎

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -126,20 +126,24 @@ bool common_hal_nativeio_spi_write(nativeio_spi_obj_t *self,
126126
}
127127

128128
bool common_hal_nativeio_spi_read(nativeio_spi_obj_t *self,
129-
uint8_t * data, size_t len) {
129+
uint8_t * data, size_t len, uint8_t write_value) {
130130
// Process data in chunks, let the pending tasks run in between
131131
size_t chunk_size = 1024; // TODO this should depend on baudrate
132132
size_t count = len / chunk_size;
133133
size_t i = 0;
134+
uint32_t long_write_value = ((uint32_t) write_value) << 24 |
135+
write_value << 16 |
136+
write_value << 8 |
137+
write_value;
134138
for (size_t j = 0; j < count; ++j) {
135139
for (size_t k = 0; k < chunk_size; ++k) {
136-
data[i] = spi_rx8(HSPI);
140+
data[i] = spi_transaction(HSPI, 0, 0, 0, 0, 0, 0, 8, long_write_value);
137141
++i;
138142
}
139143
ets_loop_iter();
140144
}
141145
while (i < len) {
142-
data[i] = spi_rx8(HSPI);
146+
data[i] = spi_transaction(HSPI, 0, 0, 0, 0, 0, 0, 8, long_write_value);
143147
++i;
144148
}
145149
return true;

‎shared-bindings/nativeio/SPI.c‎

Lines changed: 66 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -189,39 +189,92 @@ STATIC mp_obj_t nativeio_spi_obj_unlock(mp_obj_t self_in) {
189189
}
190190
MP_DEFINE_CONST_FUN_OBJ_1(nativeio_spi_unlock_obj, nativeio_spi_obj_unlock);
191191

192-
//| .. method:: SPI.write(buf)
192+
//| .. method:: SPI.write(buffer, \*, start=0, end=len(buffer))
193193
//|
194194
//| Write the data contained in ``buf``. Requires the SPI being locked.
195195
//|
196-
STATIC mp_obj_t nativeio_spi_write(mp_obj_t self_in, mp_obj_t wr_buf) {
197-
mp_buffer_info_t src;
198-
mp_get_buffer_raise(wr_buf, &src, MP_BUFFER_READ);
199-
nativeio_spi_obj_t *self = MP_OBJ_TO_PTR(self_in);
196+
//| :param bytearray buffer: buffer containing the bytes to write
197+
//| :param int start: Index to start writing from
198+
//| :param int end: Index to read up to but not include
199+
//|
200+
STATIC mp_obj_t nativeio_spi_write(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
201+
enum { ARG_buffer, ARG_start, ARG_end };
202+
static const mp_arg_t allowed_args[] = {
203+
{ MP_QSTR_buffer, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
204+
{ MP_QSTR_start, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
205+
{ MP_QSTR_end, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = INT_MAX} },
206+
};
207+
nativeio_spi_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]);
200208
check_lock(self);
201-
bool ok = common_hal_nativeio_spi_write(self, src.buf, src.len);
209+
mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
210+
mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
211+
212+
mp_buffer_info_t bufinfo;
213+
mp_get_buffer_raise(args[ARG_buffer].u_obj, &bufinfo, MP_BUFFER_READ);
214+
int32_t end = args[ARG_end].u_int;
215+
if (end < 0) {
216+
end += bufinfo.len;
217+
}
218+
uint32_t start = args[ARG_start].u_int;
219+
uint32_t len = end - start;
220+
if ((uint32_t) end < start) {
221+
len = 0;
222+
} else if (len > bufinfo.len) {
223+
len = bufinfo.len;
224+
}
225+
226+
bool ok = common_hal_nativeio_spi_write(self, ((uint8_t*)bufinfo.buf) + start, len);
202227
if (!ok) {
203228
nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, "SPI bus error"));
204229
}
205230
return mp_const_none;
206231
}
207-
MP_DEFINE_CONST_FUN_OBJ_2(nativeio_spi_write_obj, nativeio_spi_write);
232+
MP_DEFINE_CONST_FUN_OBJ_KW(nativeio_spi_write_obj, 2, nativeio_spi_write);
208233

209234

210-
//| .. method:: SPI.readinto(buf)
235+
//| .. method:: SPI.readinto(buffer, \*, start=0, end=len(buffer), write_value=0)
211236
//|
212237
//| Read into the buffer specified by ``buf`` while writing zeroes. Requires the SPI being locked.
213238
//|
214-
STATIC mp_obj_t nativeio_spi_readinto(size_t n_args, const mp_obj_t *args) {
239+
//| :param bytearray buffer: buffer to write into
240+
//| :param int start: Index to start writing at
241+
//| :param int end: Index to write up to but not include
242+
//| :param int write_value: Value to write reading. (Usually ignored.)
243+
//|
244+
STATIC mp_obj_t nativeio_spi_readinto(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
245+
enum { ARG_buffer, ARG_start, ARG_end, ARG_write_value };
246+
static const mp_arg_t allowed_args[] = {
247+
{ MP_QSTR_buffer, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
248+
{ MP_QSTR_start, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
249+
{ MP_QSTR_end, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = INT_MAX} },
250+
{ MP_QSTR_write_value,MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
251+
};
252+
nativeio_spi_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]);
253+
check_lock(self);
254+
mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
255+
mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
256+
215257
mp_buffer_info_t bufinfo;
216-
mp_get_buffer_raise(args[1], &bufinfo, MP_BUFFER_WRITE);
217-
check_lock(args[0]);
218-
bool ok = common_hal_nativeio_spi_read(args[0], bufinfo.buf, bufinfo.len);
258+
mp_get_buffer_raise(args[ARG_buffer].u_obj, &bufinfo, MP_BUFFER_WRITE);
259+
int32_t end = args[ARG_end].u_int;
260+
if (end < 0) {
261+
end += bufinfo.len;
262+
}
263+
uint32_t start = args[ARG_start].u_int;
264+
uint32_t len = end - start;
265+
if ((uint32_t) end < start) {
266+
len = 0;
267+
} else if (len > bufinfo.len) {
268+
len = bufinfo.len;
269+
}
270+
271+
bool ok = common_hal_nativeio_spi_read(self, ((uint8_t*)bufinfo.buf) + start, len, args[ARG_write_value].u_int);
219272
if (!ok) {
220273
nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, "SPI bus error"));
221274
}
222275
return mp_const_none;
223276
}
224-
MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(nativeio_spi_readinto_obj, 2, 2, nativeio_spi_readinto);
277+
MP_DEFINE_CONST_FUN_OBJ_KW(nativeio_spi_readinto_obj, 2, nativeio_spi_readinto);
225278

226279
STATIC const mp_rom_map_elem_t nativeio_spi_locals_dict_table[] = {
227280
{ MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&nativeio_spi_deinit_obj) },

‎shared-bindings/nativeio/SPI.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,6 @@ extern void common_hal_nativeio_spi_unlock(nativeio_spi_obj_t *self);
5252
extern bool common_hal_nativeio_spi_write(nativeio_spi_obj_t *self, const uint8_t *data, size_t len);
5353

5454
// Reads in len bytes while outputting zeroes.
55-
extern bool common_hal_nativeio_spi_read(nativeio_spi_obj_t *self, uint8_t *data, size_t len);
55+
extern bool common_hal_nativeio_spi_read(nativeio_spi_obj_t *self, uint8_t *data, size_t len, uint8_t write_value);
5656

5757
#endif // __MICROPY_INCLUDED_SHARED_BINDINGS_NATIVEIO_SPI_H__

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