// Licensed to the .NET Foundation under one or more agreements.

// The .NET Foundation licenses this file to you under the MIT license.

// See the LICENSE file in the project root for more information.

/*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

XX XX

XX ARM/ARM64 Code Generator Common Code XX

XX XX

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

*/

#include "jitpch.h"

#ifdef _MSC_VER

#pragma hdrstop

#endif

#ifdef _TARGET_ARMARCH_ // This file is ONLY used for ARM and ARM64 architectures

#include "codegen.h"

#include "lower.h"

#include "gcinfo.h"

#include "emit.h"

//------------------------------------------------------------------------

// genStackPointerConstantAdjustment: add a specified constant value to the stack pointer.

// No probe is done.

//

// Arguments:

// spDelta - the value to add to SP. Must be negative or zero.

//

// Return Value:

// None.

//

void CodeGen::genStackPointerConstantAdjustment(ssize_t spDelta)

{

assert(spDelta < 0);

// We assert that the SP change is less than one page. If it's greater, you should have called a

// function that does a probe, which will in turn call this function.

assert((target_size_t)(-spDelta) <= compiler->eeGetPageSize());

inst_RV_IV(INS_sub, REG_SPBASE, -spDelta, EA_PTRSIZE);

}

//------------------------------------------------------------------------

// genStackPointerConstantAdjustmentWithProbe: add a specified constant value to the stack pointer,

// and probe the stack as appropriate. Should only be called as a helper for

// genStackPointerConstantAdjustmentLoopWithProbe.

//

// Arguments:

// spDelta - the value to add to SP. Must be negative or zero. If zero, the probe happens,

// but the stack pointer doesn't move.

// regTmp - temporary register to use as target for probe load instruction

//

// Return Value:

// None.

//

void CodeGen::genStackPointerConstantAdjustmentWithProbe(ssize_t spDelta, regNumber regTmp)

{

GetEmitter()->emitIns_R_R_I(INS_ldr, EA_4BYTE, regTmp, REG_SP, 0);

genStackPointerConstantAdjustment(spDelta);

}

//------------------------------------------------------------------------

// genStackPointerConstantAdjustmentLoopWithProbe: Add a specified constant value to the stack pointer,

// and probe the stack as appropriate. Generates one probe per page, up to the total amount required.

// This will generate a sequence of probes in-line.

//

// Arguments:

// spDelta - the value to add to SP. Must be negative.

// regTmp - temporary register to use as target for probe load instruction

//

// Return Value:

// Offset in bytes from SP to last probed address.

//

target_ssize_t CodeGen::genStackPointerConstantAdjustmentLoopWithProbe(ssize_t spDelta, regNumber regTmp)

{

assert(spDelta < 0);

const target_size_t pageSize = compiler->eeGetPageSize();

ssize_t spRemainingDelta = spDelta;

do

{

ssize_t spOneDelta = -(ssize_t)min((target_size_t)-spRemainingDelta, pageSize);

genStackPointerConstantAdjustmentWithProbe(spOneDelta, regTmp);

spRemainingDelta -= spOneDelta;

} while (spRemainingDelta < 0);

// What offset from the final SP was the last probe? This depends on the fact that

// genStackPointerConstantAdjustmentWithProbe() probes first, then does "SUB SP".

target_size_t lastTouchDelta = (target_size_t)(-spDelta) % pageSize;

if ((lastTouchDelta == 0) || (lastTouchDelta + STACK_PROBE_BOUNDARY_THRESHOLD_BYTES > pageSize))

{

// We haven't probed almost a complete page. If lastTouchDelta==0, then spDelta was an exact

// multiple of pageSize, which means we last probed exactly one page back. Otherwise, we probed

// the page, but very far from the end. If the next action on the stack might subtract from SP

// first, before touching the current SP, then we do one more probe at the very bottom. This can

// happen on x86, for example, when we copy an argument to the stack using a "SUB ESP; REP MOV"

// strategy.

GetEmitter()->emitIns_R_R_I(INS_ldr, EA_4BYTE, regTmp, REG_SP, 0);

lastTouchDelta = 0;

}

return lastTouchDelta;

}

//------------------------------------------------------------------------

// genCodeForTreeNode Generate code for a single node in the tree.

//

// Preconditions:

// All operands have been evaluated.

//

void CodeGen::genCodeForTreeNode(GenTree* treeNode)

{

regNumber targetReg = treeNode->GetRegNum();

var_types targetType = treeNode->TypeGet();

emitter* emit = GetEmitter();

#ifdef DEBUG

// Validate that all the operands for the current node are consumed in order.

// This is important because LSRA ensures that any necessary copies will be

// handled correctly.

lastConsumedNode = nullptr;

if (compiler->verbose)

{

unsigned seqNum = treeNode->gtSeqNum; // Useful for setting a conditional break in Visual Studio

compiler->gtDispLIRNode(treeNode, "Generating: ");

}

#endif // DEBUG

// Is this a node whose value is already in a register? LSRA denotes this by

// setting the GTF_REUSE_REG_VAL flag.

if (treeNode->IsReuseRegVal())

{

// For now, this is only used for constant nodes.

assert((treeNode->OperGet() == GT_CNS_INT) || (treeNode->OperGet() == GT_CNS_DBL));

JITDUMP(" TreeNode is marked ReuseReg\n");

return;

}

// contained nodes are part of their parents for codegen purposes

// ex : immediates, most LEAs

if (treeNode->isContained())

{

return;

}

switch (treeNode->gtOper)

{

case GT_START_NONGC:

GetEmitter()->emitDisableGC();

break;

case GT_START_PREEMPTGC:

// Kill callee saves GC registers, and create a label

// so that information gets propagated to the emitter.

gcInfo.gcMarkRegSetNpt(RBM_INT_CALLEE_SAVED);

genDefineTempLabel(genCreateTempLabel());

break;

case GT_PROF_HOOK:

// We should be seeing this only if profiler hook is needed

noway_assert(compiler->compIsProfilerHookNeeded());

#ifdef PROFILING_SUPPORTED

// Right now this node is used only for tail calls. In future if

// we intend to use it for Enter or Leave hooks, add a data member

// to this node indicating the kind of profiler hook. For example,

// helper number can be used.

genProfilingLeaveCallback(CORINFO_HELP_PROF_FCN_TAILCALL);

#endif // PROFILING_SUPPORTED

break;

case GT_LCLHEAP:

genLclHeap(treeNode);

break;

case GT_CNS_INT:

case GT_CNS_DBL:

genSetRegToConst(targetReg, targetType, treeNode);

genProduceReg(treeNode);

break;

case GT_NOT:

case GT_NEG:

genCodeForNegNot(treeNode);

break;

case GT_MOD:

case GT_UMOD:

case GT_DIV:

case GT_UDIV:

genCodeForDivMod(treeNode->AsOp());

break;

case GT_OR:

case GT_XOR:

case GT_AND:

assert(varTypeIsIntegralOrI(treeNode));

__fallthrough;

#if !defined(_TARGET_64BIT_)

case GT_ADD_LO:

case GT_ADD_HI:

case GT_SUB_LO:

case GT_SUB_HI:

#endif // !defined(_TARGET_64BIT_)

case GT_ADD:

case GT_SUB:

case GT_MUL:

genConsumeOperands(treeNode->AsOp());

genCodeForBinary(treeNode->AsOp());

break;

case GT_LSH:

case GT_RSH:

case GT_RSZ:

// case GT_ROL: // No ROL instruction on ARM; it has been lowered to ROR.

case GT_ROR:

genCodeForShift(treeNode);

break;

#if !defined(_TARGET_64BIT_)

case GT_LSH_HI:

case GT_RSH_LO:

genCodeForShiftLong(treeNode);

break;

#endif // !defined(_TARGET_64BIT_)

case GT_CAST:

genCodeForCast(treeNode->AsOp());

break;

case GT_BITCAST:

{

GenTree* op1 = treeNode->AsOp()->gtOp1;

if (varTypeIsFloating(treeNode) != varTypeIsFloating(op1))

{

#ifdef _TARGET_ARM64_

inst_RV_RV(INS_fmov, targetReg, genConsumeReg(op1), targetType);

#else // !_TARGET_ARM64_

if (varTypeIsFloating(treeNode))

{

// GT_BITCAST on ARM is only used to cast floating-point arguments to integer

// registers. Nobody generates GT_BITCAST from int to float currently.

NYI_ARM("GT_BITCAST from 'int' to 'float'");

}

else

{

assert(varTypeIsFloating(op1));

if (op1->TypeGet() == TYP_FLOAT)

{

inst_RV_RV(INS_vmov_f2i, targetReg, genConsumeReg(op1), targetType);

}

else

{

assert(op1->TypeGet() == TYP_DOUBLE);

regNumber otherReg = treeNode->AsMultiRegOp()->gtOtherReg;

assert(otherReg != REG_NA);

inst_RV_RV_RV(INS_vmov_d2i, targetReg, otherReg, genConsumeReg(op1), EA_8BYTE);

}

}

#endif // !_TARGET_ARM64_

}

else

{

inst_RV_RV(ins_Copy(targetType), targetReg, genConsumeReg(op1), targetType);

}

}

break;

case GT_LCL_FLD_ADDR:

case GT_LCL_VAR_ADDR:

genCodeForLclAddr(treeNode);

break;

case GT_LCL_FLD:

genCodeForLclFld(treeNode->AsLclFld());

break;

case GT_LCL_VAR:

genCodeForLclVar(treeNode->AsLclVar());

break;

case GT_STORE_LCL_FLD:

genCodeForStoreLclFld(treeNode->AsLclFld());

break;

case GT_STORE_LCL_VAR:

genCodeForStoreLclVar(treeNode->AsLclVar());

break;

case GT_RETFILT:

case GT_RETURN:

genReturn(treeNode);

break;

case GT_LEA:

// If we are here, it is the case where there is an LEA that cannot be folded into a parent instruction.

genLeaInstruction(treeNode->AsAddrMode());

break;

case GT_INDEX_ADDR:

genCodeForIndexAddr(treeNode->AsIndexAddr());

break;

case GT_IND:

genCodeForIndir(treeNode->AsIndir());

break;

#ifdef _TARGET_ARM_

case GT_MUL_LONG:

genCodeForMulLong(treeNode->AsMultiRegOp());

break;

#endif // _TARGET_ARM_

#ifdef _TARGET_ARM64_

case GT_MULHI:

genCodeForMulHi(treeNode->AsOp());

break;

case GT_SWAP:

genCodeForSwap(treeNode->AsOp());

break;

#endif // _TARGET_ARM64_

case GT_JMP:

genJmpMethod(treeNode);

break;

case GT_CKFINITE:

genCkfinite(treeNode);

break;

case GT_INTRINSIC:

genIntrinsic(treeNode);

break;

#ifdef FEATURE_SIMD

case GT_SIMD:

genSIMDIntrinsic(treeNode->AsSIMD());

break;

#endif // FEATURE_SIMD

#ifdef FEATURE_HW_INTRINSICS

case GT_HWINTRINSIC:

genHWIntrinsic(treeNode->AsHWIntrinsic());

break;

#endif // FEATURE_HW_INTRINSICS

case GT_EQ:

case GT_NE:

case GT_LT:

case GT_LE:

case GT_GE:

case GT_GT:

case GT_CMP:

#ifdef _TARGET_ARM64_

case GT_TEST_EQ:

case GT_TEST_NE:

#endif // _TARGET_ARM64_

genCodeForCompare(treeNode->AsOp());

break;

case GT_JTRUE:

genCodeForJumpTrue(treeNode->AsOp());

break;

#ifdef _TARGET_ARM64_

case GT_JCMP:

genCodeForJumpCompare(treeNode->AsOp());

break;

#endif // _TARGET_ARM64_

case GT_JCC:

genCodeForJcc(treeNode->AsCC());

break;

case GT_SETCC:

genCodeForSetcc(treeNode->AsCC());

break;

case GT_RETURNTRAP:

genCodeForReturnTrap(treeNode->AsOp());

break;

case GT_STOREIND:

genCodeForStoreInd(treeNode->AsStoreInd());

break;

case GT_COPY:

// This is handled at the time we call genConsumeReg() on the GT_COPY

break;

case GT_LIST:

case GT_FIELD_LIST:

// Should always be marked contained.

assert(!"LIST, FIELD_LIST nodes should always be marked contained.");

break;

case GT_PUTARG_STK:

genPutArgStk(treeNode->AsPutArgStk());

break;

case GT_PUTARG_REG:

genPutArgReg(treeNode->AsOp());

break;

#if FEATURE_ARG_SPLIT

case GT_PUTARG_SPLIT:

genPutArgSplit(treeNode->AsPutArgSplit());

break;

#endif // FEATURE_ARG_SPLIT

case GT_CALL:

genCallInstruction(treeNode->AsCall());

break;

case GT_MEMORYBARRIER:

instGen_MemoryBarrier();

break;

#ifdef _TARGET_ARM64_

case GT_XCHG:

case GT_XADD:

genLockedInstructions(treeNode->AsOp());

break;

case GT_CMPXCHG:

genCodeForCmpXchg(treeNode->AsCmpXchg());

break;

#endif // _TARGET_ARM64_

case GT_RELOAD:

// do nothing - reload is just a marker.

// The parent node will call genConsumeReg on this which will trigger the unspill of this node's child

// into the register specified in this node.

break;

case GT_NOP:

break;

case GT_KEEPALIVE:

if (treeNode->AsOp()->gtOp1->isContained())

{

// For this case we simply need to update the lifetime of the local.

genUpdateLife(treeNode->AsOp()->gtOp1);

}

else

{

genConsumeReg(treeNode->AsOp()->gtOp1);

}

break;

case GT_NO_OP:

instGen(INS_nop);

break;

case GT_ARR_BOUNDS_CHECK:

#ifdef FEATURE_SIMD

case GT_SIMD_CHK:

#endif // FEATURE_SIMD

#ifdef FEATURE_HW_INTRINSICS

case GT_HW_INTRINSIC_CHK:

#endif // FEATURE_HW_INTRINSICS

genRangeCheck(treeNode);

break;

case GT_PHYSREG:

genCodeForPhysReg(treeNode->AsPhysReg());

break;

case GT_NULLCHECK:

genCodeForNullCheck(treeNode->AsOp());

break;

case GT_CATCH_ARG:

noway_assert(handlerGetsXcptnObj(compiler->compCurBB->bbCatchTyp));

/* Catch arguments get passed in a register. genCodeForBBlist()

would have marked it as holding a GC object, but not used. */

noway_assert(gcInfo.gcRegGCrefSetCur & RBM_EXCEPTION_OBJECT);

genConsumeReg(treeNode);

break;

case GT_PINVOKE_PROLOG:

noway_assert(((gcInfo.gcRegGCrefSetCur | gcInfo.gcRegByrefSetCur) & ~fullIntArgRegMask()) == 0);

// the runtime side requires the codegen here to be consistent

emit->emitDisableRandomNops();

break;

case GT_LABEL:

genPendingCallLabel = genCreateTempLabel();

emit->emitIns_R_L(INS_adr, EA_PTRSIZE, genPendingCallLabel, targetReg);

break;

case GT_STORE_OBJ:

case GT_STORE_DYN_BLK:

case GT_STORE_BLK:

genCodeForStoreBlk(treeNode->AsBlk());

break;

case GT_JMPTABLE:

genJumpTable(treeNode);

break;

case GT_SWITCH_TABLE:

genTableBasedSwitch(treeNode);

break;

case GT_ARR_INDEX:

genCodeForArrIndex(treeNode->AsArrIndex());

break;

case GT_ARR_OFFSET:

genCodeForArrOffset(treeNode->AsArrOffs());

break;

#ifdef _TARGET_ARM_

case GT_CLS_VAR_ADDR:

emit->emitIns_R_C(INS_lea, EA_PTRSIZE, targetReg, treeNode->AsClsVar()->gtClsVarHnd, 0);

genProduceReg(treeNode);

break;

case GT_LONG:

assert(treeNode->isUsedFromReg());

genConsumeRegs(treeNode);

break;

#endif // _TARGET_ARM_

case GT_IL_OFFSET:

// Do nothing; these nodes are simply markers for debug info.

break;

default:

{

#ifdef DEBUG

char message[256];

_snprintf_s(message, _countof(message), _TRUNCATE, "NYI: Unimplemented node type %s",

GenTree::OpName(treeNode->OperGet()));

NYIRAW(message);

#else

NYI("unimplemented node");

#endif

}

break;

}

}

//------------------------------------------------------------------------

// genSetRegToIcon: Generate code that will set the given register to the integer constant.

//

void CodeGen::genSetRegToIcon(regNumber reg, ssize_t val, var_types type, insFlags flags)

{

// Reg cannot be a FP reg

assert(!genIsValidFloatReg(reg));

// The only TYP_REF constant that can come this path is a managed 'null' since it is not

// relocatable. Other ref type constants (e.g. string objects) go through a different

// code path.

noway_assert(type != TYP_REF || val == 0);

instGen_Set_Reg_To_Imm(emitActualTypeSize(type), reg, val, flags);

}

//---------------------------------------------------------------------

// genSetGSSecurityCookie: Set the "GS" security cookie in the prolog.

//

// Arguments:

// initReg - register to use as a scratch register

// pInitRegZeroed - OUT parameter. *pInitRegZeroed is set to 'false' if and only if

// this call sets 'initReg' to a non-zero value.

//

// Return Value:

// None

//

void CodeGen::genSetGSSecurityCookie(regNumber initReg, bool* pInitRegZeroed)

{

assert(compiler->compGeneratingProlog);

if (!compiler->getNeedsGSSecurityCookie())

{

return;

}

if (compiler->gsGlobalSecurityCookieAddr == nullptr)

{

noway_assert(compiler->gsGlobalSecurityCookieVal != 0);

// initReg = #GlobalSecurityCookieVal; [frame.GSSecurityCookie] = initReg

genSetRegToIcon(initReg, compiler->gsGlobalSecurityCookieVal, TYP_I_IMPL);

GetEmitter()->emitIns_S_R(INS_str, EA_PTRSIZE, initReg, compiler->lvaGSSecurityCookie, 0);

}

else

{

instGen_Set_Reg_To_Imm(EA_PTR_DSP_RELOC, initReg, (ssize_t)compiler->gsGlobalSecurityCookieAddr);

GetEmitter()->emitIns_R_R_I(INS_ldr, EA_PTRSIZE, initReg, initReg, 0);

regSet.verifyRegUsed(initReg);

GetEmitter()->emitIns_S_R(INS_str, EA_PTRSIZE, initReg, compiler->lvaGSSecurityCookie, 0);

}

*pInitRegZeroed = false;

}

//---------------------------------------------------------------------

// genIntrinsic - generate code for a given intrinsic

//

// Arguments

// treeNode - the GT_INTRINSIC node

//

// Return value:

// None

//

void CodeGen::genIntrinsic(GenTree* treeNode)

{

assert(treeNode->OperIs(GT_INTRINSIC));

// Both operand and its result must be of the same floating point type.

GenTree* srcNode = treeNode->AsOp()->gtOp1;

assert(varTypeIsFloating(srcNode));

assert(srcNode->TypeGet() == treeNode->TypeGet());

// Right now only Abs/Ceiling/Floor/Round/Sqrt are treated as math intrinsics.

//

switch (treeNode->AsIntrinsic()->gtIntrinsicId)

{

case CORINFO_INTRINSIC_Abs:

genConsumeOperands(treeNode->AsOp());

GetEmitter()->emitInsBinary(INS_ABS, emitActualTypeSize(treeNode), treeNode, srcNode);

break;

#ifdef _TARGET_ARM64_

case CORINFO_INTRINSIC_Ceiling:

genConsumeOperands(treeNode->AsOp());

GetEmitter()->emitInsBinary(INS_frintp, emitActualTypeSize(treeNode), treeNode, srcNode);

break;

case CORINFO_INTRINSIC_Floor:

genConsumeOperands(treeNode->AsOp());

GetEmitter()->emitInsBinary(INS_frintm, emitActualTypeSize(treeNode), treeNode, srcNode);

break;

case CORINFO_INTRINSIC_Round:

genConsumeOperands(treeNode->AsOp());

GetEmitter()->emitInsBinary(INS_frintn, emitActualTypeSize(treeNode), treeNode, srcNode);

break;

#endif // _TARGET_ARM64_

case CORINFO_INTRINSIC_Sqrt:

genConsumeOperands(treeNode->AsOp());

GetEmitter()->emitInsBinary(INS_SQRT, emitActualTypeSize(treeNode), treeNode, srcNode);

break;

default:

assert(!"genIntrinsic: Unsupported intrinsic");

unreached();

}

genProduceReg(treeNode);

}

//---------------------------------------------------------------------

// genPutArgStk - generate code for a GT_PUTARG_STK node

//

// Arguments

// treeNode - the GT_PUTARG_STK node

//

// Return value:

// None

//

void CodeGen::genPutArgStk(GenTreePutArgStk* treeNode)

{

assert(treeNode->OperIs(GT_PUTARG_STK));

GenTree* source = treeNode->gtOp1;

var_types targetType = genActualType(source->TypeGet());

emitter* emit = GetEmitter();

// This is the varNum for our store operations,

// typically this is the varNum for the Outgoing arg space

// When we are generating a tail call it will be the varNum for arg0

unsigned varNumOut = (unsigned)-1;

unsigned argOffsetMax = (unsigned)-1; // Records the maximum size of this area for assert checks

// Get argument offset to use with 'varNumOut'

// Here we cross check that argument offset hasn't changed from lowering to codegen since

// we are storing arg slot number in GT_PUTARG_STK node in lowering phase.

unsigned argOffsetOut = treeNode->gtSlotNum * TARGET_POINTER_SIZE;

#ifdef DEBUG

fgArgTabEntry* curArgTabEntry = compiler->gtArgEntryByNode(treeNode->gtCall, treeNode);

assert(curArgTabEntry);

assert(argOffsetOut == (curArgTabEntry->slotNum * TARGET_POINTER_SIZE));

#endif // DEBUG

// Whether to setup stk arg in incoming or out-going arg area?

// Fast tail calls implemented as epilog+jmp = stk arg is setup in incoming arg area.

// All other calls - stk arg is setup in out-going arg area.

if (treeNode->putInIncomingArgArea())

{

varNumOut = getFirstArgWithStackSlot();

argOffsetMax = compiler->compArgSize;

#if FEATURE_FASTTAILCALL

// This must be a fast tail call.

assert(treeNode->gtCall->IsFastTailCall());

// Since it is a fast tail call, the existence of first incoming arg is guaranteed

// because fast tail call requires that in-coming arg area of caller is >= out-going

// arg area required for tail call.

LclVarDsc* varDsc = &(compiler->lvaTable[varNumOut]);

assert(varDsc != nullptr);

#endif // FEATURE_FASTTAILCALL

}

else

{

varNumOut = compiler->lvaOutgoingArgSpaceVar;

argOffsetMax = compiler->lvaOutgoingArgSpaceSize;

}

bool isStruct = (targetType == TYP_STRUCT) || (source->OperGet() == GT_FIELD_LIST);

if (!isStruct) // a normal non-Struct argument

{

if (varTypeIsSIMD(targetType))

{

assert(!source->isContained());

regNumber srcReg = genConsumeReg(source);

emitAttr storeAttr = emitTypeSize(targetType);

assert((srcReg != REG_NA) && (genIsValidFloatReg(srcReg)));

emit->emitIns_S_R(INS_str, storeAttr, srcReg, varNumOut, argOffsetOut);

argOffsetOut += EA_SIZE_IN_BYTES(storeAttr);

assert(argOffsetOut <= argOffsetMax); // We can't write beyound the outgoing area area

return;

}

instruction storeIns = ins_Store(targetType);

emitAttr storeAttr = emitTypeSize(targetType);

// If it is contained then source must be the integer constant zero

if (source->isContained())

{

#ifdef _TARGET_ARM64_

assert(source->OperGet() == GT_CNS_INT);

assert(source->AsIntConCommon()->IconValue() == 0);

emit->emitIns_S_R(storeIns, storeAttr, REG_ZR, varNumOut, argOffsetOut);

#else // !_TARGET_ARM64_

// There is no zero register on ARM32

unreached();

#endif // !_TARGET_ARM64

}

else

{

genConsumeReg(source);

emit->emitIns_S_R(storeIns, storeAttr, source->GetRegNum(), varNumOut, argOffsetOut);

#ifdef _TARGET_ARM_

if (targetType == TYP_LONG)

{

// This case currently only occurs for double types that are passed as TYP_LONG;

// actual long types would have been decomposed by now.

assert(source->IsCopyOrReload());

regNumber otherReg = (regNumber)source->AsCopyOrReload()->GetRegNumByIdx(1);

assert(otherReg != REG_NA);

argOffsetOut += EA_4BYTE;

emit->emitIns_S_R(storeIns, storeAttr, otherReg, varNumOut, argOffsetOut);

}

#endif // _TARGET_ARM_

}

argOffsetOut += EA_SIZE_IN_BYTES(storeAttr);

assert(argOffsetOut <= argOffsetMax); // We can't write beyound the outgoing area area

}

else // We have some kind of a struct argument

{

assert(source->isContained()); // We expect that this node was marked as contained in Lower

if (source->OperGet() == GT_FIELD_LIST)

{

genPutArgStkFieldList(treeNode, varNumOut);

}

else // We must have a GT_OBJ or a GT_LCL_VAR

{

noway_assert((source->OperGet() == GT_LCL_VAR) || (source->OperGet() == GT_OBJ));

var_types targetType = source->TypeGet();

noway_assert(varTypeIsStruct(targetType));

// We will copy this struct to the stack, possibly using a ldp/ldr instruction

// in ARM64/ARM

// Setup loReg (and hiReg) from the internal registers that we reserved in lower.

//

regNumber loReg = treeNode->ExtractTempReg();

#ifdef _TARGET_ARM64_

regNumber hiReg = treeNode->GetSingleTempReg();

#endif // _TARGET_ARM64_

regNumber addrReg = REG_NA;

GenTreeLclVarCommon* varNode = nullptr;

GenTree* addrNode = nullptr;

if (source->OperGet() == GT_LCL_VAR)

{

varNode = source->AsLclVarCommon();

}

else // we must have a GT_OBJ

{

assert(source->OperGet() == GT_OBJ);

addrNode = source->AsOp()->gtOp1;

// addrNode can either be a GT_LCL_VAR_ADDR or an address expression

//

if (addrNode->OperGet() == GT_LCL_VAR_ADDR)

{

// We have a GT_OBJ(GT_LCL_VAR_ADDR)

//

// We will treat this case the same as above

// (i.e if we just had this GT_LCL_VAR directly as the source)

// so update 'source' to point this GT_LCL_VAR_ADDR node

// and continue to the codegen for the LCL_VAR node below

//

varNode = addrNode->AsLclVarCommon();

addrNode = nullptr;

}

else // addrNode is used

{

// Generate code to load the address that we need into a register

genConsumeAddress(addrNode);

addrReg = addrNode->GetRegNum();

#ifdef _TARGET_ARM64_

// If addrReg equal to loReg, swap(loReg, hiReg)

// This reduces code complexity by only supporting one addrReg overwrite case

if (loReg == addrReg)

{

loReg = hiReg;

hiReg = addrReg;

}

#endif // _TARGET_ARM64_

}

}

// Either varNode or addrNOde must have been setup above,

// the xor ensures that only one of the two is setup, not both

assert((varNode != nullptr) ^ (addrNode != nullptr));

ClassLayout* layout;

unsigned structSize;

bool isHfa;

// Setup the structSize, isHFa, and gcPtrCount

if (source->OperGet() == GT_LCL_VAR)

{

assert(varNode != nullptr);

LclVarDsc* varDsc = compiler->lvaGetDesc(varNode);

// This struct also must live in the stack frame

// And it can't live in a register (SIMD)

assert(varDsc->lvType == TYP_STRUCT);

assert(varDsc->lvOnFrame && !varDsc->lvRegister);

structSize = varDsc->lvSize(); // This yields the roundUp size, but that is fine

// as that is how much stack is allocated for this LclVar

isHfa = varDsc->lvIsHfa();

layout = varDsc->GetLayout();

}

else // we must have a GT_OBJ

{

assert(source->OperGet() == GT_OBJ);

// If the source is an OBJ node then we need to use the type information

// it provides (size and GC layout) even if the node wraps a lclvar. Due

// to struct reinterpretation (e.g. Unsafe.As<X, Y>) it is possible that

// the OBJ node has a different type than the lclvar.

layout = source->AsObj()->GetLayout();

structSize = layout->GetSize();

// The codegen code below doesn't have proper support for struct sizes

// that are not multiple of the slot size. Call arg morphing handles this

// case by copying non-local values to temporary local variables.

// More generally, we can always round up the struct size when the OBJ node

// wraps a local variable because the local variable stack allocation size

// is also rounded up to be a multiple of the slot size.

if (varNode != nullptr)

{

structSize = roundUp(structSize, TARGET_POINTER_SIZE);

}

else

{

assert((structSize % TARGET_POINTER_SIZE) == 0);

}

isHfa = compiler->IsHfa(layout->GetClassHandle());

}

// If we have an HFA we can't have any GC pointers,

// if not then the max size for the the struct is 16 bytes

if (isHfa)

{

noway_assert(!layout->HasGCPtr());

}

#ifdef _TARGET_ARM64_

else

{

noway_assert(structSize <= 2 * TARGET_POINTER_SIZE);

}

noway_assert(structSize <= MAX_PASS_MULTIREG_BYTES);

#endif // _TARGET_ARM64_

int remainingSize = structSize;

unsigned structOffset = 0;

unsigned nextIndex = 0;

#ifdef _TARGET_ARM64_

// For a >= 16-byte structSize we will generate a ldp and stp instruction each loop

// ldp x2, x3, [x0]

// stp x2, x3, [sp, #16]

while (remainingSize >= 2 * TARGET_POINTER_SIZE)

{

var_types type0 = layout->GetGCPtrType(nextIndex + 0);

var_types type1 = layout->GetGCPtrType(nextIndex + 1);

if (varNode != nullptr)

{

// Load from our varNumImp source

emit->emitIns_R_R_S_S(INS_ldp, emitTypeSize(type0), emitTypeSize(type1), loReg, hiReg,

varNode->GetLclNum(), structOffset);

}

else

{

// check for case of destroying the addrRegister while we still need it

assert(loReg != addrReg);

noway_assert((remainingSize == 2 * TARGET_POINTER_SIZE) || (hiReg != addrReg));

// Load from our address expression source

emit->emitIns_R_R_R_I(INS_ldp, emitTypeSize(type0), loReg, hiReg, addrReg, structOffset,

INS_OPTS_NONE, emitTypeSize(type0));

}

// Emit stp instruction to store the two registers into the outgoing argument area

emit->emitIns_S_S_R_R(INS_stp, emitTypeSize(type0), emitTypeSize(type1), loReg, hiReg, varNumOut,

argOffsetOut);

argOffsetOut += (2 * TARGET_POINTER_SIZE); // We stored 16-bytes of the struct

assert(argOffsetOut <= argOffsetMax); // We can't write beyound the outgoing area area

remainingSize -= (2 * TARGET_POINTER_SIZE); // We loaded 16-bytes of the struct

structOffset += (2 * TARGET_POINTER_SIZE);

nextIndex += 2;

}

#else // _TARGET_ARM_

// For a >= 4 byte structSize we will generate a ldr and str instruction each loop

// ldr r2, [r0]

// str r2, [sp, #16]

while (remainingSize >= TARGET_POINTER_SIZE)

{

var_types type = layout->GetGCPtrType(nextIndex);

if (varNode != nullptr)

{

// Load from our varNumImp source

emit->emitIns_R_S(INS_ldr, emitTypeSize(type), loReg, varNode->GetLclNum(), structOffset);

}

else

{

// check for case of destroying the addrRegister while we still need it

assert(loReg != addrReg || remainingSize == TARGET_POINTER_SIZE);

// Load from our address expression source

emit->emitIns_R_R_I(INS_ldr, emitTypeSize(type), loReg, addrReg, structOffset);

}

// Emit str instruction to store the register into the outgoing argument area

emit->emitIns_S_R(INS_str, emitTypeSize(type), loReg, varNumOut, argOffsetOut);

argOffsetOut += TARGET_POINTER_SIZE; // We stored 4-bytes of the struct

assert(argOffsetOut <= argOffsetMax); // We can't write beyound the outgoing area area

remainingSize -= TARGET_POINTER_SIZE; // We loaded 4-bytes of the struct

structOffset += TARGET_POINTER_SIZE;

nextIndex += 1;

}

#endif // _TARGET_ARM_