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[MERGE chakra-core#743] SIMD.js Lowerer BugFix + Unittest updates
Merge pull request chakra-core#743 from arunetm:SimdLowererBugFix1.2 1. Lowerer bug fix for Uint16x8 Equal builtin to use the right instruction. 2. Lowerer bug fix for Min/Max operations for Float32x4 type to use legalization. 3. Updating simd unittests. Fixes chakra-core#749
2 parents c5fc8c6 + 8c59d76 commit b5b94d9

4 files changed

Lines changed: 17 additions & 10 deletions

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‎lib/Backend/LowerMDShared.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1619,6 +1619,7 @@ LowererMD::Legalize(IR::Instr *const instr, bool fPostRegAlloc)
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case Js::OpCode::CMPLEPD:
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case Js::OpCode::CMPEQPD:
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case Js::OpCode::CMPNEQPD:
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case Js::OpCode::CMPUNORDPS:
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case Js::OpCode::PUNPCKLBW:
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case Js::OpCode::PUNPCKLDQ:
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case Js::OpCode::PUNPCKLWD:

‎lib/Backend/LowerMDSharedSimd128.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3325,7 +3325,7 @@ void LowererMD::Simd128InitOpcodeMap()
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SET_SIMDOPCODE(Simd128_Add_U8 , PADDW);
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SET_SIMDOPCODE(Simd128_Sub_U8 , PSUBW);
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SET_SIMDOPCODE(Simd128_Mul_U8 , PMULLW);
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SET_SIMDOPCODE(Simd128_Eq_U8 , PCMPEQB); // same as int16X8.equal
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SET_SIMDOPCODE(Simd128_Eq_U8 , PCMPEQW); // same as int16X8.equal
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SET_SIMDOPCODE(Simd128_AddSaturate_U8 , PADDUSW);
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SET_SIMDOPCODE(Simd128_SubSaturate_U8 , PSUBUSW);
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@@ -3337,7 +3337,7 @@ void LowererMD::Simd128InitOpcodeMap()
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SET_SIMDOPCODE(Simd128_Sub_U16 , PSUBB);
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SET_SIMDOPCODE(Simd128_Min_U16 , PMINUB);
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SET_SIMDOPCODE(Simd128_Max_U16 , PMAXUB);
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SET_SIMDOPCODE(Simd128_Eq_U16 , PCMPEQB); // same as int16x8.equal
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SET_SIMDOPCODE(Simd128_Eq_U16 , PCMPEQB); // same as int8x16.equal
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SET_SIMDOPCODE(Simd128_AddSaturate_U16 , PADDUSB);
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SET_SIMDOPCODE(Simd128_SubSaturate_U16 , PSUBUSB);
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‎test/SIMD.float32x4.asmjs/testMinMax.js‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -200,16 +200,22 @@ function asmModule(stdlib, imports) {
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var m = asmModule(this, {g1:SIMD.Float32x4(90934.2,123.9,419.39,449.0), g2:SIMD.Int32x4(-1065353216, -1073741824,-1077936128, -1082130432)});
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equalSimd([-34183.8984375, -3401, -569437, -32234.099609375], m.func1(), SIMD.Float32x4, "Func1");
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equalSimd([-34183.8984375, -3401, -569437, -32234.099609375], m.func1(), SIMD.Float32x4, "Func1");
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equalSimd([-5033.2001953125, -11201.5, 665.3400268554687, 334.79998779296875], m.func2(), SIMD.Float32x4, "Func2");
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equalSimd([-5033.2001953125, -11201.5, 665.3400268554687, 334.79998779296875], m.func2(), SIMD.Float32x4, "Func2");
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equalSimd([-5033.2001953125, -3401, 665.3400268554687, -32234.099609375], m.func3(), SIMD.Float32x4, "Func3");
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equalSimd([-5033.2001953125, -3401, 665.3400268554687, -32234.099609375], m.func3(), SIMD.Float32x4, "Func3");
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equalSimd([5033.2001953125, 0, 665.3400268554687, 0], m.func4(), SIMD.Float32x4, "Func4");
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equalSimd([5033.2001953125, 0, 665.3400268554687, 0], m.func4(), SIMD.Float32x4, "Func4");
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equalSimd([-5033.2001953125, -3401, 665.3400268554687, 334.79998779296875], m.func5(), SIMD.Float32x4, "Func5");
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equalSimd([-5033.2001953125, -3401, 665.3400268554687, 334.79998779296875], m.func5(), SIMD.Float32x4, "Func5");
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equalSimd([1194580.375, 212344.125, 63236.9296875, 65534.98828125], m.func6(), SIMD.Float32x4, "Func6");
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equalSimd([1194580.375, 212344.125, 63236.9296875, 65534.98828125], m.func6(), SIMD.Float32x4, "Func6");
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print("PASS");

‎test/SIMD.int8x16.asmjs/testMisc.js‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -405,14 +405,14 @@ var ret7 = m.func7(v1, v2, v3, v1, v2);
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var ret8 = m.func8(v1, v2, v3, v1, v2);
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// printSimdBaseline(ret8, "SIMD.Int8x16", "ret8", "func8");
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//
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// equal(-1410, ret1);
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// equalSimd([1, 2, 3, 4, 3, 4, 5, 6, 1, 6, 0, 4, 6, 1, 4, 0], ret2, SIMD.Int8x16, "func2")
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// equalSimd([0, 1, 1, 1, 3, 3, 3, 3, 1, 3, 1, 1, 0, 0, 0, 0], ret3, SIMD.Int8x16, "func3")
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// equalSimd([120, 46, 79, 93, -95, -59, 7, 7, 120, 46, 79, 93, -95, -59, 7, 7], ret4, SIMD.Int8x16, "func4")
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// equalSimd([36, -23, 41, -92, 89, 16, 1, 0, 36, -23, 41, -92, 89, 16, 1, 0], ret5, SIMD.Int8x16, "func5")
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// equalSimd([48, -128, -104, -128, -1, -1, -17, -128, 48, -128, -104, -128, -1, -1, -17, -128], ret6, SIMD.Int8x16, "func6")
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// equalSimd([10, 20, 30, -10, -10, -20, -30, -40, -96, -16, 64, -102, 76, -14, -118, -10], ret7, SIMD.Int8x16, "func7")
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// equalSimd([121, -38, -37, 77, 17, -12, 29, -102, -30, -40, -112, -99, 86, -17, -57, -79], ret8, SIMD.Int8x16, "func8")
408+
equal(-1410, ret1);
409+
equalSimd([1, 2, 3, 4, 3, 4, 5, 6, 1, 6, 0, 4, 6, 1, 4, 0], ret2, SIMD.Int8x16, "func2")
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equalSimd([0, 1, 1, 1, 3, 3, 3, 3, 1, 3, 1, 1, 0, 0, 0, 0], ret3, SIMD.Int8x16, "func3")
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equalSimd([120, 46, 79, 93, -95, -59, 7, 7, 120, 46, 79, 93, -95, -59, 7, 7], ret4, SIMD.Int8x16, "func4")
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equalSimd([36, -23, 41, -92, 89, 16, 1, 0, 36, -23, 41, -92, 89, 16, 1, 0], ret5, SIMD.Int8x16, "func5")
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equalSimd([47, -128, -107, -128, -5, -6, -23, -128, 47, -128, -107, -128, -5, -6, -23, -128], ret6, SIMD.Int8x16, "func6")
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equalSimd([10, 20, 30, -10, -10, -20, -30, -40, -96, -16, 64, -102, 76, -14, -118, -10], ret7, SIMD.Int8x16, "func7")
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equalSimd([121, -38, -37, 77, 17, -12, 29, -102, -30, -40, -112, -99, 86, -17, -57, -79], ret8, SIMD.Int8x16, "func8")
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print("PASS");
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