Skip to content

Commit a167178

Browse files
KrovatkinKrovatkin
committed
commenting out float64x2 and removing xor/or/and/not for floats and min/max for ints
removing code under #if 0 moving ext opcodes in place of non ext ones
1 parent b41fc74 commit a167178

8 files changed

Lines changed: 29 additions & 262 deletions

File tree

‎lib/Backend/LowerMDShared.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -346,7 +346,6 @@ class LowererMD
346346
IR::Instr* Simd128LowerLessThan(IR::Instr* instr);
347347
IR::Instr* Simd128LowerLessThanOrEqual(IR::Instr* instr);
348348
IR::Instr* Simd128LowerGreaterThanOrEqual(IR::Instr* instr);
349-
IR::Instr* Simd128LowerMinMax(IR::Instr* instr);
350349
IR::Instr* Simd128LowerMinMax_F4(IR::Instr* instr);
351350
IR::Instr* Simd128LowerMinMaxNum(IR::Instr* instr);
352351
IR::Instr* Simd128LowerAnyTrue(IR::Instr* instr);

‎lib/Backend/LowerMDSharedSimd128.cpp‎

Lines changed: 2 additions & 156 deletions
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,6 @@ bool LowererMD::Simd128TryLowerMappedInstruction(IR::Instr *instr)
6969
break;
7070
#endif // 0
7171

72-
case Js::OpCode::Simd128_Not_F4:
7372
case Js::OpCode::Simd128_Not_I4:
7473
case Js::OpCode::Simd128_Not_I16:
7574
case Js::OpCode::Simd128_Not_I8:
@@ -343,16 +342,6 @@ IR::Instr* LowererMD::Simd128LowerUnMappedInstruction(IR::Instr *instr)
343342
case Js::OpCode::Simd128_GtEq_I16:
344343
return Simd128LowerGreaterThanOrEqual(instr);
345344

346-
case Js::OpCode::Simd128_Min_I4:
347-
case Js::OpCode::Simd128_Max_I4:
348-
case Js::OpCode::Simd128_Min_I16:
349-
case Js::OpCode::Simd128_Max_I16:
350-
case Js::OpCode::Simd128_Min_U4:
351-
case Js::OpCode::Simd128_Max_U4:
352-
case Js::OpCode::Simd128_Min_U8:
353-
case Js::OpCode::Simd128_Max_U8:
354-
return Simd128LowerMinMax(instr);
355-
356345
case Js::OpCode::Simd128_Min_F4:
357346
case Js::OpCode::Simd128_Max_F4:
358347
return Simd128LowerMinMax_F4(instr);
@@ -2189,143 +2178,6 @@ IR::Instr* LowererMD::Simd128LowerGreaterThanOrEqual(IR::Instr* instr)
21892178
return pInstr;
21902179
}
21912180

2192-
IR::Instr* LowererMD::Simd128LowerMinMax(IR::Instr* instr)
2193-
{
2194-
Assert(instr->m_opcode == Js::OpCode::Simd128_Min_I4 || instr->m_opcode == Js::OpCode::Simd128_Max_I4 ||
2195-
instr->m_opcode == Js::OpCode::Simd128_Min_I16 || instr->m_opcode == Js::OpCode::Simd128_Max_I16 ||
2196-
instr->m_opcode == Js::OpCode::Simd128_Min_U4 || instr->m_opcode == Js::OpCode::Simd128_Max_U4 ||
2197-
instr->m_opcode == Js::OpCode::Simd128_Min_U8 || instr->m_opcode == Js::OpCode::Simd128_Max_U8 );
2198-
2199-
IR::Instr *pInstr;
2200-
IR::Opnd* dst = instr->GetDst();
2201-
IR::Opnd* src1 = instr->GetSrc1();
2202-
IR::Opnd* src2 = instr->GetSrc2();
2203-
Assert(dst->IsRegOpnd() && dst->IsSimd128());
2204-
Assert(src1->IsRegOpnd() && src1->IsSimd128());
2205-
Assert(src2->IsRegOpnd() && src2->IsSimd128());
2206-
IR::RegOpnd* tmp1 = IR::RegOpnd::New(src1->GetType(), m_func);
2207-
IR::RegOpnd* tmp2 = IR::RegOpnd::New(src1->GetType(), m_func);
2208-
IR::RegOpnd* mask = IR::RegOpnd::New(src1->GetType(), m_func);
2209-
IR::RegOpnd* tmpT = IR::RegOpnd::New(src1->GetType(), m_func);
2210-
IR::RegOpnd* tmpF = IR::RegOpnd::New(src1->GetType(), m_func);
2211-
2212-
if (instr->m_opcode == Js::OpCode::Simd128_Min_I4 || instr->m_opcode == Js::OpCode::Simd128_Max_I4 ||
2213-
instr->m_opcode == Js::OpCode::Simd128_Min_I16 || instr->m_opcode == Js::OpCode::Simd128_Max_I16 ||
2214-
instr->m_opcode == Js::OpCode::Simd128_Min_U4 || instr->m_opcode == Js::OpCode::Simd128_Max_U4)
2215-
{
2216-
// uint32x4.min/max:
2217-
// tmp1 = pxor src1, xmmword ptr [__xmm@X86_DWORD_SIGNBITS]
2218-
// tmp2 = pxor src2, xmmword ptr [__xmm@X86_DWORD_SIGNBITS]
2219-
2220-
// int32x4.min/max or int8x16.min/max:
2221-
// movaps tmp1, src1
2222-
// movaps tmp2, src2
2223-
2224-
if (instr->m_opcode == Js::OpCode::Simd128_Min_U4 || instr->m_opcode == Js::OpCode::Simd128_Max_U4)
2225-
{
2226-
pInstr = IR::Instr::New(Js::OpCode::PXOR, tmp1, src1, IR::MemRefOpnd::New((void*)&X86_DWORD_SIGNBITS, TySimd128I4, m_func), m_func);
2227-
instr->InsertBefore(pInstr);
2228-
Legalize(pInstr);
2229-
2230-
pInstr = IR::Instr::New(Js::OpCode::PXOR, tmp2, src2, IR::MemRefOpnd::New((void*)&X86_DWORD_SIGNBITS, TySimd128I4, m_func), m_func);
2231-
instr->InsertBefore(pInstr);
2232-
Legalize(pInstr);
2233-
}
2234-
else
2235-
{
2236-
pInstr = IR::Instr::New(Js::OpCode::MOVAPS, tmp1, src1, m_func);
2237-
instr->InsertBefore(pInstr);
2238-
Legalize(pInstr);
2239-
2240-
pInstr = IR::Instr::New(Js::OpCode::MOVAPS, tmp2, src2, m_func);
2241-
instr->InsertBefore(pInstr);
2242-
Legalize(pInstr);
2243-
}
2244-
2245-
// mask = pcmpgtd tmp1, tmp2 (swap src for Min, pcmpgtb: int8x16)
2246-
// tmpT = pand mask, tmp1
2247-
// tmpF = pandn mask, tmp2
2248-
// dst = por tmpT, tmpF
2249-
Js::OpCode cmpOpcode = Js::OpCode::PCMPGTD;
2250-
if (instr->m_opcode == Js::OpCode::Simd128_Min_I16 || instr->m_opcode == Js::OpCode::Simd128_Max_I16)
2251-
{
2252-
cmpOpcode = Js::OpCode::PCMPGTB;
2253-
}
2254-
2255-
// mask = pcmpgtd src1, src2 [pcmpgtb]
2256-
if (instr->m_opcode == Js::OpCode::Simd128_Min_I4 || instr->m_opcode == Js::OpCode::Simd128_Min_I16 ||
2257-
instr->m_opcode == Js::OpCode::Simd128_Min_U4)
2258-
{
2259-
pInstr = IR::Instr::New(cmpOpcode, mask, tmp2, tmp1, m_func); //swap src when is Min() case
2260-
}
2261-
else
2262-
{
2263-
pInstr = IR::Instr::New(cmpOpcode, mask, tmp1, tmp2, m_func);
2264-
}
2265-
instr->InsertBefore(pInstr);
2266-
Legalize(pInstr);
2267-
2268-
// tmpT = pand mask, src1
2269-
pInstr = IR::Instr::New(Js::OpCode::PAND, tmpT, mask, src1, m_func);
2270-
instr->InsertBefore(pInstr);
2271-
Legalize(pInstr);
2272-
2273-
// tmpF = pandn mask, src2
2274-
pInstr = IR::Instr::New(Js::OpCode::PANDN, tmpF, mask, src2, m_func);
2275-
instr->InsertBefore(pInstr);
2276-
Legalize(pInstr);
2277-
2278-
// dst = por tmpT, tmpF
2279-
pInstr = IR::Instr::New(Js::OpCode::POR, dst, tmpT, tmpF, m_func);
2280-
instr->InsertBefore(pInstr);
2281-
Legalize(pInstr);
2282-
}
2283-
else
2284-
{
2285-
Js::OpCode cmpOpcode = Js::OpCode::PMINSW;
2286-
if (instr->m_opcode == Js::OpCode::Simd128_Max_U8)
2287-
{
2288-
cmpOpcode = Js::OpCode::PMAXSW;
2289-
}
2290-
// uint16x8.min/max:
2291-
// movaps mask, xmmword ptr [@X86_WORD_SIGNBITS]
2292-
// tmp1 = pxor src1, mask
2293-
// tmp2 = pxor src2, mask
2294-
// dst = PMINSW tmp1, tmp2 [or PMAXSW]
2295-
// dst = pxor dst, mask
2296-
2297-
// movaps mask, xmmword ptr [@X86_WORD_SIGNBITS]
2298-
pInstr = IR::Instr::New(Js::OpCode::MOVAPS, mask, IR::MemRefOpnd::New((void*)&X86_WORD_SIGNBITS, TySimd128I4, m_func), m_func);
2299-
instr->InsertBefore(pInstr);
2300-
Legalize(pInstr);
2301-
2302-
// tmp1 = pxor src1, mask
2303-
pInstr = IR::Instr::New(Js::OpCode::PXOR, tmp1, src1, mask, m_func);
2304-
instr->InsertBefore(pInstr);
2305-
Legalize(pInstr);
2306-
2307-
// tmp2 = pxor src2, mask
2308-
pInstr = IR::Instr::New(Js::OpCode::PXOR, tmp2, src2, mask, m_func);
2309-
instr->InsertBefore(pInstr);
2310-
Legalize(pInstr);
2311-
2312-
// dst = PMINSW tmp1, tmp2 [or PMAXSW]
2313-
pInstr = IR::Instr::New(cmpOpcode, dst, tmp1, tmp2, m_func);
2314-
instr->InsertBefore(pInstr);
2315-
Legalize(pInstr);
2316-
2317-
// dst = pxor dst, mask
2318-
pInstr = IR::Instr::New(Js::OpCode::PXOR, dst, dst, mask, m_func);
2319-
instr->InsertBefore(pInstr);
2320-
Legalize(pInstr);
2321-
}
2322-
2323-
pInstr = instr->m_prev;
2324-
instr->Remove();
2325-
2326-
return pInstr;
2327-
}
2328-
23292181
IR::Instr* LowererMD::Simd128LowerMinMax_F4(IR::Instr* instr)
23302182
{
23312183
IR::Instr *pInstr;
@@ -3387,10 +3239,7 @@ void LowererMD::Simd128InitOpcodeMap()
33873239
SET_SIMDOPCODE(Simd128_Neq_F4 , CMPNEQPS); // CMPNEQPS
33883240
SET_SIMDOPCODE(Simd128_Gt_F4 , CMPLTPS); // CMPLTPS (swap srcs)
33893241
SET_SIMDOPCODE(Simd128_GtEq_F4 , CMPLEPS); // CMPLEPS (swap srcs)
3390-
SET_SIMDOPCODE(Simd128_And_F4 , ANDPS);
3391-
SET_SIMDOPCODE(Simd128_Or_F4 , ORPS);
3392-
SET_SIMDOPCODE(Simd128_Xor_F4 , XORPS );
3393-
SET_SIMDOPCODE(Simd128_Not_F4 , XORPS );
3242+
33943243

33953244
#if 0
33963245
SET_SIMDOPCODE(Simd128_FromFloat32x4_D2, CVTPS2PD);
@@ -3421,8 +3270,6 @@ void LowererMD::Simd128InitOpcodeMap()
34213270
SET_SIMDOPCODE(Simd128_Add_I8 , PADDW);
34223271
SET_SIMDOPCODE(Simd128_Sub_I8 , PSUBW);
34233272
SET_SIMDOPCODE(Simd128_Mul_I8 , PMULLW);
3424-
SET_SIMDOPCODE(Simd128_Min_I8 , PMINSW);
3425-
SET_SIMDOPCODE(Simd128_Max_I8 , PMAXSW);
34263273
SET_SIMDOPCODE(Simd128_Eq_I8 , PCMPEQW);
34273274
SET_SIMDOPCODE(Simd128_Lt_I8 , PCMPGTW); // (swap srcs)
34283275
SET_SIMDOPCODE(Simd128_Gt_I8 , PCMPGTW);
@@ -3457,8 +3304,7 @@ void LowererMD::Simd128InitOpcodeMap()
34573304
SET_SIMDOPCODE(Simd128_Not_U16 , XORPS);
34583305
SET_SIMDOPCODE(Simd128_Add_U16 , PADDB);
34593306
SET_SIMDOPCODE(Simd128_Sub_U16 , PSUBB);
3460-
SET_SIMDOPCODE(Simd128_Min_U16 , PMINUB);
3461-
SET_SIMDOPCODE(Simd128_Max_U16 , PMAXUB);
3307+
34623308
SET_SIMDOPCODE(Simd128_Eq_U16 , PCMPEQB); // same as int8x16.equal
34633309
SET_SIMDOPCODE(Simd128_AddSaturate_U16 , PADDUSB);
34643310
SET_SIMDOPCODE(Simd128_SubSaturate_U16 , PSUBUSB);

0 commit comments

Comments
 (0)