diff --git a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Application/Core/Src/main.c b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Application/Core/Src/main.c index dd30023..aec4734 100644 --- a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Application/Core/Src/main.c +++ b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Application/Core/Src/main.c @@ -36,7 +36,7 @@ /* Private macro -------------------------------------------------------------*/ /* USER CODE BEGIN PM */ #define MAJOR 0 //APP Major version Number -#define MINOR 2 //APP Minor version Number +#define MINOR 3 //APP Minor version Number /* USER CODE END PM */ /* Private variables ---------------------------------------------------------*/ @@ -101,9 +101,9 @@ int main(void) /* USER CODE BEGIN 3 */ HAL_GPIO_WritePin( GPIOB, GPIO_PIN_7, GPIO_PIN_SET ); - HAL_Delay(5000); //5 Sec delay + HAL_Delay(200); //5 Sec delay HAL_GPIO_WritePin( GPIOB, GPIO_PIN_7, GPIO_PIN_RESET ); - HAL_Delay(5000); //5 Sec delay + HAL_Delay(200); //5 Sec delay } /* USER CODE END 3 */ } diff --git a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Application/Debug/Blinky.bin b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Application/Debug/Blinky.bin index 05cd73b..0550538 100644 Binary files a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Application/Debug/Blinky.bin and b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Application/Debug/Blinky.bin differ diff --git a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Application/Debug/Blinky.list b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Application/Debug/Blinky.list index 07e6adb..3978c70 100644 --- a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Application/Debug/Blinky.list +++ b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Application/Debug/Blinky.list @@ -5,25 +5,25 @@ Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001f8 08040000 08040000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA - 1 .text 00003944 08040200 08040200 00010200 2**4 + 1 .text 00003940 08040200 08040200 00010200 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE - 2 .rodata 000000d0 08043b44 08043b44 00013b44 2**2 + 2 .rodata 000000d0 08043b40 08043b40 00013b40 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 3 .ARM.extab 00000000 08043c14 08043c14 00020070 2**0 + 3 .ARM.extab 00000000 08043c10 08043c10 00020070 2**0 CONTENTS - 4 .ARM 00000008 08043c14 08043c14 00013c14 2**2 + 4 .ARM 00000008 08043c10 08043c10 00013c10 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 5 .preinit_array 00000000 08043c1c 08043c1c 00020070 2**0 + 5 .preinit_array 00000000 08043c18 08043c18 00020070 2**0 CONTENTS, ALLOC, LOAD, DATA - 6 .init_array 00000004 08043c1c 08043c1c 00013c1c 2**2 + 6 .init_array 00000004 08043c18 08043c18 00013c18 2**2 CONTENTS, ALLOC, LOAD, DATA - 7 .fini_array 00000004 08043c20 08043c20 00013c20 2**2 + 7 .fini_array 00000004 08043c1c 08043c1c 00013c1c 2**2 CONTENTS, ALLOC, LOAD, DATA - 8 .data 00000070 20000000 08043c24 00020000 2**2 + 8 .data 00000070 20000000 08043c20 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA - 9 .bss 000000c0 20000070 08043c94 00020070 2**2 + 9 .bss 000000c0 20000070 08043c90 00020070 2**2 ALLOC - 10 ._user_heap_stack 00000600 20000130 08043c94 00020130 2**0 + 10 ._user_heap_stack 00000600 20000130 08043c90 00020130 2**0 ALLOC 11 .ARM.attributes 0000002e 00000000 00000000 00020070 2**0 CONTENTS, READONLY @@ -37,13 +37,13 @@ Idx Name Size VMA LMA File off Algn CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 000277c6 00000000 00000000 0002bf58 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 17 .debug_line 0000881c 00000000 00000000 0005371e 2**0 + 17 .debug_line 00008818 00000000 00000000 0005371e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 18 .debug_str 000f1d82 00000000 00000000 0005bf3a 2**0 + 18 .debug_str 000f1d82 00000000 00000000 0005bf36 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 19 .comment 00000053 00000000 00000000 0014dcbc 2**0 + 19 .comment 00000053 00000000 00000000 0014dcb8 2**0 CONTENTS, READONLY - 20 .debug_frame 000024e0 00000000 00000000 0014dd10 2**2 + 20 .debug_frame 000024e0 00000000 00000000 0014dd0c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: @@ -62,7 +62,7 @@ Disassembly of section .text: 8040216: bd10 pop {r4, pc} 8040218: 20000070 .word 0x20000070 804021c: 00000000 .word 0x00000000 - 8040220: 08043b2c .word 0x08043b2c + 8040220: 08043b28 .word 0x08043b28 08040224 : 8040224: b508 push {r3, lr} @@ -74,7 +74,7 @@ Disassembly of section .text: 8040232: bd08 pop {r3, pc} 8040234: 00000000 .word 0x00000000 8040238: 20000074 .word 0x20000074 - 804023c: 08043b2c .word 0x08043b2c + 804023c: 08043b28 .word 0x08043b28 08040240 : 8040240: f001 01ff and.w r1, r1, #255 ; 0xff @@ -426,8293 +426,8293 @@ int main(void) /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); - 80405dc: f000 fa99 bl 8040b12 + 80405dc: f000 fa97 bl 8040b0e /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); - 80405e0: f000 f822 bl 8040628 + 80405e0: f000 f820 bl 8040624 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); - 80405e4: f000 f8ca bl 804077c + 80405e4: f000 f8c8 bl 8040778 MX_USART3_UART_Init(); - 80405e8: f000 f898 bl 804071c + 80405e8: f000 f896 bl 8040718 /* USER CODE BEGIN 2 */ printf("Starting Application(%d.%d)\r\n", APP_Version[0], APP_Version[1] ); 80405ec: 2300 movs r3, #0 - 80405ee: 2202 movs r2, #2 + 80405ee: 2203 movs r2, #3 80405f0: 4619 mov r1, r3 - 80405f2: 480b ldr r0, [pc, #44] ; (8040620 ) - 80405f4: f002 fb44 bl 8042c80 + 80405f2: 480a ldr r0, [pc, #40] ; (804061c ) + 80405f4: f002 fb42 bl 8042c7c while (1) { /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ - HAL_GPIO_WritePin( GPIOB, GPIO_PIN_7, GPIO_PIN_SET ); + HAL_GPIO_WritePin( GPIOB, GPIO_PIN_7, GPIO_PIN_SET ); 80405f8: 2201 movs r2, #1 80405fa: 2180 movs r1, #128 ; 0x80 - 80405fc: 4809 ldr r0, [pc, #36] ; (8040624 ) - 80405fe: f000 fd9b bl 8041138 - HAL_Delay(5000); //5 Sec delay - 8040602: f241 3088 movw r0, #5000 ; 0x1388 - 8040606: f000 fae1 bl 8040bcc - HAL_GPIO_WritePin( GPIOB, GPIO_PIN_7, GPIO_PIN_RESET ); - 804060a: 2200 movs r2, #0 - 804060c: 2180 movs r1, #128 ; 0x80 - 804060e: 4805 ldr r0, [pc, #20] ; (8040624 ) - 8040610: f000 fd92 bl 8041138 - HAL_Delay(5000); //5 Sec delay - 8040614: f241 3088 movw r0, #5000 ; 0x1388 - 8040618: f000 fad8 bl 8040bcc - HAL_GPIO_WritePin( GPIOB, GPIO_PIN_7, GPIO_PIN_SET ); - 804061c: e7ec b.n 80405f8 - 804061e: bf00 nop - 8040620: 08043b44 .word 0x08043b44 - 8040624: 40020400 .word 0x40020400 - -08040628 : + 80405fc: 4808 ldr r0, [pc, #32] ; (8040620 ) + 80405fe: f000 fd99 bl 8041134 + HAL_Delay(200); //5 Sec delay + 8040602: 20c8 movs r0, #200 ; 0xc8 + 8040604: f000 fae0 bl 8040bc8 + HAL_GPIO_WritePin( GPIOB, GPIO_PIN_7, GPIO_PIN_RESET ); + 8040608: 2200 movs r2, #0 + 804060a: 2180 movs r1, #128 ; 0x80 + 804060c: 4804 ldr r0, [pc, #16] ; (8040620 ) + 804060e: f000 fd91 bl 8041134 + HAL_Delay(200); //5 Sec delay + 8040612: 20c8 movs r0, #200 ; 0xc8 + 8040614: f000 fad8 bl 8040bc8 + HAL_GPIO_WritePin( GPIOB, GPIO_PIN_7, GPIO_PIN_SET ); + 8040618: e7ee b.n 80405f8 + 804061a: bf00 nop + 804061c: 08043b40 .word 0x08043b40 + 8040620: 40020400 .word 0x40020400 + +08040624 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { - 8040628: b580 push {r7, lr} - 804062a: b0b8 sub sp, #224 ; 0xe0 - 804062c: af00 add r7, sp, #0 + 8040624: b580 push {r7, lr} + 8040626: b0b8 sub sp, #224 ; 0xe0 + 8040628: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - 804062e: f107 03ac add.w r3, r7, #172 ; 0xac - 8040632: 2234 movs r2, #52 ; 0x34 - 8040634: 2100 movs r1, #0 - 8040636: 4618 mov r0, r3 - 8040638: f002 fb1a bl 8042c70 + 804062a: f107 03ac add.w r3, r7, #172 ; 0xac + 804062e: 2234 movs r2, #52 ; 0x34 + 8040630: 2100 movs r1, #0 + 8040632: 4618 mov r0, r3 + 8040634: f002 fb1a bl 8042c6c RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - 804063c: f107 0398 add.w r3, r7, #152 ; 0x98 - 8040640: 2200 movs r2, #0 - 8040642: 601a str r2, [r3, #0] - 8040644: 605a str r2, [r3, #4] - 8040646: 609a str r2, [r3, #8] - 8040648: 60da str r2, [r3, #12] - 804064a: 611a str r2, [r3, #16] + 8040638: f107 0398 add.w r3, r7, #152 ; 0x98 + 804063c: 2200 movs r2, #0 + 804063e: 601a str r2, [r3, #0] + 8040640: 605a str r2, [r3, #4] + 8040642: 609a str r2, [r3, #8] + 8040644: 60da str r2, [r3, #12] + 8040646: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - 804064c: f107 0308 add.w r3, r7, #8 - 8040650: 2290 movs r2, #144 ; 0x90 - 8040652: 2100 movs r1, #0 - 8040654: 4618 mov r0, r3 - 8040656: f002 fb0b bl 8042c70 + 8040648: f107 0308 add.w r3, r7, #8 + 804064c: 2290 movs r2, #144 ; 0x90 + 804064e: 2100 movs r1, #0 + 8040650: 4618 mov r0, r3 + 8040652: f002 fb0b bl 8042c6c /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); - 804065a: 4b2e ldr r3, [pc, #184] ; (8040714 ) - 804065c: 6c1b ldr r3, [r3, #64] ; 0x40 - 804065e: 4a2d ldr r2, [pc, #180] ; (8040714 ) - 8040660: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 8040664: 6413 str r3, [r2, #64] ; 0x40 - 8040666: 4b2b ldr r3, [pc, #172] ; (8040714 ) - 8040668: 6c1b ldr r3, [r3, #64] ; 0x40 - 804066a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 804066e: 607b str r3, [r7, #4] - 8040670: 687b ldr r3, [r7, #4] + 8040656: 4b2e ldr r3, [pc, #184] ; (8040710 ) + 8040658: 6c1b ldr r3, [r3, #64] ; 0x40 + 804065a: 4a2d ldr r2, [pc, #180] ; (8040710 ) + 804065c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8040660: 6413 str r3, [r2, #64] ; 0x40 + 8040662: 4b2b ldr r3, [pc, #172] ; (8040710 ) + 8040664: 6c1b ldr r3, [r3, #64] ; 0x40 + 8040666: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 804066a: 607b str r3, [r7, #4] + 804066c: 687b ldr r3, [r7, #4] __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); - 8040672: 4b29 ldr r3, [pc, #164] ; (8040718 ) - 8040674: 681b ldr r3, [r3, #0] - 8040676: f423 4340 bic.w r3, r3, #49152 ; 0xc000 - 804067a: 4a27 ldr r2, [pc, #156] ; (8040718 ) - 804067c: f443 4380 orr.w r3, r3, #16384 ; 0x4000 - 8040680: 6013 str r3, [r2, #0] - 8040682: 4b25 ldr r3, [pc, #148] ; (8040718 ) - 8040684: 681b ldr r3, [r3, #0] - 8040686: f403 4340 and.w r3, r3, #49152 ; 0xc000 - 804068a: 603b str r3, [r7, #0] - 804068c: 683b ldr r3, [r7, #0] + 804066e: 4b29 ldr r3, [pc, #164] ; (8040714 ) + 8040670: 681b ldr r3, [r3, #0] + 8040672: f423 4340 bic.w r3, r3, #49152 ; 0xc000 + 8040676: 4a27 ldr r2, [pc, #156] ; (8040714 ) + 8040678: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 804067c: 6013 str r3, [r2, #0] + 804067e: 4b25 ldr r3, [pc, #148] ; (8040714 ) + 8040680: 681b ldr r3, [r3, #0] + 8040682: f403 4340 and.w r3, r3, #49152 ; 0xc000 + 8040686: 603b str r3, [r7, #0] + 8040688: 683b ldr r3, [r7, #0] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - 804068e: 2302 movs r3, #2 - 8040690: f8c7 30ac str.w r3, [r7, #172] ; 0xac + 804068a: 2302 movs r3, #2 + 804068c: f8c7 30ac str.w r3, [r7, #172] ; 0xac RCC_OscInitStruct.HSIState = RCC_HSI_ON; - 8040694: 2301 movs r3, #1 - 8040696: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 + 8040690: 2301 movs r3, #1 + 8040692: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - 804069a: 2310 movs r3, #16 - 804069c: f8c7 30bc str.w r3, [r7, #188] ; 0xbc + 8040696: 2310 movs r3, #16 + 8040698: f8c7 30bc str.w r3, [r7, #188] ; 0xbc RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - 80406a0: 2300 movs r3, #0 - 80406a2: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 + 804069c: 2300 movs r3, #0 + 804069e: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - 80406a6: f107 03ac add.w r3, r7, #172 ; 0xac - 80406aa: 4618 mov r0, r3 - 80406ac: f000 fd5e bl 804116c - 80406b0: 4603 mov r3, r0 - 80406b2: 2b00 cmp r3, #0 - 80406b4: d001 beq.n 80406ba + 80406a2: f107 03ac add.w r3, r7, #172 ; 0xac + 80406a6: 4618 mov r0, r3 + 80406a8: f000 fd5e bl 8041168 + 80406ac: 4603 mov r3, r0 + 80406ae: 2b00 cmp r3, #0 + 80406b0: d001 beq.n 80406b6 { Error_Handler(); - 80406b6: f000 f8b1 bl 804081c + 80406b2: f000 f8b1 bl 8040818 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - 80406ba: 230f movs r3, #15 - 80406bc: f8c7 3098 str.w r3, [r7, #152] ; 0x98 + 80406b6: 230f movs r3, #15 + 80406b8: f8c7 3098 str.w r3, [r7, #152] ; 0x98 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; - 80406c0: 2300 movs r3, #0 - 80406c2: f8c7 309c str.w r3, [r7, #156] ; 0x9c + 80406bc: 2300 movs r3, #0 + 80406be: f8c7 309c str.w r3, [r7, #156] ; 0x9c RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - 80406c6: 2300 movs r3, #0 - 80406c8: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 + 80406c2: 2300 movs r3, #0 + 80406c4: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - 80406cc: 2300 movs r3, #0 - 80406ce: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 + 80406c8: 2300 movs r3, #0 + 80406ca: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - 80406d2: 2300 movs r3, #0 - 80406d4: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 + 80406ce: 2300 movs r3, #0 + 80406d0: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) - 80406d8: f107 0398 add.w r3, r7, #152 ; 0x98 - 80406dc: 2100 movs r1, #0 - 80406de: 4618 mov r0, r3 - 80406e0: f000 fff2 bl 80416c8 - 80406e4: 4603 mov r3, r0 - 80406e6: 2b00 cmp r3, #0 - 80406e8: d001 beq.n 80406ee + 80406d4: f107 0398 add.w r3, r7, #152 ; 0x98 + 80406d8: 2100 movs r1, #0 + 80406da: 4618 mov r0, r3 + 80406dc: f000 fff2 bl 80416c4 + 80406e0: 4603 mov r3, r0 + 80406e2: 2b00 cmp r3, #0 + 80406e4: d001 beq.n 80406ea { Error_Handler(); - 80406ea: f000 f897 bl 804081c + 80406e6: f000 f897 bl 8040818 } PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3; - 80406ee: f44f 7380 mov.w r3, #256 ; 0x100 - 80406f2: 60bb str r3, [r7, #8] + 80406ea: f44f 7380 mov.w r3, #256 ; 0x100 + 80406ee: 60bb str r3, [r7, #8] PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; - 80406f4: 2300 movs r3, #0 - 80406f6: 657b str r3, [r7, #84] ; 0x54 + 80406f0: 2300 movs r3, #0 + 80406f2: 657b str r3, [r7, #84] ; 0x54 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - 80406f8: f107 0308 add.w r3, r7, #8 - 80406fc: 4618 mov r0, r3 - 80406fe: f001 f9b9 bl 8041a74 - 8040702: 4603 mov r3, r0 - 8040704: 2b00 cmp r3, #0 - 8040706: d001 beq.n 804070c + 80406f4: f107 0308 add.w r3, r7, #8 + 80406f8: 4618 mov r0, r3 + 80406fa: f001 f9b9 bl 8041a70 + 80406fe: 4603 mov r3, r0 + 8040700: 2b00 cmp r3, #0 + 8040702: d001 beq.n 8040708 { Error_Handler(); - 8040708: f000 f888 bl 804081c + 8040704: f000 f888 bl 8040818 } } - 804070c: bf00 nop - 804070e: 37e0 adds r7, #224 ; 0xe0 - 8040710: 46bd mov sp, r7 - 8040712: bd80 pop {r7, pc} - 8040714: 40023800 .word 0x40023800 - 8040718: 40007000 .word 0x40007000 - -0804071c : + 8040708: bf00 nop + 804070a: 37e0 adds r7, #224 ; 0xe0 + 804070c: 46bd mov sp, r7 + 804070e: bd80 pop {r7, pc} + 8040710: 40023800 .word 0x40023800 + 8040714: 40007000 .word 0x40007000 + +08040718 : * @brief USART3 Initialization Function * @param None * @retval None */ static void MX_USART3_UART_Init(void) { - 804071c: b580 push {r7, lr} - 804071e: af00 add r7, sp, #0 + 8040718: b580 push {r7, lr} + 804071a: af00 add r7, sp, #0 /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; - 8040720: 4b14 ldr r3, [pc, #80] ; (8040774 ) - 8040722: 4a15 ldr r2, [pc, #84] ; (8040778 ) - 8040724: 601a str r2, [r3, #0] + 804071c: 4b14 ldr r3, [pc, #80] ; (8040770 ) + 804071e: 4a15 ldr r2, [pc, #84] ; (8040774 ) + 8040720: 601a str r2, [r3, #0] huart3.Init.BaudRate = 115200; - 8040726: 4b13 ldr r3, [pc, #76] ; (8040774 ) - 8040728: f44f 32e1 mov.w r2, #115200 ; 0x1c200 - 804072c: 605a str r2, [r3, #4] + 8040722: 4b13 ldr r3, [pc, #76] ; (8040770 ) + 8040724: f44f 32e1 mov.w r2, #115200 ; 0x1c200 + 8040728: 605a str r2, [r3, #4] huart3.Init.WordLength = UART_WORDLENGTH_8B; - 804072e: 4b11 ldr r3, [pc, #68] ; (8040774 ) - 8040730: 2200 movs r2, #0 - 8040732: 609a str r2, [r3, #8] + 804072a: 4b11 ldr r3, [pc, #68] ; (8040770 ) + 804072c: 2200 movs r2, #0 + 804072e: 609a str r2, [r3, #8] huart3.Init.StopBits = UART_STOPBITS_1; - 8040734: 4b0f ldr r3, [pc, #60] ; (8040774 ) - 8040736: 2200 movs r2, #0 - 8040738: 60da str r2, [r3, #12] + 8040730: 4b0f ldr r3, [pc, #60] ; (8040770 ) + 8040732: 2200 movs r2, #0 + 8040734: 60da str r2, [r3, #12] huart3.Init.Parity = UART_PARITY_NONE; - 804073a: 4b0e ldr r3, [pc, #56] ; (8040774 ) - 804073c: 2200 movs r2, #0 - 804073e: 611a str r2, [r3, #16] + 8040736: 4b0e ldr r3, [pc, #56] ; (8040770 ) + 8040738: 2200 movs r2, #0 + 804073a: 611a str r2, [r3, #16] huart3.Init.Mode = UART_MODE_TX_RX; - 8040740: 4b0c ldr r3, [pc, #48] ; (8040774 ) - 8040742: 220c movs r2, #12 - 8040744: 615a str r2, [r3, #20] + 804073c: 4b0c ldr r3, [pc, #48] ; (8040770 ) + 804073e: 220c movs r2, #12 + 8040740: 615a str r2, [r3, #20] huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; - 8040746: 4b0b ldr r3, [pc, #44] ; (8040774 ) - 8040748: 2200 movs r2, #0 - 804074a: 619a str r2, [r3, #24] + 8040742: 4b0b ldr r3, [pc, #44] ; (8040770 ) + 8040744: 2200 movs r2, #0 + 8040746: 619a str r2, [r3, #24] huart3.Init.OverSampling = UART_OVERSAMPLING_16; - 804074c: 4b09 ldr r3, [pc, #36] ; (8040774 ) - 804074e: 2200 movs r2, #0 - 8040750: 61da str r2, [r3, #28] + 8040748: 4b09 ldr r3, [pc, #36] ; (8040770 ) + 804074a: 2200 movs r2, #0 + 804074c: 61da str r2, [r3, #28] huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - 8040752: 4b08 ldr r3, [pc, #32] ; (8040774 ) - 8040754: 2200 movs r2, #0 - 8040756: 621a str r2, [r3, #32] + 804074e: 4b08 ldr r3, [pc, #32] ; (8040770 ) + 8040750: 2200 movs r2, #0 + 8040752: 621a str r2, [r3, #32] huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - 8040758: 4b06 ldr r3, [pc, #24] ; (8040774 ) - 804075a: 2200 movs r2, #0 - 804075c: 625a str r2, [r3, #36] ; 0x24 + 8040754: 4b06 ldr r3, [pc, #24] ; (8040770 ) + 8040756: 2200 movs r2, #0 + 8040758: 625a str r2, [r3, #36] ; 0x24 if (HAL_UART_Init(&huart3) != HAL_OK) - 804075e: 4805 ldr r0, [pc, #20] ; (8040774 ) - 8040760: f001 fdb0 bl 80422c4 - 8040764: 4603 mov r3, r0 - 8040766: 2b00 cmp r3, #0 - 8040768: d001 beq.n 804076e + 804075a: 4805 ldr r0, [pc, #20] ; (8040770 ) + 804075c: f001 fdb0 bl 80422c0 + 8040760: 4603 mov r3, r0 + 8040762: 2b00 cmp r3, #0 + 8040764: d001 beq.n 804076a { Error_Handler(); - 804076a: f000 f857 bl 804081c + 8040766: f000 f857 bl 8040818 } /* USER CODE BEGIN USART3_Init 2 */ /* USER CODE END USART3_Init 2 */ } + 804076a: bf00 nop + 804076c: bd80 pop {r7, pc} 804076e: bf00 nop - 8040770: bd80 pop {r7, pc} - 8040772: bf00 nop - 8040774: 20000098 .word 0x20000098 - 8040778: 40004800 .word 0x40004800 + 8040770: 20000098 .word 0x20000098 + 8040774: 40004800 .word 0x40004800 -0804077c : +08040778 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { - 804077c: b580 push {r7, lr} - 804077e: b088 sub sp, #32 - 8040780: af00 add r7, sp, #0 + 8040778: b580 push {r7, lr} + 804077a: b088 sub sp, #32 + 804077c: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8040782: f107 030c add.w r3, r7, #12 - 8040786: 2200 movs r2, #0 - 8040788: 601a str r2, [r3, #0] - 804078a: 605a str r2, [r3, #4] - 804078c: 609a str r2, [r3, #8] - 804078e: 60da str r2, [r3, #12] - 8040790: 611a str r2, [r3, #16] + 804077e: f107 030c add.w r3, r7, #12 + 8040782: 2200 movs r2, #0 + 8040784: 601a str r2, [r3, #0] + 8040786: 605a str r2, [r3, #4] + 8040788: 609a str r2, [r3, #8] + 804078a: 60da str r2, [r3, #12] + 804078c: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOD_CLK_ENABLE(); - 8040792: 4b17 ldr r3, [pc, #92] ; (80407f0 ) - 8040794: 6b1b ldr r3, [r3, #48] ; 0x30 - 8040796: 4a16 ldr r2, [pc, #88] ; (80407f0 ) - 8040798: f043 0308 orr.w r3, r3, #8 - 804079c: 6313 str r3, [r2, #48] ; 0x30 - 804079e: 4b14 ldr r3, [pc, #80] ; (80407f0 ) - 80407a0: 6b1b ldr r3, [r3, #48] ; 0x30 - 80407a2: f003 0308 and.w r3, r3, #8 - 80407a6: 60bb str r3, [r7, #8] - 80407a8: 68bb ldr r3, [r7, #8] + 804078e: 4b17 ldr r3, [pc, #92] ; (80407ec ) + 8040790: 6b1b ldr r3, [r3, #48] ; 0x30 + 8040792: 4a16 ldr r2, [pc, #88] ; (80407ec ) + 8040794: f043 0308 orr.w r3, r3, #8 + 8040798: 6313 str r3, [r2, #48] ; 0x30 + 804079a: 4b14 ldr r3, [pc, #80] ; (80407ec ) + 804079c: 6b1b ldr r3, [r3, #48] ; 0x30 + 804079e: f003 0308 and.w r3, r3, #8 + 80407a2: 60bb str r3, [r7, #8] + 80407a4: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); - 80407aa: 4b11 ldr r3, [pc, #68] ; (80407f0 ) - 80407ac: 6b1b ldr r3, [r3, #48] ; 0x30 - 80407ae: 4a10 ldr r2, [pc, #64] ; (80407f0 ) - 80407b0: f043 0302 orr.w r3, r3, #2 - 80407b4: 6313 str r3, [r2, #48] ; 0x30 - 80407b6: 4b0e ldr r3, [pc, #56] ; (80407f0 ) - 80407b8: 6b1b ldr r3, [r3, #48] ; 0x30 - 80407ba: f003 0302 and.w r3, r3, #2 - 80407be: 607b str r3, [r7, #4] - 80407c0: 687b ldr r3, [r7, #4] + 80407a6: 4b11 ldr r3, [pc, #68] ; (80407ec ) + 80407a8: 6b1b ldr r3, [r3, #48] ; 0x30 + 80407aa: 4a10 ldr r2, [pc, #64] ; (80407ec ) + 80407ac: f043 0302 orr.w r3, r3, #2 + 80407b0: 6313 str r3, [r2, #48] ; 0x30 + 80407b2: 4b0e ldr r3, [pc, #56] ; (80407ec ) + 80407b4: 6b1b ldr r3, [r3, #48] ; 0x30 + 80407b6: f003 0302 and.w r3, r3, #2 + 80407ba: 607b str r3, [r7, #4] + 80407bc: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_RESET); - 80407c2: 2200 movs r2, #0 - 80407c4: 2180 movs r1, #128 ; 0x80 - 80407c6: 480b ldr r0, [pc, #44] ; (80407f4 ) - 80407c8: f000 fcb6 bl 8041138 + 80407be: 2200 movs r2, #0 + 80407c0: 2180 movs r1, #128 ; 0x80 + 80407c2: 480b ldr r0, [pc, #44] ; (80407f0 ) + 80407c4: f000 fcb6 bl 8041134 /*Configure GPIO pin : PB7 */ GPIO_InitStruct.Pin = GPIO_PIN_7; - 80407cc: 2380 movs r3, #128 ; 0x80 - 80407ce: 60fb str r3, [r7, #12] + 80407c8: 2380 movs r3, #128 ; 0x80 + 80407ca: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 80407d0: 2301 movs r3, #1 - 80407d2: 613b str r3, [r7, #16] + 80407cc: 2301 movs r3, #1 + 80407ce: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; - 80407d4: 2300 movs r3, #0 - 80407d6: 617b str r3, [r7, #20] + 80407d0: 2300 movs r3, #0 + 80407d2: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 80407d8: 2300 movs r3, #0 - 80407da: 61bb str r3, [r7, #24] + 80407d4: 2300 movs r3, #0 + 80407d6: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - 80407dc: f107 030c add.w r3, r7, #12 - 80407e0: 4619 mov r1, r3 - 80407e2: 4804 ldr r0, [pc, #16] ; (80407f4 ) - 80407e4: f000 fafc bl 8040de0 + 80407d8: f107 030c add.w r3, r7, #12 + 80407dc: 4619 mov r1, r3 + 80407de: 4804 ldr r0, [pc, #16] ; (80407f0 ) + 80407e0: f000 fafc bl 8040ddc } - 80407e8: bf00 nop - 80407ea: 3720 adds r7, #32 - 80407ec: 46bd mov sp, r7 - 80407ee: bd80 pop {r7, pc} - 80407f0: 40023800 .word 0x40023800 - 80407f4: 40020400 .word 0x40020400 - -080407f8 <__io_putchar>: + 80407e4: bf00 nop + 80407e6: 3720 adds r7, #32 + 80407e8: 46bd mov sp, r7 + 80407ea: bd80 pop {r7, pc} + 80407ec: 40023800 .word 0x40023800 + 80407f0: 40020400 .word 0x40020400 + +080407f4 <__io_putchar>: set to 'Yes') calls __io_putchar() */ int __io_putchar(int ch) #else int fputc(int ch, FILE *f) #endif /* __GNUC__ */ { - 80407f8: b580 push {r7, lr} - 80407fa: b082 sub sp, #8 - 80407fc: af00 add r7, sp, #0 - 80407fe: 6078 str r0, [r7, #4] + 80407f4: b580 push {r7, lr} + 80407f6: b082 sub sp, #8 + 80407f8: af00 add r7, sp, #0 + 80407fa: 6078 str r0, [r7, #4] /* Place your implementation of fputc here */ /* e.g. write a character to the UART3 and Loop until the end of transmission */ HAL_UART_Transmit(&huart3, (uint8_t *)&ch, 1, HAL_MAX_DELAY); - 8040800: 1d39 adds r1, r7, #4 - 8040802: f04f 33ff mov.w r3, #4294967295 - 8040806: 2201 movs r2, #1 - 8040808: 4803 ldr r0, [pc, #12] ; (8040818 <__io_putchar+0x20>) - 804080a: f001 fda9 bl 8042360 + 80407fc: 1d39 adds r1, r7, #4 + 80407fe: f04f 33ff mov.w r3, #4294967295 + 8040802: 2201 movs r2, #1 + 8040804: 4803 ldr r0, [pc, #12] ; (8040814 <__io_putchar+0x20>) + 8040806: f001 fda9 bl 804235c return ch; - 804080e: 687b ldr r3, [r7, #4] + 804080a: 687b ldr r3, [r7, #4] } - 8040810: 4618 mov r0, r3 - 8040812: 3708 adds r7, #8 - 8040814: 46bd mov sp, r7 - 8040816: bd80 pop {r7, pc} - 8040818: 20000098 .word 0x20000098 + 804080c: 4618 mov r0, r3 + 804080e: 3708 adds r7, #8 + 8040810: 46bd mov sp, r7 + 8040812: bd80 pop {r7, pc} + 8040814: 20000098 .word 0x20000098 -0804081c : +08040818 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { - 804081c: b480 push {r7} - 804081e: af00 add r7, sp, #0 + 8040818: b480 push {r7} + 804081a: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); - 8040820: b672 cpsid i + 804081c: b672 cpsid i } - 8040822: bf00 nop + 804081e: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) - 8040824: e7fe b.n 8040824 + 8040820: e7fe b.n 8040820 ... -08040828 : +08040824 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { - 8040828: b480 push {r7} - 804082a: b083 sub sp, #12 - 804082c: af00 add r7, sp, #0 + 8040824: b480 push {r7} + 8040826: b083 sub sp, #12 + 8040828: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_PWR_CLK_ENABLE(); - 804082e: 4b0f ldr r3, [pc, #60] ; (804086c ) - 8040830: 6c1b ldr r3, [r3, #64] ; 0x40 - 8040832: 4a0e ldr r2, [pc, #56] ; (804086c ) - 8040834: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 8040838: 6413 str r3, [r2, #64] ; 0x40 - 804083a: 4b0c ldr r3, [pc, #48] ; (804086c ) - 804083c: 6c1b ldr r3, [r3, #64] ; 0x40 - 804083e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8040842: 607b str r3, [r7, #4] - 8040844: 687b ldr r3, [r7, #4] + 804082a: 4b0f ldr r3, [pc, #60] ; (8040868 ) + 804082c: 6c1b ldr r3, [r3, #64] ; 0x40 + 804082e: 4a0e ldr r2, [pc, #56] ; (8040868 ) + 8040830: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8040834: 6413 str r3, [r2, #64] ; 0x40 + 8040836: 4b0c ldr r3, [pc, #48] ; (8040868 ) + 8040838: 6c1b ldr r3, [r3, #64] ; 0x40 + 804083a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 804083e: 607b str r3, [r7, #4] + 8040840: 687b ldr r3, [r7, #4] __HAL_RCC_SYSCFG_CLK_ENABLE(); - 8040846: 4b09 ldr r3, [pc, #36] ; (804086c ) - 8040848: 6c5b ldr r3, [r3, #68] ; 0x44 - 804084a: 4a08 ldr r2, [pc, #32] ; (804086c ) - 804084c: f443 4380 orr.w r3, r3, #16384 ; 0x4000 - 8040850: 6453 str r3, [r2, #68] ; 0x44 - 8040852: 4b06 ldr r3, [pc, #24] ; (804086c ) - 8040854: 6c5b ldr r3, [r3, #68] ; 0x44 - 8040856: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 804085a: 603b str r3, [r7, #0] - 804085c: 683b ldr r3, [r7, #0] + 8040842: 4b09 ldr r3, [pc, #36] ; (8040868 ) + 8040844: 6c5b ldr r3, [r3, #68] ; 0x44 + 8040846: 4a08 ldr r2, [pc, #32] ; (8040868 ) + 8040848: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 804084c: 6453 str r3, [r2, #68] ; 0x44 + 804084e: 4b06 ldr r3, [pc, #24] ; (8040868 ) + 8040850: 6c5b ldr r3, [r3, #68] ; 0x44 + 8040852: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8040856: 603b str r3, [r7, #0] + 8040858: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } - 804085e: bf00 nop - 8040860: 370c adds r7, #12 - 8040862: 46bd mov sp, r7 - 8040864: f85d 7b04 ldr.w r7, [sp], #4 - 8040868: 4770 bx lr - 804086a: bf00 nop - 804086c: 40023800 .word 0x40023800 - -08040870 : + 804085a: bf00 nop + 804085c: 370c adds r7, #12 + 804085e: 46bd mov sp, r7 + 8040860: f85d 7b04 ldr.w r7, [sp], #4 + 8040864: 4770 bx lr + 8040866: bf00 nop + 8040868: 40023800 .word 0x40023800 + +0804086c : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { - 8040870: b580 push {r7, lr} - 8040872: b08a sub sp, #40 ; 0x28 - 8040874: af00 add r7, sp, #0 - 8040876: 6078 str r0, [r7, #4] + 804086c: b580 push {r7, lr} + 804086e: b08a sub sp, #40 ; 0x28 + 8040870: af00 add r7, sp, #0 + 8040872: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8040878: f107 0314 add.w r3, r7, #20 - 804087c: 2200 movs r2, #0 - 804087e: 601a str r2, [r3, #0] - 8040880: 605a str r2, [r3, #4] - 8040882: 609a str r2, [r3, #8] - 8040884: 60da str r2, [r3, #12] - 8040886: 611a str r2, [r3, #16] + 8040874: f107 0314 add.w r3, r7, #20 + 8040878: 2200 movs r2, #0 + 804087a: 601a str r2, [r3, #0] + 804087c: 605a str r2, [r3, #4] + 804087e: 609a str r2, [r3, #8] + 8040880: 60da str r2, [r3, #12] + 8040882: 611a str r2, [r3, #16] if(huart->Instance==USART3) - 8040888: 687b ldr r3, [r7, #4] - 804088a: 681b ldr r3, [r3, #0] - 804088c: 4a17 ldr r2, [pc, #92] ; (80408ec ) - 804088e: 4293 cmp r3, r2 - 8040890: d128 bne.n 80408e4 + 8040884: 687b ldr r3, [r7, #4] + 8040886: 681b ldr r3, [r3, #0] + 8040888: 4a17 ldr r2, [pc, #92] ; (80408e8 ) + 804088a: 4293 cmp r3, r2 + 804088c: d128 bne.n 80408e0 { /* USER CODE BEGIN USART3_MspInit 0 */ /* USER CODE END USART3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART3_CLK_ENABLE(); - 8040892: 4b17 ldr r3, [pc, #92] ; (80408f0 ) - 8040894: 6c1b ldr r3, [r3, #64] ; 0x40 - 8040896: 4a16 ldr r2, [pc, #88] ; (80408f0 ) - 8040898: f443 2380 orr.w r3, r3, #262144 ; 0x40000 - 804089c: 6413 str r3, [r2, #64] ; 0x40 - 804089e: 4b14 ldr r3, [pc, #80] ; (80408f0 ) - 80408a0: 6c1b ldr r3, [r3, #64] ; 0x40 - 80408a2: f403 2380 and.w r3, r3, #262144 ; 0x40000 - 80408a6: 613b str r3, [r7, #16] - 80408a8: 693b ldr r3, [r7, #16] + 804088e: 4b17 ldr r3, [pc, #92] ; (80408ec ) + 8040890: 6c1b ldr r3, [r3, #64] ; 0x40 + 8040892: 4a16 ldr r2, [pc, #88] ; (80408ec ) + 8040894: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 8040898: 6413 str r3, [r2, #64] ; 0x40 + 804089a: 4b14 ldr r3, [pc, #80] ; (80408ec ) + 804089c: 6c1b ldr r3, [r3, #64] ; 0x40 + 804089e: f403 2380 and.w r3, r3, #262144 ; 0x40000 + 80408a2: 613b str r3, [r7, #16] + 80408a4: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOD_CLK_ENABLE(); - 80408aa: 4b11 ldr r3, [pc, #68] ; (80408f0 ) - 80408ac: 6b1b ldr r3, [r3, #48] ; 0x30 - 80408ae: 4a10 ldr r2, [pc, #64] ; (80408f0 ) - 80408b0: f043 0308 orr.w r3, r3, #8 - 80408b4: 6313 str r3, [r2, #48] ; 0x30 - 80408b6: 4b0e ldr r3, [pc, #56] ; (80408f0 ) - 80408b8: 6b1b ldr r3, [r3, #48] ; 0x30 - 80408ba: f003 0308 and.w r3, r3, #8 - 80408be: 60fb str r3, [r7, #12] - 80408c0: 68fb ldr r3, [r7, #12] + 80408a6: 4b11 ldr r3, [pc, #68] ; (80408ec ) + 80408a8: 6b1b ldr r3, [r3, #48] ; 0x30 + 80408aa: 4a10 ldr r2, [pc, #64] ; (80408ec ) + 80408ac: f043 0308 orr.w r3, r3, #8 + 80408b0: 6313 str r3, [r2, #48] ; 0x30 + 80408b2: 4b0e ldr r3, [pc, #56] ; (80408ec ) + 80408b4: 6b1b ldr r3, [r3, #48] ; 0x30 + 80408b6: f003 0308 and.w r3, r3, #8 + 80408ba: 60fb str r3, [r7, #12] + 80408bc: 68fb ldr r3, [r7, #12] /**USART3 GPIO Configuration PD8 ------> USART3_TX PD9 ------> USART3_RX */ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; - 80408c2: f44f 7340 mov.w r3, #768 ; 0x300 - 80408c6: 617b str r3, [r7, #20] + 80408be: f44f 7340 mov.w r3, #768 ; 0x300 + 80408c2: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 80408c8: 2302 movs r3, #2 - 80408ca: 61bb str r3, [r7, #24] + 80408c4: 2302 movs r3, #2 + 80408c6: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; - 80408cc: 2300 movs r3, #0 - 80408ce: 61fb str r3, [r7, #28] + 80408c8: 2300 movs r3, #0 + 80408ca: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - 80408d0: 2303 movs r3, #3 - 80408d2: 623b str r3, [r7, #32] + 80408cc: 2303 movs r3, #3 + 80408ce: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF7_USART3; - 80408d4: 2307 movs r3, #7 - 80408d6: 627b str r3, [r7, #36] ; 0x24 + 80408d0: 2307 movs r3, #7 + 80408d2: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - 80408d8: f107 0314 add.w r3, r7, #20 - 80408dc: 4619 mov r1, r3 - 80408de: 4805 ldr r0, [pc, #20] ; (80408f4 ) - 80408e0: f000 fa7e bl 8040de0 + 80408d4: f107 0314 add.w r3, r7, #20 + 80408d8: 4619 mov r1, r3 + 80408da: 4805 ldr r0, [pc, #20] ; (80408f0 ) + 80408dc: f000 fa7e bl 8040ddc /* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE END USART3_MspInit 1 */ } } - 80408e4: bf00 nop - 80408e6: 3728 adds r7, #40 ; 0x28 - 80408e8: 46bd mov sp, r7 - 80408ea: bd80 pop {r7, pc} - 80408ec: 40004800 .word 0x40004800 - 80408f0: 40023800 .word 0x40023800 - 80408f4: 40020c00 .word 0x40020c00 - -080408f8 : + 80408e0: bf00 nop + 80408e2: 3728 adds r7, #40 ; 0x28 + 80408e4: 46bd mov sp, r7 + 80408e6: bd80 pop {r7, pc} + 80408e8: 40004800 .word 0x40004800 + 80408ec: 40023800 .word 0x40023800 + 80408f0: 40020c00 .word 0x40020c00 + +080408f4 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { - 80408f8: b480 push {r7} - 80408fa: af00 add r7, sp, #0 + 80408f4: b480 push {r7} + 80408f6: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) - 80408fc: e7fe b.n 80408fc + 80408f8: e7fe b.n 80408f8 -080408fe : +080408fa : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { - 80408fe: b480 push {r7} - 8040900: af00 add r7, sp, #0 + 80408fa: b480 push {r7} + 80408fc: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) - 8040902: e7fe b.n 8040902 + 80408fe: e7fe b.n 80408fe -08040904 : +08040900 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { - 8040904: b480 push {r7} - 8040906: af00 add r7, sp, #0 + 8040900: b480 push {r7} + 8040902: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) - 8040908: e7fe b.n 8040908 + 8040904: e7fe b.n 8040904 -0804090a : +08040906 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { - 804090a: b480 push {r7} - 804090c: af00 add r7, sp, #0 + 8040906: b480 push {r7} + 8040908: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) - 804090e: e7fe b.n 804090e + 804090a: e7fe b.n 804090a -08040910 : +0804090c : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { - 8040910: b480 push {r7} - 8040912: af00 add r7, sp, #0 + 804090c: b480 push {r7} + 804090e: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) - 8040914: e7fe b.n 8040914 + 8040910: e7fe b.n 8040910 -08040916 : +08040912 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { - 8040916: b480 push {r7} - 8040918: af00 add r7, sp, #0 + 8040912: b480 push {r7} + 8040914: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } - 804091a: bf00 nop - 804091c: 46bd mov sp, r7 - 804091e: f85d 7b04 ldr.w r7, [sp], #4 - 8040922: 4770 bx lr + 8040916: bf00 nop + 8040918: 46bd mov sp, r7 + 804091a: f85d 7b04 ldr.w r7, [sp], #4 + 804091e: 4770 bx lr -08040924 : +08040920 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { - 8040924: b480 push {r7} - 8040926: af00 add r7, sp, #0 + 8040920: b480 push {r7} + 8040922: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } - 8040928: bf00 nop - 804092a: 46bd mov sp, r7 - 804092c: f85d 7b04 ldr.w r7, [sp], #4 - 8040930: 4770 bx lr + 8040924: bf00 nop + 8040926: 46bd mov sp, r7 + 8040928: f85d 7b04 ldr.w r7, [sp], #4 + 804092c: 4770 bx lr -08040932 : +0804092e : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { - 8040932: b480 push {r7} - 8040934: af00 add r7, sp, #0 + 804092e: b480 push {r7} + 8040930: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } - 8040936: bf00 nop - 8040938: 46bd mov sp, r7 - 804093a: f85d 7b04 ldr.w r7, [sp], #4 - 804093e: 4770 bx lr + 8040932: bf00 nop + 8040934: 46bd mov sp, r7 + 8040936: f85d 7b04 ldr.w r7, [sp], #4 + 804093a: 4770 bx lr -08040940 : +0804093c : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { - 8040940: b580 push {r7, lr} - 8040942: af00 add r7, sp, #0 + 804093c: b580 push {r7, lr} + 804093e: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); - 8040944: f000 f922 bl 8040b8c + 8040940: f000 f922 bl 8040b88 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } - 8040948: bf00 nop - 804094a: bd80 pop {r7, pc} + 8040944: bf00 nop + 8040946: bd80 pop {r7, pc} -0804094c <_read>: +08040948 <_read>: _kill(status, -1); while (1) {} /* Make sure we hang here */ } __attribute__((weak)) int _read(int file, char *ptr, int len) { - 804094c: b580 push {r7, lr} - 804094e: b086 sub sp, #24 - 8040950: af00 add r7, sp, #0 - 8040952: 60f8 str r0, [r7, #12] - 8040954: 60b9 str r1, [r7, #8] - 8040956: 607a str r2, [r7, #4] + 8040948: b580 push {r7, lr} + 804094a: b086 sub sp, #24 + 804094c: af00 add r7, sp, #0 + 804094e: 60f8 str r0, [r7, #12] + 8040950: 60b9 str r1, [r7, #8] + 8040952: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) - 8040958: 2300 movs r3, #0 - 804095a: 617b str r3, [r7, #20] - 804095c: e00a b.n 8040974 <_read+0x28> + 8040954: 2300 movs r3, #0 + 8040956: 617b str r3, [r7, #20] + 8040958: e00a b.n 8040970 <_read+0x28> { *ptr++ = __io_getchar(); - 804095e: f3af 8000 nop.w - 8040962: 4601 mov r1, r0 - 8040964: 68bb ldr r3, [r7, #8] - 8040966: 1c5a adds r2, r3, #1 - 8040968: 60ba str r2, [r7, #8] - 804096a: b2ca uxtb r2, r1 - 804096c: 701a strb r2, [r3, #0] + 804095a: f3af 8000 nop.w + 804095e: 4601 mov r1, r0 + 8040960: 68bb ldr r3, [r7, #8] + 8040962: 1c5a adds r2, r3, #1 + 8040964: 60ba str r2, [r7, #8] + 8040966: b2ca uxtb r2, r1 + 8040968: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) - 804096e: 697b ldr r3, [r7, #20] - 8040970: 3301 adds r3, #1 - 8040972: 617b str r3, [r7, #20] - 8040974: 697a ldr r2, [r7, #20] - 8040976: 687b ldr r3, [r7, #4] - 8040978: 429a cmp r2, r3 - 804097a: dbf0 blt.n 804095e <_read+0x12> + 804096a: 697b ldr r3, [r7, #20] + 804096c: 3301 adds r3, #1 + 804096e: 617b str r3, [r7, #20] + 8040970: 697a ldr r2, [r7, #20] + 8040972: 687b ldr r3, [r7, #4] + 8040974: 429a cmp r2, r3 + 8040976: dbf0 blt.n 804095a <_read+0x12> } return len; - 804097c: 687b ldr r3, [r7, #4] + 8040978: 687b ldr r3, [r7, #4] } - 804097e: 4618 mov r0, r3 - 8040980: 3718 adds r7, #24 - 8040982: 46bd mov sp, r7 - 8040984: bd80 pop {r7, pc} + 804097a: 4618 mov r0, r3 + 804097c: 3718 adds r7, #24 + 804097e: 46bd mov sp, r7 + 8040980: bd80 pop {r7, pc} -08040986 <_write>: +08040982 <_write>: __attribute__((weak)) int _write(int file, char *ptr, int len) { - 8040986: b580 push {r7, lr} - 8040988: b086 sub sp, #24 - 804098a: af00 add r7, sp, #0 - 804098c: 60f8 str r0, [r7, #12] - 804098e: 60b9 str r1, [r7, #8] - 8040990: 607a str r2, [r7, #4] + 8040982: b580 push {r7, lr} + 8040984: b086 sub sp, #24 + 8040986: af00 add r7, sp, #0 + 8040988: 60f8 str r0, [r7, #12] + 804098a: 60b9 str r1, [r7, #8] + 804098c: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) - 8040992: 2300 movs r3, #0 - 8040994: 617b str r3, [r7, #20] - 8040996: e009 b.n 80409ac <_write+0x26> + 804098e: 2300 movs r3, #0 + 8040990: 617b str r3, [r7, #20] + 8040992: e009 b.n 80409a8 <_write+0x26> { __io_putchar(*ptr++); - 8040998: 68bb ldr r3, [r7, #8] - 804099a: 1c5a adds r2, r3, #1 - 804099c: 60ba str r2, [r7, #8] - 804099e: 781b ldrb r3, [r3, #0] - 80409a0: 4618 mov r0, r3 - 80409a2: f7ff ff29 bl 80407f8 <__io_putchar> + 8040994: 68bb ldr r3, [r7, #8] + 8040996: 1c5a adds r2, r3, #1 + 8040998: 60ba str r2, [r7, #8] + 804099a: 781b ldrb r3, [r3, #0] + 804099c: 4618 mov r0, r3 + 804099e: f7ff ff29 bl 80407f4 <__io_putchar> for (DataIdx = 0; DataIdx < len; DataIdx++) - 80409a6: 697b ldr r3, [r7, #20] - 80409a8: 3301 adds r3, #1 - 80409aa: 617b str r3, [r7, #20] - 80409ac: 697a ldr r2, [r7, #20] - 80409ae: 687b ldr r3, [r7, #4] - 80409b0: 429a cmp r2, r3 - 80409b2: dbf1 blt.n 8040998 <_write+0x12> + 80409a2: 697b ldr r3, [r7, #20] + 80409a4: 3301 adds r3, #1 + 80409a6: 617b str r3, [r7, #20] + 80409a8: 697a ldr r2, [r7, #20] + 80409aa: 687b ldr r3, [r7, #4] + 80409ac: 429a cmp r2, r3 + 80409ae: dbf1 blt.n 8040994 <_write+0x12> } return len; - 80409b4: 687b ldr r3, [r7, #4] + 80409b0: 687b ldr r3, [r7, #4] } - 80409b6: 4618 mov r0, r3 - 80409b8: 3718 adds r7, #24 - 80409ba: 46bd mov sp, r7 - 80409bc: bd80 pop {r7, pc} + 80409b2: 4618 mov r0, r3 + 80409b4: 3718 adds r7, #24 + 80409b6: 46bd mov sp, r7 + 80409b8: bd80 pop {r7, pc} -080409be <_close>: +080409ba <_close>: int _close(int file) { - 80409be: b480 push {r7} - 80409c0: b083 sub sp, #12 - 80409c2: af00 add r7, sp, #0 - 80409c4: 6078 str r0, [r7, #4] + 80409ba: b480 push {r7} + 80409bc: b083 sub sp, #12 + 80409be: af00 add r7, sp, #0 + 80409c0: 6078 str r0, [r7, #4] return -1; - 80409c6: f04f 33ff mov.w r3, #4294967295 + 80409c2: f04f 33ff mov.w r3, #4294967295 } - 80409ca: 4618 mov r0, r3 - 80409cc: 370c adds r7, #12 - 80409ce: 46bd mov sp, r7 - 80409d0: f85d 7b04 ldr.w r7, [sp], #4 - 80409d4: 4770 bx lr + 80409c6: 4618 mov r0, r3 + 80409c8: 370c adds r7, #12 + 80409ca: 46bd mov sp, r7 + 80409cc: f85d 7b04 ldr.w r7, [sp], #4 + 80409d0: 4770 bx lr -080409d6 <_fstat>: +080409d2 <_fstat>: int _fstat(int file, struct stat *st) { - 80409d6: b480 push {r7} - 80409d8: b083 sub sp, #12 - 80409da: af00 add r7, sp, #0 - 80409dc: 6078 str r0, [r7, #4] - 80409de: 6039 str r1, [r7, #0] + 80409d2: b480 push {r7} + 80409d4: b083 sub sp, #12 + 80409d6: af00 add r7, sp, #0 + 80409d8: 6078 str r0, [r7, #4] + 80409da: 6039 str r1, [r7, #0] st->st_mode = S_IFCHR; - 80409e0: 683b ldr r3, [r7, #0] - 80409e2: f44f 5200 mov.w r2, #8192 ; 0x2000 - 80409e6: 605a str r2, [r3, #4] + 80409dc: 683b ldr r3, [r7, #0] + 80409de: f44f 5200 mov.w r2, #8192 ; 0x2000 + 80409e2: 605a str r2, [r3, #4] return 0; - 80409e8: 2300 movs r3, #0 + 80409e4: 2300 movs r3, #0 } - 80409ea: 4618 mov r0, r3 - 80409ec: 370c adds r7, #12 - 80409ee: 46bd mov sp, r7 - 80409f0: f85d 7b04 ldr.w r7, [sp], #4 - 80409f4: 4770 bx lr + 80409e6: 4618 mov r0, r3 + 80409e8: 370c adds r7, #12 + 80409ea: 46bd mov sp, r7 + 80409ec: f85d 7b04 ldr.w r7, [sp], #4 + 80409f0: 4770 bx lr -080409f6 <_isatty>: +080409f2 <_isatty>: int _isatty(int file) { - 80409f6: b480 push {r7} - 80409f8: b083 sub sp, #12 - 80409fa: af00 add r7, sp, #0 - 80409fc: 6078 str r0, [r7, #4] + 80409f2: b480 push {r7} + 80409f4: b083 sub sp, #12 + 80409f6: af00 add r7, sp, #0 + 80409f8: 6078 str r0, [r7, #4] return 1; - 80409fe: 2301 movs r3, #1 + 80409fa: 2301 movs r3, #1 } - 8040a00: 4618 mov r0, r3 - 8040a02: 370c adds r7, #12 - 8040a04: 46bd mov sp, r7 - 8040a06: f85d 7b04 ldr.w r7, [sp], #4 - 8040a0a: 4770 bx lr + 80409fc: 4618 mov r0, r3 + 80409fe: 370c adds r7, #12 + 8040a00: 46bd mov sp, r7 + 8040a02: f85d 7b04 ldr.w r7, [sp], #4 + 8040a06: 4770 bx lr -08040a0c <_lseek>: +08040a08 <_lseek>: int _lseek(int file, int ptr, int dir) { - 8040a0c: b480 push {r7} - 8040a0e: b085 sub sp, #20 - 8040a10: af00 add r7, sp, #0 - 8040a12: 60f8 str r0, [r7, #12] - 8040a14: 60b9 str r1, [r7, #8] - 8040a16: 607a str r2, [r7, #4] + 8040a08: b480 push {r7} + 8040a0a: b085 sub sp, #20 + 8040a0c: af00 add r7, sp, #0 + 8040a0e: 60f8 str r0, [r7, #12] + 8040a10: 60b9 str r1, [r7, #8] + 8040a12: 607a str r2, [r7, #4] return 0; - 8040a18: 2300 movs r3, #0 + 8040a14: 2300 movs r3, #0 } - 8040a1a: 4618 mov r0, r3 - 8040a1c: 3714 adds r7, #20 - 8040a1e: 46bd mov sp, r7 - 8040a20: f85d 7b04 ldr.w r7, [sp], #4 - 8040a24: 4770 bx lr + 8040a16: 4618 mov r0, r3 + 8040a18: 3714 adds r7, #20 + 8040a1a: 46bd mov sp, r7 + 8040a1c: f85d 7b04 ldr.w r7, [sp], #4 + 8040a20: 4770 bx lr ... -08040a28 <_sbrk>: +08040a24 <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { - 8040a28: b580 push {r7, lr} - 8040a2a: b086 sub sp, #24 - 8040a2c: af00 add r7, sp, #0 - 8040a2e: 6078 str r0, [r7, #4] + 8040a24: b580 push {r7, lr} + 8040a26: b086 sub sp, #24 + 8040a28: af00 add r7, sp, #0 + 8040a2a: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; - 8040a30: 4a14 ldr r2, [pc, #80] ; (8040a84 <_sbrk+0x5c>) - 8040a32: 4b15 ldr r3, [pc, #84] ; (8040a88 <_sbrk+0x60>) - 8040a34: 1ad3 subs r3, r2, r3 - 8040a36: 617b str r3, [r7, #20] + 8040a2c: 4a14 ldr r2, [pc, #80] ; (8040a80 <_sbrk+0x5c>) + 8040a2e: 4b15 ldr r3, [pc, #84] ; (8040a84 <_sbrk+0x60>) + 8040a30: 1ad3 subs r3, r2, r3 + 8040a32: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; - 8040a38: 697b ldr r3, [r7, #20] - 8040a3a: 613b str r3, [r7, #16] + 8040a34: 697b ldr r3, [r7, #20] + 8040a36: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) - 8040a3c: 4b13 ldr r3, [pc, #76] ; (8040a8c <_sbrk+0x64>) - 8040a3e: 681b ldr r3, [r3, #0] - 8040a40: 2b00 cmp r3, #0 - 8040a42: d102 bne.n 8040a4a <_sbrk+0x22> + 8040a38: 4b13 ldr r3, [pc, #76] ; (8040a88 <_sbrk+0x64>) + 8040a3a: 681b ldr r3, [r3, #0] + 8040a3c: 2b00 cmp r3, #0 + 8040a3e: d102 bne.n 8040a46 <_sbrk+0x22> { __sbrk_heap_end = &_end; - 8040a44: 4b11 ldr r3, [pc, #68] ; (8040a8c <_sbrk+0x64>) - 8040a46: 4a12 ldr r2, [pc, #72] ; (8040a90 <_sbrk+0x68>) - 8040a48: 601a str r2, [r3, #0] + 8040a40: 4b11 ldr r3, [pc, #68] ; (8040a88 <_sbrk+0x64>) + 8040a42: 4a12 ldr r2, [pc, #72] ; (8040a8c <_sbrk+0x68>) + 8040a44: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) - 8040a4a: 4b10 ldr r3, [pc, #64] ; (8040a8c <_sbrk+0x64>) - 8040a4c: 681a ldr r2, [r3, #0] - 8040a4e: 687b ldr r3, [r7, #4] - 8040a50: 4413 add r3, r2 - 8040a52: 693a ldr r2, [r7, #16] - 8040a54: 429a cmp r2, r3 - 8040a56: d207 bcs.n 8040a68 <_sbrk+0x40> + 8040a46: 4b10 ldr r3, [pc, #64] ; (8040a88 <_sbrk+0x64>) + 8040a48: 681a ldr r2, [r3, #0] + 8040a4a: 687b ldr r3, [r7, #4] + 8040a4c: 4413 add r3, r2 + 8040a4e: 693a ldr r2, [r7, #16] + 8040a50: 429a cmp r2, r3 + 8040a52: d207 bcs.n 8040a64 <_sbrk+0x40> { errno = ENOMEM; - 8040a58: f002 f8e0 bl 8042c1c <__errno> - 8040a5c: 4603 mov r3, r0 - 8040a5e: 220c movs r2, #12 - 8040a60: 601a str r2, [r3, #0] + 8040a54: f002 f8e0 bl 8042c18 <__errno> + 8040a58: 4603 mov r3, r0 + 8040a5a: 220c movs r2, #12 + 8040a5c: 601a str r2, [r3, #0] return (void *)-1; - 8040a62: f04f 33ff mov.w r3, #4294967295 - 8040a66: e009 b.n 8040a7c <_sbrk+0x54> + 8040a5e: f04f 33ff mov.w r3, #4294967295 + 8040a62: e009 b.n 8040a78 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; - 8040a68: 4b08 ldr r3, [pc, #32] ; (8040a8c <_sbrk+0x64>) - 8040a6a: 681b ldr r3, [r3, #0] - 8040a6c: 60fb str r3, [r7, #12] + 8040a64: 4b08 ldr r3, [pc, #32] ; (8040a88 <_sbrk+0x64>) + 8040a66: 681b ldr r3, [r3, #0] + 8040a68: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; - 8040a6e: 4b07 ldr r3, [pc, #28] ; (8040a8c <_sbrk+0x64>) - 8040a70: 681a ldr r2, [r3, #0] - 8040a72: 687b ldr r3, [r7, #4] - 8040a74: 4413 add r3, r2 - 8040a76: 4a05 ldr r2, [pc, #20] ; (8040a8c <_sbrk+0x64>) - 8040a78: 6013 str r3, [r2, #0] + 8040a6a: 4b07 ldr r3, [pc, #28] ; (8040a88 <_sbrk+0x64>) + 8040a6c: 681a ldr r2, [r3, #0] + 8040a6e: 687b ldr r3, [r7, #4] + 8040a70: 4413 add r3, r2 + 8040a72: 4a05 ldr r2, [pc, #20] ; (8040a88 <_sbrk+0x64>) + 8040a74: 6013 str r3, [r2, #0] return (void *)prev_heap_end; - 8040a7a: 68fb ldr r3, [r7, #12] + 8040a76: 68fb ldr r3, [r7, #12] } - 8040a7c: 4618 mov r0, r3 - 8040a7e: 3718 adds r7, #24 - 8040a80: 46bd mov sp, r7 - 8040a82: bd80 pop {r7, pc} - 8040a84: 20080000 .word 0x20080000 - 8040a88: 00000400 .word 0x00000400 - 8040a8c: 2000008c .word 0x2000008c - 8040a90: 20000130 .word 0x20000130 - -08040a94 : + 8040a78: 4618 mov r0, r3 + 8040a7a: 3718 adds r7, #24 + 8040a7c: 46bd mov sp, r7 + 8040a7e: bd80 pop {r7, pc} + 8040a80: 20080000 .word 0x20080000 + 8040a84: 00000400 .word 0x00000400 + 8040a88: 2000008c .word 0x2000008c + 8040a8c: 20000130 .word 0x20000130 + +08040a90 : * SystemFrequency variable. * @param None * @retval None */ void SystemInit(void) { - 8040a94: b480 push {r7} - 8040a96: af00 add r7, sp, #0 + 8040a90: b480 push {r7} + 8040a92: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - 8040a98: 4b07 ldr r3, [pc, #28] ; (8040ab8 ) - 8040a9a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8040a9e: 4a06 ldr r2, [pc, #24] ; (8040ab8 ) - 8040aa0: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 - 8040aa4: f8c2 3088 str.w r3, [r2, #136] ; 0x88 + 8040a94: 4b07 ldr r3, [pc, #28] ; (8040ab4 ) + 8040a96: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8040a9a: 4a06 ldr r2, [pc, #24] ; (8040ab4 ) + 8040a9c: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 + 8040aa0: f8c2 3088 str.w r3, [r2, #136] ; 0x88 #endif /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ - 8040aa8: 4b03 ldr r3, [pc, #12] ; (8040ab8 ) - 8040aaa: 4a04 ldr r2, [pc, #16] ; (8040abc ) - 8040aac: 609a str r2, [r3, #8] + 8040aa4: 4b03 ldr r3, [pc, #12] ; (8040ab4 ) + 8040aa6: 4a04 ldr r2, [pc, #16] ; (8040ab8 ) + 8040aa8: 609a str r2, [r3, #8] #endif /* USER_VECT_TAB_ADDRESS */ } - 8040aae: bf00 nop - 8040ab0: 46bd mov sp, r7 - 8040ab2: f85d 7b04 ldr.w r7, [sp], #4 - 8040ab6: 4770 bx lr - 8040ab8: e000ed00 .word 0xe000ed00 - 8040abc: 08040000 .word 0x08040000 + 8040aaa: bf00 nop + 8040aac: 46bd mov sp, r7 + 8040aae: f85d 7b04 ldr.w r7, [sp], #4 + 8040ab2: 4770 bx lr + 8040ab4: e000ed00 .word 0xe000ed00 + 8040ab8: 08040000 .word 0x08040000 -08040ac0 : +08040abc : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ - 8040ac0: f8df d034 ldr.w sp, [pc, #52] ; 8040af8 + 8040abc: f8df d034 ldr.w sp, [pc, #52] ; 8040af4 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata - 8040ac4: 480d ldr r0, [pc, #52] ; (8040afc ) + 8040ac0: 480d ldr r0, [pc, #52] ; (8040af8 ) ldr r1, =_edata - 8040ac6: 490e ldr r1, [pc, #56] ; (8040b00 ) + 8040ac2: 490e ldr r1, [pc, #56] ; (8040afc ) ldr r2, =_sidata - 8040ac8: 4a0e ldr r2, [pc, #56] ; (8040b04 ) + 8040ac4: 4a0e ldr r2, [pc, #56] ; (8040b00 ) movs r3, #0 - 8040aca: 2300 movs r3, #0 + 8040ac6: 2300 movs r3, #0 b LoopCopyDataInit - 8040acc: e002 b.n 8040ad4 + 8040ac8: e002 b.n 8040ad0 -08040ace : +08040aca : CopyDataInit: ldr r4, [r2, r3] - 8040ace: 58d4 ldr r4, [r2, r3] + 8040aca: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] - 8040ad0: 50c4 str r4, [r0, r3] + 8040acc: 50c4 str r4, [r0, r3] adds r3, r3, #4 - 8040ad2: 3304 adds r3, #4 + 8040ace: 3304 adds r3, #4 -08040ad4 : +08040ad0 : LoopCopyDataInit: adds r4, r0, r3 - 8040ad4: 18c4 adds r4, r0, r3 + 8040ad0: 18c4 adds r4, r0, r3 cmp r4, r1 - 8040ad6: 428c cmp r4, r1 + 8040ad2: 428c cmp r4, r1 bcc CopyDataInit - 8040ad8: d3f9 bcc.n 8040ace + 8040ad4: d3f9 bcc.n 8040aca /* Zero fill the bss segment. */ ldr r2, =_sbss - 8040ada: 4a0b ldr r2, [pc, #44] ; (8040b08 ) + 8040ad6: 4a0b ldr r2, [pc, #44] ; (8040b04 ) ldr r4, =_ebss - 8040adc: 4c0b ldr r4, [pc, #44] ; (8040b0c ) + 8040ad8: 4c0b ldr r4, [pc, #44] ; (8040b08 ) movs r3, #0 - 8040ade: 2300 movs r3, #0 + 8040ada: 2300 movs r3, #0 b LoopFillZerobss - 8040ae0: e001 b.n 8040ae6 + 8040adc: e001 b.n 8040ae2 -08040ae2 : +08040ade : FillZerobss: str r3, [r2] - 8040ae2: 6013 str r3, [r2, #0] + 8040ade: 6013 str r3, [r2, #0] adds r2, r2, #4 - 8040ae4: 3204 adds r2, #4 + 8040ae0: 3204 adds r2, #4 -08040ae6 : +08040ae2 : LoopFillZerobss: cmp r2, r4 - 8040ae6: 42a2 cmp r2, r4 + 8040ae2: 42a2 cmp r2, r4 bcc FillZerobss - 8040ae8: d3fb bcc.n 8040ae2 + 8040ae4: d3fb bcc.n 8040ade /* Call the clock system initialization function.*/ bl SystemInit - 8040aea: f7ff ffd3 bl 8040a94 + 8040ae6: f7ff ffd3 bl 8040a90 /* Call static constructors */ bl __libc_init_array - 8040aee: f002 f89b bl 8042c28 <__libc_init_array> + 8040aea: f002 f89b bl 8042c24 <__libc_init_array> /* Call the application's entry point.*/ bl main - 8040af2: f7ff fd71 bl 80405d8
+ 8040aee: f7ff fd73 bl 80405d8
bx lr - 8040af6: 4770 bx lr + 8040af2: 4770 bx lr ldr sp, =_estack /* set stack pointer */ - 8040af8: 20080000 .word 0x20080000 + 8040af4: 20080000 .word 0x20080000 ldr r0, =_sdata - 8040afc: 20000000 .word 0x20000000 + 8040af8: 20000000 .word 0x20000000 ldr r1, =_edata - 8040b00: 20000070 .word 0x20000070 + 8040afc: 20000070 .word 0x20000070 ldr r2, =_sidata - 8040b04: 08043c24 .word 0x08043c24 + 8040b00: 08043c20 .word 0x08043c20 ldr r2, =_sbss - 8040b08: 20000070 .word 0x20000070 + 8040b04: 20000070 .word 0x20000070 ldr r4, =_ebss - 8040b0c: 20000130 .word 0x20000130 + 8040b08: 20000130 .word 0x20000130 -08040b10 : +08040b0c : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop - 8040b10: e7fe b.n 8040b10 + 8040b0c: e7fe b.n 8040b0c -08040b12 : +08040b0e : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { - 8040b12: b580 push {r7, lr} - 8040b14: af00 add r7, sp, #0 + 8040b0e: b580 push {r7, lr} + 8040b10: af00 add r7, sp, #0 #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - 8040b16: 2003 movs r0, #3 - 8040b18: f000 f92e bl 8040d78 + 8040b12: 2003 movs r0, #3 + 8040b14: f000 f92e bl 8040d74 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); - 8040b1c: 2000 movs r0, #0 - 8040b1e: f000 f805 bl 8040b2c + 8040b18: 2000 movs r0, #0 + 8040b1a: f000 f805 bl 8040b28 /* Init the low level hardware */ HAL_MspInit(); - 8040b22: f7ff fe81 bl 8040828 + 8040b1e: f7ff fe81 bl 8040824 /* Return function status */ return HAL_OK; - 8040b26: 2300 movs r3, #0 + 8040b22: 2300 movs r3, #0 } - 8040b28: 4618 mov r0, r3 - 8040b2a: bd80 pop {r7, pc} + 8040b24: 4618 mov r0, r3 + 8040b26: bd80 pop {r7, pc} -08040b2c : +08040b28 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - 8040b2c: b580 push {r7, lr} - 8040b2e: b082 sub sp, #8 - 8040b30: af00 add r7, sp, #0 - 8040b32: 6078 str r0, [r7, #4] + 8040b28: b580 push {r7, lr} + 8040b2a: b082 sub sp, #8 + 8040b2c: af00 add r7, sp, #0 + 8040b2e: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) - 8040b34: 4b12 ldr r3, [pc, #72] ; (8040b80 ) - 8040b36: 681a ldr r2, [r3, #0] - 8040b38: 4b12 ldr r3, [pc, #72] ; (8040b84 ) - 8040b3a: 781b ldrb r3, [r3, #0] - 8040b3c: 4619 mov r1, r3 - 8040b3e: f44f 737a mov.w r3, #1000 ; 0x3e8 - 8040b42: fbb3 f3f1 udiv r3, r3, r1 - 8040b46: fbb2 f3f3 udiv r3, r2, r3 - 8040b4a: 4618 mov r0, r3 - 8040b4c: f000 f93b bl 8040dc6 - 8040b50: 4603 mov r3, r0 - 8040b52: 2b00 cmp r3, #0 - 8040b54: d001 beq.n 8040b5a + 8040b30: 4b12 ldr r3, [pc, #72] ; (8040b7c ) + 8040b32: 681a ldr r2, [r3, #0] + 8040b34: 4b12 ldr r3, [pc, #72] ; (8040b80 ) + 8040b36: 781b ldrb r3, [r3, #0] + 8040b38: 4619 mov r1, r3 + 8040b3a: f44f 737a mov.w r3, #1000 ; 0x3e8 + 8040b3e: fbb3 f3f1 udiv r3, r3, r1 + 8040b42: fbb2 f3f3 udiv r3, r2, r3 + 8040b46: 4618 mov r0, r3 + 8040b48: f000 f93b bl 8040dc2 + 8040b4c: 4603 mov r3, r0 + 8040b4e: 2b00 cmp r3, #0 + 8040b50: d001 beq.n 8040b56 { return HAL_ERROR; - 8040b56: 2301 movs r3, #1 - 8040b58: e00e b.n 8040b78 + 8040b52: 2301 movs r3, #1 + 8040b54: e00e b.n 8040b74 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - 8040b5a: 687b ldr r3, [r7, #4] - 8040b5c: 2b0f cmp r3, #15 - 8040b5e: d80a bhi.n 8040b76 + 8040b56: 687b ldr r3, [r7, #4] + 8040b58: 2b0f cmp r3, #15 + 8040b5a: d80a bhi.n 8040b72 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - 8040b60: 2200 movs r2, #0 - 8040b62: 6879 ldr r1, [r7, #4] - 8040b64: f04f 30ff mov.w r0, #4294967295 - 8040b68: f000 f911 bl 8040d8e + 8040b5c: 2200 movs r2, #0 + 8040b5e: 6879 ldr r1, [r7, #4] + 8040b60: f04f 30ff mov.w r0, #4294967295 + 8040b64: f000 f911 bl 8040d8a uwTickPrio = TickPriority; - 8040b6c: 4a06 ldr r2, [pc, #24] ; (8040b88 ) - 8040b6e: 687b ldr r3, [r7, #4] - 8040b70: 6013 str r3, [r2, #0] + 8040b68: 4a06 ldr r2, [pc, #24] ; (8040b84 ) + 8040b6a: 687b ldr r3, [r7, #4] + 8040b6c: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; - 8040b72: 2300 movs r3, #0 - 8040b74: e000 b.n 8040b78 + 8040b6e: 2300 movs r3, #0 + 8040b70: e000 b.n 8040b74 return HAL_ERROR; - 8040b76: 2301 movs r3, #1 + 8040b72: 2301 movs r3, #1 } - 8040b78: 4618 mov r0, r3 - 8040b7a: 3708 adds r7, #8 - 8040b7c: 46bd mov sp, r7 - 8040b7e: bd80 pop {r7, pc} - 8040b80: 20000000 .word 0x20000000 - 8040b84: 20000008 .word 0x20000008 - 8040b88: 20000004 .word 0x20000004 - -08040b8c : + 8040b74: 4618 mov r0, r3 + 8040b76: 3708 adds r7, #8 + 8040b78: 46bd mov sp, r7 + 8040b7a: bd80 pop {r7, pc} + 8040b7c: 20000000 .word 0x20000000 + 8040b80: 20000008 .word 0x20000008 + 8040b84: 20000004 .word 0x20000004 + +08040b88 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { - 8040b8c: b480 push {r7} - 8040b8e: af00 add r7, sp, #0 + 8040b88: b480 push {r7} + 8040b8a: af00 add r7, sp, #0 uwTick += uwTickFreq; - 8040b90: 4b06 ldr r3, [pc, #24] ; (8040bac ) - 8040b92: 781b ldrb r3, [r3, #0] - 8040b94: 461a mov r2, r3 - 8040b96: 4b06 ldr r3, [pc, #24] ; (8040bb0 ) - 8040b98: 681b ldr r3, [r3, #0] - 8040b9a: 4413 add r3, r2 - 8040b9c: 4a04 ldr r2, [pc, #16] ; (8040bb0 ) - 8040b9e: 6013 str r3, [r2, #0] + 8040b8c: 4b06 ldr r3, [pc, #24] ; (8040ba8 ) + 8040b8e: 781b ldrb r3, [r3, #0] + 8040b90: 461a mov r2, r3 + 8040b92: 4b06 ldr r3, [pc, #24] ; (8040bac ) + 8040b94: 681b ldr r3, [r3, #0] + 8040b96: 4413 add r3, r2 + 8040b98: 4a04 ldr r2, [pc, #16] ; (8040bac ) + 8040b9a: 6013 str r3, [r2, #0] } - 8040ba0: bf00 nop - 8040ba2: 46bd mov sp, r7 - 8040ba4: f85d 7b04 ldr.w r7, [sp], #4 - 8040ba8: 4770 bx lr - 8040baa: bf00 nop - 8040bac: 20000008 .word 0x20000008 - 8040bb0: 2000011c .word 0x2000011c - -08040bb4 : + 8040b9c: bf00 nop + 8040b9e: 46bd mov sp, r7 + 8040ba0: f85d 7b04 ldr.w r7, [sp], #4 + 8040ba4: 4770 bx lr + 8040ba6: bf00 nop + 8040ba8: 20000008 .word 0x20000008 + 8040bac: 2000011c .word 0x2000011c + +08040bb0 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { - 8040bb4: b480 push {r7} - 8040bb6: af00 add r7, sp, #0 + 8040bb0: b480 push {r7} + 8040bb2: af00 add r7, sp, #0 return uwTick; - 8040bb8: 4b03 ldr r3, [pc, #12] ; (8040bc8 ) - 8040bba: 681b ldr r3, [r3, #0] + 8040bb4: 4b03 ldr r3, [pc, #12] ; (8040bc4 ) + 8040bb6: 681b ldr r3, [r3, #0] } - 8040bbc: 4618 mov r0, r3 - 8040bbe: 46bd mov sp, r7 - 8040bc0: f85d 7b04 ldr.w r7, [sp], #4 - 8040bc4: 4770 bx lr - 8040bc6: bf00 nop - 8040bc8: 2000011c .word 0x2000011c - -08040bcc : + 8040bb8: 4618 mov r0, r3 + 8040bba: 46bd mov sp, r7 + 8040bbc: f85d 7b04 ldr.w r7, [sp], #4 + 8040bc0: 4770 bx lr + 8040bc2: bf00 nop + 8040bc4: 2000011c .word 0x2000011c + +08040bc8 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { - 8040bcc: b580 push {r7, lr} - 8040bce: b084 sub sp, #16 - 8040bd0: af00 add r7, sp, #0 - 8040bd2: 6078 str r0, [r7, #4] + 8040bc8: b580 push {r7, lr} + 8040bca: b084 sub sp, #16 + 8040bcc: af00 add r7, sp, #0 + 8040bce: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); - 8040bd4: f7ff ffee bl 8040bb4 - 8040bd8: 60b8 str r0, [r7, #8] + 8040bd0: f7ff ffee bl 8040bb0 + 8040bd4: 60b8 str r0, [r7, #8] uint32_t wait = Delay; - 8040bda: 687b ldr r3, [r7, #4] - 8040bdc: 60fb str r3, [r7, #12] + 8040bd6: 687b ldr r3, [r7, #4] + 8040bd8: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) - 8040bde: 68fb ldr r3, [r7, #12] - 8040be0: f1b3 3fff cmp.w r3, #4294967295 - 8040be4: d005 beq.n 8040bf2 + 8040bda: 68fb ldr r3, [r7, #12] + 8040bdc: f1b3 3fff cmp.w r3, #4294967295 + 8040be0: d005 beq.n 8040bee { wait += (uint32_t)(uwTickFreq); - 8040be6: 4b0a ldr r3, [pc, #40] ; (8040c10 ) - 8040be8: 781b ldrb r3, [r3, #0] - 8040bea: 461a mov r2, r3 - 8040bec: 68fb ldr r3, [r7, #12] - 8040bee: 4413 add r3, r2 - 8040bf0: 60fb str r3, [r7, #12] + 8040be2: 4b0a ldr r3, [pc, #40] ; (8040c0c ) + 8040be4: 781b ldrb r3, [r3, #0] + 8040be6: 461a mov r2, r3 + 8040be8: 68fb ldr r3, [r7, #12] + 8040bea: 4413 add r3, r2 + 8040bec: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) - 8040bf2: bf00 nop - 8040bf4: f7ff ffde bl 8040bb4 - 8040bf8: 4602 mov r2, r0 - 8040bfa: 68bb ldr r3, [r7, #8] - 8040bfc: 1ad3 subs r3, r2, r3 - 8040bfe: 68fa ldr r2, [r7, #12] - 8040c00: 429a cmp r2, r3 - 8040c02: d8f7 bhi.n 8040bf4 + 8040bee: bf00 nop + 8040bf0: f7ff ffde bl 8040bb0 + 8040bf4: 4602 mov r2, r0 + 8040bf6: 68bb ldr r3, [r7, #8] + 8040bf8: 1ad3 subs r3, r2, r3 + 8040bfa: 68fa ldr r2, [r7, #12] + 8040bfc: 429a cmp r2, r3 + 8040bfe: d8f7 bhi.n 8040bf0 { } } - 8040c04: bf00 nop - 8040c06: bf00 nop - 8040c08: 3710 adds r7, #16 - 8040c0a: 46bd mov sp, r7 - 8040c0c: bd80 pop {r7, pc} - 8040c0e: bf00 nop - 8040c10: 20000008 .word 0x20000008 - -08040c14 <__NVIC_SetPriorityGrouping>: + 8040c00: bf00 nop + 8040c02: bf00 nop + 8040c04: 3710 adds r7, #16 + 8040c06: 46bd mov sp, r7 + 8040c08: bd80 pop {r7, pc} + 8040c0a: bf00 nop + 8040c0c: 20000008 .word 0x20000008 + +08040c10 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - 8040c14: b480 push {r7} - 8040c16: b085 sub sp, #20 - 8040c18: af00 add r7, sp, #0 - 8040c1a: 6078 str r0, [r7, #4] + 8040c10: b480 push {r7} + 8040c12: b085 sub sp, #20 + 8040c14: af00 add r7, sp, #0 + 8040c16: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 8040c1c: 687b ldr r3, [r7, #4] - 8040c1e: f003 0307 and.w r3, r3, #7 - 8040c22: 60fb str r3, [r7, #12] + 8040c18: 687b ldr r3, [r7, #4] + 8040c1a: f003 0307 and.w r3, r3, #7 + 8040c1e: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ - 8040c24: 4b0b ldr r3, [pc, #44] ; (8040c54 <__NVIC_SetPriorityGrouping+0x40>) - 8040c26: 68db ldr r3, [r3, #12] - 8040c28: 60bb str r3, [r7, #8] + 8040c20: 4b0b ldr r3, [pc, #44] ; (8040c50 <__NVIC_SetPriorityGrouping+0x40>) + 8040c22: 68db ldr r3, [r3, #12] + 8040c24: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - 8040c2a: 68ba ldr r2, [r7, #8] - 8040c2c: f64f 03ff movw r3, #63743 ; 0xf8ff - 8040c30: 4013 ands r3, r2 - 8040c32: 60bb str r3, [r7, #8] + 8040c26: 68ba ldr r2, [r7, #8] + 8040c28: f64f 03ff movw r3, #63743 ; 0xf8ff + 8040c2c: 4013 ands r3, r2 + 8040c2e: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - 8040c34: 68fb ldr r3, [r7, #12] - 8040c36: 021a lsls r2, r3, #8 + 8040c30: 68fb ldr r3, [r7, #12] + 8040c32: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - 8040c38: 68bb ldr r3, [r7, #8] - 8040c3a: 431a orrs r2, r3 + 8040c34: 68bb ldr r3, [r7, #8] + 8040c36: 431a orrs r2, r3 reg_value = (reg_value | - 8040c3c: 4b06 ldr r3, [pc, #24] ; (8040c58 <__NVIC_SetPriorityGrouping+0x44>) - 8040c3e: 4313 orrs r3, r2 - 8040c40: 60bb str r3, [r7, #8] + 8040c38: 4b06 ldr r3, [pc, #24] ; (8040c54 <__NVIC_SetPriorityGrouping+0x44>) + 8040c3a: 4313 orrs r3, r2 + 8040c3c: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; - 8040c42: 4a04 ldr r2, [pc, #16] ; (8040c54 <__NVIC_SetPriorityGrouping+0x40>) - 8040c44: 68bb ldr r3, [r7, #8] - 8040c46: 60d3 str r3, [r2, #12] + 8040c3e: 4a04 ldr r2, [pc, #16] ; (8040c50 <__NVIC_SetPriorityGrouping+0x40>) + 8040c40: 68bb ldr r3, [r7, #8] + 8040c42: 60d3 str r3, [r2, #12] } - 8040c48: bf00 nop - 8040c4a: 3714 adds r7, #20 - 8040c4c: 46bd mov sp, r7 - 8040c4e: f85d 7b04 ldr.w r7, [sp], #4 - 8040c52: 4770 bx lr - 8040c54: e000ed00 .word 0xe000ed00 - 8040c58: 05fa0000 .word 0x05fa0000 - -08040c5c <__NVIC_GetPriorityGrouping>: + 8040c44: bf00 nop + 8040c46: 3714 adds r7, #20 + 8040c48: 46bd mov sp, r7 + 8040c4a: f85d 7b04 ldr.w r7, [sp], #4 + 8040c4e: 4770 bx lr + 8040c50: e000ed00 .word 0xe000ed00 + 8040c54: 05fa0000 .word 0x05fa0000 + +08040c58 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { - 8040c5c: b480 push {r7} - 8040c5e: af00 add r7, sp, #0 + 8040c58: b480 push {r7} + 8040c5a: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); - 8040c60: 4b04 ldr r3, [pc, #16] ; (8040c74 <__NVIC_GetPriorityGrouping+0x18>) - 8040c62: 68db ldr r3, [r3, #12] - 8040c64: 0a1b lsrs r3, r3, #8 - 8040c66: f003 0307 and.w r3, r3, #7 + 8040c5c: 4b04 ldr r3, [pc, #16] ; (8040c70 <__NVIC_GetPriorityGrouping+0x18>) + 8040c5e: 68db ldr r3, [r3, #12] + 8040c60: 0a1b lsrs r3, r3, #8 + 8040c62: f003 0307 and.w r3, r3, #7 } - 8040c6a: 4618 mov r0, r3 - 8040c6c: 46bd mov sp, r7 - 8040c6e: f85d 7b04 ldr.w r7, [sp], #4 - 8040c72: 4770 bx lr - 8040c74: e000ed00 .word 0xe000ed00 + 8040c66: 4618 mov r0, r3 + 8040c68: 46bd mov sp, r7 + 8040c6a: f85d 7b04 ldr.w r7, [sp], #4 + 8040c6e: 4770 bx lr + 8040c70: e000ed00 .word 0xe000ed00 -08040c78 <__NVIC_SetPriority>: +08040c74 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - 8040c78: b480 push {r7} - 8040c7a: b083 sub sp, #12 - 8040c7c: af00 add r7, sp, #0 - 8040c7e: 4603 mov r3, r0 - 8040c80: 6039 str r1, [r7, #0] - 8040c82: 71fb strb r3, [r7, #7] + 8040c74: b480 push {r7} + 8040c76: b083 sub sp, #12 + 8040c78: af00 add r7, sp, #0 + 8040c7a: 4603 mov r3, r0 + 8040c7c: 6039 str r1, [r7, #0] + 8040c7e: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) - 8040c84: f997 3007 ldrsb.w r3, [r7, #7] - 8040c88: 2b00 cmp r3, #0 - 8040c8a: db0a blt.n 8040ca2 <__NVIC_SetPriority+0x2a> + 8040c80: f997 3007 ldrsb.w r3, [r7, #7] + 8040c84: 2b00 cmp r3, #0 + 8040c86: db0a blt.n 8040c9e <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 8040c8c: 683b ldr r3, [r7, #0] - 8040c8e: b2da uxtb r2, r3 - 8040c90: 490c ldr r1, [pc, #48] ; (8040cc4 <__NVIC_SetPriority+0x4c>) - 8040c92: f997 3007 ldrsb.w r3, [r7, #7] - 8040c96: 0112 lsls r2, r2, #4 - 8040c98: b2d2 uxtb r2, r2 - 8040c9a: 440b add r3, r1 - 8040c9c: f883 2300 strb.w r2, [r3, #768] ; 0x300 + 8040c88: 683b ldr r3, [r7, #0] + 8040c8a: b2da uxtb r2, r3 + 8040c8c: 490c ldr r1, [pc, #48] ; (8040cc0 <__NVIC_SetPriority+0x4c>) + 8040c8e: f997 3007 ldrsb.w r3, [r7, #7] + 8040c92: 0112 lsls r2, r2, #4 + 8040c94: b2d2 uxtb r2, r2 + 8040c96: 440b add r3, r1 + 8040c98: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } - 8040ca0: e00a b.n 8040cb8 <__NVIC_SetPriority+0x40> + 8040c9c: e00a b.n 8040cb4 <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 8040ca2: 683b ldr r3, [r7, #0] - 8040ca4: b2da uxtb r2, r3 - 8040ca6: 4908 ldr r1, [pc, #32] ; (8040cc8 <__NVIC_SetPriority+0x50>) - 8040ca8: 79fb ldrb r3, [r7, #7] - 8040caa: f003 030f and.w r3, r3, #15 - 8040cae: 3b04 subs r3, #4 - 8040cb0: 0112 lsls r2, r2, #4 - 8040cb2: b2d2 uxtb r2, r2 - 8040cb4: 440b add r3, r1 - 8040cb6: 761a strb r2, [r3, #24] + 8040c9e: 683b ldr r3, [r7, #0] + 8040ca0: b2da uxtb r2, r3 + 8040ca2: 4908 ldr r1, [pc, #32] ; (8040cc4 <__NVIC_SetPriority+0x50>) + 8040ca4: 79fb ldrb r3, [r7, #7] + 8040ca6: f003 030f and.w r3, r3, #15 + 8040caa: 3b04 subs r3, #4 + 8040cac: 0112 lsls r2, r2, #4 + 8040cae: b2d2 uxtb r2, r2 + 8040cb0: 440b add r3, r1 + 8040cb2: 761a strb r2, [r3, #24] } - 8040cb8: bf00 nop - 8040cba: 370c adds r7, #12 - 8040cbc: 46bd mov sp, r7 - 8040cbe: f85d 7b04 ldr.w r7, [sp], #4 - 8040cc2: 4770 bx lr - 8040cc4: e000e100 .word 0xe000e100 - 8040cc8: e000ed00 .word 0xe000ed00 - -08040ccc : + 8040cb4: bf00 nop + 8040cb6: 370c adds r7, #12 + 8040cb8: 46bd mov sp, r7 + 8040cba: f85d 7b04 ldr.w r7, [sp], #4 + 8040cbe: 4770 bx lr + 8040cc0: e000e100 .word 0xe000e100 + 8040cc4: e000ed00 .word 0xe000ed00 + +08040cc8 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { - 8040ccc: b480 push {r7} - 8040cce: b089 sub sp, #36 ; 0x24 - 8040cd0: af00 add r7, sp, #0 - 8040cd2: 60f8 str r0, [r7, #12] - 8040cd4: 60b9 str r1, [r7, #8] - 8040cd6: 607a str r2, [r7, #4] + 8040cc8: b480 push {r7} + 8040cca: b089 sub sp, #36 ; 0x24 + 8040ccc: af00 add r7, sp, #0 + 8040cce: 60f8 str r0, [r7, #12] + 8040cd0: 60b9 str r1, [r7, #8] + 8040cd2: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 8040cd8: 68fb ldr r3, [r7, #12] - 8040cda: f003 0307 and.w r3, r3, #7 - 8040cde: 61fb str r3, [r7, #28] + 8040cd4: 68fb ldr r3, [r7, #12] + 8040cd6: f003 0307 and.w r3, r3, #7 + 8040cda: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - 8040ce0: 69fb ldr r3, [r7, #28] - 8040ce2: f1c3 0307 rsb r3, r3, #7 - 8040ce6: 2b04 cmp r3, #4 - 8040ce8: bf28 it cs - 8040cea: 2304 movcs r3, #4 - 8040cec: 61bb str r3, [r7, #24] + 8040cdc: 69fb ldr r3, [r7, #28] + 8040cde: f1c3 0307 rsb r3, r3, #7 + 8040ce2: 2b04 cmp r3, #4 + 8040ce4: bf28 it cs + 8040ce6: 2304 movcs r3, #4 + 8040ce8: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - 8040cee: 69fb ldr r3, [r7, #28] - 8040cf0: 3304 adds r3, #4 - 8040cf2: 2b06 cmp r3, #6 - 8040cf4: d902 bls.n 8040cfc - 8040cf6: 69fb ldr r3, [r7, #28] - 8040cf8: 3b03 subs r3, #3 - 8040cfa: e000 b.n 8040cfe - 8040cfc: 2300 movs r3, #0 - 8040cfe: 617b str r3, [r7, #20] + 8040cea: 69fb ldr r3, [r7, #28] + 8040cec: 3304 adds r3, #4 + 8040cee: 2b06 cmp r3, #6 + 8040cf0: d902 bls.n 8040cf8 + 8040cf2: 69fb ldr r3, [r7, #28] + 8040cf4: 3b03 subs r3, #3 + 8040cf6: e000 b.n 8040cfa + 8040cf8: 2300 movs r3, #0 + 8040cfa: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 8040d00: f04f 32ff mov.w r2, #4294967295 - 8040d04: 69bb ldr r3, [r7, #24] - 8040d06: fa02 f303 lsl.w r3, r2, r3 - 8040d0a: 43da mvns r2, r3 - 8040d0c: 68bb ldr r3, [r7, #8] - 8040d0e: 401a ands r2, r3 - 8040d10: 697b ldr r3, [r7, #20] - 8040d12: 409a lsls r2, r3 + 8040cfc: f04f 32ff mov.w r2, #4294967295 + 8040d00: 69bb ldr r3, [r7, #24] + 8040d02: fa02 f303 lsl.w r3, r2, r3 + 8040d06: 43da mvns r2, r3 + 8040d08: 68bb ldr r3, [r7, #8] + 8040d0a: 401a ands r2, r3 + 8040d0c: 697b ldr r3, [r7, #20] + 8040d0e: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - 8040d14: f04f 31ff mov.w r1, #4294967295 - 8040d18: 697b ldr r3, [r7, #20] - 8040d1a: fa01 f303 lsl.w r3, r1, r3 - 8040d1e: 43d9 mvns r1, r3 - 8040d20: 687b ldr r3, [r7, #4] - 8040d22: 400b ands r3, r1 + 8040d10: f04f 31ff mov.w r1, #4294967295 + 8040d14: 697b ldr r3, [r7, #20] + 8040d16: fa01 f303 lsl.w r3, r1, r3 + 8040d1a: 43d9 mvns r1, r3 + 8040d1c: 687b ldr r3, [r7, #4] + 8040d1e: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 8040d24: 4313 orrs r3, r2 + 8040d20: 4313 orrs r3, r2 ); } - 8040d26: 4618 mov r0, r3 - 8040d28: 3724 adds r7, #36 ; 0x24 - 8040d2a: 46bd mov sp, r7 - 8040d2c: f85d 7b04 ldr.w r7, [sp], #4 - 8040d30: 4770 bx lr + 8040d22: 4618 mov r0, r3 + 8040d24: 3724 adds r7, #36 ; 0x24 + 8040d26: 46bd mov sp, r7 + 8040d28: f85d 7b04 ldr.w r7, [sp], #4 + 8040d2c: 4770 bx lr ... -08040d34 : +08040d30 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - 8040d34: b580 push {r7, lr} - 8040d36: b082 sub sp, #8 - 8040d38: af00 add r7, sp, #0 - 8040d3a: 6078 str r0, [r7, #4] + 8040d30: b580 push {r7, lr} + 8040d32: b082 sub sp, #8 + 8040d34: af00 add r7, sp, #0 + 8040d36: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - 8040d3c: 687b ldr r3, [r7, #4] - 8040d3e: 3b01 subs r3, #1 - 8040d40: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 - 8040d44: d301 bcc.n 8040d4a + 8040d38: 687b ldr r3, [r7, #4] + 8040d3a: 3b01 subs r3, #1 + 8040d3c: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 + 8040d40: d301 bcc.n 8040d46 { return (1UL); /* Reload value impossible */ - 8040d46: 2301 movs r3, #1 - 8040d48: e00f b.n 8040d6a + 8040d42: 2301 movs r3, #1 + 8040d44: e00f b.n 8040d66 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - 8040d4a: 4a0a ldr r2, [pc, #40] ; (8040d74 ) - 8040d4c: 687b ldr r3, [r7, #4] - 8040d4e: 3b01 subs r3, #1 - 8040d50: 6053 str r3, [r2, #4] + 8040d46: 4a0a ldr r2, [pc, #40] ; (8040d70 ) + 8040d48: 687b ldr r3, [r7, #4] + 8040d4a: 3b01 subs r3, #1 + 8040d4c: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - 8040d52: 210f movs r1, #15 - 8040d54: f04f 30ff mov.w r0, #4294967295 - 8040d58: f7ff ff8e bl 8040c78 <__NVIC_SetPriority> + 8040d4e: 210f movs r1, #15 + 8040d50: f04f 30ff mov.w r0, #4294967295 + 8040d54: f7ff ff8e bl 8040c74 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - 8040d5c: 4b05 ldr r3, [pc, #20] ; (8040d74 ) - 8040d5e: 2200 movs r2, #0 - 8040d60: 609a str r2, [r3, #8] + 8040d58: 4b05 ldr r3, [pc, #20] ; (8040d70 ) + 8040d5a: 2200 movs r2, #0 + 8040d5c: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - 8040d62: 4b04 ldr r3, [pc, #16] ; (8040d74 ) - 8040d64: 2207 movs r2, #7 - 8040d66: 601a str r2, [r3, #0] + 8040d5e: 4b04 ldr r3, [pc, #16] ; (8040d70 ) + 8040d60: 2207 movs r2, #7 + 8040d62: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ - 8040d68: 2300 movs r3, #0 + 8040d64: 2300 movs r3, #0 } - 8040d6a: 4618 mov r0, r3 - 8040d6c: 3708 adds r7, #8 - 8040d6e: 46bd mov sp, r7 - 8040d70: bd80 pop {r7, pc} - 8040d72: bf00 nop - 8040d74: e000e010 .word 0xe000e010 - -08040d78 : + 8040d66: 4618 mov r0, r3 + 8040d68: 3708 adds r7, #8 + 8040d6a: 46bd mov sp, r7 + 8040d6c: bd80 pop {r7, pc} + 8040d6e: bf00 nop + 8040d70: e000e010 .word 0xe000e010 + +08040d74 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - 8040d78: b580 push {r7, lr} - 8040d7a: b082 sub sp, #8 - 8040d7c: af00 add r7, sp, #0 - 8040d7e: 6078 str r0, [r7, #4] + 8040d74: b580 push {r7, lr} + 8040d76: b082 sub sp, #8 + 8040d78: af00 add r7, sp, #0 + 8040d7a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); - 8040d80: 6878 ldr r0, [r7, #4] - 8040d82: f7ff ff47 bl 8040c14 <__NVIC_SetPriorityGrouping> + 8040d7c: 6878 ldr r0, [r7, #4] + 8040d7e: f7ff ff47 bl 8040c10 <__NVIC_SetPriorityGrouping> } - 8040d86: bf00 nop - 8040d88: 3708 adds r7, #8 - 8040d8a: 46bd mov sp, r7 - 8040d8c: bd80 pop {r7, pc} + 8040d82: bf00 nop + 8040d84: 3708 adds r7, #8 + 8040d86: 46bd mov sp, r7 + 8040d88: bd80 pop {r7, pc} -08040d8e : +08040d8a : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { - 8040d8e: b580 push {r7, lr} - 8040d90: b086 sub sp, #24 - 8040d92: af00 add r7, sp, #0 - 8040d94: 4603 mov r3, r0 - 8040d96: 60b9 str r1, [r7, #8] - 8040d98: 607a str r2, [r7, #4] - 8040d9a: 73fb strb r3, [r7, #15] + 8040d8a: b580 push {r7, lr} + 8040d8c: b086 sub sp, #24 + 8040d8e: af00 add r7, sp, #0 + 8040d90: 4603 mov r3, r0 + 8040d92: 60b9 str r1, [r7, #8] + 8040d94: 607a str r2, [r7, #4] + 8040d96: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00; - 8040d9c: 2300 movs r3, #0 - 8040d9e: 617b str r3, [r7, #20] + 8040d98: 2300 movs r3, #0 + 8040d9a: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); - 8040da0: f7ff ff5c bl 8040c5c <__NVIC_GetPriorityGrouping> - 8040da4: 6178 str r0, [r7, #20] + 8040d9c: f7ff ff5c bl 8040c58 <__NVIC_GetPriorityGrouping> + 8040da0: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); - 8040da6: 687a ldr r2, [r7, #4] - 8040da8: 68b9 ldr r1, [r7, #8] - 8040daa: 6978 ldr r0, [r7, #20] - 8040dac: f7ff ff8e bl 8040ccc - 8040db0: 4602 mov r2, r0 - 8040db2: f997 300f ldrsb.w r3, [r7, #15] - 8040db6: 4611 mov r1, r2 - 8040db8: 4618 mov r0, r3 - 8040dba: f7ff ff5d bl 8040c78 <__NVIC_SetPriority> + 8040da2: 687a ldr r2, [r7, #4] + 8040da4: 68b9 ldr r1, [r7, #8] + 8040da6: 6978 ldr r0, [r7, #20] + 8040da8: f7ff ff8e bl 8040cc8 + 8040dac: 4602 mov r2, r0 + 8040dae: f997 300f ldrsb.w r3, [r7, #15] + 8040db2: 4611 mov r1, r2 + 8040db4: 4618 mov r0, r3 + 8040db6: f7ff ff5d bl 8040c74 <__NVIC_SetPriority> } - 8040dbe: bf00 nop - 8040dc0: 3718 adds r7, #24 - 8040dc2: 46bd mov sp, r7 - 8040dc4: bd80 pop {r7, pc} + 8040dba: bf00 nop + 8040dbc: 3718 adds r7, #24 + 8040dbe: 46bd mov sp, r7 + 8040dc0: bd80 pop {r7, pc} -08040dc6 : +08040dc2 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { - 8040dc6: b580 push {r7, lr} - 8040dc8: b082 sub sp, #8 - 8040dca: af00 add r7, sp, #0 - 8040dcc: 6078 str r0, [r7, #4] + 8040dc2: b580 push {r7, lr} + 8040dc4: b082 sub sp, #8 + 8040dc6: af00 add r7, sp, #0 + 8040dc8: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); - 8040dce: 6878 ldr r0, [r7, #4] - 8040dd0: f7ff ffb0 bl 8040d34 - 8040dd4: 4603 mov r3, r0 + 8040dca: 6878 ldr r0, [r7, #4] + 8040dcc: f7ff ffb0 bl 8040d30 + 8040dd0: 4603 mov r3, r0 } - 8040dd6: 4618 mov r0, r3 - 8040dd8: 3708 adds r7, #8 - 8040dda: 46bd mov sp, r7 - 8040ddc: bd80 pop {r7, pc} + 8040dd2: 4618 mov r0, r3 + 8040dd4: 3708 adds r7, #8 + 8040dd6: 46bd mov sp, r7 + 8040dd8: bd80 pop {r7, pc} ... -08040de0 : +08040ddc : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { - 8040de0: b480 push {r7} - 8040de2: b089 sub sp, #36 ; 0x24 - 8040de4: af00 add r7, sp, #0 - 8040de6: 6078 str r0, [r7, #4] - 8040de8: 6039 str r1, [r7, #0] + 8040ddc: b480 push {r7} + 8040dde: b089 sub sp, #36 ; 0x24 + 8040de0: af00 add r7, sp, #0 + 8040de2: 6078 str r0, [r7, #4] + 8040de4: 6039 str r1, [r7, #0] uint32_t position = 0x00; - 8040dea: 2300 movs r3, #0 - 8040dec: 61fb str r3, [r7, #28] + 8040de6: 2300 movs r3, #0 + 8040de8: 61fb str r3, [r7, #28] uint32_t ioposition = 0x00; - 8040dee: 2300 movs r3, #0 - 8040df0: 617b str r3, [r7, #20] + 8040dea: 2300 movs r3, #0 + 8040dec: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00; - 8040df2: 2300 movs r3, #0 - 8040df4: 613b str r3, [r7, #16] + 8040dee: 2300 movs r3, #0 + 8040df0: 613b str r3, [r7, #16] uint32_t temp = 0x00; - 8040df6: 2300 movs r3, #0 - 8040df8: 61bb str r3, [r7, #24] + 8040df2: 2300 movs r3, #0 + 8040df4: 61bb str r3, [r7, #24] assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ for(position = 0; position < GPIO_NUMBER; position++) - 8040dfa: 2300 movs r3, #0 - 8040dfc: 61fb str r3, [r7, #28] - 8040dfe: e175 b.n 80410ec + 8040df6: 2300 movs r3, #0 + 8040df8: 61fb str r3, [r7, #28] + 8040dfa: e175 b.n 80410e8 { /* Get the IO position */ ioposition = ((uint32_t)0x01) << position; - 8040e00: 2201 movs r2, #1 - 8040e02: 69fb ldr r3, [r7, #28] - 8040e04: fa02 f303 lsl.w r3, r2, r3 - 8040e08: 617b str r3, [r7, #20] + 8040dfc: 2201 movs r2, #1 + 8040dfe: 69fb ldr r3, [r7, #28] + 8040e00: fa02 f303 lsl.w r3, r2, r3 + 8040e04: 617b str r3, [r7, #20] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; - 8040e0a: 683b ldr r3, [r7, #0] - 8040e0c: 681b ldr r3, [r3, #0] - 8040e0e: 697a ldr r2, [r7, #20] - 8040e10: 4013 ands r3, r2 - 8040e12: 613b str r3, [r7, #16] + 8040e06: 683b ldr r3, [r7, #0] + 8040e08: 681b ldr r3, [r3, #0] + 8040e0a: 697a ldr r2, [r7, #20] + 8040e0c: 4013 ands r3, r2 + 8040e0e: 613b str r3, [r7, #16] if(iocurrent == ioposition) - 8040e14: 693a ldr r2, [r7, #16] - 8040e16: 697b ldr r3, [r7, #20] - 8040e18: 429a cmp r2, r3 - 8040e1a: f040 8164 bne.w 80410e6 + 8040e10: 693a ldr r2, [r7, #16] + 8040e12: 697b ldr r3, [r7, #20] + 8040e14: 429a cmp r2, r3 + 8040e16: f040 8164 bne.w 80410e2 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || - 8040e1e: 683b ldr r3, [r7, #0] - 8040e20: 685b ldr r3, [r3, #4] - 8040e22: 2b01 cmp r3, #1 - 8040e24: d00b beq.n 8040e3e - 8040e26: 683b ldr r3, [r7, #0] - 8040e28: 685b ldr r3, [r3, #4] - 8040e2a: 2b02 cmp r3, #2 - 8040e2c: d007 beq.n 8040e3e + 8040e1a: 683b ldr r3, [r7, #0] + 8040e1c: 685b ldr r3, [r3, #4] + 8040e1e: 2b01 cmp r3, #1 + 8040e20: d00b beq.n 8040e3a + 8040e22: 683b ldr r3, [r7, #0] + 8040e24: 685b ldr r3, [r3, #4] + 8040e26: 2b02 cmp r3, #2 + 8040e28: d007 beq.n 8040e3a (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - 8040e2e: 683b ldr r3, [r7, #0] - 8040e30: 685b ldr r3, [r3, #4] + 8040e2a: 683b ldr r3, [r7, #0] + 8040e2c: 685b ldr r3, [r3, #4] if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || - 8040e32: 2b11 cmp r3, #17 - 8040e34: d003 beq.n 8040e3e + 8040e2e: 2b11 cmp r3, #17 + 8040e30: d003 beq.n 8040e3a (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - 8040e36: 683b ldr r3, [r7, #0] - 8040e38: 685b ldr r3, [r3, #4] - 8040e3a: 2b12 cmp r3, #18 - 8040e3c: d130 bne.n 8040ea0 + 8040e32: 683b ldr r3, [r7, #0] + 8040e34: 685b ldr r3, [r3, #4] + 8040e36: 2b12 cmp r3, #18 + 8040e38: d130 bne.n 8040e9c { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; - 8040e3e: 687b ldr r3, [r7, #4] - 8040e40: 689b ldr r3, [r3, #8] - 8040e42: 61bb str r3, [r7, #24] + 8040e3a: 687b ldr r3, [r7, #4] + 8040e3c: 689b ldr r3, [r3, #8] + 8040e3e: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); - 8040e44: 69fb ldr r3, [r7, #28] - 8040e46: 005b lsls r3, r3, #1 - 8040e48: 2203 movs r2, #3 - 8040e4a: fa02 f303 lsl.w r3, r2, r3 - 8040e4e: 43db mvns r3, r3 - 8040e50: 69ba ldr r2, [r7, #24] - 8040e52: 4013 ands r3, r2 - 8040e54: 61bb str r3, [r7, #24] + 8040e40: 69fb ldr r3, [r7, #28] + 8040e42: 005b lsls r3, r3, #1 + 8040e44: 2203 movs r2, #3 + 8040e46: fa02 f303 lsl.w r3, r2, r3 + 8040e4a: 43db mvns r3, r3 + 8040e4c: 69ba ldr r2, [r7, #24] + 8040e4e: 4013 ands r3, r2 + 8040e50: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2)); - 8040e56: 683b ldr r3, [r7, #0] - 8040e58: 68da ldr r2, [r3, #12] - 8040e5a: 69fb ldr r3, [r7, #28] - 8040e5c: 005b lsls r3, r3, #1 - 8040e5e: fa02 f303 lsl.w r3, r2, r3 - 8040e62: 69ba ldr r2, [r7, #24] - 8040e64: 4313 orrs r3, r2 - 8040e66: 61bb str r3, [r7, #24] + 8040e52: 683b ldr r3, [r7, #0] + 8040e54: 68da ldr r2, [r3, #12] + 8040e56: 69fb ldr r3, [r7, #28] + 8040e58: 005b lsls r3, r3, #1 + 8040e5a: fa02 f303 lsl.w r3, r2, r3 + 8040e5e: 69ba ldr r2, [r7, #24] + 8040e60: 4313 orrs r3, r2 + 8040e62: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; - 8040e68: 687b ldr r3, [r7, #4] - 8040e6a: 69ba ldr r2, [r7, #24] - 8040e6c: 609a str r2, [r3, #8] + 8040e64: 687b ldr r3, [r7, #4] + 8040e66: 69ba ldr r2, [r7, #24] + 8040e68: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; - 8040e6e: 687b ldr r3, [r7, #4] - 8040e70: 685b ldr r3, [r3, #4] - 8040e72: 61bb str r3, [r7, #24] + 8040e6a: 687b ldr r3, [r7, #4] + 8040e6c: 685b ldr r3, [r3, #4] + 8040e6e: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT_0 << position) ; - 8040e74: 2201 movs r2, #1 - 8040e76: 69fb ldr r3, [r7, #28] - 8040e78: fa02 f303 lsl.w r3, r2, r3 - 8040e7c: 43db mvns r3, r3 - 8040e7e: 69ba ldr r2, [r7, #24] - 8040e80: 4013 ands r3, r2 - 8040e82: 61bb str r3, [r7, #24] + 8040e70: 2201 movs r2, #1 + 8040e72: 69fb ldr r3, [r7, #28] + 8040e74: fa02 f303 lsl.w r3, r2, r3 + 8040e78: 43db mvns r3, r3 + 8040e7a: 69ba ldr r2, [r7, #24] + 8040e7c: 4013 ands r3, r2 + 8040e7e: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); - 8040e84: 683b ldr r3, [r7, #0] - 8040e86: 685b ldr r3, [r3, #4] - 8040e88: 091b lsrs r3, r3, #4 - 8040e8a: f003 0201 and.w r2, r3, #1 - 8040e8e: 69fb ldr r3, [r7, #28] - 8040e90: fa02 f303 lsl.w r3, r2, r3 - 8040e94: 69ba ldr r2, [r7, #24] - 8040e96: 4313 orrs r3, r2 - 8040e98: 61bb str r3, [r7, #24] + 8040e80: 683b ldr r3, [r7, #0] + 8040e82: 685b ldr r3, [r3, #4] + 8040e84: 091b lsrs r3, r3, #4 + 8040e86: f003 0201 and.w r2, r3, #1 + 8040e8a: 69fb ldr r3, [r7, #28] + 8040e8c: fa02 f303 lsl.w r3, r2, r3 + 8040e90: 69ba ldr r2, [r7, #24] + 8040e92: 4313 orrs r3, r2 + 8040e94: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; - 8040e9a: 687b ldr r3, [r7, #4] - 8040e9c: 69ba ldr r2, [r7, #24] - 8040e9e: 605a str r2, [r3, #4] + 8040e96: 687b ldr r3, [r7, #4] + 8040e98: 69ba ldr r2, [r7, #24] + 8040e9a: 605a str r2, [r3, #4] } /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; - 8040ea0: 687b ldr r3, [r7, #4] - 8040ea2: 68db ldr r3, [r3, #12] - 8040ea4: 61bb str r3, [r7, #24] + 8040e9c: 687b ldr r3, [r7, #4] + 8040e9e: 68db ldr r3, [r3, #12] + 8040ea0: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); - 8040ea6: 69fb ldr r3, [r7, #28] - 8040ea8: 005b lsls r3, r3, #1 - 8040eaa: 2203 movs r2, #3 - 8040eac: fa02 f303 lsl.w r3, r2, r3 - 8040eb0: 43db mvns r3, r3 - 8040eb2: 69ba ldr r2, [r7, #24] - 8040eb4: 4013 ands r3, r2 - 8040eb6: 61bb str r3, [r7, #24] + 8040ea2: 69fb ldr r3, [r7, #28] + 8040ea4: 005b lsls r3, r3, #1 + 8040ea6: 2203 movs r2, #3 + 8040ea8: fa02 f303 lsl.w r3, r2, r3 + 8040eac: 43db mvns r3, r3 + 8040eae: 69ba ldr r2, [r7, #24] + 8040eb0: 4013 ands r3, r2 + 8040eb2: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2)); - 8040eb8: 683b ldr r3, [r7, #0] - 8040eba: 689a ldr r2, [r3, #8] - 8040ebc: 69fb ldr r3, [r7, #28] - 8040ebe: 005b lsls r3, r3, #1 - 8040ec0: fa02 f303 lsl.w r3, r2, r3 - 8040ec4: 69ba ldr r2, [r7, #24] - 8040ec6: 4313 orrs r3, r2 - 8040ec8: 61bb str r3, [r7, #24] + 8040eb4: 683b ldr r3, [r7, #0] + 8040eb6: 689a ldr r2, [r3, #8] + 8040eb8: 69fb ldr r3, [r7, #28] + 8040eba: 005b lsls r3, r3, #1 + 8040ebc: fa02 f303 lsl.w r3, r2, r3 + 8040ec0: 69ba ldr r2, [r7, #24] + 8040ec2: 4313 orrs r3, r2 + 8040ec4: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; - 8040eca: 687b ldr r3, [r7, #4] - 8040ecc: 69ba ldr r2, [r7, #24] - 8040ece: 60da str r2, [r3, #12] + 8040ec6: 687b ldr r3, [r7, #4] + 8040ec8: 69ba ldr r2, [r7, #24] + 8040eca: 60da str r2, [r3, #12] /* In case of Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - 8040ed0: 683b ldr r3, [r7, #0] - 8040ed2: 685b ldr r3, [r3, #4] - 8040ed4: 2b02 cmp r3, #2 - 8040ed6: d003 beq.n 8040ee0 - 8040ed8: 683b ldr r3, [r7, #0] - 8040eda: 685b ldr r3, [r3, #4] - 8040edc: 2b12 cmp r3, #18 - 8040ede: d123 bne.n 8040f28 + 8040ecc: 683b ldr r3, [r7, #0] + 8040ece: 685b ldr r3, [r3, #4] + 8040ed0: 2b02 cmp r3, #2 + 8040ed2: d003 beq.n 8040edc + 8040ed4: 683b ldr r3, [r7, #0] + 8040ed6: 685b ldr r3, [r3, #4] + 8040ed8: 2b12 cmp r3, #18 + 8040eda: d123 bne.n 8040f24 { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3]; - 8040ee0: 69fb ldr r3, [r7, #28] - 8040ee2: 08da lsrs r2, r3, #3 - 8040ee4: 687b ldr r3, [r7, #4] - 8040ee6: 3208 adds r2, #8 - 8040ee8: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 8040eec: 61bb str r3, [r7, #24] + 8040edc: 69fb ldr r3, [r7, #28] + 8040ede: 08da lsrs r2, r3, #3 + 8040ee0: 687b ldr r3, [r7, #4] + 8040ee2: 3208 adds r2, #8 + 8040ee4: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8040ee8: 61bb str r3, [r7, #24] temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; - 8040eee: 69fb ldr r3, [r7, #28] - 8040ef0: f003 0307 and.w r3, r3, #7 - 8040ef4: 009b lsls r3, r3, #2 - 8040ef6: 220f movs r2, #15 - 8040ef8: fa02 f303 lsl.w r3, r2, r3 - 8040efc: 43db mvns r3, r3 - 8040efe: 69ba ldr r2, [r7, #24] - 8040f00: 4013 ands r3, r2 - 8040f02: 61bb str r3, [r7, #24] + 8040eea: 69fb ldr r3, [r7, #28] + 8040eec: f003 0307 and.w r3, r3, #7 + 8040ef0: 009b lsls r3, r3, #2 + 8040ef2: 220f movs r2, #15 + 8040ef4: fa02 f303 lsl.w r3, r2, r3 + 8040ef8: 43db mvns r3, r3 + 8040efa: 69ba ldr r2, [r7, #24] + 8040efc: 4013 ands r3, r2 + 8040efe: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); - 8040f04: 683b ldr r3, [r7, #0] - 8040f06: 691a ldr r2, [r3, #16] - 8040f08: 69fb ldr r3, [r7, #28] - 8040f0a: f003 0307 and.w r3, r3, #7 - 8040f0e: 009b lsls r3, r3, #2 - 8040f10: fa02 f303 lsl.w r3, r2, r3 - 8040f14: 69ba ldr r2, [r7, #24] - 8040f16: 4313 orrs r3, r2 - 8040f18: 61bb str r3, [r7, #24] + 8040f00: 683b ldr r3, [r7, #0] + 8040f02: 691a ldr r2, [r3, #16] + 8040f04: 69fb ldr r3, [r7, #28] + 8040f06: f003 0307 and.w r3, r3, #7 + 8040f0a: 009b lsls r3, r3, #2 + 8040f0c: fa02 f303 lsl.w r3, r2, r3 + 8040f10: 69ba ldr r2, [r7, #24] + 8040f12: 4313 orrs r3, r2 + 8040f14: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3] = temp; - 8040f1a: 69fb ldr r3, [r7, #28] - 8040f1c: 08da lsrs r2, r3, #3 - 8040f1e: 687b ldr r3, [r7, #4] - 8040f20: 3208 adds r2, #8 - 8040f22: 69b9 ldr r1, [r7, #24] - 8040f24: f843 1022 str.w r1, [r3, r2, lsl #2] + 8040f16: 69fb ldr r3, [r7, #28] + 8040f18: 08da lsrs r2, r3, #3 + 8040f1a: 687b ldr r3, [r7, #4] + 8040f1c: 3208 adds r2, #8 + 8040f1e: 69b9 ldr r1, [r7, #24] + 8040f20: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; - 8040f28: 687b ldr r3, [r7, #4] - 8040f2a: 681b ldr r3, [r3, #0] - 8040f2c: 61bb str r3, [r7, #24] + 8040f24: 687b ldr r3, [r7, #4] + 8040f26: 681b ldr r3, [r3, #0] + 8040f28: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2)); - 8040f2e: 69fb ldr r3, [r7, #28] - 8040f30: 005b lsls r3, r3, #1 - 8040f32: 2203 movs r2, #3 - 8040f34: fa02 f303 lsl.w r3, r2, r3 - 8040f38: 43db mvns r3, r3 - 8040f3a: 69ba ldr r2, [r7, #24] - 8040f3c: 4013 ands r3, r2 - 8040f3e: 61bb str r3, [r7, #24] + 8040f2a: 69fb ldr r3, [r7, #28] + 8040f2c: 005b lsls r3, r3, #1 + 8040f2e: 2203 movs r2, #3 + 8040f30: fa02 f303 lsl.w r3, r2, r3 + 8040f34: 43db mvns r3, r3 + 8040f36: 69ba ldr r2, [r7, #24] + 8040f38: 4013 ands r3, r2 + 8040f3a: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); - 8040f40: 683b ldr r3, [r7, #0] - 8040f42: 685b ldr r3, [r3, #4] - 8040f44: f003 0203 and.w r2, r3, #3 - 8040f48: 69fb ldr r3, [r7, #28] - 8040f4a: 005b lsls r3, r3, #1 - 8040f4c: fa02 f303 lsl.w r3, r2, r3 - 8040f50: 69ba ldr r2, [r7, #24] - 8040f52: 4313 orrs r3, r2 - 8040f54: 61bb str r3, [r7, #24] + 8040f3c: 683b ldr r3, [r7, #0] + 8040f3e: 685b ldr r3, [r3, #4] + 8040f40: f003 0203 and.w r2, r3, #3 + 8040f44: 69fb ldr r3, [r7, #28] + 8040f46: 005b lsls r3, r3, #1 + 8040f48: fa02 f303 lsl.w r3, r2, r3 + 8040f4c: 69ba ldr r2, [r7, #24] + 8040f4e: 4313 orrs r3, r2 + 8040f50: 61bb str r3, [r7, #24] GPIOx->MODER = temp; - 8040f56: 687b ldr r3, [r7, #4] - 8040f58: 69ba ldr r2, [r7, #24] - 8040f5a: 601a str r2, [r3, #0] + 8040f52: 687b ldr r3, [r7, #4] + 8040f54: 69ba ldr r2, [r7, #24] + 8040f56: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) - 8040f5c: 683b ldr r3, [r7, #0] - 8040f5e: 685b ldr r3, [r3, #4] - 8040f60: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8040f64: 2b00 cmp r3, #0 - 8040f66: f000 80be beq.w 80410e6 + 8040f58: 683b ldr r3, [r7, #0] + 8040f5a: 685b ldr r3, [r3, #4] + 8040f5c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8040f60: 2b00 cmp r3, #0 + 8040f62: f000 80be beq.w 80410e2 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - 8040f6a: 4b66 ldr r3, [pc, #408] ; (8041104 ) - 8040f6c: 6c5b ldr r3, [r3, #68] ; 0x44 - 8040f6e: 4a65 ldr r2, [pc, #404] ; (8041104 ) - 8040f70: f443 4380 orr.w r3, r3, #16384 ; 0x4000 - 8040f74: 6453 str r3, [r2, #68] ; 0x44 - 8040f76: 4b63 ldr r3, [pc, #396] ; (8041104 ) - 8040f78: 6c5b ldr r3, [r3, #68] ; 0x44 - 8040f7a: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 8040f7e: 60fb str r3, [r7, #12] - 8040f80: 68fb ldr r3, [r7, #12] + 8040f66: 4b66 ldr r3, [pc, #408] ; (8041100 ) + 8040f68: 6c5b ldr r3, [r3, #68] ; 0x44 + 8040f6a: 4a65 ldr r2, [pc, #404] ; (8041100 ) + 8040f6c: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 8040f70: 6453 str r3, [r2, #68] ; 0x44 + 8040f72: 4b63 ldr r3, [pc, #396] ; (8041100 ) + 8040f74: 6c5b ldr r3, [r3, #68] ; 0x44 + 8040f76: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8040f7a: 60fb str r3, [r7, #12] + 8040f7c: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2]; - 8040f82: 4a61 ldr r2, [pc, #388] ; (8041108 ) - 8040f84: 69fb ldr r3, [r7, #28] - 8040f86: 089b lsrs r3, r3, #2 - 8040f88: 3302 adds r3, #2 - 8040f8a: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 8040f8e: 61bb str r3, [r7, #24] + 8040f7e: 4a61 ldr r2, [pc, #388] ; (8041104 ) + 8040f80: 69fb ldr r3, [r7, #28] + 8040f82: 089b lsrs r3, r3, #2 + 8040f84: 3302 adds r3, #2 + 8040f86: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8040f8a: 61bb str r3, [r7, #24] temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); - 8040f90: 69fb ldr r3, [r7, #28] - 8040f92: f003 0303 and.w r3, r3, #3 - 8040f96: 009b lsls r3, r3, #2 - 8040f98: 220f movs r2, #15 - 8040f9a: fa02 f303 lsl.w r3, r2, r3 - 8040f9e: 43db mvns r3, r3 - 8040fa0: 69ba ldr r2, [r7, #24] - 8040fa2: 4013 ands r3, r2 - 8040fa4: 61bb str r3, [r7, #24] + 8040f8c: 69fb ldr r3, [r7, #28] + 8040f8e: f003 0303 and.w r3, r3, #3 + 8040f92: 009b lsls r3, r3, #2 + 8040f94: 220f movs r2, #15 + 8040f96: fa02 f303 lsl.w r3, r2, r3 + 8040f9a: 43db mvns r3, r3 + 8040f9c: 69ba ldr r2, [r7, #24] + 8040f9e: 4013 ands r3, r2 + 8040fa0: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); - 8040fa6: 687b ldr r3, [r7, #4] - 8040fa8: 4a58 ldr r2, [pc, #352] ; (804110c ) - 8040faa: 4293 cmp r3, r2 - 8040fac: d037 beq.n 804101e - 8040fae: 687b ldr r3, [r7, #4] - 8040fb0: 4a57 ldr r2, [pc, #348] ; (8041110 ) - 8040fb2: 4293 cmp r3, r2 - 8040fb4: d031 beq.n 804101a - 8040fb6: 687b ldr r3, [r7, #4] - 8040fb8: 4a56 ldr r2, [pc, #344] ; (8041114 ) - 8040fba: 4293 cmp r3, r2 - 8040fbc: d02b beq.n 8041016 - 8040fbe: 687b ldr r3, [r7, #4] - 8040fc0: 4a55 ldr r2, [pc, #340] ; (8041118 ) - 8040fc2: 4293 cmp r3, r2 - 8040fc4: d025 beq.n 8041012 - 8040fc6: 687b ldr r3, [r7, #4] - 8040fc8: 4a54 ldr r2, [pc, #336] ; (804111c ) - 8040fca: 4293 cmp r3, r2 - 8040fcc: d01f beq.n 804100e - 8040fce: 687b ldr r3, [r7, #4] - 8040fd0: 4a53 ldr r2, [pc, #332] ; (8041120 ) - 8040fd2: 4293 cmp r3, r2 - 8040fd4: d019 beq.n 804100a - 8040fd6: 687b ldr r3, [r7, #4] - 8040fd8: 4a52 ldr r2, [pc, #328] ; (8041124 ) - 8040fda: 4293 cmp r3, r2 - 8040fdc: d013 beq.n 8041006 - 8040fde: 687b ldr r3, [r7, #4] - 8040fe0: 4a51 ldr r2, [pc, #324] ; (8041128 ) - 8040fe2: 4293 cmp r3, r2 - 8040fe4: d00d beq.n 8041002 - 8040fe6: 687b ldr r3, [r7, #4] - 8040fe8: 4a50 ldr r2, [pc, #320] ; (804112c ) - 8040fea: 4293 cmp r3, r2 - 8040fec: d007 beq.n 8040ffe - 8040fee: 687b ldr r3, [r7, #4] - 8040ff0: 4a4f ldr r2, [pc, #316] ; (8041130 ) - 8040ff2: 4293 cmp r3, r2 - 8040ff4: d101 bne.n 8040ffa - 8040ff6: 2309 movs r3, #9 - 8040ff8: e012 b.n 8041020 - 8040ffa: 230a movs r3, #10 - 8040ffc: e010 b.n 8041020 - 8040ffe: 2308 movs r3, #8 - 8041000: e00e b.n 8041020 - 8041002: 2307 movs r3, #7 - 8041004: e00c b.n 8041020 - 8041006: 2306 movs r3, #6 - 8041008: e00a b.n 8041020 - 804100a: 2305 movs r3, #5 - 804100c: e008 b.n 8041020 - 804100e: 2304 movs r3, #4 - 8041010: e006 b.n 8041020 - 8041012: 2303 movs r3, #3 - 8041014: e004 b.n 8041020 - 8041016: 2302 movs r3, #2 - 8041018: e002 b.n 8041020 - 804101a: 2301 movs r3, #1 - 804101c: e000 b.n 8041020 - 804101e: 2300 movs r3, #0 - 8041020: 69fa ldr r2, [r7, #28] - 8041022: f002 0203 and.w r2, r2, #3 - 8041026: 0092 lsls r2, r2, #2 - 8041028: 4093 lsls r3, r2 - 804102a: 69ba ldr r2, [r7, #24] - 804102c: 4313 orrs r3, r2 - 804102e: 61bb str r3, [r7, #24] + 8040fa2: 687b ldr r3, [r7, #4] + 8040fa4: 4a58 ldr r2, [pc, #352] ; (8041108 ) + 8040fa6: 4293 cmp r3, r2 + 8040fa8: d037 beq.n 804101a + 8040faa: 687b ldr r3, [r7, #4] + 8040fac: 4a57 ldr r2, [pc, #348] ; (804110c ) + 8040fae: 4293 cmp r3, r2 + 8040fb0: d031 beq.n 8041016 + 8040fb2: 687b ldr r3, [r7, #4] + 8040fb4: 4a56 ldr r2, [pc, #344] ; (8041110 ) + 8040fb6: 4293 cmp r3, r2 + 8040fb8: d02b beq.n 8041012 + 8040fba: 687b ldr r3, [r7, #4] + 8040fbc: 4a55 ldr r2, [pc, #340] ; (8041114 ) + 8040fbe: 4293 cmp r3, r2 + 8040fc0: d025 beq.n 804100e + 8040fc2: 687b ldr r3, [r7, #4] + 8040fc4: 4a54 ldr r2, [pc, #336] ; (8041118 ) + 8040fc6: 4293 cmp r3, r2 + 8040fc8: d01f beq.n 804100a + 8040fca: 687b ldr r3, [r7, #4] + 8040fcc: 4a53 ldr r2, [pc, #332] ; (804111c ) + 8040fce: 4293 cmp r3, r2 + 8040fd0: d019 beq.n 8041006 + 8040fd2: 687b ldr r3, [r7, #4] + 8040fd4: 4a52 ldr r2, [pc, #328] ; (8041120 ) + 8040fd6: 4293 cmp r3, r2 + 8040fd8: d013 beq.n 8041002 + 8040fda: 687b ldr r3, [r7, #4] + 8040fdc: 4a51 ldr r2, [pc, #324] ; (8041124 ) + 8040fde: 4293 cmp r3, r2 + 8040fe0: d00d beq.n 8040ffe + 8040fe2: 687b ldr r3, [r7, #4] + 8040fe4: 4a50 ldr r2, [pc, #320] ; (8041128 ) + 8040fe6: 4293 cmp r3, r2 + 8040fe8: d007 beq.n 8040ffa + 8040fea: 687b ldr r3, [r7, #4] + 8040fec: 4a4f ldr r2, [pc, #316] ; (804112c ) + 8040fee: 4293 cmp r3, r2 + 8040ff0: d101 bne.n 8040ff6 + 8040ff2: 2309 movs r3, #9 + 8040ff4: e012 b.n 804101c + 8040ff6: 230a movs r3, #10 + 8040ff8: e010 b.n 804101c + 8040ffa: 2308 movs r3, #8 + 8040ffc: e00e b.n 804101c + 8040ffe: 2307 movs r3, #7 + 8041000: e00c b.n 804101c + 8041002: 2306 movs r3, #6 + 8041004: e00a b.n 804101c + 8041006: 2305 movs r3, #5 + 8041008: e008 b.n 804101c + 804100a: 2304 movs r3, #4 + 804100c: e006 b.n 804101c + 804100e: 2303 movs r3, #3 + 8041010: e004 b.n 804101c + 8041012: 2302 movs r3, #2 + 8041014: e002 b.n 804101c + 8041016: 2301 movs r3, #1 + 8041018: e000 b.n 804101c + 804101a: 2300 movs r3, #0 + 804101c: 69fa ldr r2, [r7, #28] + 804101e: f002 0203 and.w r2, r2, #3 + 8041022: 0092 lsls r2, r2, #2 + 8041024: 4093 lsls r3, r2 + 8041026: 69ba ldr r2, [r7, #24] + 8041028: 4313 orrs r3, r2 + 804102a: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2] = temp; - 8041030: 4935 ldr r1, [pc, #212] ; (8041108 ) - 8041032: 69fb ldr r3, [r7, #28] - 8041034: 089b lsrs r3, r3, #2 - 8041036: 3302 adds r3, #2 - 8041038: 69ba ldr r2, [r7, #24] - 804103a: f841 2023 str.w r2, [r1, r3, lsl #2] + 804102c: 4935 ldr r1, [pc, #212] ; (8041104 ) + 804102e: 69fb ldr r3, [r7, #28] + 8041030: 089b lsrs r3, r3, #2 + 8041032: 3302 adds r3, #2 + 8041034: 69ba ldr r2, [r7, #24] + 8041036: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear EXTI line configuration */ temp = EXTI->IMR; - 804103e: 4b3d ldr r3, [pc, #244] ; (8041134 ) - 8041040: 681b ldr r3, [r3, #0] - 8041042: 61bb str r3, [r7, #24] + 804103a: 4b3d ldr r3, [pc, #244] ; (8041130 ) + 804103c: 681b ldr r3, [r3, #0] + 804103e: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); - 8041044: 693b ldr r3, [r7, #16] - 8041046: 43db mvns r3, r3 - 8041048: 69ba ldr r2, [r7, #24] - 804104a: 4013 ands r3, r2 - 804104c: 61bb str r3, [r7, #24] + 8041040: 693b ldr r3, [r7, #16] + 8041042: 43db mvns r3, r3 + 8041044: 69ba ldr r2, [r7, #24] + 8041046: 4013 ands r3, r2 + 8041048: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) - 804104e: 683b ldr r3, [r7, #0] - 8041050: 685b ldr r3, [r3, #4] - 8041052: f403 3380 and.w r3, r3, #65536 ; 0x10000 - 8041056: 2b00 cmp r3, #0 - 8041058: d003 beq.n 8041062 + 804104a: 683b ldr r3, [r7, #0] + 804104c: 685b ldr r3, [r3, #4] + 804104e: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8041052: 2b00 cmp r3, #0 + 8041054: d003 beq.n 804105e { temp |= iocurrent; - 804105a: 69ba ldr r2, [r7, #24] - 804105c: 693b ldr r3, [r7, #16] - 804105e: 4313 orrs r3, r2 - 8041060: 61bb str r3, [r7, #24] + 8041056: 69ba ldr r2, [r7, #24] + 8041058: 693b ldr r3, [r7, #16] + 804105a: 4313 orrs r3, r2 + 804105c: 61bb str r3, [r7, #24] } EXTI->IMR = temp; - 8041062: 4a34 ldr r2, [pc, #208] ; (8041134 ) - 8041064: 69bb ldr r3, [r7, #24] - 8041066: 6013 str r3, [r2, #0] + 804105e: 4a34 ldr r2, [pc, #208] ; (8041130 ) + 8041060: 69bb ldr r3, [r7, #24] + 8041062: 6013 str r3, [r2, #0] temp = EXTI->EMR; - 8041068: 4b32 ldr r3, [pc, #200] ; (8041134 ) - 804106a: 685b ldr r3, [r3, #4] - 804106c: 61bb str r3, [r7, #24] + 8041064: 4b32 ldr r3, [pc, #200] ; (8041130 ) + 8041066: 685b ldr r3, [r3, #4] + 8041068: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); - 804106e: 693b ldr r3, [r7, #16] - 8041070: 43db mvns r3, r3 - 8041072: 69ba ldr r2, [r7, #24] - 8041074: 4013 ands r3, r2 - 8041076: 61bb str r3, [r7, #24] + 804106a: 693b ldr r3, [r7, #16] + 804106c: 43db mvns r3, r3 + 804106e: 69ba ldr r2, [r7, #24] + 8041070: 4013 ands r3, r2 + 8041072: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) - 8041078: 683b ldr r3, [r7, #0] - 804107a: 685b ldr r3, [r3, #4] - 804107c: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 8041080: 2b00 cmp r3, #0 - 8041082: d003 beq.n 804108c + 8041074: 683b ldr r3, [r7, #0] + 8041076: 685b ldr r3, [r3, #4] + 8041078: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 804107c: 2b00 cmp r3, #0 + 804107e: d003 beq.n 8041088 { temp |= iocurrent; - 8041084: 69ba ldr r2, [r7, #24] - 8041086: 693b ldr r3, [r7, #16] - 8041088: 4313 orrs r3, r2 - 804108a: 61bb str r3, [r7, #24] + 8041080: 69ba ldr r2, [r7, #24] + 8041082: 693b ldr r3, [r7, #16] + 8041084: 4313 orrs r3, r2 + 8041086: 61bb str r3, [r7, #24] } EXTI->EMR = temp; - 804108c: 4a29 ldr r2, [pc, #164] ; (8041134 ) - 804108e: 69bb ldr r3, [r7, #24] - 8041090: 6053 str r3, [r2, #4] + 8041088: 4a29 ldr r2, [pc, #164] ; (8041130 ) + 804108a: 69bb ldr r3, [r7, #24] + 804108c: 6053 str r3, [r2, #4] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; - 8041092: 4b28 ldr r3, [pc, #160] ; (8041134 ) - 8041094: 689b ldr r3, [r3, #8] - 8041096: 61bb str r3, [r7, #24] + 804108e: 4b28 ldr r3, [pc, #160] ; (8041130 ) + 8041090: 689b ldr r3, [r3, #8] + 8041092: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); - 8041098: 693b ldr r3, [r7, #16] - 804109a: 43db mvns r3, r3 - 804109c: 69ba ldr r2, [r7, #24] - 804109e: 4013 ands r3, r2 - 80410a0: 61bb str r3, [r7, #24] + 8041094: 693b ldr r3, [r7, #16] + 8041096: 43db mvns r3, r3 + 8041098: 69ba ldr r2, [r7, #24] + 804109a: 4013 ands r3, r2 + 804109c: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) - 80410a2: 683b ldr r3, [r7, #0] - 80410a4: 685b ldr r3, [r3, #4] - 80410a6: f403 1380 and.w r3, r3, #1048576 ; 0x100000 - 80410aa: 2b00 cmp r3, #0 - 80410ac: d003 beq.n 80410b6 + 804109e: 683b ldr r3, [r7, #0] + 80410a0: 685b ldr r3, [r3, #4] + 80410a2: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 80410a6: 2b00 cmp r3, #0 + 80410a8: d003 beq.n 80410b2 { temp |= iocurrent; - 80410ae: 69ba ldr r2, [r7, #24] - 80410b0: 693b ldr r3, [r7, #16] - 80410b2: 4313 orrs r3, r2 - 80410b4: 61bb str r3, [r7, #24] + 80410aa: 69ba ldr r2, [r7, #24] + 80410ac: 693b ldr r3, [r7, #16] + 80410ae: 4313 orrs r3, r2 + 80410b0: 61bb str r3, [r7, #24] } EXTI->RTSR = temp; - 80410b6: 4a1f ldr r2, [pc, #124] ; (8041134 ) - 80410b8: 69bb ldr r3, [r7, #24] - 80410ba: 6093 str r3, [r2, #8] + 80410b2: 4a1f ldr r2, [pc, #124] ; (8041130 ) + 80410b4: 69bb ldr r3, [r7, #24] + 80410b6: 6093 str r3, [r2, #8] temp = EXTI->FTSR; - 80410bc: 4b1d ldr r3, [pc, #116] ; (8041134 ) - 80410be: 68db ldr r3, [r3, #12] - 80410c0: 61bb str r3, [r7, #24] + 80410b8: 4b1d ldr r3, [pc, #116] ; (8041130 ) + 80410ba: 68db ldr r3, [r3, #12] + 80410bc: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); - 80410c2: 693b ldr r3, [r7, #16] - 80410c4: 43db mvns r3, r3 - 80410c6: 69ba ldr r2, [r7, #24] - 80410c8: 4013 ands r3, r2 - 80410ca: 61bb str r3, [r7, #24] + 80410be: 693b ldr r3, [r7, #16] + 80410c0: 43db mvns r3, r3 + 80410c2: 69ba ldr r2, [r7, #24] + 80410c4: 4013 ands r3, r2 + 80410c6: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) - 80410cc: 683b ldr r3, [r7, #0] - 80410ce: 685b ldr r3, [r3, #4] - 80410d0: f403 1300 and.w r3, r3, #2097152 ; 0x200000 - 80410d4: 2b00 cmp r3, #0 - 80410d6: d003 beq.n 80410e0 + 80410c8: 683b ldr r3, [r7, #0] + 80410ca: 685b ldr r3, [r3, #4] + 80410cc: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 80410d0: 2b00 cmp r3, #0 + 80410d2: d003 beq.n 80410dc { temp |= iocurrent; - 80410d8: 69ba ldr r2, [r7, #24] - 80410da: 693b ldr r3, [r7, #16] - 80410dc: 4313 orrs r3, r2 - 80410de: 61bb str r3, [r7, #24] + 80410d4: 69ba ldr r2, [r7, #24] + 80410d6: 693b ldr r3, [r7, #16] + 80410d8: 4313 orrs r3, r2 + 80410da: 61bb str r3, [r7, #24] } EXTI->FTSR = temp; - 80410e0: 4a14 ldr r2, [pc, #80] ; (8041134 ) - 80410e2: 69bb ldr r3, [r7, #24] - 80410e4: 60d3 str r3, [r2, #12] + 80410dc: 4a14 ldr r2, [pc, #80] ; (8041130 ) + 80410de: 69bb ldr r3, [r7, #24] + 80410e0: 60d3 str r3, [r2, #12] for(position = 0; position < GPIO_NUMBER; position++) - 80410e6: 69fb ldr r3, [r7, #28] - 80410e8: 3301 adds r3, #1 - 80410ea: 61fb str r3, [r7, #28] - 80410ec: 69fb ldr r3, [r7, #28] - 80410ee: 2b0f cmp r3, #15 - 80410f0: f67f ae86 bls.w 8040e00 + 80410e2: 69fb ldr r3, [r7, #28] + 80410e4: 3301 adds r3, #1 + 80410e6: 61fb str r3, [r7, #28] + 80410e8: 69fb ldr r3, [r7, #28] + 80410ea: 2b0f cmp r3, #15 + 80410ec: f67f ae86 bls.w 8040dfc } } } } - 80410f4: bf00 nop - 80410f6: bf00 nop - 80410f8: 3724 adds r7, #36 ; 0x24 - 80410fa: 46bd mov sp, r7 - 80410fc: f85d 7b04 ldr.w r7, [sp], #4 - 8041100: 4770 bx lr - 8041102: bf00 nop - 8041104: 40023800 .word 0x40023800 - 8041108: 40013800 .word 0x40013800 - 804110c: 40020000 .word 0x40020000 - 8041110: 40020400 .word 0x40020400 - 8041114: 40020800 .word 0x40020800 - 8041118: 40020c00 .word 0x40020c00 - 804111c: 40021000 .word 0x40021000 - 8041120: 40021400 .word 0x40021400 - 8041124: 40021800 .word 0x40021800 - 8041128: 40021c00 .word 0x40021c00 - 804112c: 40022000 .word 0x40022000 - 8041130: 40022400 .word 0x40022400 - 8041134: 40013c00 .word 0x40013c00 - -08041138 : + 80410f0: bf00 nop + 80410f2: bf00 nop + 80410f4: 3724 adds r7, #36 ; 0x24 + 80410f6: 46bd mov sp, r7 + 80410f8: f85d 7b04 ldr.w r7, [sp], #4 + 80410fc: 4770 bx lr + 80410fe: bf00 nop + 8041100: 40023800 .word 0x40023800 + 8041104: 40013800 .word 0x40013800 + 8041108: 40020000 .word 0x40020000 + 804110c: 40020400 .word 0x40020400 + 8041110: 40020800 .word 0x40020800 + 8041114: 40020c00 .word 0x40020c00 + 8041118: 40021000 .word 0x40021000 + 804111c: 40021400 .word 0x40021400 + 8041120: 40021800 .word 0x40021800 + 8041124: 40021c00 .word 0x40021c00 + 8041128: 40022000 .word 0x40022000 + 804112c: 40022400 .word 0x40022400 + 8041130: 40013c00 .word 0x40013c00 + +08041134 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { - 8041138: b480 push {r7} - 804113a: b083 sub sp, #12 - 804113c: af00 add r7, sp, #0 - 804113e: 6078 str r0, [r7, #4] - 8041140: 460b mov r3, r1 - 8041142: 807b strh r3, [r7, #2] - 8041144: 4613 mov r3, r2 - 8041146: 707b strb r3, [r7, #1] + 8041134: b480 push {r7} + 8041136: b083 sub sp, #12 + 8041138: af00 add r7, sp, #0 + 804113a: 6078 str r0, [r7, #4] + 804113c: 460b mov r3, r1 + 804113e: 807b strh r3, [r7, #2] + 8041140: 4613 mov r3, r2 + 8041142: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) - 8041148: 787b ldrb r3, [r7, #1] - 804114a: 2b00 cmp r3, #0 - 804114c: d003 beq.n 8041156 + 8041144: 787b ldrb r3, [r7, #1] + 8041146: 2b00 cmp r3, #0 + 8041148: d003 beq.n 8041152 { GPIOx->BSRR = GPIO_Pin; - 804114e: 887a ldrh r2, [r7, #2] - 8041150: 687b ldr r3, [r7, #4] - 8041152: 619a str r2, [r3, #24] + 804114a: 887a ldrh r2, [r7, #2] + 804114c: 687b ldr r3, [r7, #4] + 804114e: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; } } - 8041154: e003 b.n 804115e + 8041150: e003 b.n 804115a GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; - 8041156: 887b ldrh r3, [r7, #2] - 8041158: 041a lsls r2, r3, #16 - 804115a: 687b ldr r3, [r7, #4] - 804115c: 619a str r2, [r3, #24] + 8041152: 887b ldrh r3, [r7, #2] + 8041154: 041a lsls r2, r3, #16 + 8041156: 687b ldr r3, [r7, #4] + 8041158: 619a str r2, [r3, #24] } - 804115e: bf00 nop - 8041160: 370c adds r7, #12 - 8041162: 46bd mov sp, r7 - 8041164: f85d 7b04 ldr.w r7, [sp], #4 - 8041168: 4770 bx lr + 804115a: bf00 nop + 804115c: 370c adds r7, #12 + 804115e: 46bd mov sp, r7 + 8041160: f85d 7b04 ldr.w r7, [sp], #4 + 8041164: 4770 bx lr ... -0804116c : +08041168 : * supported by this function. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - 804116c: b580 push {r7, lr} - 804116e: b086 sub sp, #24 - 8041170: af00 add r7, sp, #0 - 8041172: 6078 str r0, [r7, #4] + 8041168: b580 push {r7, lr} + 804116a: b086 sub sp, #24 + 804116c: af00 add r7, sp, #0 + 804116e: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; FlagStatus pwrclkchanged = RESET; - 8041174: 2300 movs r3, #0 - 8041176: 75fb strb r3, [r7, #23] + 8041170: 2300 movs r3, #0 + 8041172: 75fb strb r3, [r7, #23] /* Check Null pointer */ if (RCC_OscInitStruct == NULL) - 8041178: 687b ldr r3, [r7, #4] - 804117a: 2b00 cmp r3, #0 - 804117c: d101 bne.n 8041182 + 8041174: 687b ldr r3, [r7, #4] + 8041176: 2b00 cmp r3, #0 + 8041178: d101 bne.n 804117e { return HAL_ERROR; - 804117e: 2301 movs r3, #1 - 8041180: e29b b.n 80416ba + 804117a: 2301 movs r3, #1 + 804117c: e29b b.n 80416b6 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - 8041182: 687b ldr r3, [r7, #4] - 8041184: 681b ldr r3, [r3, #0] - 8041186: f003 0301 and.w r3, r3, #1 - 804118a: 2b00 cmp r3, #0 - 804118c: f000 8087 beq.w 804129e + 804117e: 687b ldr r3, [r7, #4] + 8041180: 681b ldr r3, [r3, #0] + 8041182: f003 0301 and.w r3, r3, #1 + 8041186: 2b00 cmp r3, #0 + 8041188: f000 8087 beq.w 804129a { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) - 8041190: 4b96 ldr r3, [pc, #600] ; (80413ec ) - 8041192: 689b ldr r3, [r3, #8] - 8041194: f003 030c and.w r3, r3, #12 - 8041198: 2b04 cmp r3, #4 - 804119a: d00c beq.n 80411b6 + 804118c: 4b96 ldr r3, [pc, #600] ; (80413e8 ) + 804118e: 689b ldr r3, [r3, #8] + 8041190: f003 030c and.w r3, r3, #12 + 8041194: 2b04 cmp r3, #4 + 8041196: d00c beq.n 80411b2 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) - 804119c: 4b93 ldr r3, [pc, #588] ; (80413ec ) - 804119e: 689b ldr r3, [r3, #8] - 80411a0: f003 030c and.w r3, r3, #12 - 80411a4: 2b08 cmp r3, #8 - 80411a6: d112 bne.n 80411ce - 80411a8: 4b90 ldr r3, [pc, #576] ; (80413ec ) - 80411aa: 685b ldr r3, [r3, #4] - 80411ac: f403 0380 and.w r3, r3, #4194304 ; 0x400000 - 80411b0: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 - 80411b4: d10b bne.n 80411ce + 8041198: 4b93 ldr r3, [pc, #588] ; (80413e8 ) + 804119a: 689b ldr r3, [r3, #8] + 804119c: f003 030c and.w r3, r3, #12 + 80411a0: 2b08 cmp r3, #8 + 80411a2: d112 bne.n 80411ca + 80411a4: 4b90 ldr r3, [pc, #576] ; (80413e8 ) + 80411a6: 685b ldr r3, [r3, #4] + 80411a8: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 80411ac: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 80411b0: d10b bne.n 80411ca { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 80411b6: 4b8d ldr r3, [pc, #564] ; (80413ec ) - 80411b8: 681b ldr r3, [r3, #0] - 80411ba: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 80411be: 2b00 cmp r3, #0 - 80411c0: d06c beq.n 804129c - 80411c2: 687b ldr r3, [r7, #4] - 80411c4: 685b ldr r3, [r3, #4] - 80411c6: 2b00 cmp r3, #0 - 80411c8: d168 bne.n 804129c + 80411b2: 4b8d ldr r3, [pc, #564] ; (80413e8 ) + 80411b4: 681b ldr r3, [r3, #0] + 80411b6: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 80411ba: 2b00 cmp r3, #0 + 80411bc: d06c beq.n 8041298 + 80411be: 687b ldr r3, [r7, #4] + 80411c0: 685b ldr r3, [r3, #4] + 80411c2: 2b00 cmp r3, #0 + 80411c4: d168 bne.n 8041298 { return HAL_ERROR; - 80411ca: 2301 movs r3, #1 - 80411cc: e275 b.n 80416ba + 80411c6: 2301 movs r3, #1 + 80411c8: e275 b.n 80416b6 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - 80411ce: 687b ldr r3, [r7, #4] - 80411d0: 685b ldr r3, [r3, #4] - 80411d2: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 - 80411d6: d106 bne.n 80411e6 - 80411d8: 4b84 ldr r3, [pc, #528] ; (80413ec ) - 80411da: 681b ldr r3, [r3, #0] - 80411dc: 4a83 ldr r2, [pc, #524] ; (80413ec ) - 80411de: f443 3380 orr.w r3, r3, #65536 ; 0x10000 - 80411e2: 6013 str r3, [r2, #0] - 80411e4: e02e b.n 8041244 - 80411e6: 687b ldr r3, [r7, #4] - 80411e8: 685b ldr r3, [r3, #4] - 80411ea: 2b00 cmp r3, #0 - 80411ec: d10c bne.n 8041208 - 80411ee: 4b7f ldr r3, [pc, #508] ; (80413ec ) - 80411f0: 681b ldr r3, [r3, #0] - 80411f2: 4a7e ldr r2, [pc, #504] ; (80413ec ) - 80411f4: f423 3380 bic.w r3, r3, #65536 ; 0x10000 - 80411f8: 6013 str r3, [r2, #0] - 80411fa: 4b7c ldr r3, [pc, #496] ; (80413ec ) - 80411fc: 681b ldr r3, [r3, #0] - 80411fe: 4a7b ldr r2, [pc, #492] ; (80413ec ) - 8041200: f423 2380 bic.w r3, r3, #262144 ; 0x40000 - 8041204: 6013 str r3, [r2, #0] - 8041206: e01d b.n 8041244 - 8041208: 687b ldr r3, [r7, #4] - 804120a: 685b ldr r3, [r3, #4] - 804120c: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 - 8041210: d10c bne.n 804122c - 8041212: 4b76 ldr r3, [pc, #472] ; (80413ec ) - 8041214: 681b ldr r3, [r3, #0] - 8041216: 4a75 ldr r2, [pc, #468] ; (80413ec ) - 8041218: f443 2380 orr.w r3, r3, #262144 ; 0x40000 - 804121c: 6013 str r3, [r2, #0] - 804121e: 4b73 ldr r3, [pc, #460] ; (80413ec ) - 8041220: 681b ldr r3, [r3, #0] - 8041222: 4a72 ldr r2, [pc, #456] ; (80413ec ) - 8041224: f443 3380 orr.w r3, r3, #65536 ; 0x10000 - 8041228: 6013 str r3, [r2, #0] - 804122a: e00b b.n 8041244 - 804122c: 4b6f ldr r3, [pc, #444] ; (80413ec ) - 804122e: 681b ldr r3, [r3, #0] - 8041230: 4a6e ldr r2, [pc, #440] ; (80413ec ) - 8041232: f423 3380 bic.w r3, r3, #65536 ; 0x10000 - 8041236: 6013 str r3, [r2, #0] - 8041238: 4b6c ldr r3, [pc, #432] ; (80413ec ) - 804123a: 681b ldr r3, [r3, #0] - 804123c: 4a6b ldr r2, [pc, #428] ; (80413ec ) - 804123e: f423 2380 bic.w r3, r3, #262144 ; 0x40000 - 8041242: 6013 str r3, [r2, #0] + 80411ca: 687b ldr r3, [r7, #4] + 80411cc: 685b ldr r3, [r3, #4] + 80411ce: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 80411d2: d106 bne.n 80411e2 + 80411d4: 4b84 ldr r3, [pc, #528] ; (80413e8 ) + 80411d6: 681b ldr r3, [r3, #0] + 80411d8: 4a83 ldr r2, [pc, #524] ; (80413e8 ) + 80411da: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 80411de: 6013 str r3, [r2, #0] + 80411e0: e02e b.n 8041240 + 80411e2: 687b ldr r3, [r7, #4] + 80411e4: 685b ldr r3, [r3, #4] + 80411e6: 2b00 cmp r3, #0 + 80411e8: d10c bne.n 8041204 + 80411ea: 4b7f ldr r3, [pc, #508] ; (80413e8 ) + 80411ec: 681b ldr r3, [r3, #0] + 80411ee: 4a7e ldr r2, [pc, #504] ; (80413e8 ) + 80411f0: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 80411f4: 6013 str r3, [r2, #0] + 80411f6: 4b7c ldr r3, [pc, #496] ; (80413e8 ) + 80411f8: 681b ldr r3, [r3, #0] + 80411fa: 4a7b ldr r2, [pc, #492] ; (80413e8 ) + 80411fc: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 8041200: 6013 str r3, [r2, #0] + 8041202: e01d b.n 8041240 + 8041204: 687b ldr r3, [r7, #4] + 8041206: 685b ldr r3, [r3, #4] + 8041208: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 + 804120c: d10c bne.n 8041228 + 804120e: 4b76 ldr r3, [pc, #472] ; (80413e8 ) + 8041210: 681b ldr r3, [r3, #0] + 8041212: 4a75 ldr r2, [pc, #468] ; (80413e8 ) + 8041214: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 8041218: 6013 str r3, [r2, #0] + 804121a: 4b73 ldr r3, [pc, #460] ; (80413e8 ) + 804121c: 681b ldr r3, [r3, #0] + 804121e: 4a72 ldr r2, [pc, #456] ; (80413e8 ) + 8041220: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8041224: 6013 str r3, [r2, #0] + 8041226: e00b b.n 8041240 + 8041228: 4b6f ldr r3, [pc, #444] ; (80413e8 ) + 804122a: 681b ldr r3, [r3, #0] + 804122c: 4a6e ldr r2, [pc, #440] ; (80413e8 ) + 804122e: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8041232: 6013 str r3, [r2, #0] + 8041234: 4b6c ldr r3, [pc, #432] ; (80413e8 ) + 8041236: 681b ldr r3, [r3, #0] + 8041238: 4a6b ldr r2, [pc, #428] ; (80413e8 ) + 804123a: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 804123e: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - 8041244: 687b ldr r3, [r7, #4] - 8041246: 685b ldr r3, [r3, #4] - 8041248: 2b00 cmp r3, #0 - 804124a: d013 beq.n 8041274 + 8041240: 687b ldr r3, [r7, #4] + 8041242: 685b ldr r3, [r3, #4] + 8041244: 2b00 cmp r3, #0 + 8041246: d013 beq.n 8041270 { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 804124c: f7ff fcb2 bl 8040bb4 - 8041250: 6138 str r0, [r7, #16] + 8041248: f7ff fcb2 bl 8040bb0 + 804124c: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 8041252: e008 b.n 8041266 + 804124e: e008 b.n 8041262 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - 8041254: f7ff fcae bl 8040bb4 - 8041258: 4602 mov r2, r0 - 804125a: 693b ldr r3, [r7, #16] - 804125c: 1ad3 subs r3, r2, r3 - 804125e: 2b64 cmp r3, #100 ; 0x64 - 8041260: d901 bls.n 8041266 + 8041250: f7ff fcae bl 8040bb0 + 8041254: 4602 mov r2, r0 + 8041256: 693b ldr r3, [r7, #16] + 8041258: 1ad3 subs r3, r2, r3 + 804125a: 2b64 cmp r3, #100 ; 0x64 + 804125c: d901 bls.n 8041262 { return HAL_TIMEOUT; - 8041262: 2303 movs r3, #3 - 8041264: e229 b.n 80416ba + 804125e: 2303 movs r3, #3 + 8041260: e229 b.n 80416b6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 8041266: 4b61 ldr r3, [pc, #388] ; (80413ec ) - 8041268: 681b ldr r3, [r3, #0] - 804126a: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 804126e: 2b00 cmp r3, #0 - 8041270: d0f0 beq.n 8041254 - 8041272: e014 b.n 804129e + 8041262: 4b61 ldr r3, [pc, #388] ; (80413e8 ) + 8041264: 681b ldr r3, [r3, #0] + 8041266: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 804126a: 2b00 cmp r3, #0 + 804126c: d0f0 beq.n 8041250 + 804126e: e014 b.n 804129a } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8041274: f7ff fc9e bl 8040bb4 - 8041278: 6138 str r0, [r7, #16] + 8041270: f7ff fc9e bl 8040bb0 + 8041274: 6138 str r0, [r7, #16] /* Wait till HSE is bypassed or disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - 804127a: e008 b.n 804128e + 8041276: e008 b.n 804128a { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - 804127c: f7ff fc9a bl 8040bb4 - 8041280: 4602 mov r2, r0 - 8041282: 693b ldr r3, [r7, #16] - 8041284: 1ad3 subs r3, r2, r3 - 8041286: 2b64 cmp r3, #100 ; 0x64 - 8041288: d901 bls.n 804128e + 8041278: f7ff fc9a bl 8040bb0 + 804127c: 4602 mov r2, r0 + 804127e: 693b ldr r3, [r7, #16] + 8041280: 1ad3 subs r3, r2, r3 + 8041282: 2b64 cmp r3, #100 ; 0x64 + 8041284: d901 bls.n 804128a { return HAL_TIMEOUT; - 804128a: 2303 movs r3, #3 - 804128c: e215 b.n 80416ba + 8041286: 2303 movs r3, #3 + 8041288: e215 b.n 80416b6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - 804128e: 4b57 ldr r3, [pc, #348] ; (80413ec ) - 8041290: 681b ldr r3, [r3, #0] - 8041292: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 8041296: 2b00 cmp r3, #0 - 8041298: d1f0 bne.n 804127c - 804129a: e000 b.n 804129e + 804128a: 4b57 ldr r3, [pc, #348] ; (80413e8 ) + 804128c: 681b ldr r3, [r3, #0] + 804128e: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8041292: 2b00 cmp r3, #0 + 8041294: d1f0 bne.n 8041278 + 8041296: e000 b.n 804129a if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 804129c: bf00 nop + 8041298: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - 804129e: 687b ldr r3, [r7, #4] - 80412a0: 681b ldr r3, [r3, #0] - 80412a2: f003 0302 and.w r3, r3, #2 - 80412a6: 2b00 cmp r3, #0 - 80412a8: d069 beq.n 804137e + 804129a: 687b ldr r3, [r7, #4] + 804129c: 681b ldr r3, [r3, #0] + 804129e: f003 0302 and.w r3, r3, #2 + 80412a2: 2b00 cmp r3, #0 + 80412a4: d069 beq.n 804137a /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) - 80412aa: 4b50 ldr r3, [pc, #320] ; (80413ec ) - 80412ac: 689b ldr r3, [r3, #8] - 80412ae: f003 030c and.w r3, r3, #12 - 80412b2: 2b00 cmp r3, #0 - 80412b4: d00b beq.n 80412ce + 80412a6: 4b50 ldr r3, [pc, #320] ; (80413e8 ) + 80412a8: 689b ldr r3, [r3, #8] + 80412aa: f003 030c and.w r3, r3, #12 + 80412ae: 2b00 cmp r3, #0 + 80412b0: d00b beq.n 80412ca || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) - 80412b6: 4b4d ldr r3, [pc, #308] ; (80413ec ) - 80412b8: 689b ldr r3, [r3, #8] - 80412ba: f003 030c and.w r3, r3, #12 - 80412be: 2b08 cmp r3, #8 - 80412c0: d11c bne.n 80412fc - 80412c2: 4b4a ldr r3, [pc, #296] ; (80413ec ) - 80412c4: 685b ldr r3, [r3, #4] - 80412c6: f403 0380 and.w r3, r3, #4194304 ; 0x400000 - 80412ca: 2b00 cmp r3, #0 - 80412cc: d116 bne.n 80412fc + 80412b2: 4b4d ldr r3, [pc, #308] ; (80413e8 ) + 80412b4: 689b ldr r3, [r3, #8] + 80412b6: f003 030c and.w r3, r3, #12 + 80412ba: 2b08 cmp r3, #8 + 80412bc: d11c bne.n 80412f8 + 80412be: 4b4a ldr r3, [pc, #296] ; (80413e8 ) + 80412c0: 685b ldr r3, [r3, #4] + 80412c2: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 80412c6: 2b00 cmp r3, #0 + 80412c8: d116 bne.n 80412f8 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - 80412ce: 4b47 ldr r3, [pc, #284] ; (80413ec ) - 80412d0: 681b ldr r3, [r3, #0] - 80412d2: f003 0302 and.w r3, r3, #2 - 80412d6: 2b00 cmp r3, #0 - 80412d8: d005 beq.n 80412e6 - 80412da: 687b ldr r3, [r7, #4] - 80412dc: 68db ldr r3, [r3, #12] - 80412de: 2b01 cmp r3, #1 - 80412e0: d001 beq.n 80412e6 + 80412ca: 4b47 ldr r3, [pc, #284] ; (80413e8 ) + 80412cc: 681b ldr r3, [r3, #0] + 80412ce: f003 0302 and.w r3, r3, #2 + 80412d2: 2b00 cmp r3, #0 + 80412d4: d005 beq.n 80412e2 + 80412d6: 687b ldr r3, [r7, #4] + 80412d8: 68db ldr r3, [r3, #12] + 80412da: 2b01 cmp r3, #1 + 80412dc: d001 beq.n 80412e2 { return HAL_ERROR; - 80412e2: 2301 movs r3, #1 - 80412e4: e1e9 b.n 80416ba + 80412de: 2301 movs r3, #1 + 80412e0: e1e9 b.n 80416b6 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 80412e6: 4b41 ldr r3, [pc, #260] ; (80413ec ) - 80412e8: 681b ldr r3, [r3, #0] - 80412ea: f023 02f8 bic.w r2, r3, #248 ; 0xf8 - 80412ee: 687b ldr r3, [r7, #4] - 80412f0: 691b ldr r3, [r3, #16] - 80412f2: 00db lsls r3, r3, #3 - 80412f4: 493d ldr r1, [pc, #244] ; (80413ec ) - 80412f6: 4313 orrs r3, r2 - 80412f8: 600b str r3, [r1, #0] + 80412e2: 4b41 ldr r3, [pc, #260] ; (80413e8 ) + 80412e4: 681b ldr r3, [r3, #0] + 80412e6: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 80412ea: 687b ldr r3, [r7, #4] + 80412ec: 691b ldr r3, [r3, #16] + 80412ee: 00db lsls r3, r3, #3 + 80412f0: 493d ldr r1, [pc, #244] ; (80413e8 ) + 80412f2: 4313 orrs r3, r2 + 80412f4: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - 80412fa: e040 b.n 804137e + 80412f6: e040 b.n 804137a } } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) - 80412fc: 687b ldr r3, [r7, #4] - 80412fe: 68db ldr r3, [r3, #12] - 8041300: 2b00 cmp r3, #0 - 8041302: d023 beq.n 804134c + 80412f8: 687b ldr r3, [r7, #4] + 80412fa: 68db ldr r3, [r3, #12] + 80412fc: 2b00 cmp r3, #0 + 80412fe: d023 beq.n 8041348 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); - 8041304: 4b39 ldr r3, [pc, #228] ; (80413ec ) - 8041306: 681b ldr r3, [r3, #0] - 8041308: 4a38 ldr r2, [pc, #224] ; (80413ec ) - 804130a: f043 0301 orr.w r3, r3, #1 - 804130e: 6013 str r3, [r2, #0] + 8041300: 4b39 ldr r3, [pc, #228] ; (80413e8 ) + 8041302: 681b ldr r3, [r3, #0] + 8041304: 4a38 ldr r2, [pc, #224] ; (80413e8 ) + 8041306: f043 0301 orr.w r3, r3, #1 + 804130a: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8041310: f7ff fc50 bl 8040bb4 - 8041314: 6138 str r0, [r7, #16] + 804130c: f7ff fc50 bl 8040bb0 + 8041310: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 8041316: e008 b.n 804132a + 8041312: e008 b.n 8041326 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - 8041318: f7ff fc4c bl 8040bb4 - 804131c: 4602 mov r2, r0 - 804131e: 693b ldr r3, [r7, #16] - 8041320: 1ad3 subs r3, r2, r3 - 8041322: 2b02 cmp r3, #2 - 8041324: d901 bls.n 804132a + 8041314: f7ff fc4c bl 8040bb0 + 8041318: 4602 mov r2, r0 + 804131a: 693b ldr r3, [r7, #16] + 804131c: 1ad3 subs r3, r2, r3 + 804131e: 2b02 cmp r3, #2 + 8041320: d901 bls.n 8041326 { return HAL_TIMEOUT; - 8041326: 2303 movs r3, #3 - 8041328: e1c7 b.n 80416ba + 8041322: 2303 movs r3, #3 + 8041324: e1c7 b.n 80416b6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 804132a: 4b30 ldr r3, [pc, #192] ; (80413ec ) - 804132c: 681b ldr r3, [r3, #0] - 804132e: f003 0302 and.w r3, r3, #2 - 8041332: 2b00 cmp r3, #0 - 8041334: d0f0 beq.n 8041318 + 8041326: 4b30 ldr r3, [pc, #192] ; (80413e8 ) + 8041328: 681b ldr r3, [r3, #0] + 804132a: f003 0302 and.w r3, r3, #2 + 804132e: 2b00 cmp r3, #0 + 8041330: d0f0 beq.n 8041314 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 8041336: 4b2d ldr r3, [pc, #180] ; (80413ec ) - 8041338: 681b ldr r3, [r3, #0] - 804133a: f023 02f8 bic.w r2, r3, #248 ; 0xf8 - 804133e: 687b ldr r3, [r7, #4] - 8041340: 691b ldr r3, [r3, #16] - 8041342: 00db lsls r3, r3, #3 - 8041344: 4929 ldr r1, [pc, #164] ; (80413ec ) - 8041346: 4313 orrs r3, r2 - 8041348: 600b str r3, [r1, #0] - 804134a: e018 b.n 804137e + 8041332: 4b2d ldr r3, [pc, #180] ; (80413e8 ) + 8041334: 681b ldr r3, [r3, #0] + 8041336: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 804133a: 687b ldr r3, [r7, #4] + 804133c: 691b ldr r3, [r3, #16] + 804133e: 00db lsls r3, r3, #3 + 8041340: 4929 ldr r1, [pc, #164] ; (80413e8 ) + 8041342: 4313 orrs r3, r2 + 8041344: 600b str r3, [r1, #0] + 8041346: e018 b.n 804137a } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); - 804134c: 4b27 ldr r3, [pc, #156] ; (80413ec ) - 804134e: 681b ldr r3, [r3, #0] - 8041350: 4a26 ldr r2, [pc, #152] ; (80413ec ) - 8041352: f023 0301 bic.w r3, r3, #1 - 8041356: 6013 str r3, [r2, #0] + 8041348: 4b27 ldr r3, [pc, #156] ; (80413e8 ) + 804134a: 681b ldr r3, [r3, #0] + 804134c: 4a26 ldr r2, [pc, #152] ; (80413e8 ) + 804134e: f023 0301 bic.w r3, r3, #1 + 8041352: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8041358: f7ff fc2c bl 8040bb4 - 804135c: 6138 str r0, [r7, #16] + 8041354: f7ff fc2c bl 8040bb0 + 8041358: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - 804135e: e008 b.n 8041372 + 804135a: e008 b.n 804136e { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - 8041360: f7ff fc28 bl 8040bb4 - 8041364: 4602 mov r2, r0 - 8041366: 693b ldr r3, [r7, #16] - 8041368: 1ad3 subs r3, r2, r3 - 804136a: 2b02 cmp r3, #2 - 804136c: d901 bls.n 8041372 + 804135c: f7ff fc28 bl 8040bb0 + 8041360: 4602 mov r2, r0 + 8041362: 693b ldr r3, [r7, #16] + 8041364: 1ad3 subs r3, r2, r3 + 8041366: 2b02 cmp r3, #2 + 8041368: d901 bls.n 804136e { return HAL_TIMEOUT; - 804136e: 2303 movs r3, #3 - 8041370: e1a3 b.n 80416ba + 804136a: 2303 movs r3, #3 + 804136c: e1a3 b.n 80416b6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - 8041372: 4b1e ldr r3, [pc, #120] ; (80413ec ) - 8041374: 681b ldr r3, [r3, #0] - 8041376: f003 0302 and.w r3, r3, #2 - 804137a: 2b00 cmp r3, #0 - 804137c: d1f0 bne.n 8041360 + 804136e: 4b1e ldr r3, [pc, #120] ; (80413e8 ) + 8041370: 681b ldr r3, [r3, #0] + 8041372: f003 0302 and.w r3, r3, #2 + 8041376: 2b00 cmp r3, #0 + 8041378: d1f0 bne.n 804135c } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - 804137e: 687b ldr r3, [r7, #4] - 8041380: 681b ldr r3, [r3, #0] - 8041382: f003 0308 and.w r3, r3, #8 - 8041386: 2b00 cmp r3, #0 - 8041388: d038 beq.n 80413fc + 804137a: 687b ldr r3, [r7, #4] + 804137c: 681b ldr r3, [r3, #0] + 804137e: f003 0308 and.w r3, r3, #8 + 8041382: 2b00 cmp r3, #0 + 8041384: d038 beq.n 80413f8 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) - 804138a: 687b ldr r3, [r7, #4] - 804138c: 695b ldr r3, [r3, #20] - 804138e: 2b00 cmp r3, #0 - 8041390: d019 beq.n 80413c6 + 8041386: 687b ldr r3, [r7, #4] + 8041388: 695b ldr r3, [r3, #20] + 804138a: 2b00 cmp r3, #0 + 804138c: d019 beq.n 80413c2 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); - 8041392: 4b16 ldr r3, [pc, #88] ; (80413ec ) - 8041394: 6f5b ldr r3, [r3, #116] ; 0x74 - 8041396: 4a15 ldr r2, [pc, #84] ; (80413ec ) - 8041398: f043 0301 orr.w r3, r3, #1 - 804139c: 6753 str r3, [r2, #116] ; 0x74 + 804138e: 4b16 ldr r3, [pc, #88] ; (80413e8 ) + 8041390: 6f5b ldr r3, [r3, #116] ; 0x74 + 8041392: 4a15 ldr r2, [pc, #84] ; (80413e8 ) + 8041394: f043 0301 orr.w r3, r3, #1 + 8041398: 6753 str r3, [r2, #116] ; 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); - 804139e: f7ff fc09 bl 8040bb4 - 80413a2: 6138 str r0, [r7, #16] + 804139a: f7ff fc09 bl 8040bb0 + 804139e: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - 80413a4: e008 b.n 80413b8 + 80413a0: e008 b.n 80413b4 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - 80413a6: f7ff fc05 bl 8040bb4 - 80413aa: 4602 mov r2, r0 - 80413ac: 693b ldr r3, [r7, #16] - 80413ae: 1ad3 subs r3, r2, r3 - 80413b0: 2b02 cmp r3, #2 - 80413b2: d901 bls.n 80413b8 + 80413a2: f7ff fc05 bl 8040bb0 + 80413a6: 4602 mov r2, r0 + 80413a8: 693b ldr r3, [r7, #16] + 80413aa: 1ad3 subs r3, r2, r3 + 80413ac: 2b02 cmp r3, #2 + 80413ae: d901 bls.n 80413b4 { return HAL_TIMEOUT; - 80413b4: 2303 movs r3, #3 - 80413b6: e180 b.n 80416ba + 80413b0: 2303 movs r3, #3 + 80413b2: e180 b.n 80416b6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - 80413b8: 4b0c ldr r3, [pc, #48] ; (80413ec ) - 80413ba: 6f5b ldr r3, [r3, #116] ; 0x74 - 80413bc: f003 0302 and.w r3, r3, #2 - 80413c0: 2b00 cmp r3, #0 - 80413c2: d0f0 beq.n 80413a6 - 80413c4: e01a b.n 80413fc + 80413b4: 4b0c ldr r3, [pc, #48] ; (80413e8 ) + 80413b6: 6f5b ldr r3, [r3, #116] ; 0x74 + 80413b8: f003 0302 and.w r3, r3, #2 + 80413bc: 2b00 cmp r3, #0 + 80413be: d0f0 beq.n 80413a2 + 80413c0: e01a b.n 80413f8 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); - 80413c6: 4b09 ldr r3, [pc, #36] ; (80413ec ) - 80413c8: 6f5b ldr r3, [r3, #116] ; 0x74 - 80413ca: 4a08 ldr r2, [pc, #32] ; (80413ec ) - 80413cc: f023 0301 bic.w r3, r3, #1 - 80413d0: 6753 str r3, [r2, #116] ; 0x74 + 80413c2: 4b09 ldr r3, [pc, #36] ; (80413e8 ) + 80413c4: 6f5b ldr r3, [r3, #116] ; 0x74 + 80413c6: 4a08 ldr r2, [pc, #32] ; (80413e8 ) + 80413c8: f023 0301 bic.w r3, r3, #1 + 80413cc: 6753 str r3, [r2, #116] ; 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); - 80413d2: f7ff fbef bl 8040bb4 - 80413d6: 6138 str r0, [r7, #16] + 80413ce: f7ff fbef bl 8040bb0 + 80413d2: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - 80413d8: e00a b.n 80413f0 + 80413d4: e00a b.n 80413ec { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - 80413da: f7ff fbeb bl 8040bb4 - 80413de: 4602 mov r2, r0 - 80413e0: 693b ldr r3, [r7, #16] - 80413e2: 1ad3 subs r3, r2, r3 - 80413e4: 2b02 cmp r3, #2 - 80413e6: d903 bls.n 80413f0 + 80413d6: f7ff fbeb bl 8040bb0 + 80413da: 4602 mov r2, r0 + 80413dc: 693b ldr r3, [r7, #16] + 80413de: 1ad3 subs r3, r2, r3 + 80413e0: 2b02 cmp r3, #2 + 80413e2: d903 bls.n 80413ec { return HAL_TIMEOUT; - 80413e8: 2303 movs r3, #3 - 80413ea: e166 b.n 80416ba - 80413ec: 40023800 .word 0x40023800 + 80413e4: 2303 movs r3, #3 + 80413e6: e166 b.n 80416b6 + 80413e8: 40023800 .word 0x40023800 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - 80413f0: 4b92 ldr r3, [pc, #584] ; (804163c ) - 80413f2: 6f5b ldr r3, [r3, #116] ; 0x74 - 80413f4: f003 0302 and.w r3, r3, #2 - 80413f8: 2b00 cmp r3, #0 - 80413fa: d1ee bne.n 80413da + 80413ec: 4b92 ldr r3, [pc, #584] ; (8041638 ) + 80413ee: 6f5b ldr r3, [r3, #116] ; 0x74 + 80413f0: f003 0302 and.w r3, r3, #2 + 80413f4: 2b00 cmp r3, #0 + 80413f6: d1ee bne.n 80413d6 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - 80413fc: 687b ldr r3, [r7, #4] - 80413fe: 681b ldr r3, [r3, #0] - 8041400: f003 0304 and.w r3, r3, #4 - 8041404: 2b00 cmp r3, #0 - 8041406: f000 80a4 beq.w 8041552 + 80413f8: 687b ldr r3, [r7, #4] + 80413fa: 681b ldr r3, [r3, #0] + 80413fc: f003 0304 and.w r3, r3, #4 + 8041400: 2b00 cmp r3, #0 + 8041402: f000 80a4 beq.w 804154e /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) - 804140a: 4b8c ldr r3, [pc, #560] ; (804163c ) - 804140c: 6c1b ldr r3, [r3, #64] ; 0x40 - 804140e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8041412: 2b00 cmp r3, #0 - 8041414: d10d bne.n 8041432 + 8041406: 4b8c ldr r3, [pc, #560] ; (8041638 ) + 8041408: 6c1b ldr r3, [r3, #64] ; 0x40 + 804140a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 804140e: 2b00 cmp r3, #0 + 8041410: d10d bne.n 804142e { /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - 8041416: 4b89 ldr r3, [pc, #548] ; (804163c ) - 8041418: 6c1b ldr r3, [r3, #64] ; 0x40 - 804141a: 4a88 ldr r2, [pc, #544] ; (804163c ) - 804141c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 8041420: 6413 str r3, [r2, #64] ; 0x40 - 8041422: 4b86 ldr r3, [pc, #536] ; (804163c ) - 8041424: 6c1b ldr r3, [r3, #64] ; 0x40 - 8041426: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 804142a: 60bb str r3, [r7, #8] - 804142c: 68bb ldr r3, [r7, #8] + 8041412: 4b89 ldr r3, [pc, #548] ; (8041638 ) + 8041414: 6c1b ldr r3, [r3, #64] ; 0x40 + 8041416: 4a88 ldr r2, [pc, #544] ; (8041638 ) + 8041418: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 804141c: 6413 str r3, [r2, #64] ; 0x40 + 804141e: 4b86 ldr r3, [pc, #536] ; (8041638 ) + 8041420: 6c1b ldr r3, [r3, #64] ; 0x40 + 8041422: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8041426: 60bb str r3, [r7, #8] + 8041428: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; - 804142e: 2301 movs r3, #1 - 8041430: 75fb strb r3, [r7, #23] + 804142a: 2301 movs r3, #1 + 804142c: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - 8041432: 4b83 ldr r3, [pc, #524] ; (8041640 ) - 8041434: 681b ldr r3, [r3, #0] - 8041436: f403 7380 and.w r3, r3, #256 ; 0x100 - 804143a: 2b00 cmp r3, #0 - 804143c: d118 bne.n 8041470 + 804142e: 4b83 ldr r3, [pc, #524] ; (804163c ) + 8041430: 681b ldr r3, [r3, #0] + 8041432: f403 7380 and.w r3, r3, #256 ; 0x100 + 8041436: 2b00 cmp r3, #0 + 8041438: d118 bne.n 804146c { /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; - 804143e: 4b80 ldr r3, [pc, #512] ; (8041640 ) - 8041440: 681b ldr r3, [r3, #0] - 8041442: 4a7f ldr r2, [pc, #508] ; (8041640 ) - 8041444: f443 7380 orr.w r3, r3, #256 ; 0x100 - 8041448: 6013 str r3, [r2, #0] + 804143a: 4b80 ldr r3, [pc, #512] ; (804163c ) + 804143c: 681b ldr r3, [r3, #0] + 804143e: 4a7f ldr r2, [pc, #508] ; (804163c ) + 8041440: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8041444: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - 804144a: f7ff fbb3 bl 8040bb4 - 804144e: 6138 str r0, [r7, #16] + 8041446: f7ff fbb3 bl 8040bb0 + 804144a: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - 8041450: e008 b.n 8041464 + 804144c: e008 b.n 8041460 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - 8041452: f7ff fbaf bl 8040bb4 - 8041456: 4602 mov r2, r0 - 8041458: 693b ldr r3, [r7, #16] - 804145a: 1ad3 subs r3, r2, r3 - 804145c: 2b64 cmp r3, #100 ; 0x64 - 804145e: d901 bls.n 8041464 + 804144e: f7ff fbaf bl 8040bb0 + 8041452: 4602 mov r2, r0 + 8041454: 693b ldr r3, [r7, #16] + 8041456: 1ad3 subs r3, r2, r3 + 8041458: 2b64 cmp r3, #100 ; 0x64 + 804145a: d901 bls.n 8041460 { return HAL_TIMEOUT; - 8041460: 2303 movs r3, #3 - 8041462: e12a b.n 80416ba + 804145c: 2303 movs r3, #3 + 804145e: e12a b.n 80416b6 while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - 8041464: 4b76 ldr r3, [pc, #472] ; (8041640 ) - 8041466: 681b ldr r3, [r3, #0] - 8041468: f403 7380 and.w r3, r3, #256 ; 0x100 - 804146c: 2b00 cmp r3, #0 - 804146e: d0f0 beq.n 8041452 + 8041460: 4b76 ldr r3, [pc, #472] ; (804163c ) + 8041462: 681b ldr r3, [r3, #0] + 8041464: f403 7380 and.w r3, r3, #256 ; 0x100 + 8041468: 2b00 cmp r3, #0 + 804146a: d0f0 beq.n 804144e } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - 8041470: 687b ldr r3, [r7, #4] - 8041472: 689b ldr r3, [r3, #8] - 8041474: 2b01 cmp r3, #1 - 8041476: d106 bne.n 8041486 - 8041478: 4b70 ldr r3, [pc, #448] ; (804163c ) - 804147a: 6f1b ldr r3, [r3, #112] ; 0x70 - 804147c: 4a6f ldr r2, [pc, #444] ; (804163c ) - 804147e: f043 0301 orr.w r3, r3, #1 - 8041482: 6713 str r3, [r2, #112] ; 0x70 - 8041484: e02d b.n 80414e2 - 8041486: 687b ldr r3, [r7, #4] - 8041488: 689b ldr r3, [r3, #8] - 804148a: 2b00 cmp r3, #0 - 804148c: d10c bne.n 80414a8 - 804148e: 4b6b ldr r3, [pc, #428] ; (804163c ) - 8041490: 6f1b ldr r3, [r3, #112] ; 0x70 - 8041492: 4a6a ldr r2, [pc, #424] ; (804163c ) - 8041494: f023 0301 bic.w r3, r3, #1 - 8041498: 6713 str r3, [r2, #112] ; 0x70 - 804149a: 4b68 ldr r3, [pc, #416] ; (804163c ) - 804149c: 6f1b ldr r3, [r3, #112] ; 0x70 - 804149e: 4a67 ldr r2, [pc, #412] ; (804163c ) - 80414a0: f023 0304 bic.w r3, r3, #4 - 80414a4: 6713 str r3, [r2, #112] ; 0x70 - 80414a6: e01c b.n 80414e2 - 80414a8: 687b ldr r3, [r7, #4] - 80414aa: 689b ldr r3, [r3, #8] - 80414ac: 2b05 cmp r3, #5 - 80414ae: d10c bne.n 80414ca - 80414b0: 4b62 ldr r3, [pc, #392] ; (804163c ) - 80414b2: 6f1b ldr r3, [r3, #112] ; 0x70 - 80414b4: 4a61 ldr r2, [pc, #388] ; (804163c ) - 80414b6: f043 0304 orr.w r3, r3, #4 - 80414ba: 6713 str r3, [r2, #112] ; 0x70 - 80414bc: 4b5f ldr r3, [pc, #380] ; (804163c ) - 80414be: 6f1b ldr r3, [r3, #112] ; 0x70 - 80414c0: 4a5e ldr r2, [pc, #376] ; (804163c ) - 80414c2: f043 0301 orr.w r3, r3, #1 - 80414c6: 6713 str r3, [r2, #112] ; 0x70 - 80414c8: e00b b.n 80414e2 - 80414ca: 4b5c ldr r3, [pc, #368] ; (804163c ) - 80414cc: 6f1b ldr r3, [r3, #112] ; 0x70 - 80414ce: 4a5b ldr r2, [pc, #364] ; (804163c ) - 80414d0: f023 0301 bic.w r3, r3, #1 - 80414d4: 6713 str r3, [r2, #112] ; 0x70 - 80414d6: 4b59 ldr r3, [pc, #356] ; (804163c ) - 80414d8: 6f1b ldr r3, [r3, #112] ; 0x70 - 80414da: 4a58 ldr r2, [pc, #352] ; (804163c ) - 80414dc: f023 0304 bic.w r3, r3, #4 - 80414e0: 6713 str r3, [r2, #112] ; 0x70 + 804146c: 687b ldr r3, [r7, #4] + 804146e: 689b ldr r3, [r3, #8] + 8041470: 2b01 cmp r3, #1 + 8041472: d106 bne.n 8041482 + 8041474: 4b70 ldr r3, [pc, #448] ; (8041638 ) + 8041476: 6f1b ldr r3, [r3, #112] ; 0x70 + 8041478: 4a6f ldr r2, [pc, #444] ; (8041638 ) + 804147a: f043 0301 orr.w r3, r3, #1 + 804147e: 6713 str r3, [r2, #112] ; 0x70 + 8041480: e02d b.n 80414de + 8041482: 687b ldr r3, [r7, #4] + 8041484: 689b ldr r3, [r3, #8] + 8041486: 2b00 cmp r3, #0 + 8041488: d10c bne.n 80414a4 + 804148a: 4b6b ldr r3, [pc, #428] ; (8041638 ) + 804148c: 6f1b ldr r3, [r3, #112] ; 0x70 + 804148e: 4a6a ldr r2, [pc, #424] ; (8041638 ) + 8041490: f023 0301 bic.w r3, r3, #1 + 8041494: 6713 str r3, [r2, #112] ; 0x70 + 8041496: 4b68 ldr r3, [pc, #416] ; (8041638 ) + 8041498: 6f1b ldr r3, [r3, #112] ; 0x70 + 804149a: 4a67 ldr r2, [pc, #412] ; (8041638 ) + 804149c: f023 0304 bic.w r3, r3, #4 + 80414a0: 6713 str r3, [r2, #112] ; 0x70 + 80414a2: e01c b.n 80414de + 80414a4: 687b ldr r3, [r7, #4] + 80414a6: 689b ldr r3, [r3, #8] + 80414a8: 2b05 cmp r3, #5 + 80414aa: d10c bne.n 80414c6 + 80414ac: 4b62 ldr r3, [pc, #392] ; (8041638 ) + 80414ae: 6f1b ldr r3, [r3, #112] ; 0x70 + 80414b0: 4a61 ldr r2, [pc, #388] ; (8041638 ) + 80414b2: f043 0304 orr.w r3, r3, #4 + 80414b6: 6713 str r3, [r2, #112] ; 0x70 + 80414b8: 4b5f ldr r3, [pc, #380] ; (8041638 ) + 80414ba: 6f1b ldr r3, [r3, #112] ; 0x70 + 80414bc: 4a5e ldr r2, [pc, #376] ; (8041638 ) + 80414be: f043 0301 orr.w r3, r3, #1 + 80414c2: 6713 str r3, [r2, #112] ; 0x70 + 80414c4: e00b b.n 80414de + 80414c6: 4b5c ldr r3, [pc, #368] ; (8041638 ) + 80414c8: 6f1b ldr r3, [r3, #112] ; 0x70 + 80414ca: 4a5b ldr r2, [pc, #364] ; (8041638 ) + 80414cc: f023 0301 bic.w r3, r3, #1 + 80414d0: 6713 str r3, [r2, #112] ; 0x70 + 80414d2: 4b59 ldr r3, [pc, #356] ; (8041638 ) + 80414d4: 6f1b ldr r3, [r3, #112] ; 0x70 + 80414d6: 4a58 ldr r2, [pc, #352] ; (8041638 ) + 80414d8: f023 0304 bic.w r3, r3, #4 + 80414dc: 6713 str r3, [r2, #112] ; 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) - 80414e2: 687b ldr r3, [r7, #4] - 80414e4: 689b ldr r3, [r3, #8] - 80414e6: 2b00 cmp r3, #0 - 80414e8: d015 beq.n 8041516 + 80414de: 687b ldr r3, [r7, #4] + 80414e0: 689b ldr r3, [r3, #8] + 80414e2: 2b00 cmp r3, #0 + 80414e4: d015 beq.n 8041512 { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 80414ea: f7ff fb63 bl 8040bb4 - 80414ee: 6138 str r0, [r7, #16] + 80414e6: f7ff fb63 bl 8040bb0 + 80414ea: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 80414f0: e00a b.n 8041508 + 80414ec: e00a b.n 8041504 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 80414f2: f7ff fb5f bl 8040bb4 - 80414f6: 4602 mov r2, r0 - 80414f8: 693b ldr r3, [r7, #16] - 80414fa: 1ad3 subs r3, r2, r3 - 80414fc: f241 3288 movw r2, #5000 ; 0x1388 - 8041500: 4293 cmp r3, r2 - 8041502: d901 bls.n 8041508 + 80414ee: f7ff fb5f bl 8040bb0 + 80414f2: 4602 mov r2, r0 + 80414f4: 693b ldr r3, [r7, #16] + 80414f6: 1ad3 subs r3, r2, r3 + 80414f8: f241 3288 movw r2, #5000 ; 0x1388 + 80414fc: 4293 cmp r3, r2 + 80414fe: d901 bls.n 8041504 { return HAL_TIMEOUT; - 8041504: 2303 movs r3, #3 - 8041506: e0d8 b.n 80416ba + 8041500: 2303 movs r3, #3 + 8041502: e0d8 b.n 80416b6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 8041508: 4b4c ldr r3, [pc, #304] ; (804163c ) - 804150a: 6f1b ldr r3, [r3, #112] ; 0x70 - 804150c: f003 0302 and.w r3, r3, #2 - 8041510: 2b00 cmp r3, #0 - 8041512: d0ee beq.n 80414f2 - 8041514: e014 b.n 8041540 + 8041504: 4b4c ldr r3, [pc, #304] ; (8041638 ) + 8041506: 6f1b ldr r3, [r3, #112] ; 0x70 + 8041508: f003 0302 and.w r3, r3, #2 + 804150c: 2b00 cmp r3, #0 + 804150e: d0ee beq.n 80414ee + 8041510: e014 b.n 804153c } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8041516: f7ff fb4d bl 8040bb4 - 804151a: 6138 str r0, [r7, #16] + 8041512: f7ff fb4d bl 8040bb0 + 8041516: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - 804151c: e00a b.n 8041534 + 8041518: e00a b.n 8041530 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 804151e: f7ff fb49 bl 8040bb4 - 8041522: 4602 mov r2, r0 - 8041524: 693b ldr r3, [r7, #16] - 8041526: 1ad3 subs r3, r2, r3 - 8041528: f241 3288 movw r2, #5000 ; 0x1388 - 804152c: 4293 cmp r3, r2 - 804152e: d901 bls.n 8041534 + 804151a: f7ff fb49 bl 8040bb0 + 804151e: 4602 mov r2, r0 + 8041520: 693b ldr r3, [r7, #16] + 8041522: 1ad3 subs r3, r2, r3 + 8041524: f241 3288 movw r2, #5000 ; 0x1388 + 8041528: 4293 cmp r3, r2 + 804152a: d901 bls.n 8041530 { return HAL_TIMEOUT; - 8041530: 2303 movs r3, #3 - 8041532: e0c2 b.n 80416ba + 804152c: 2303 movs r3, #3 + 804152e: e0c2 b.n 80416b6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - 8041534: 4b41 ldr r3, [pc, #260] ; (804163c ) - 8041536: 6f1b ldr r3, [r3, #112] ; 0x70 - 8041538: f003 0302 and.w r3, r3, #2 - 804153c: 2b00 cmp r3, #0 - 804153e: d1ee bne.n 804151e + 8041530: 4b41 ldr r3, [pc, #260] ; (8041638 ) + 8041532: 6f1b ldr r3, [r3, #112] ; 0x70 + 8041534: f003 0302 and.w r3, r3, #2 + 8041538: 2b00 cmp r3, #0 + 804153a: d1ee bne.n 804151a } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) - 8041540: 7dfb ldrb r3, [r7, #23] - 8041542: 2b01 cmp r3, #1 - 8041544: d105 bne.n 8041552 + 804153c: 7dfb ldrb r3, [r7, #23] + 804153e: 2b01 cmp r3, #1 + 8041540: d105 bne.n 804154e { __HAL_RCC_PWR_CLK_DISABLE(); - 8041546: 4b3d ldr r3, [pc, #244] ; (804163c ) - 8041548: 6c1b ldr r3, [r3, #64] ; 0x40 - 804154a: 4a3c ldr r2, [pc, #240] ; (804163c ) - 804154c: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 - 8041550: 6413 str r3, [r2, #64] ; 0x40 + 8041542: 4b3d ldr r3, [pc, #244] ; (8041638 ) + 8041544: 6c1b ldr r3, [r3, #64] ; 0x40 + 8041546: 4a3c ldr r2, [pc, #240] ; (8041638 ) + 8041548: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 804154c: 6413 str r3, [r2, #64] ; 0x40 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) - 8041552: 687b ldr r3, [r7, #4] - 8041554: 699b ldr r3, [r3, #24] - 8041556: 2b00 cmp r3, #0 - 8041558: f000 80ae beq.w 80416b8 + 804154e: 687b ldr r3, [r7, #4] + 8041550: 699b ldr r3, [r3, #24] + 8041552: 2b00 cmp r3, #0 + 8041554: f000 80ae beq.w 80416b4 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - 804155c: 4b37 ldr r3, [pc, #220] ; (804163c ) - 804155e: 689b ldr r3, [r3, #8] - 8041560: f003 030c and.w r3, r3, #12 - 8041564: 2b08 cmp r3, #8 - 8041566: d06d beq.n 8041644 + 8041558: 4b37 ldr r3, [pc, #220] ; (8041638 ) + 804155a: 689b ldr r3, [r3, #8] + 804155c: f003 030c and.w r3, r3, #12 + 8041560: 2b08 cmp r3, #8 + 8041562: d06d beq.n 8041640 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) - 8041568: 687b ldr r3, [r7, #4] - 804156a: 699b ldr r3, [r3, #24] - 804156c: 2b02 cmp r3, #2 - 804156e: d14b bne.n 8041608 + 8041564: 687b ldr r3, [r7, #4] + 8041566: 699b ldr r3, [r3, #24] + 8041568: 2b02 cmp r3, #2 + 804156a: d14b bne.n 8041604 #if defined (RCC_PLLCFGR_PLLR) assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); #endif /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - 8041570: 4b32 ldr r3, [pc, #200] ; (804163c ) - 8041572: 681b ldr r3, [r3, #0] - 8041574: 4a31 ldr r2, [pc, #196] ; (804163c ) - 8041576: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 - 804157a: 6013 str r3, [r2, #0] + 804156c: 4b32 ldr r3, [pc, #200] ; (8041638 ) + 804156e: 681b ldr r3, [r3, #0] + 8041570: 4a31 ldr r2, [pc, #196] ; (8041638 ) + 8041572: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 8041576: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 804157c: f7ff fb1a bl 8040bb4 - 8041580: 6138 str r0, [r7, #16] + 8041578: f7ff fb1a bl 8040bb0 + 804157c: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 8041582: e008 b.n 8041596 + 804157e: e008 b.n 8041592 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - 8041584: f7ff fb16 bl 8040bb4 - 8041588: 4602 mov r2, r0 - 804158a: 693b ldr r3, [r7, #16] - 804158c: 1ad3 subs r3, r2, r3 - 804158e: 2b02 cmp r3, #2 - 8041590: d901 bls.n 8041596 + 8041580: f7ff fb16 bl 8040bb0 + 8041584: 4602 mov r2, r0 + 8041586: 693b ldr r3, [r7, #16] + 8041588: 1ad3 subs r3, r2, r3 + 804158a: 2b02 cmp r3, #2 + 804158c: d901 bls.n 8041592 { return HAL_TIMEOUT; - 8041592: 2303 movs r3, #3 - 8041594: e091 b.n 80416ba + 804158e: 2303 movs r3, #3 + 8041590: e091 b.n 80416b6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 8041596: 4b29 ldr r3, [pc, #164] ; (804163c ) - 8041598: 681b ldr r3, [r3, #0] - 804159a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 804159e: 2b00 cmp r3, #0 - 80415a0: d1f0 bne.n 8041584 + 8041592: 4b29 ldr r3, [pc, #164] ; (8041638 ) + 8041594: 681b ldr r3, [r3, #0] + 8041596: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 804159a: 2b00 cmp r3, #0 + 804159c: d1f0 bne.n 8041580 } } /* Configure the main PLL clock source, multiplication and division factors. */ #if defined (RCC_PLLCFGR_PLLR) __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 804159e: 687b ldr r3, [r7, #4] + 80415a0: 69da ldr r2, [r3, #28] 80415a2: 687b ldr r3, [r7, #4] - 80415a4: 69da ldr r2, [r3, #28] - 80415a6: 687b ldr r3, [r7, #4] - 80415a8: 6a1b ldr r3, [r3, #32] - 80415aa: 431a orrs r2, r3 - 80415ac: 687b ldr r3, [r7, #4] - 80415ae: 6a5b ldr r3, [r3, #36] ; 0x24 - 80415b0: 019b lsls r3, r3, #6 - 80415b2: 431a orrs r2, r3 - 80415b4: 687b ldr r3, [r7, #4] - 80415b6: 6a9b ldr r3, [r3, #40] ; 0x28 - 80415b8: 085b lsrs r3, r3, #1 - 80415ba: 3b01 subs r3, #1 - 80415bc: 041b lsls r3, r3, #16 - 80415be: 431a orrs r2, r3 - 80415c0: 687b ldr r3, [r7, #4] - 80415c2: 6adb ldr r3, [r3, #44] ; 0x2c - 80415c4: 061b lsls r3, r3, #24 - 80415c6: 431a orrs r2, r3 - 80415c8: 687b ldr r3, [r7, #4] - 80415ca: 6b1b ldr r3, [r3, #48] ; 0x30 - 80415cc: 071b lsls r3, r3, #28 - 80415ce: 491b ldr r1, [pc, #108] ; (804163c ) - 80415d0: 4313 orrs r3, r2 - 80415d2: 604b str r3, [r1, #4] + 80415a4: 6a1b ldr r3, [r3, #32] + 80415a6: 431a orrs r2, r3 + 80415a8: 687b ldr r3, [r7, #4] + 80415aa: 6a5b ldr r3, [r3, #36] ; 0x24 + 80415ac: 019b lsls r3, r3, #6 + 80415ae: 431a orrs r2, r3 + 80415b0: 687b ldr r3, [r7, #4] + 80415b2: 6a9b ldr r3, [r3, #40] ; 0x28 + 80415b4: 085b lsrs r3, r3, #1 + 80415b6: 3b01 subs r3, #1 + 80415b8: 041b lsls r3, r3, #16 + 80415ba: 431a orrs r2, r3 + 80415bc: 687b ldr r3, [r7, #4] + 80415be: 6adb ldr r3, [r3, #44] ; 0x2c + 80415c0: 061b lsls r3, r3, #24 + 80415c2: 431a orrs r2, r3 + 80415c4: 687b ldr r3, [r7, #4] + 80415c6: 6b1b ldr r3, [r3, #48] ; 0x30 + 80415c8: 071b lsls r3, r3, #28 + 80415ca: 491b ldr r1, [pc, #108] ; (8041638 ) + 80415cc: 4313 orrs r3, r2 + 80415ce: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ); #endif /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); - 80415d4: 4b19 ldr r3, [pc, #100] ; (804163c ) - 80415d6: 681b ldr r3, [r3, #0] - 80415d8: 4a18 ldr r2, [pc, #96] ; (804163c ) - 80415da: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 - 80415de: 6013 str r3, [r2, #0] + 80415d0: 4b19 ldr r3, [pc, #100] ; (8041638 ) + 80415d2: 681b ldr r3, [r3, #0] + 80415d4: 4a18 ldr r2, [pc, #96] ; (8041638 ) + 80415d6: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 + 80415da: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 80415e0: f7ff fae8 bl 8040bb4 - 80415e4: 6138 str r0, [r7, #16] + 80415dc: f7ff fae8 bl 8040bb0 + 80415e0: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 80415e6: e008 b.n 80415fa + 80415e2: e008 b.n 80415f6 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - 80415e8: f7ff fae4 bl 8040bb4 - 80415ec: 4602 mov r2, r0 - 80415ee: 693b ldr r3, [r7, #16] - 80415f0: 1ad3 subs r3, r2, r3 - 80415f2: 2b02 cmp r3, #2 - 80415f4: d901 bls.n 80415fa + 80415e4: f7ff fae4 bl 8040bb0 + 80415e8: 4602 mov r2, r0 + 80415ea: 693b ldr r3, [r7, #16] + 80415ec: 1ad3 subs r3, r2, r3 + 80415ee: 2b02 cmp r3, #2 + 80415f0: d901 bls.n 80415f6 { return HAL_TIMEOUT; - 80415f6: 2303 movs r3, #3 - 80415f8: e05f b.n 80416ba + 80415f2: 2303 movs r3, #3 + 80415f4: e05f b.n 80416b6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 80415fa: 4b10 ldr r3, [pc, #64] ; (804163c ) - 80415fc: 681b ldr r3, [r3, #0] - 80415fe: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 8041602: 2b00 cmp r3, #0 - 8041604: d0f0 beq.n 80415e8 - 8041606: e057 b.n 80416b8 + 80415f6: 4b10 ldr r3, [pc, #64] ; (8041638 ) + 80415f8: 681b ldr r3, [r3, #0] + 80415fa: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 80415fe: 2b00 cmp r3, #0 + 8041600: d0f0 beq.n 80415e4 + 8041602: e057 b.n 80416b4 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - 8041608: 4b0c ldr r3, [pc, #48] ; (804163c ) - 804160a: 681b ldr r3, [r3, #0] - 804160c: 4a0b ldr r2, [pc, #44] ; (804163c ) - 804160e: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 - 8041612: 6013 str r3, [r2, #0] + 8041604: 4b0c ldr r3, [pc, #48] ; (8041638 ) + 8041606: 681b ldr r3, [r3, #0] + 8041608: 4a0b ldr r2, [pc, #44] ; (8041638 ) + 804160a: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 804160e: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8041614: f7ff face bl 8040bb4 - 8041618: 6138 str r0, [r7, #16] + 8041610: f7ff face bl 8040bb0 + 8041614: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 804161a: e008 b.n 804162e + 8041616: e008 b.n 804162a { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - 804161c: f7ff faca bl 8040bb4 - 8041620: 4602 mov r2, r0 - 8041622: 693b ldr r3, [r7, #16] - 8041624: 1ad3 subs r3, r2, r3 - 8041626: 2b02 cmp r3, #2 - 8041628: d901 bls.n 804162e + 8041618: f7ff faca bl 8040bb0 + 804161c: 4602 mov r2, r0 + 804161e: 693b ldr r3, [r7, #16] + 8041620: 1ad3 subs r3, r2, r3 + 8041622: 2b02 cmp r3, #2 + 8041624: d901 bls.n 804162a { return HAL_TIMEOUT; - 804162a: 2303 movs r3, #3 - 804162c: e045 b.n 80416ba + 8041626: 2303 movs r3, #3 + 8041628: e045 b.n 80416b6 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 804162e: 4b03 ldr r3, [pc, #12] ; (804163c ) - 8041630: 681b ldr r3, [r3, #0] - 8041632: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 8041636: 2b00 cmp r3, #0 - 8041638: d1f0 bne.n 804161c - 804163a: e03d b.n 80416b8 - 804163c: 40023800 .word 0x40023800 - 8041640: 40007000 .word 0x40007000 + 804162a: 4b03 ldr r3, [pc, #12] ; (8041638 ) + 804162c: 681b ldr r3, [r3, #0] + 804162e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8041632: 2b00 cmp r3, #0 + 8041634: d1f0 bne.n 8041618 + 8041636: e03d b.n 80416b4 + 8041638: 40023800 .word 0x40023800 + 804163c: 40007000 .word 0x40007000 } } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->PLLCFGR; - 8041644: 4b1f ldr r3, [pc, #124] ; (80416c4 ) - 8041646: 685b ldr r3, [r3, #4] - 8041648: 60fb str r3, [r7, #12] + 8041640: 4b1f ldr r3, [pc, #124] ; (80416c0 ) + 8041642: 685b ldr r3, [r3, #4] + 8041644: 60fb str r3, [r7, #12] #if defined (RCC_PLLCFGR_PLLR) if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || - 804164a: 687b ldr r3, [r7, #4] - 804164c: 699b ldr r3, [r3, #24] - 804164e: 2b01 cmp r3, #1 - 8041650: d030 beq.n 80416b4 + 8041646: 687b ldr r3, [r7, #4] + 8041648: 699b ldr r3, [r3, #24] + 804164a: 2b01 cmp r3, #1 + 804164c: d030 beq.n 80416b0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 8041652: 68fb ldr r3, [r7, #12] - 8041654: f403 0280 and.w r2, r3, #4194304 ; 0x400000 - 8041658: 687b ldr r3, [r7, #4] - 804165a: 69db ldr r3, [r3, #28] + 804164e: 68fb ldr r3, [r7, #12] + 8041650: f403 0280 and.w r2, r3, #4194304 ; 0x400000 + 8041654: 687b ldr r3, [r7, #4] + 8041656: 69db ldr r3, [r3, #28] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || - 804165c: 429a cmp r2, r3 - 804165e: d129 bne.n 80416b4 + 8041658: 429a cmp r2, r3 + 804165a: d129 bne.n 80416b0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || - 8041660: 68fb ldr r3, [r7, #12] - 8041662: f003 023f and.w r2, r3, #63 ; 0x3f - 8041666: 687b ldr r3, [r7, #4] - 8041668: 6a1b ldr r3, [r3, #32] + 804165c: 68fb ldr r3, [r7, #12] + 804165e: f003 023f and.w r2, r3, #63 ; 0x3f + 8041662: 687b ldr r3, [r7, #4] + 8041664: 6a1b ldr r3, [r3, #32] (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 804166a: 429a cmp r2, r3 - 804166c: d122 bne.n 80416b4 + 8041666: 429a cmp r2, r3 + 8041668: d122 bne.n 80416b0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || - 804166e: 68fa ldr r2, [r7, #12] - 8041670: f647 73c0 movw r3, #32704 ; 0x7fc0 - 8041674: 4013 ands r3, r2 - 8041676: 687a ldr r2, [r7, #4] - 8041678: 6a52 ldr r2, [r2, #36] ; 0x24 - 804167a: 0192 lsls r2, r2, #6 + 804166a: 68fa ldr r2, [r7, #12] + 804166c: f647 73c0 movw r3, #32704 ; 0x7fc0 + 8041670: 4013 ands r3, r2 + 8041672: 687a ldr r2, [r7, #4] + 8041674: 6a52 ldr r2, [r2, #36] ; 0x24 + 8041676: 0192 lsls r2, r2, #6 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || - 804167c: 4293 cmp r3, r2 - 804167e: d119 bne.n 80416b4 + 8041678: 4293 cmp r3, r2 + 804167a: d119 bne.n 80416b0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || - 8041680: 68fb ldr r3, [r7, #12] - 8041682: f403 3240 and.w r2, r3, #196608 ; 0x30000 - 8041686: 687b ldr r3, [r7, #4] - 8041688: 6a9b ldr r3, [r3, #40] ; 0x28 - 804168a: 085b lsrs r3, r3, #1 - 804168c: 3b01 subs r3, #1 - 804168e: 041b lsls r3, r3, #16 + 804167c: 68fb ldr r3, [r7, #12] + 804167e: f403 3240 and.w r2, r3, #196608 ; 0x30000 + 8041682: 687b ldr r3, [r7, #4] + 8041684: 6a9b ldr r3, [r3, #40] ; 0x28 + 8041686: 085b lsrs r3, r3, #1 + 8041688: 3b01 subs r3, #1 + 804168a: 041b lsls r3, r3, #16 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || - 8041690: 429a cmp r2, r3 - 8041692: d10f bne.n 80416b4 + 804168c: 429a cmp r2, r3 + 804168e: d10f bne.n 80416b0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || - 8041694: 68fb ldr r3, [r7, #12] - 8041696: f003 6270 and.w r2, r3, #251658240 ; 0xf000000 - 804169a: 687b ldr r3, [r7, #4] - 804169c: 6adb ldr r3, [r3, #44] ; 0x2c - 804169e: 061b lsls r3, r3, #24 + 8041690: 68fb ldr r3, [r7, #12] + 8041692: f003 6270 and.w r2, r3, #251658240 ; 0xf000000 + 8041696: 687b ldr r3, [r7, #4] + 8041698: 6adb ldr r3, [r3, #44] ; 0x2c + 804169a: 061b lsls r3, r3, #24 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || - 80416a0: 429a cmp r2, r3 - 80416a2: d107 bne.n 80416b4 + 804169c: 429a cmp r2, r3 + 804169e: d107 bne.n 80416b0 (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) - 80416a4: 68fb ldr r3, [r7, #12] - 80416a6: f003 42e0 and.w r2, r3, #1879048192 ; 0x70000000 - 80416aa: 687b ldr r3, [r7, #4] - 80416ac: 6b1b ldr r3, [r3, #48] ; 0x30 - 80416ae: 071b lsls r3, r3, #28 + 80416a0: 68fb ldr r3, [r7, #12] + 80416a2: f003 42e0 and.w r2, r3, #1879048192 ; 0x70000000 + 80416a6: 687b ldr r3, [r7, #4] + 80416a8: 6b1b ldr r3, [r3, #48] ; 0x30 + 80416aa: 071b lsls r3, r3, #28 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || - 80416b0: 429a cmp r2, r3 - 80416b2: d001 beq.n 80416b8 + 80416ac: 429a cmp r2, r3 + 80416ae: d001 beq.n 80416b4 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) #endif { return HAL_ERROR; - 80416b4: 2301 movs r3, #1 - 80416b6: e000 b.n 80416ba + 80416b0: 2301 movs r3, #1 + 80416b2: e000 b.n 80416b6 } } } return HAL_OK; - 80416b8: 2300 movs r3, #0 + 80416b4: 2300 movs r3, #0 } - 80416ba: 4618 mov r0, r3 - 80416bc: 3718 adds r7, #24 - 80416be: 46bd mov sp, r7 - 80416c0: bd80 pop {r7, pc} - 80416c2: bf00 nop - 80416c4: 40023800 .word 0x40023800 - -080416c8 : + 80416b6: 4618 mov r0, r3 + 80416b8: 3718 adds r7, #24 + 80416ba: 46bd mov sp, r7 + 80416bc: bd80 pop {r7, pc} + 80416be: bf00 nop + 80416c0: 40023800 .word 0x40023800 + +080416c4 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { - 80416c8: b580 push {r7, lr} - 80416ca: b084 sub sp, #16 - 80416cc: af00 add r7, sp, #0 - 80416ce: 6078 str r0, [r7, #4] - 80416d0: 6039 str r1, [r7, #0] + 80416c4: b580 push {r7, lr} + 80416c6: b084 sub sp, #16 + 80416c8: af00 add r7, sp, #0 + 80416ca: 6078 str r0, [r7, #4] + 80416cc: 6039 str r1, [r7, #0] uint32_t tickstart = 0; - 80416d2: 2300 movs r3, #0 - 80416d4: 60fb str r3, [r7, #12] + 80416ce: 2300 movs r3, #0 + 80416d0: 60fb str r3, [r7, #12] /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) - 80416d6: 687b ldr r3, [r7, #4] - 80416d8: 2b00 cmp r3, #0 - 80416da: d101 bne.n 80416e0 + 80416d2: 687b ldr r3, [r7, #4] + 80416d4: 2b00 cmp r3, #0 + 80416d6: d101 bne.n 80416dc { return HAL_ERROR; - 80416dc: 2301 movs r3, #1 - 80416de: e0d0 b.n 8041882 + 80416d8: 2301 movs r3, #1 + 80416da: e0d0 b.n 804187e /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) - 80416e0: 4b6a ldr r3, [pc, #424] ; (804188c ) - 80416e2: 681b ldr r3, [r3, #0] - 80416e4: f003 030f and.w r3, r3, #15 - 80416e8: 683a ldr r2, [r7, #0] - 80416ea: 429a cmp r2, r3 - 80416ec: d910 bls.n 8041710 + 80416dc: 4b6a ldr r3, [pc, #424] ; (8041888 ) + 80416de: 681b ldr r3, [r3, #0] + 80416e0: f003 030f and.w r3, r3, #15 + 80416e4: 683a ldr r2, [r7, #0] + 80416e6: 429a cmp r2, r3 + 80416e8: d910 bls.n 804170c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 80416ee: 4b67 ldr r3, [pc, #412] ; (804188c ) - 80416f0: 681b ldr r3, [r3, #0] - 80416f2: f023 020f bic.w r2, r3, #15 - 80416f6: 4965 ldr r1, [pc, #404] ; (804188c ) - 80416f8: 683b ldr r3, [r7, #0] - 80416fa: 4313 orrs r3, r2 - 80416fc: 600b str r3, [r1, #0] + 80416ea: 4b67 ldr r3, [pc, #412] ; (8041888 ) + 80416ec: 681b ldr r3, [r3, #0] + 80416ee: f023 020f bic.w r2, r3, #15 + 80416f2: 4965 ldr r1, [pc, #404] ; (8041888 ) + 80416f4: 683b ldr r3, [r7, #0] + 80416f6: 4313 orrs r3, r2 + 80416f8: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) - 80416fe: 4b63 ldr r3, [pc, #396] ; (804188c ) - 8041700: 681b ldr r3, [r3, #0] - 8041702: f003 030f and.w r3, r3, #15 - 8041706: 683a ldr r2, [r7, #0] - 8041708: 429a cmp r2, r3 - 804170a: d001 beq.n 8041710 + 80416fa: 4b63 ldr r3, [pc, #396] ; (8041888 ) + 80416fc: 681b ldr r3, [r3, #0] + 80416fe: f003 030f and.w r3, r3, #15 + 8041702: 683a ldr r2, [r7, #0] + 8041704: 429a cmp r2, r3 + 8041706: d001 beq.n 804170c { return HAL_ERROR; - 804170c: 2301 movs r3, #1 - 804170e: e0b8 b.n 8041882 + 8041708: 2301 movs r3, #1 + 804170a: e0b8 b.n 804187e } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - 8041710: 687b ldr r3, [r7, #4] - 8041712: 681b ldr r3, [r3, #0] - 8041714: f003 0302 and.w r3, r3, #2 - 8041718: 2b00 cmp r3, #0 - 804171a: d020 beq.n 804175e + 804170c: 687b ldr r3, [r7, #4] + 804170e: 681b ldr r3, [r3, #0] + 8041710: f003 0302 and.w r3, r3, #2 + 8041714: 2b00 cmp r3, #0 + 8041716: d020 beq.n 804175a { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 804171c: 687b ldr r3, [r7, #4] - 804171e: 681b ldr r3, [r3, #0] - 8041720: f003 0304 and.w r3, r3, #4 - 8041724: 2b00 cmp r3, #0 - 8041726: d005 beq.n 8041734 + 8041718: 687b ldr r3, [r7, #4] + 804171a: 681b ldr r3, [r3, #0] + 804171c: f003 0304 and.w r3, r3, #4 + 8041720: 2b00 cmp r3, #0 + 8041722: d005 beq.n 8041730 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); - 8041728: 4b59 ldr r3, [pc, #356] ; (8041890 ) - 804172a: 689b ldr r3, [r3, #8] - 804172c: 4a58 ldr r2, [pc, #352] ; (8041890 ) - 804172e: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00 - 8041732: 6093 str r3, [r2, #8] + 8041724: 4b59 ldr r3, [pc, #356] ; (804188c ) + 8041726: 689b ldr r3, [r3, #8] + 8041728: 4a58 ldr r2, [pc, #352] ; (804188c ) + 804172a: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00 + 804172e: 6093 str r3, [r2, #8] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - 8041734: 687b ldr r3, [r7, #4] - 8041736: 681b ldr r3, [r3, #0] - 8041738: f003 0308 and.w r3, r3, #8 - 804173c: 2b00 cmp r3, #0 - 804173e: d005 beq.n 804174c + 8041730: 687b ldr r3, [r7, #4] + 8041732: 681b ldr r3, [r3, #0] + 8041734: f003 0308 and.w r3, r3, #8 + 8041738: 2b00 cmp r3, #0 + 804173a: d005 beq.n 8041748 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); - 8041740: 4b53 ldr r3, [pc, #332] ; (8041890 ) - 8041742: 689b ldr r3, [r3, #8] - 8041744: 4a52 ldr r2, [pc, #328] ; (8041890 ) - 8041746: f443 4360 orr.w r3, r3, #57344 ; 0xe000 - 804174a: 6093 str r3, [r2, #8] + 804173c: 4b53 ldr r3, [pc, #332] ; (804188c ) + 804173e: 689b ldr r3, [r3, #8] + 8041740: 4a52 ldr r2, [pc, #328] ; (804188c ) + 8041742: f443 4360 orr.w r3, r3, #57344 ; 0xe000 + 8041746: 6093 str r3, [r2, #8] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - 804174c: 4b50 ldr r3, [pc, #320] ; (8041890 ) - 804174e: 689b ldr r3, [r3, #8] - 8041750: f023 02f0 bic.w r2, r3, #240 ; 0xf0 - 8041754: 687b ldr r3, [r7, #4] - 8041756: 689b ldr r3, [r3, #8] - 8041758: 494d ldr r1, [pc, #308] ; (8041890 ) - 804175a: 4313 orrs r3, r2 - 804175c: 608b str r3, [r1, #8] + 8041748: 4b50 ldr r3, [pc, #320] ; (804188c ) + 804174a: 689b ldr r3, [r3, #8] + 804174c: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 8041750: 687b ldr r3, [r7, #4] + 8041752: 689b ldr r3, [r3, #8] + 8041754: 494d ldr r1, [pc, #308] ; (804188c ) + 8041756: 4313 orrs r3, r2 + 8041758: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - 804175e: 687b ldr r3, [r7, #4] - 8041760: 681b ldr r3, [r3, #0] - 8041762: f003 0301 and.w r3, r3, #1 - 8041766: 2b00 cmp r3, #0 - 8041768: d040 beq.n 80417ec + 804175a: 687b ldr r3, [r7, #4] + 804175c: 681b ldr r3, [r3, #0] + 804175e: f003 0301 and.w r3, r3, #1 + 8041762: 2b00 cmp r3, #0 + 8041764: d040 beq.n 80417e8 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - 804176a: 687b ldr r3, [r7, #4] - 804176c: 685b ldr r3, [r3, #4] - 804176e: 2b01 cmp r3, #1 - 8041770: d107 bne.n 8041782 + 8041766: 687b ldr r3, [r7, #4] + 8041768: 685b ldr r3, [r3, #4] + 804176a: 2b01 cmp r3, #1 + 804176c: d107 bne.n 804177e { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 8041772: 4b47 ldr r3, [pc, #284] ; (8041890 ) - 8041774: 681b ldr r3, [r3, #0] - 8041776: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 804177a: 2b00 cmp r3, #0 - 804177c: d115 bne.n 80417aa + 804176e: 4b47 ldr r3, [pc, #284] ; (804188c ) + 8041770: 681b ldr r3, [r3, #0] + 8041772: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8041776: 2b00 cmp r3, #0 + 8041778: d115 bne.n 80417a6 { return HAL_ERROR; - 804177e: 2301 movs r3, #1 - 8041780: e07f b.n 8041882 + 804177a: 2301 movs r3, #1 + 804177c: e07f b.n 804187e } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - 8041782: 687b ldr r3, [r7, #4] - 8041784: 685b ldr r3, [r3, #4] - 8041786: 2b02 cmp r3, #2 - 8041788: d107 bne.n 804179a + 804177e: 687b ldr r3, [r7, #4] + 8041780: 685b ldr r3, [r3, #4] + 8041782: 2b02 cmp r3, #2 + 8041784: d107 bne.n 8041796 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 804178a: 4b41 ldr r3, [pc, #260] ; (8041890 ) - 804178c: 681b ldr r3, [r3, #0] - 804178e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 8041792: 2b00 cmp r3, #0 - 8041794: d109 bne.n 80417aa + 8041786: 4b41 ldr r3, [pc, #260] ; (804188c ) + 8041788: 681b ldr r3, [r3, #0] + 804178a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 804178e: 2b00 cmp r3, #0 + 8041790: d109 bne.n 80417a6 { return HAL_ERROR; - 8041796: 2301 movs r3, #1 - 8041798: e073 b.n 8041882 + 8041792: 2301 movs r3, #1 + 8041794: e073 b.n 804187e } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 804179a: 4b3d ldr r3, [pc, #244] ; (8041890 ) - 804179c: 681b ldr r3, [r3, #0] - 804179e: f003 0302 and.w r3, r3, #2 - 80417a2: 2b00 cmp r3, #0 - 80417a4: d101 bne.n 80417aa + 8041796: 4b3d ldr r3, [pc, #244] ; (804188c ) + 8041798: 681b ldr r3, [r3, #0] + 804179a: f003 0302 and.w r3, r3, #2 + 804179e: 2b00 cmp r3, #0 + 80417a0: d101 bne.n 80417a6 { return HAL_ERROR; - 80417a6: 2301 movs r3, #1 - 80417a8: e06b b.n 8041882 + 80417a2: 2301 movs r3, #1 + 80417a4: e06b b.n 804187e } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - 80417aa: 4b39 ldr r3, [pc, #228] ; (8041890 ) - 80417ac: 689b ldr r3, [r3, #8] - 80417ae: f023 0203 bic.w r2, r3, #3 - 80417b2: 687b ldr r3, [r7, #4] - 80417b4: 685b ldr r3, [r3, #4] - 80417b6: 4936 ldr r1, [pc, #216] ; (8041890 ) - 80417b8: 4313 orrs r3, r2 - 80417ba: 608b str r3, [r1, #8] + 80417a6: 4b39 ldr r3, [pc, #228] ; (804188c ) + 80417a8: 689b ldr r3, [r3, #8] + 80417aa: f023 0203 bic.w r2, r3, #3 + 80417ae: 687b ldr r3, [r7, #4] + 80417b0: 685b ldr r3, [r3, #4] + 80417b2: 4936 ldr r1, [pc, #216] ; (804188c ) + 80417b4: 4313 orrs r3, r2 + 80417b6: 608b str r3, [r1, #8] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 80417bc: f7ff f9fa bl 8040bb4 - 80417c0: 60f8 str r0, [r7, #12] + 80417b8: f7ff f9fa bl 8040bb0 + 80417bc: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 80417c2: e00a b.n 80417da + 80417be: e00a b.n 80417d6 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - 80417c4: f7ff f9f6 bl 8040bb4 - 80417c8: 4602 mov r2, r0 - 80417ca: 68fb ldr r3, [r7, #12] - 80417cc: 1ad3 subs r3, r2, r3 - 80417ce: f241 3288 movw r2, #5000 ; 0x1388 - 80417d2: 4293 cmp r3, r2 - 80417d4: d901 bls.n 80417da + 80417c0: f7ff f9f6 bl 8040bb0 + 80417c4: 4602 mov r2, r0 + 80417c6: 68fb ldr r3, [r7, #12] + 80417c8: 1ad3 subs r3, r2, r3 + 80417ca: f241 3288 movw r2, #5000 ; 0x1388 + 80417ce: 4293 cmp r3, r2 + 80417d0: d901 bls.n 80417d6 { return HAL_TIMEOUT; - 80417d6: 2303 movs r3, #3 - 80417d8: e053 b.n 8041882 + 80417d2: 2303 movs r3, #3 + 80417d4: e053 b.n 804187e while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 80417da: 4b2d ldr r3, [pc, #180] ; (8041890 ) - 80417dc: 689b ldr r3, [r3, #8] - 80417de: f003 020c and.w r2, r3, #12 - 80417e2: 687b ldr r3, [r7, #4] - 80417e4: 685b ldr r3, [r3, #4] - 80417e6: 009b lsls r3, r3, #2 - 80417e8: 429a cmp r2, r3 - 80417ea: d1eb bne.n 80417c4 + 80417d6: 4b2d ldr r3, [pc, #180] ; (804188c ) + 80417d8: 689b ldr r3, [r3, #8] + 80417da: f003 020c and.w r2, r3, #12 + 80417de: 687b ldr r3, [r7, #4] + 80417e0: 685b ldr r3, [r3, #4] + 80417e2: 009b lsls r3, r3, #2 + 80417e4: 429a cmp r2, r3 + 80417e6: d1eb bne.n 80417c0 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) - 80417ec: 4b27 ldr r3, [pc, #156] ; (804188c ) - 80417ee: 681b ldr r3, [r3, #0] - 80417f0: f003 030f and.w r3, r3, #15 - 80417f4: 683a ldr r2, [r7, #0] - 80417f6: 429a cmp r2, r3 - 80417f8: d210 bcs.n 804181c + 80417e8: 4b27 ldr r3, [pc, #156] ; (8041888 ) + 80417ea: 681b ldr r3, [r3, #0] + 80417ec: f003 030f and.w r3, r3, #15 + 80417f0: 683a ldr r2, [r7, #0] + 80417f2: 429a cmp r2, r3 + 80417f4: d210 bcs.n 8041818 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 80417fa: 4b24 ldr r3, [pc, #144] ; (804188c ) - 80417fc: 681b ldr r3, [r3, #0] - 80417fe: f023 020f bic.w r2, r3, #15 - 8041802: 4922 ldr r1, [pc, #136] ; (804188c ) - 8041804: 683b ldr r3, [r7, #0] - 8041806: 4313 orrs r3, r2 - 8041808: 600b str r3, [r1, #0] + 80417f6: 4b24 ldr r3, [pc, #144] ; (8041888 ) + 80417f8: 681b ldr r3, [r3, #0] + 80417fa: f023 020f bic.w r2, r3, #15 + 80417fe: 4922 ldr r1, [pc, #136] ; (8041888 ) + 8041800: 683b ldr r3, [r7, #0] + 8041802: 4313 orrs r3, r2 + 8041804: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) - 804180a: 4b20 ldr r3, [pc, #128] ; (804188c ) - 804180c: 681b ldr r3, [r3, #0] - 804180e: f003 030f and.w r3, r3, #15 - 8041812: 683a ldr r2, [r7, #0] - 8041814: 429a cmp r2, r3 - 8041816: d001 beq.n 804181c + 8041806: 4b20 ldr r3, [pc, #128] ; (8041888 ) + 8041808: 681b ldr r3, [r3, #0] + 804180a: f003 030f and.w r3, r3, #15 + 804180e: 683a ldr r2, [r7, #0] + 8041810: 429a cmp r2, r3 + 8041812: d001 beq.n 8041818 { return HAL_ERROR; - 8041818: 2301 movs r3, #1 - 804181a: e032 b.n 8041882 + 8041814: 2301 movs r3, #1 + 8041816: e032 b.n 804187e } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 804181c: 687b ldr r3, [r7, #4] - 804181e: 681b ldr r3, [r3, #0] - 8041820: f003 0304 and.w r3, r3, #4 - 8041824: 2b00 cmp r3, #0 - 8041826: d008 beq.n 804183a + 8041818: 687b ldr r3, [r7, #4] + 804181a: 681b ldr r3, [r3, #0] + 804181c: f003 0304 and.w r3, r3, #4 + 8041820: 2b00 cmp r3, #0 + 8041822: d008 beq.n 8041836 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); - 8041828: 4b19 ldr r3, [pc, #100] ; (8041890 ) - 804182a: 689b ldr r3, [r3, #8] - 804182c: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 - 8041830: 687b ldr r3, [r7, #4] - 8041832: 68db ldr r3, [r3, #12] - 8041834: 4916 ldr r1, [pc, #88] ; (8041890 ) - 8041836: 4313 orrs r3, r2 - 8041838: 608b str r3, [r1, #8] + 8041824: 4b19 ldr r3, [pc, #100] ; (804188c ) + 8041826: 689b ldr r3, [r3, #8] + 8041828: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 + 804182c: 687b ldr r3, [r7, #4] + 804182e: 68db ldr r3, [r3, #12] + 8041830: 4916 ldr r1, [pc, #88] ; (804188c ) + 8041832: 4313 orrs r3, r2 + 8041834: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - 804183a: 687b ldr r3, [r7, #4] - 804183c: 681b ldr r3, [r3, #0] - 804183e: f003 0308 and.w r3, r3, #8 - 8041842: 2b00 cmp r3, #0 - 8041844: d009 beq.n 804185a + 8041836: 687b ldr r3, [r7, #4] + 8041838: 681b ldr r3, [r3, #0] + 804183a: f003 0308 and.w r3, r3, #8 + 804183e: 2b00 cmp r3, #0 + 8041840: d009 beq.n 8041856 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); - 8041846: 4b12 ldr r3, [pc, #72] ; (8041890 ) - 8041848: 689b ldr r3, [r3, #8] - 804184a: f423 4260 bic.w r2, r3, #57344 ; 0xe000 - 804184e: 687b ldr r3, [r7, #4] - 8041850: 691b ldr r3, [r3, #16] - 8041852: 00db lsls r3, r3, #3 - 8041854: 490e ldr r1, [pc, #56] ; (8041890 ) - 8041856: 4313 orrs r3, r2 - 8041858: 608b str r3, [r1, #8] + 8041842: 4b12 ldr r3, [pc, #72] ; (804188c ) + 8041844: 689b ldr r3, [r3, #8] + 8041846: f423 4260 bic.w r2, r3, #57344 ; 0xe000 + 804184a: 687b ldr r3, [r7, #4] + 804184c: 691b ldr r3, [r3, #16] + 804184e: 00db lsls r3, r3, #3 + 8041850: 490e ldr r1, [pc, #56] ; (804188c ) + 8041852: 4313 orrs r3, r2 + 8041854: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; - 804185a: f000 f821 bl 80418a0 - 804185e: 4602 mov r2, r0 - 8041860: 4b0b ldr r3, [pc, #44] ; (8041890 ) - 8041862: 689b ldr r3, [r3, #8] - 8041864: 091b lsrs r3, r3, #4 - 8041866: f003 030f and.w r3, r3, #15 - 804186a: 490a ldr r1, [pc, #40] ; (8041894 ) - 804186c: 5ccb ldrb r3, [r1, r3] - 804186e: fa22 f303 lsr.w r3, r2, r3 - 8041872: 4a09 ldr r2, [pc, #36] ; (8041898 ) - 8041874: 6013 str r3, [r2, #0] + 8041856: f000 f821 bl 804189c + 804185a: 4602 mov r2, r0 + 804185c: 4b0b ldr r3, [pc, #44] ; (804188c ) + 804185e: 689b ldr r3, [r3, #8] + 8041860: 091b lsrs r3, r3, #4 + 8041862: f003 030f and.w r3, r3, #15 + 8041866: 490a ldr r1, [pc, #40] ; (8041890 ) + 8041868: 5ccb ldrb r3, [r1, r3] + 804186a: fa22 f303 lsr.w r3, r2, r3 + 804186e: 4a09 ldr r2, [pc, #36] ; (8041894 ) + 8041870: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); - 8041876: 4b09 ldr r3, [pc, #36] ; (804189c ) - 8041878: 681b ldr r3, [r3, #0] - 804187a: 4618 mov r0, r3 - 804187c: f7ff f956 bl 8040b2c + 8041872: 4b09 ldr r3, [pc, #36] ; (8041898 ) + 8041874: 681b ldr r3, [r3, #0] + 8041876: 4618 mov r0, r3 + 8041878: f7ff f956 bl 8040b28 return HAL_OK; - 8041880: 2300 movs r3, #0 + 804187c: 2300 movs r3, #0 } - 8041882: 4618 mov r0, r3 - 8041884: 3710 adds r7, #16 - 8041886: 46bd mov sp, r7 - 8041888: bd80 pop {r7, pc} - 804188a: bf00 nop - 804188c: 40023c00 .word 0x40023c00 - 8041890: 40023800 .word 0x40023800 - 8041894: 08043b64 .word 0x08043b64 - 8041898: 20000000 .word 0x20000000 - 804189c: 20000004 .word 0x20000004 - -080418a0 : + 804187e: 4618 mov r0, r3 + 8041880: 3710 adds r7, #16 + 8041882: 46bd mov sp, r7 + 8041884: bd80 pop {r7, pc} + 8041886: bf00 nop + 8041888: 40023c00 .word 0x40023c00 + 804188c: 40023800 .word 0x40023800 + 8041890: 08043b60 .word 0x08043b60 + 8041894: 20000000 .word 0x20000000 + 8041898: 20000004 .word 0x20000004 + +0804189c : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { - 80418a0: b5b0 push {r4, r5, r7, lr} - 80418a2: b084 sub sp, #16 - 80418a4: af00 add r7, sp, #0 + 804189c: b5b0 push {r4, r5, r7, lr} + 804189e: b084 sub sp, #16 + 80418a0: af00 add r7, sp, #0 uint32_t pllm = 0, pllvco = 0, pllp = 0; + 80418a2: 2100 movs r1, #0 + 80418a4: 6079 str r1, [r7, #4] 80418a6: 2100 movs r1, #0 - 80418a8: 6079 str r1, [r7, #4] + 80418a8: 60f9 str r1, [r7, #12] 80418aa: 2100 movs r1, #0 - 80418ac: 60f9 str r1, [r7, #12] - 80418ae: 2100 movs r1, #0 - 80418b0: 6039 str r1, [r7, #0] + 80418ac: 6039 str r1, [r7, #0] uint32_t sysclockfreq = 0; - 80418b2: 2100 movs r1, #0 - 80418b4: 60b9 str r1, [r7, #8] + 80418ae: 2100 movs r1, #0 + 80418b0: 60b9 str r1, [r7, #8] /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) - 80418b6: 4952 ldr r1, [pc, #328] ; (8041a00 ) - 80418b8: 6889 ldr r1, [r1, #8] - 80418ba: f001 010c and.w r1, r1, #12 + 80418b2: 4952 ldr r1, [pc, #328] ; (80419fc ) + 80418b4: 6889 ldr r1, [r1, #8] + 80418b6: f001 010c and.w r1, r1, #12 + 80418ba: 2908 cmp r1, #8 + 80418bc: d00d beq.n 80418da 80418be: 2908 cmp r1, #8 - 80418c0: d00d beq.n 80418de - 80418c2: 2908 cmp r1, #8 - 80418c4: f200 8094 bhi.w 80419f0 - 80418c8: 2900 cmp r1, #0 - 80418ca: d002 beq.n 80418d2 - 80418cc: 2904 cmp r1, #4 - 80418ce: d003 beq.n 80418d8 - 80418d0: e08e b.n 80419f0 + 80418c0: f200 8094 bhi.w 80419ec + 80418c4: 2900 cmp r1, #0 + 80418c6: d002 beq.n 80418ce + 80418c8: 2904 cmp r1, #4 + 80418ca: d003 beq.n 80418d4 + 80418cc: e08e b.n 80419ec { case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; - 80418d2: 4b4c ldr r3, [pc, #304] ; (8041a04 ) - 80418d4: 60bb str r3, [r7, #8] + 80418ce: 4b4c ldr r3, [pc, #304] ; (8041a00 ) + 80418d0: 60bb str r3, [r7, #8] break; - 80418d6: e08e b.n 80419f6 + 80418d2: e08e b.n 80419f2 } case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ { sysclockfreq = HSE_VALUE; - 80418d8: 4b4b ldr r3, [pc, #300] ; (8041a08 ) - 80418da: 60bb str r3, [r7, #8] + 80418d4: 4b4b ldr r3, [pc, #300] ; (8041a04 ) + 80418d6: 60bb str r3, [r7, #8] break; - 80418dc: e08b b.n 80419f6 + 80418d8: e08b b.n 80419f2 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - 80418de: 4948 ldr r1, [pc, #288] ; (8041a00 ) - 80418e0: 6849 ldr r1, [r1, #4] - 80418e2: f001 013f and.w r1, r1, #63 ; 0x3f - 80418e6: 6079 str r1, [r7, #4] + 80418da: 4948 ldr r1, [pc, #288] ; (80419fc ) + 80418dc: 6849 ldr r1, [r1, #4] + 80418de: f001 013f and.w r1, r1, #63 ; 0x3f + 80418e2: 6079 str r1, [r7, #4] if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI) - 80418e8: 4945 ldr r1, [pc, #276] ; (8041a00 ) - 80418ea: 6849 ldr r1, [r1, #4] - 80418ec: f401 0180 and.w r1, r1, #4194304 ; 0x400000 - 80418f0: 2900 cmp r1, #0 - 80418f2: d024 beq.n 804193e + 80418e4: 4945 ldr r1, [pc, #276] ; (80419fc ) + 80418e6: 6849 ldr r1, [r1, #4] + 80418e8: f401 0180 and.w r1, r1, #4194304 ; 0x400000 + 80418ec: 2900 cmp r1, #0 + 80418ee: d024 beq.n 804193a { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); - 80418f4: 4942 ldr r1, [pc, #264] ; (8041a00 ) - 80418f6: 6849 ldr r1, [r1, #4] - 80418f8: 0989 lsrs r1, r1, #6 - 80418fa: 4608 mov r0, r1 - 80418fc: f04f 0100 mov.w r1, #0 - 8041900: f240 14ff movw r4, #511 ; 0x1ff - 8041904: f04f 0500 mov.w r5, #0 - 8041908: ea00 0204 and.w r2, r0, r4 - 804190c: ea01 0305 and.w r3, r1, r5 - 8041910: 493d ldr r1, [pc, #244] ; (8041a08 ) - 8041912: fb01 f003 mul.w r0, r1, r3 - 8041916: 2100 movs r1, #0 - 8041918: fb01 f102 mul.w r1, r1, r2 - 804191c: 1844 adds r4, r0, r1 - 804191e: 493a ldr r1, [pc, #232] ; (8041a08 ) - 8041920: fba2 0101 umull r0, r1, r2, r1 - 8041924: 1863 adds r3, r4, r1 - 8041926: 4619 mov r1, r3 - 8041928: 687b ldr r3, [r7, #4] - 804192a: 461a mov r2, r3 - 804192c: f04f 0300 mov.w r3, #0 - 8041930: f7fe fcd6 bl 80402e0 <__aeabi_uldivmod> - 8041934: 4602 mov r2, r0 - 8041936: 460b mov r3, r1 - 8041938: 4613 mov r3, r2 - 804193a: 60fb str r3, [r7, #12] - 804193c: e04a b.n 80419d4 + 80418f0: 4942 ldr r1, [pc, #264] ; (80419fc ) + 80418f2: 6849 ldr r1, [r1, #4] + 80418f4: 0989 lsrs r1, r1, #6 + 80418f6: 4608 mov r0, r1 + 80418f8: f04f 0100 mov.w r1, #0 + 80418fc: f240 14ff movw r4, #511 ; 0x1ff + 8041900: f04f 0500 mov.w r5, #0 + 8041904: ea00 0204 and.w r2, r0, r4 + 8041908: ea01 0305 and.w r3, r1, r5 + 804190c: 493d ldr r1, [pc, #244] ; (8041a04 ) + 804190e: fb01 f003 mul.w r0, r1, r3 + 8041912: 2100 movs r1, #0 + 8041914: fb01 f102 mul.w r1, r1, r2 + 8041918: 1844 adds r4, r0, r1 + 804191a: 493a ldr r1, [pc, #232] ; (8041a04 ) + 804191c: fba2 0101 umull r0, r1, r2, r1 + 8041920: 1863 adds r3, r4, r1 + 8041922: 4619 mov r1, r3 + 8041924: 687b ldr r3, [r7, #4] + 8041926: 461a mov r2, r3 + 8041928: f04f 0300 mov.w r3, #0 + 804192c: f7fe fcd8 bl 80402e0 <__aeabi_uldivmod> + 8041930: 4602 mov r2, r0 + 8041932: 460b mov r3, r1 + 8041934: 4613 mov r3, r2 + 8041936: 60fb str r3, [r7, #12] + 8041938: e04a b.n 80419d0 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); - 804193e: 4b30 ldr r3, [pc, #192] ; (8041a00 ) - 8041940: 685b ldr r3, [r3, #4] - 8041942: 099b lsrs r3, r3, #6 - 8041944: 461a mov r2, r3 - 8041946: f04f 0300 mov.w r3, #0 - 804194a: f240 10ff movw r0, #511 ; 0x1ff - 804194e: f04f 0100 mov.w r1, #0 - 8041952: ea02 0400 and.w r4, r2, r0 - 8041956: ea03 0501 and.w r5, r3, r1 - 804195a: 4620 mov r0, r4 - 804195c: 4629 mov r1, r5 - 804195e: f04f 0200 mov.w r2, #0 - 8041962: f04f 0300 mov.w r3, #0 - 8041966: 014b lsls r3, r1, #5 - 8041968: ea43 63d0 orr.w r3, r3, r0, lsr #27 - 804196c: 0142 lsls r2, r0, #5 - 804196e: 4610 mov r0, r2 - 8041970: 4619 mov r1, r3 - 8041972: 1b00 subs r0, r0, r4 - 8041974: eb61 0105 sbc.w r1, r1, r5 - 8041978: f04f 0200 mov.w r2, #0 - 804197c: f04f 0300 mov.w r3, #0 - 8041980: 018b lsls r3, r1, #6 - 8041982: ea43 6390 orr.w r3, r3, r0, lsr #26 - 8041986: 0182 lsls r2, r0, #6 - 8041988: 1a12 subs r2, r2, r0 - 804198a: eb63 0301 sbc.w r3, r3, r1 - 804198e: f04f 0000 mov.w r0, #0 - 8041992: f04f 0100 mov.w r1, #0 - 8041996: 00d9 lsls r1, r3, #3 - 8041998: ea41 7152 orr.w r1, r1, r2, lsr #29 - 804199c: 00d0 lsls r0, r2, #3 - 804199e: 4602 mov r2, r0 - 80419a0: 460b mov r3, r1 - 80419a2: 1912 adds r2, r2, r4 - 80419a4: eb45 0303 adc.w r3, r5, r3 - 80419a8: f04f 0000 mov.w r0, #0 - 80419ac: f04f 0100 mov.w r1, #0 - 80419b0: 0299 lsls r1, r3, #10 - 80419b2: ea41 5192 orr.w r1, r1, r2, lsr #22 - 80419b6: 0290 lsls r0, r2, #10 - 80419b8: 4602 mov r2, r0 - 80419ba: 460b mov r3, r1 - 80419bc: 4610 mov r0, r2 - 80419be: 4619 mov r1, r3 - 80419c0: 687b ldr r3, [r7, #4] - 80419c2: 461a mov r2, r3 - 80419c4: f04f 0300 mov.w r3, #0 - 80419c8: f7fe fc8a bl 80402e0 <__aeabi_uldivmod> - 80419cc: 4602 mov r2, r0 - 80419ce: 460b mov r3, r1 - 80419d0: 4613 mov r3, r2 - 80419d2: 60fb str r3, [r7, #12] + 804193a: 4b30 ldr r3, [pc, #192] ; (80419fc ) + 804193c: 685b ldr r3, [r3, #4] + 804193e: 099b lsrs r3, r3, #6 + 8041940: 461a mov r2, r3 + 8041942: f04f 0300 mov.w r3, #0 + 8041946: f240 10ff movw r0, #511 ; 0x1ff + 804194a: f04f 0100 mov.w r1, #0 + 804194e: ea02 0400 and.w r4, r2, r0 + 8041952: ea03 0501 and.w r5, r3, r1 + 8041956: 4620 mov r0, r4 + 8041958: 4629 mov r1, r5 + 804195a: f04f 0200 mov.w r2, #0 + 804195e: f04f 0300 mov.w r3, #0 + 8041962: 014b lsls r3, r1, #5 + 8041964: ea43 63d0 orr.w r3, r3, r0, lsr #27 + 8041968: 0142 lsls r2, r0, #5 + 804196a: 4610 mov r0, r2 + 804196c: 4619 mov r1, r3 + 804196e: 1b00 subs r0, r0, r4 + 8041970: eb61 0105 sbc.w r1, r1, r5 + 8041974: f04f 0200 mov.w r2, #0 + 8041978: f04f 0300 mov.w r3, #0 + 804197c: 018b lsls r3, r1, #6 + 804197e: ea43 6390 orr.w r3, r3, r0, lsr #26 + 8041982: 0182 lsls r2, r0, #6 + 8041984: 1a12 subs r2, r2, r0 + 8041986: eb63 0301 sbc.w r3, r3, r1 + 804198a: f04f 0000 mov.w r0, #0 + 804198e: f04f 0100 mov.w r1, #0 + 8041992: 00d9 lsls r1, r3, #3 + 8041994: ea41 7152 orr.w r1, r1, r2, lsr #29 + 8041998: 00d0 lsls r0, r2, #3 + 804199a: 4602 mov r2, r0 + 804199c: 460b mov r3, r1 + 804199e: 1912 adds r2, r2, r4 + 80419a0: eb45 0303 adc.w r3, r5, r3 + 80419a4: f04f 0000 mov.w r0, #0 + 80419a8: f04f 0100 mov.w r1, #0 + 80419ac: 0299 lsls r1, r3, #10 + 80419ae: ea41 5192 orr.w r1, r1, r2, lsr #22 + 80419b2: 0290 lsls r0, r2, #10 + 80419b4: 4602 mov r2, r0 + 80419b6: 460b mov r3, r1 + 80419b8: 4610 mov r0, r2 + 80419ba: 4619 mov r1, r3 + 80419bc: 687b ldr r3, [r7, #4] + 80419be: 461a mov r2, r3 + 80419c0: f04f 0300 mov.w r3, #0 + 80419c4: f7fe fc8c bl 80402e0 <__aeabi_uldivmod> + 80419c8: 4602 mov r2, r0 + 80419ca: 460b mov r3, r1 + 80419cc: 4613 mov r3, r2 + 80419ce: 60fb str r3, [r7, #12] } pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2); - 80419d4: 4b0a ldr r3, [pc, #40] ; (8041a00 ) - 80419d6: 685b ldr r3, [r3, #4] - 80419d8: 0c1b lsrs r3, r3, #16 - 80419da: f003 0303 and.w r3, r3, #3 - 80419de: 3301 adds r3, #1 - 80419e0: 005b lsls r3, r3, #1 - 80419e2: 603b str r3, [r7, #0] + 80419d0: 4b0a ldr r3, [pc, #40] ; (80419fc ) + 80419d2: 685b ldr r3, [r3, #4] + 80419d4: 0c1b lsrs r3, r3, #16 + 80419d6: f003 0303 and.w r3, r3, #3 + 80419da: 3301 adds r3, #1 + 80419dc: 005b lsls r3, r3, #1 + 80419de: 603b str r3, [r7, #0] sysclockfreq = pllvco / pllp; - 80419e4: 68fa ldr r2, [r7, #12] - 80419e6: 683b ldr r3, [r7, #0] - 80419e8: fbb2 f3f3 udiv r3, r2, r3 - 80419ec: 60bb str r3, [r7, #8] + 80419e0: 68fa ldr r2, [r7, #12] + 80419e2: 683b ldr r3, [r7, #0] + 80419e4: fbb2 f3f3 udiv r3, r2, r3 + 80419e8: 60bb str r3, [r7, #8] break; - 80419ee: e002 b.n 80419f6 + 80419ea: e002 b.n 80419f2 } default: { sysclockfreq = HSI_VALUE; - 80419f0: 4b04 ldr r3, [pc, #16] ; (8041a04 ) - 80419f2: 60bb str r3, [r7, #8] + 80419ec: 4b04 ldr r3, [pc, #16] ; (8041a00 ) + 80419ee: 60bb str r3, [r7, #8] break; - 80419f4: bf00 nop + 80419f0: bf00 nop } } return sysclockfreq; - 80419f6: 68bb ldr r3, [r7, #8] + 80419f2: 68bb ldr r3, [r7, #8] } - 80419f8: 4618 mov r0, r3 - 80419fa: 3710 adds r7, #16 - 80419fc: 46bd mov sp, r7 - 80419fe: bdb0 pop {r4, r5, r7, pc} - 8041a00: 40023800 .word 0x40023800 - 8041a04: 00f42400 .word 0x00f42400 - 8041a08: 017d7840 .word 0x017d7840 - -08041a0c : + 80419f4: 4618 mov r0, r3 + 80419f6: 3710 adds r7, #16 + 80419f8: 46bd mov sp, r7 + 80419fa: bdb0 pop {r4, r5, r7, pc} + 80419fc: 40023800 .word 0x40023800 + 8041a00: 00f42400 .word 0x00f42400 + 8041a04: 017d7840 .word 0x017d7840 + +08041a08 : * right HCLK value. Otherwise, any configuration based on this function will be incorrect. * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { - 8041a0c: b480 push {r7} - 8041a0e: af00 add r7, sp, #0 + 8041a08: b480 push {r7} + 8041a0a: af00 add r7, sp, #0 return SystemCoreClock; - 8041a10: 4b03 ldr r3, [pc, #12] ; (8041a20 ) - 8041a12: 681b ldr r3, [r3, #0] + 8041a0c: 4b03 ldr r3, [pc, #12] ; (8041a1c ) + 8041a0e: 681b ldr r3, [r3, #0] } - 8041a14: 4618 mov r0, r3 - 8041a16: 46bd mov sp, r7 - 8041a18: f85d 7b04 ldr.w r7, [sp], #4 - 8041a1c: 4770 bx lr - 8041a1e: bf00 nop - 8041a20: 20000000 .word 0x20000000 - -08041a24 : + 8041a10: 4618 mov r0, r3 + 8041a12: 46bd mov sp, r7 + 8041a14: f85d 7b04 ldr.w r7, [sp], #4 + 8041a18: 4770 bx lr + 8041a1a: bf00 nop + 8041a1c: 20000000 .word 0x20000000 + +08041a20 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { - 8041a24: b580 push {r7, lr} - 8041a26: af00 add r7, sp, #0 + 8041a20: b580 push {r7, lr} + 8041a22: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); - 8041a28: f7ff fff0 bl 8041a0c - 8041a2c: 4602 mov r2, r0 - 8041a2e: 4b05 ldr r3, [pc, #20] ; (8041a44 ) - 8041a30: 689b ldr r3, [r3, #8] - 8041a32: 0a9b lsrs r3, r3, #10 - 8041a34: f003 0307 and.w r3, r3, #7 - 8041a38: 4903 ldr r1, [pc, #12] ; (8041a48 ) - 8041a3a: 5ccb ldrb r3, [r1, r3] - 8041a3c: fa22 f303 lsr.w r3, r2, r3 + 8041a24: f7ff fff0 bl 8041a08 + 8041a28: 4602 mov r2, r0 + 8041a2a: 4b05 ldr r3, [pc, #20] ; (8041a40 ) + 8041a2c: 689b ldr r3, [r3, #8] + 8041a2e: 0a9b lsrs r3, r3, #10 + 8041a30: f003 0307 and.w r3, r3, #7 + 8041a34: 4903 ldr r1, [pc, #12] ; (8041a44 ) + 8041a36: 5ccb ldrb r3, [r1, r3] + 8041a38: fa22 f303 lsr.w r3, r2, r3 } - 8041a40: 4618 mov r0, r3 - 8041a42: bd80 pop {r7, pc} - 8041a44: 40023800 .word 0x40023800 - 8041a48: 08043b74 .word 0x08043b74 + 8041a3c: 4618 mov r0, r3 + 8041a3e: bd80 pop {r7, pc} + 8041a40: 40023800 .word 0x40023800 + 8041a44: 08043b70 .word 0x08043b70 -08041a4c : +08041a48 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { - 8041a4c: b580 push {r7, lr} - 8041a4e: af00 add r7, sp, #0 + 8041a48: b580 push {r7, lr} + 8041a4a: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); - 8041a50: f7ff ffdc bl 8041a0c - 8041a54: 4602 mov r2, r0 - 8041a56: 4b05 ldr r3, [pc, #20] ; (8041a6c ) - 8041a58: 689b ldr r3, [r3, #8] - 8041a5a: 0b5b lsrs r3, r3, #13 - 8041a5c: f003 0307 and.w r3, r3, #7 - 8041a60: 4903 ldr r1, [pc, #12] ; (8041a70 ) - 8041a62: 5ccb ldrb r3, [r1, r3] - 8041a64: fa22 f303 lsr.w r3, r2, r3 + 8041a4c: f7ff ffdc bl 8041a08 + 8041a50: 4602 mov r2, r0 + 8041a52: 4b05 ldr r3, [pc, #20] ; (8041a68 ) + 8041a54: 689b ldr r3, [r3, #8] + 8041a56: 0b5b lsrs r3, r3, #13 + 8041a58: f003 0307 and.w r3, r3, #7 + 8041a5c: 4903 ldr r1, [pc, #12] ; (8041a6c ) + 8041a5e: 5ccb ldrb r3, [r1, r3] + 8041a60: fa22 f303 lsr.w r3, r2, r3 } - 8041a68: 4618 mov r0, r3 - 8041a6a: bd80 pop {r7, pc} - 8041a6c: 40023800 .word 0x40023800 - 8041a70: 08043b74 .word 0x08043b74 + 8041a64: 4618 mov r0, r3 + 8041a66: bd80 pop {r7, pc} + 8041a68: 40023800 .word 0x40023800 + 8041a6c: 08043b70 .word 0x08043b70 -08041a74 : +08041a70 : * the backup registers) are set to their reset values. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { - 8041a74: b580 push {r7, lr} - 8041a76: b088 sub sp, #32 - 8041a78: af00 add r7, sp, #0 - 8041a7a: 6078 str r0, [r7, #4] + 8041a70: b580 push {r7, lr} + 8041a72: b088 sub sp, #32 + 8041a74: af00 add r7, sp, #0 + 8041a76: 6078 str r0, [r7, #4] uint32_t tickstart = 0; - 8041a7c: 2300 movs r3, #0 - 8041a7e: 617b str r3, [r7, #20] + 8041a78: 2300 movs r3, #0 + 8041a7a: 617b str r3, [r7, #20] uint32_t tmpreg0 = 0; - 8041a80: 2300 movs r3, #0 - 8041a82: 613b str r3, [r7, #16] + 8041a7c: 2300 movs r3, #0 + 8041a7e: 613b str r3, [r7, #16] uint32_t tmpreg1 = 0; - 8041a84: 2300 movs r3, #0 - 8041a86: 60fb str r3, [r7, #12] + 8041a80: 2300 movs r3, #0 + 8041a82: 60fb str r3, [r7, #12] uint32_t plli2sused = 0; - 8041a88: 2300 movs r3, #0 - 8041a8a: 61fb str r3, [r7, #28] + 8041a84: 2300 movs r3, #0 + 8041a86: 61fb str r3, [r7, #28] uint32_t pllsaiused = 0; - 8041a8c: 2300 movs r3, #0 - 8041a8e: 61bb str r3, [r7, #24] + 8041a88: 2300 movs r3, #0 + 8041a8a: 61bb str r3, [r7, #24] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*----------------------------------- I2S configuration ----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) - 8041a90: 687b ldr r3, [r7, #4] - 8041a92: 681b ldr r3, [r3, #0] - 8041a94: f003 0301 and.w r3, r3, #1 - 8041a98: 2b00 cmp r3, #0 - 8041a9a: d012 beq.n 8041ac2 + 8041a8c: 687b ldr r3, [r7, #4] + 8041a8e: 681b ldr r3, [r3, #0] + 8041a90: f003 0301 and.w r3, r3, #1 + 8041a94: 2b00 cmp r3, #0 + 8041a96: d012 beq.n 8041abe { /* Check the parameters */ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); - 8041a9c: 4b69 ldr r3, [pc, #420] ; (8041c44 ) - 8041a9e: 689b ldr r3, [r3, #8] - 8041aa0: 4a68 ldr r2, [pc, #416] ; (8041c44 ) - 8041aa2: f423 0300 bic.w r3, r3, #8388608 ; 0x800000 - 8041aa6: 6093 str r3, [r2, #8] - 8041aa8: 4b66 ldr r3, [pc, #408] ; (8041c44 ) - 8041aaa: 689a ldr r2, [r3, #8] - 8041aac: 687b ldr r3, [r7, #4] - 8041aae: 6b5b ldr r3, [r3, #52] ; 0x34 - 8041ab0: 4964 ldr r1, [pc, #400] ; (8041c44 ) - 8041ab2: 4313 orrs r3, r2 - 8041ab4: 608b str r3, [r1, #8] + 8041a98: 4b69 ldr r3, [pc, #420] ; (8041c40 ) + 8041a9a: 689b ldr r3, [r3, #8] + 8041a9c: 4a68 ldr r2, [pc, #416] ; (8041c40 ) + 8041a9e: f423 0300 bic.w r3, r3, #8388608 ; 0x800000 + 8041aa2: 6093 str r3, [r2, #8] + 8041aa4: 4b66 ldr r3, [pc, #408] ; (8041c40 ) + 8041aa6: 689a ldr r2, [r3, #8] + 8041aa8: 687b ldr r3, [r7, #4] + 8041aaa: 6b5b ldr r3, [r3, #52] ; 0x34 + 8041aac: 4964 ldr r1, [pc, #400] ; (8041c40 ) + 8041aae: 4313 orrs r3, r2 + 8041ab0: 608b str r3, [r1, #8] /* Enable the PLLI2S when it's used as clock source for I2S */ if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) - 8041ab6: 687b ldr r3, [r7, #4] - 8041ab8: 6b5b ldr r3, [r3, #52] ; 0x34 - 8041aba: 2b00 cmp r3, #0 - 8041abc: d101 bne.n 8041ac2 + 8041ab2: 687b ldr r3, [r7, #4] + 8041ab4: 6b5b ldr r3, [r3, #52] ; 0x34 + 8041ab6: 2b00 cmp r3, #0 + 8041ab8: d101 bne.n 8041abe { plli2sused = 1; - 8041abe: 2301 movs r3, #1 - 8041ac0: 61fb str r3, [r7, #28] + 8041aba: 2301 movs r3, #1 + 8041abc: 61fb str r3, [r7, #28] } } /*------------------------------------ SAI1 configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) - 8041ac2: 687b ldr r3, [r7, #4] - 8041ac4: 681b ldr r3, [r3, #0] - 8041ac6: f403 2300 and.w r3, r3, #524288 ; 0x80000 - 8041aca: 2b00 cmp r3, #0 - 8041acc: d017 beq.n 8041afe + 8041abe: 687b ldr r3, [r7, #4] + 8041ac0: 681b ldr r3, [r3, #0] + 8041ac2: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 8041ac6: 2b00 cmp r3, #0 + 8041ac8: d017 beq.n 8041afa { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); /* Configure SAI1 Clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); - 8041ace: 4b5d ldr r3, [pc, #372] ; (8041c44 ) - 8041ad0: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c - 8041ad4: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 - 8041ad8: 687b ldr r3, [r7, #4] - 8041ada: 6bdb ldr r3, [r3, #60] ; 0x3c - 8041adc: 4959 ldr r1, [pc, #356] ; (8041c44 ) - 8041ade: 4313 orrs r3, r2 - 8041ae0: f8c1 308c str.w r3, [r1, #140] ; 0x8c + 8041aca: 4b5d ldr r3, [pc, #372] ; (8041c40 ) + 8041acc: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8041ad0: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 + 8041ad4: 687b ldr r3, [r7, #4] + 8041ad6: 6bdb ldr r3, [r3, #60] ; 0x3c + 8041ad8: 4959 ldr r1, [pc, #356] ; (8041c40 ) + 8041ada: 4313 orrs r3, r2 + 8041adc: f8c1 308c str.w r3, [r1, #140] ; 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) - 8041ae4: 687b ldr r3, [r7, #4] - 8041ae6: 6bdb ldr r3, [r3, #60] ; 0x3c - 8041ae8: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 - 8041aec: d101 bne.n 8041af2 + 8041ae0: 687b ldr r3, [r7, #4] + 8041ae2: 6bdb ldr r3, [r3, #60] ; 0x3c + 8041ae4: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 8041ae8: d101 bne.n 8041aee { plli2sused = 1; - 8041aee: 2301 movs r3, #1 - 8041af0: 61fb str r3, [r7, #28] + 8041aea: 2301 movs r3, #1 + 8041aec: 61fb str r3, [r7, #28] } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) - 8041af2: 687b ldr r3, [r7, #4] - 8041af4: 6bdb ldr r3, [r3, #60] ; 0x3c - 8041af6: 2b00 cmp r3, #0 - 8041af8: d101 bne.n 8041afe + 8041aee: 687b ldr r3, [r7, #4] + 8041af0: 6bdb ldr r3, [r3, #60] ; 0x3c + 8041af2: 2b00 cmp r3, #0 + 8041af4: d101 bne.n 8041afa { pllsaiused = 1; - 8041afa: 2301 movs r3, #1 - 8041afc: 61bb str r3, [r7, #24] + 8041af6: 2301 movs r3, #1 + 8041af8: 61bb str r3, [r7, #24] } } /*------------------------------------ SAI2 configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) - 8041afe: 687b ldr r3, [r7, #4] - 8041b00: 681b ldr r3, [r3, #0] - 8041b02: f403 1380 and.w r3, r3, #1048576 ; 0x100000 - 8041b06: 2b00 cmp r3, #0 - 8041b08: d017 beq.n 8041b3a + 8041afa: 687b ldr r3, [r7, #4] + 8041afc: 681b ldr r3, [r3, #0] + 8041afe: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 8041b02: 2b00 cmp r3, #0 + 8041b04: d017 beq.n 8041b36 { /* Check the parameters */ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); /* Configure SAI2 Clock source */ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); - 8041b0a: 4b4e ldr r3, [pc, #312] ; (8041c44 ) - 8041b0c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c - 8041b10: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 - 8041b14: 687b ldr r3, [r7, #4] - 8041b16: 6c1b ldr r3, [r3, #64] ; 0x40 - 8041b18: 494a ldr r1, [pc, #296] ; (8041c44 ) - 8041b1a: 4313 orrs r3, r2 - 8041b1c: f8c1 308c str.w r3, [r1, #140] ; 0x8c + 8041b06: 4b4e ldr r3, [pc, #312] ; (8041c40 ) + 8041b08: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8041b0c: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 + 8041b10: 687b ldr r3, [r7, #4] + 8041b12: 6c1b ldr r3, [r3, #64] ; 0x40 + 8041b14: 494a ldr r1, [pc, #296] ; (8041c40 ) + 8041b16: 4313 orrs r3, r2 + 8041b18: f8c1 308c str.w r3, [r1, #140] ; 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) - 8041b20: 687b ldr r3, [r7, #4] - 8041b22: 6c1b ldr r3, [r3, #64] ; 0x40 - 8041b24: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 - 8041b28: d101 bne.n 8041b2e + 8041b1c: 687b ldr r3, [r7, #4] + 8041b1e: 6c1b ldr r3, [r3, #64] ; 0x40 + 8041b20: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 8041b24: d101 bne.n 8041b2a { plli2sused = 1; - 8041b2a: 2301 movs r3, #1 - 8041b2c: 61fb str r3, [r7, #28] + 8041b26: 2301 movs r3, #1 + 8041b28: 61fb str r3, [r7, #28] } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) - 8041b2e: 687b ldr r3, [r7, #4] - 8041b30: 6c1b ldr r3, [r3, #64] ; 0x40 - 8041b32: 2b00 cmp r3, #0 - 8041b34: d101 bne.n 8041b3a + 8041b2a: 687b ldr r3, [r7, #4] + 8041b2c: 6c1b ldr r3, [r3, #64] ; 0x40 + 8041b2e: 2b00 cmp r3, #0 + 8041b30: d101 bne.n 8041b36 { pllsaiused = 1; - 8041b36: 2301 movs r3, #1 - 8041b38: 61bb str r3, [r7, #24] + 8041b32: 2301 movs r3, #1 + 8041b34: 61bb str r3, [r7, #24] } } /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) - 8041b3a: 687b ldr r3, [r7, #4] - 8041b3c: 681b ldr r3, [r3, #0] - 8041b3e: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 - 8041b42: 2b00 cmp r3, #0 - 8041b44: d001 beq.n 8041b4a + 8041b36: 687b ldr r3, [r7, #4] + 8041b38: 681b ldr r3, [r3, #0] + 8041b3a: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 8041b3e: 2b00 cmp r3, #0 + 8041b40: d001 beq.n 8041b46 { plli2sused = 1; - 8041b46: 2301 movs r3, #1 - 8041b48: 61fb str r3, [r7, #28] + 8041b42: 2301 movs r3, #1 + 8041b44: 61fb str r3, [r7, #28] } /*------------------------------------ RTC configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) - 8041b4a: 687b ldr r3, [r7, #4] - 8041b4c: 681b ldr r3, [r3, #0] - 8041b4e: f003 0320 and.w r3, r3, #32 - 8041b52: 2b00 cmp r3, #0 - 8041b54: f000 808b beq.w 8041c6e + 8041b46: 687b ldr r3, [r7, #4] + 8041b48: 681b ldr r3, [r3, #0] + 8041b4a: f003 0320 and.w r3, r3, #32 + 8041b4e: 2b00 cmp r3, #0 + 8041b50: f000 808b beq.w 8041c6a { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - 8041b58: 4b3a ldr r3, [pc, #232] ; (8041c44 ) - 8041b5a: 6c1b ldr r3, [r3, #64] ; 0x40 - 8041b5c: 4a39 ldr r2, [pc, #228] ; (8041c44 ) - 8041b5e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 8041b62: 6413 str r3, [r2, #64] ; 0x40 - 8041b64: 4b37 ldr r3, [pc, #220] ; (8041c44 ) - 8041b66: 6c1b ldr r3, [r3, #64] ; 0x40 - 8041b68: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8041b6c: 60bb str r3, [r7, #8] - 8041b6e: 68bb ldr r3, [r7, #8] + 8041b54: 4b3a ldr r3, [pc, #232] ; (8041c40 ) + 8041b56: 6c1b ldr r3, [r3, #64] ; 0x40 + 8041b58: 4a39 ldr r2, [pc, #228] ; (8041c40 ) + 8041b5a: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8041b5e: 6413 str r3, [r2, #64] ; 0x40 + 8041b60: 4b37 ldr r3, [pc, #220] ; (8041c40 ) + 8041b62: 6c1b ldr r3, [r3, #64] ; 0x40 + 8041b64: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8041b68: 60bb str r3, [r7, #8] + 8041b6a: 68bb ldr r3, [r7, #8] /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; - 8041b70: 4b35 ldr r3, [pc, #212] ; (8041c48 ) - 8041b72: 681b ldr r3, [r3, #0] - 8041b74: 4a34 ldr r2, [pc, #208] ; (8041c48 ) - 8041b76: f443 7380 orr.w r3, r3, #256 ; 0x100 - 8041b7a: 6013 str r3, [r2, #0] + 8041b6c: 4b35 ldr r3, [pc, #212] ; (8041c44 ) + 8041b6e: 681b ldr r3, [r3, #0] + 8041b70: 4a34 ldr r2, [pc, #208] ; (8041c44 ) + 8041b72: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8041b76: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8041b7c: f7ff f81a bl 8040bb4 - 8041b80: 6178 str r0, [r7, #20] + 8041b78: f7ff f81a bl 8040bb0 + 8041b7c: 6178 str r0, [r7, #20] /* Wait for Backup domain Write protection disable */ while((PWR->CR1 & PWR_CR1_DBP) == RESET) - 8041b82: e008 b.n 8041b96 + 8041b7e: e008 b.n 8041b92 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - 8041b84: f7ff f816 bl 8040bb4 - 8041b88: 4602 mov r2, r0 - 8041b8a: 697b ldr r3, [r7, #20] - 8041b8c: 1ad3 subs r3, r2, r3 - 8041b8e: 2b64 cmp r3, #100 ; 0x64 - 8041b90: d901 bls.n 8041b96 + 8041b80: f7ff f816 bl 8040bb0 + 8041b84: 4602 mov r2, r0 + 8041b86: 697b ldr r3, [r7, #20] + 8041b88: 1ad3 subs r3, r2, r3 + 8041b8a: 2b64 cmp r3, #100 ; 0x64 + 8041b8c: d901 bls.n 8041b92 { return HAL_TIMEOUT; - 8041b92: 2303 movs r3, #3 - 8041b94: e38f b.n 80422b6 + 8041b8e: 2303 movs r3, #3 + 8041b90: e38f b.n 80422b2 while((PWR->CR1 & PWR_CR1_DBP) == RESET) - 8041b96: 4b2c ldr r3, [pc, #176] ; (8041c48 ) - 8041b98: 681b ldr r3, [r3, #0] - 8041b9a: f403 7380 and.w r3, r3, #256 ; 0x100 - 8041b9e: 2b00 cmp r3, #0 - 8041ba0: d0f0 beq.n 8041b84 + 8041b92: 4b2c ldr r3, [pc, #176] ; (8041c44 ) + 8041b94: 681b ldr r3, [r3, #0] + 8041b96: f403 7380 and.w r3, r3, #256 ; 0x100 + 8041b9a: 2b00 cmp r3, #0 + 8041b9c: d0f0 beq.n 8041b80 } } /* Reset the Backup domain only if the RTC Clock source selection is modified */ tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL); - 8041ba2: 4b28 ldr r3, [pc, #160] ; (8041c44 ) - 8041ba4: 6f1b ldr r3, [r3, #112] ; 0x70 - 8041ba6: f403 7340 and.w r3, r3, #768 ; 0x300 - 8041baa: 613b str r3, [r7, #16] + 8041b9e: 4b28 ldr r3, [pc, #160] ; (8041c40 ) + 8041ba0: 6f1b ldr r3, [r3, #112] ; 0x70 + 8041ba2: f403 7340 and.w r3, r3, #768 ; 0x300 + 8041ba6: 613b str r3, [r7, #16] if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) - 8041bac: 693b ldr r3, [r7, #16] - 8041bae: 2b00 cmp r3, #0 - 8041bb0: d035 beq.n 8041c1e - 8041bb2: 687b ldr r3, [r7, #4] - 8041bb4: 6b1b ldr r3, [r3, #48] ; 0x30 - 8041bb6: f403 7340 and.w r3, r3, #768 ; 0x300 - 8041bba: 693a ldr r2, [r7, #16] - 8041bbc: 429a cmp r2, r3 - 8041bbe: d02e beq.n 8041c1e + 8041ba8: 693b ldr r3, [r7, #16] + 8041baa: 2b00 cmp r3, #0 + 8041bac: d035 beq.n 8041c1a + 8041bae: 687b ldr r3, [r7, #4] + 8041bb0: 6b1b ldr r3, [r3, #48] ; 0x30 + 8041bb2: f403 7340 and.w r3, r3, #768 ; 0x300 + 8041bb6: 693a ldr r2, [r7, #16] + 8041bb8: 429a cmp r2, r3 + 8041bba: d02e beq.n 8041c1a { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); - 8041bc0: 4b20 ldr r3, [pc, #128] ; (8041c44 ) - 8041bc2: 6f1b ldr r3, [r3, #112] ; 0x70 - 8041bc4: f423 7340 bic.w r3, r3, #768 ; 0x300 - 8041bc8: 613b str r3, [r7, #16] + 8041bbc: 4b20 ldr r3, [pc, #128] ; (8041c40 ) + 8041bbe: 6f1b ldr r3, [r3, #112] ; 0x70 + 8041bc0: f423 7340 bic.w r3, r3, #768 ; 0x300 + 8041bc4: 613b str r3, [r7, #16] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); - 8041bca: 4b1e ldr r3, [pc, #120] ; (8041c44 ) - 8041bcc: 6f1b ldr r3, [r3, #112] ; 0x70 - 8041bce: 4a1d ldr r2, [pc, #116] ; (8041c44 ) - 8041bd0: f443 3380 orr.w r3, r3, #65536 ; 0x10000 - 8041bd4: 6713 str r3, [r2, #112] ; 0x70 + 8041bc6: 4b1e ldr r3, [pc, #120] ; (8041c40 ) + 8041bc8: 6f1b ldr r3, [r3, #112] ; 0x70 + 8041bca: 4a1d ldr r2, [pc, #116] ; (8041c40 ) + 8041bcc: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8041bd0: 6713 str r3, [r2, #112] ; 0x70 __HAL_RCC_BACKUPRESET_RELEASE(); - 8041bd6: 4b1b ldr r3, [pc, #108] ; (8041c44 ) - 8041bd8: 6f1b ldr r3, [r3, #112] ; 0x70 - 8041bda: 4a1a ldr r2, [pc, #104] ; (8041c44 ) - 8041bdc: f423 3380 bic.w r3, r3, #65536 ; 0x10000 - 8041be0: 6713 str r3, [r2, #112] ; 0x70 + 8041bd2: 4b1b ldr r3, [pc, #108] ; (8041c40 ) + 8041bd4: 6f1b ldr r3, [r3, #112] ; 0x70 + 8041bd6: 4a1a ldr r2, [pc, #104] ; (8041c40 ) + 8041bd8: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8041bdc: 6713 str r3, [r2, #112] ; 0x70 /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg0; - 8041be2: 4a18 ldr r2, [pc, #96] ; (8041c44 ) - 8041be4: 693b ldr r3, [r7, #16] - 8041be6: 6713 str r3, [r2, #112] ; 0x70 + 8041bde: 4a18 ldr r2, [pc, #96] ; (8041c40 ) + 8041be0: 693b ldr r3, [r7, #16] + 8041be2: 6713 str r3, [r2, #112] ; 0x70 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) - 8041be8: 4b16 ldr r3, [pc, #88] ; (8041c44 ) - 8041bea: 6f1b ldr r3, [r3, #112] ; 0x70 - 8041bec: f003 0301 and.w r3, r3, #1 - 8041bf0: 2b01 cmp r3, #1 - 8041bf2: d114 bne.n 8041c1e + 8041be4: 4b16 ldr r3, [pc, #88] ; (8041c40 ) + 8041be6: 6f1b ldr r3, [r3, #112] ; 0x70 + 8041be8: f003 0301 and.w r3, r3, #1 + 8041bec: 2b01 cmp r3, #1 + 8041bee: d114 bne.n 8041c1a { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8041bf4: f7fe ffde bl 8040bb4 - 8041bf8: 6178 str r0, [r7, #20] + 8041bf0: f7fe ffde bl 8040bb0 + 8041bf4: 6178 str r0, [r7, #20] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 8041bfa: e00a b.n 8041c12 + 8041bf6: e00a b.n 8041c0e { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - 8041bfc: f7fe ffda bl 8040bb4 - 8041c00: 4602 mov r2, r0 - 8041c02: 697b ldr r3, [r7, #20] - 8041c04: 1ad3 subs r3, r2, r3 - 8041c06: f241 3288 movw r2, #5000 ; 0x1388 - 8041c0a: 4293 cmp r3, r2 - 8041c0c: d901 bls.n 8041c12 + 8041bf8: f7fe ffda bl 8040bb0 + 8041bfc: 4602 mov r2, r0 + 8041bfe: 697b ldr r3, [r7, #20] + 8041c00: 1ad3 subs r3, r2, r3 + 8041c02: f241 3288 movw r2, #5000 ; 0x1388 + 8041c06: 4293 cmp r3, r2 + 8041c08: d901 bls.n 8041c0e { return HAL_TIMEOUT; - 8041c0e: 2303 movs r3, #3 - 8041c10: e351 b.n 80422b6 + 8041c0a: 2303 movs r3, #3 + 8041c0c: e351 b.n 80422b2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 8041c12: 4b0c ldr r3, [pc, #48] ; (8041c44 ) - 8041c14: 6f1b ldr r3, [r3, #112] ; 0x70 - 8041c16: f003 0302 and.w r3, r3, #2 - 8041c1a: 2b00 cmp r3, #0 - 8041c1c: d0ee beq.n 8041bfc + 8041c0e: 4b0c ldr r3, [pc, #48] ; (8041c40 ) + 8041c10: 6f1b ldr r3, [r3, #112] ; 0x70 + 8041c12: f003 0302 and.w r3, r3, #2 + 8041c16: 2b00 cmp r3, #0 + 8041c18: d0ee beq.n 8041bf8 } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - 8041c1e: 687b ldr r3, [r7, #4] - 8041c20: 6b1b ldr r3, [r3, #48] ; 0x30 - 8041c22: f403 7340 and.w r3, r3, #768 ; 0x300 - 8041c26: f5b3 7f40 cmp.w r3, #768 ; 0x300 - 8041c2a: d111 bne.n 8041c50 - 8041c2c: 4b05 ldr r3, [pc, #20] ; (8041c44 ) - 8041c2e: 689b ldr r3, [r3, #8] - 8041c30: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000 - 8041c34: 687b ldr r3, [r7, #4] - 8041c36: 6b19 ldr r1, [r3, #48] ; 0x30 - 8041c38: 4b04 ldr r3, [pc, #16] ; (8041c4c ) - 8041c3a: 400b ands r3, r1 - 8041c3c: 4901 ldr r1, [pc, #4] ; (8041c44 ) - 8041c3e: 4313 orrs r3, r2 - 8041c40: 608b str r3, [r1, #8] - 8041c42: e00b b.n 8041c5c - 8041c44: 40023800 .word 0x40023800 - 8041c48: 40007000 .word 0x40007000 - 8041c4c: 0ffffcff .word 0x0ffffcff - 8041c50: 4bb3 ldr r3, [pc, #716] ; (8041f20 ) - 8041c52: 689b ldr r3, [r3, #8] - 8041c54: 4ab2 ldr r2, [pc, #712] ; (8041f20 ) - 8041c56: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000 - 8041c5a: 6093 str r3, [r2, #8] - 8041c5c: 4bb0 ldr r3, [pc, #704] ; (8041f20 ) - 8041c5e: 6f1a ldr r2, [r3, #112] ; 0x70 - 8041c60: 687b ldr r3, [r7, #4] - 8041c62: 6b1b ldr r3, [r3, #48] ; 0x30 - 8041c64: f3c3 030b ubfx r3, r3, #0, #12 - 8041c68: 49ad ldr r1, [pc, #692] ; (8041f20 ) - 8041c6a: 4313 orrs r3, r2 - 8041c6c: 670b str r3, [r1, #112] ; 0x70 + 8041c1a: 687b ldr r3, [r7, #4] + 8041c1c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8041c1e: f403 7340 and.w r3, r3, #768 ; 0x300 + 8041c22: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 8041c26: d111 bne.n 8041c4c + 8041c28: 4b05 ldr r3, [pc, #20] ; (8041c40 ) + 8041c2a: 689b ldr r3, [r3, #8] + 8041c2c: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000 + 8041c30: 687b ldr r3, [r7, #4] + 8041c32: 6b19 ldr r1, [r3, #48] ; 0x30 + 8041c34: 4b04 ldr r3, [pc, #16] ; (8041c48 ) + 8041c36: 400b ands r3, r1 + 8041c38: 4901 ldr r1, [pc, #4] ; (8041c40 ) + 8041c3a: 4313 orrs r3, r2 + 8041c3c: 608b str r3, [r1, #8] + 8041c3e: e00b b.n 8041c58 + 8041c40: 40023800 .word 0x40023800 + 8041c44: 40007000 .word 0x40007000 + 8041c48: 0ffffcff .word 0x0ffffcff + 8041c4c: 4bb3 ldr r3, [pc, #716] ; (8041f1c ) + 8041c4e: 689b ldr r3, [r3, #8] + 8041c50: 4ab2 ldr r2, [pc, #712] ; (8041f1c ) + 8041c52: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000 + 8041c56: 6093 str r3, [r2, #8] + 8041c58: 4bb0 ldr r3, [pc, #704] ; (8041f1c ) + 8041c5a: 6f1a ldr r2, [r3, #112] ; 0x70 + 8041c5c: 687b ldr r3, [r7, #4] + 8041c5e: 6b1b ldr r3, [r3, #48] ; 0x30 + 8041c60: f3c3 030b ubfx r3, r3, #0, #12 + 8041c64: 49ad ldr r1, [pc, #692] ; (8041f1c ) + 8041c66: 4313 orrs r3, r2 + 8041c68: 670b str r3, [r1, #112] ; 0x70 } /*------------------------------------ TIM configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) - 8041c6e: 687b ldr r3, [r7, #4] - 8041c70: 681b ldr r3, [r3, #0] - 8041c72: f003 0310 and.w r3, r3, #16 - 8041c76: 2b00 cmp r3, #0 - 8041c78: d010 beq.n 8041c9c + 8041c6a: 687b ldr r3, [r7, #4] + 8041c6c: 681b ldr r3, [r3, #0] + 8041c6e: f003 0310 and.w r3, r3, #16 + 8041c72: 2b00 cmp r3, #0 + 8041c74: d010 beq.n 8041c98 { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); - 8041c7a: 4ba9 ldr r3, [pc, #676] ; (8041f20 ) - 8041c7c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c - 8041c80: 4aa7 ldr r2, [pc, #668] ; (8041f20 ) - 8041c82: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 - 8041c86: f8c2 308c str.w r3, [r2, #140] ; 0x8c - 8041c8a: 4ba5 ldr r3, [pc, #660] ; (8041f20 ) - 8041c8c: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c - 8041c90: 687b ldr r3, [r7, #4] - 8041c92: 6b9b ldr r3, [r3, #56] ; 0x38 - 8041c94: 49a2 ldr r1, [pc, #648] ; (8041f20 ) - 8041c96: 4313 orrs r3, r2 - 8041c98: f8c1 308c str.w r3, [r1, #140] ; 0x8c + 8041c76: 4ba9 ldr r3, [pc, #676] ; (8041f1c ) + 8041c78: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8041c7c: 4aa7 ldr r2, [pc, #668] ; (8041f1c ) + 8041c7e: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 8041c82: f8c2 308c str.w r3, [r2, #140] ; 0x8c + 8041c86: 4ba5 ldr r3, [pc, #660] ; (8041f1c ) + 8041c88: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c + 8041c8c: 687b ldr r3, [r7, #4] + 8041c8e: 6b9b ldr r3, [r3, #56] ; 0x38 + 8041c90: 49a2 ldr r1, [pc, #648] ; (8041f1c ) + 8041c92: 4313 orrs r3, r2 + 8041c94: f8c1 308c str.w r3, [r1, #140] ; 0x8c } /*-------------------------------------- I2C1 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) - 8041c9c: 687b ldr r3, [r7, #4] - 8041c9e: 681b ldr r3, [r3, #0] - 8041ca0: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 8041ca4: 2b00 cmp r3, #0 - 8041ca6: d00a beq.n 8041cbe + 8041c98: 687b ldr r3, [r7, #4] + 8041c9a: 681b ldr r3, [r3, #0] + 8041c9c: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8041ca0: 2b00 cmp r3, #0 + 8041ca2: d00a beq.n 8041cba { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); - 8041ca8: 4b9d ldr r3, [pc, #628] ; (8041f20 ) - 8041caa: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8041cae: f423 3240 bic.w r2, r3, #196608 ; 0x30000 - 8041cb2: 687b ldr r3, [r7, #4] - 8041cb4: 6e5b ldr r3, [r3, #100] ; 0x64 - 8041cb6: 499a ldr r1, [pc, #616] ; (8041f20 ) - 8041cb8: 4313 orrs r3, r2 - 8041cba: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8041ca4: 4b9d ldr r3, [pc, #628] ; (8041f1c ) + 8041ca6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8041caa: f423 3240 bic.w r2, r3, #196608 ; 0x30000 + 8041cae: 687b ldr r3, [r7, #4] + 8041cb0: 6e5b ldr r3, [r3, #100] ; 0x64 + 8041cb2: 499a ldr r1, [pc, #616] ; (8041f1c ) + 8041cb4: 4313 orrs r3, r2 + 8041cb6: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- I2C2 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) - 8041cbe: 687b ldr r3, [r7, #4] - 8041cc0: 681b ldr r3, [r3, #0] - 8041cc2: f403 4300 and.w r3, r3, #32768 ; 0x8000 - 8041cc6: 2b00 cmp r3, #0 - 8041cc8: d00a beq.n 8041ce0 + 8041cba: 687b ldr r3, [r7, #4] + 8041cbc: 681b ldr r3, [r3, #0] + 8041cbe: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 8041cc2: 2b00 cmp r3, #0 + 8041cc4: d00a beq.n 8041cdc { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); - 8041cca: 4b95 ldr r3, [pc, #596] ; (8041f20 ) - 8041ccc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8041cd0: f423 2240 bic.w r2, r3, #786432 ; 0xc0000 - 8041cd4: 687b ldr r3, [r7, #4] - 8041cd6: 6e9b ldr r3, [r3, #104] ; 0x68 - 8041cd8: 4991 ldr r1, [pc, #580] ; (8041f20 ) - 8041cda: 4313 orrs r3, r2 - 8041cdc: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8041cc6: 4b95 ldr r3, [pc, #596] ; (8041f1c ) + 8041cc8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8041ccc: f423 2240 bic.w r2, r3, #786432 ; 0xc0000 + 8041cd0: 687b ldr r3, [r7, #4] + 8041cd2: 6e9b ldr r3, [r3, #104] ; 0x68 + 8041cd4: 4991 ldr r1, [pc, #580] ; (8041f1c ) + 8041cd6: 4313 orrs r3, r2 + 8041cd8: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- I2C3 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) - 8041ce0: 687b ldr r3, [r7, #4] - 8041ce2: 681b ldr r3, [r3, #0] - 8041ce4: f403 3380 and.w r3, r3, #65536 ; 0x10000 - 8041ce8: 2b00 cmp r3, #0 - 8041cea: d00a beq.n 8041d02 + 8041cdc: 687b ldr r3, [r7, #4] + 8041cde: 681b ldr r3, [r3, #0] + 8041ce0: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8041ce4: 2b00 cmp r3, #0 + 8041ce6: d00a beq.n 8041cfe { /* Check the parameters */ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); - 8041cec: 4b8c ldr r3, [pc, #560] ; (8041f20 ) - 8041cee: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8041cf2: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 - 8041cf6: 687b ldr r3, [r7, #4] - 8041cf8: 6edb ldr r3, [r3, #108] ; 0x6c - 8041cfa: 4989 ldr r1, [pc, #548] ; (8041f20 ) - 8041cfc: 4313 orrs r3, r2 - 8041cfe: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8041ce8: 4b8c ldr r3, [pc, #560] ; (8041f1c ) + 8041cea: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8041cee: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 + 8041cf2: 687b ldr r3, [r7, #4] + 8041cf4: 6edb ldr r3, [r3, #108] ; 0x6c + 8041cf6: 4989 ldr r1, [pc, #548] ; (8041f1c ) + 8041cf8: 4313 orrs r3, r2 + 8041cfa: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- I2C4 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) - 8041d02: 687b ldr r3, [r7, #4] - 8041d04: 681b ldr r3, [r3, #0] - 8041d06: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 8041d0a: 2b00 cmp r3, #0 - 8041d0c: d00a beq.n 8041d24 + 8041cfe: 687b ldr r3, [r7, #4] + 8041d00: 681b ldr r3, [r3, #0] + 8041d02: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8041d06: 2b00 cmp r3, #0 + 8041d08: d00a beq.n 8041d20 { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); /* Configure the I2C4 clock source */ __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); - 8041d0e: 4b84 ldr r3, [pc, #528] ; (8041f20 ) - 8041d10: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8041d14: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 - 8041d18: 687b ldr r3, [r7, #4] - 8041d1a: 6f1b ldr r3, [r3, #112] ; 0x70 - 8041d1c: 4980 ldr r1, [pc, #512] ; (8041f20 ) - 8041d1e: 4313 orrs r3, r2 - 8041d20: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8041d0a: 4b84 ldr r3, [pc, #528] ; (8041f1c ) + 8041d0c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8041d10: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 + 8041d14: 687b ldr r3, [r7, #4] + 8041d16: 6f1b ldr r3, [r3, #112] ; 0x70 + 8041d18: 4980 ldr r1, [pc, #512] ; (8041f1c ) + 8041d1a: 4313 orrs r3, r2 + 8041d1c: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- USART1 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) - 8041d24: 687b ldr r3, [r7, #4] - 8041d26: 681b ldr r3, [r3, #0] - 8041d28: f003 0340 and.w r3, r3, #64 ; 0x40 - 8041d2c: 2b00 cmp r3, #0 - 8041d2e: d00a beq.n 8041d46 + 8041d20: 687b ldr r3, [r7, #4] + 8041d22: 681b ldr r3, [r3, #0] + 8041d24: f003 0340 and.w r3, r3, #64 ; 0x40 + 8041d28: 2b00 cmp r3, #0 + 8041d2a: d00a beq.n 8041d42 { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); - 8041d30: 4b7b ldr r3, [pc, #492] ; (8041f20 ) - 8041d32: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8041d36: f023 0203 bic.w r2, r3, #3 - 8041d3a: 687b ldr r3, [r7, #4] - 8041d3c: 6c5b ldr r3, [r3, #68] ; 0x44 - 8041d3e: 4978 ldr r1, [pc, #480] ; (8041f20 ) - 8041d40: 4313 orrs r3, r2 - 8041d42: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8041d2c: 4b7b ldr r3, [pc, #492] ; (8041f1c ) + 8041d2e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8041d32: f023 0203 bic.w r2, r3, #3 + 8041d36: 687b ldr r3, [r7, #4] + 8041d38: 6c5b ldr r3, [r3, #68] ; 0x44 + 8041d3a: 4978 ldr r1, [pc, #480] ; (8041f1c ) + 8041d3c: 4313 orrs r3, r2 + 8041d3e: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- USART2 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) - 8041d46: 687b ldr r3, [r7, #4] - 8041d48: 681b ldr r3, [r3, #0] - 8041d4a: f003 0380 and.w r3, r3, #128 ; 0x80 - 8041d4e: 2b00 cmp r3, #0 - 8041d50: d00a beq.n 8041d68 + 8041d42: 687b ldr r3, [r7, #4] + 8041d44: 681b ldr r3, [r3, #0] + 8041d46: f003 0380 and.w r3, r3, #128 ; 0x80 + 8041d4a: 2b00 cmp r3, #0 + 8041d4c: d00a beq.n 8041d64 { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); - 8041d52: 4b73 ldr r3, [pc, #460] ; (8041f20 ) - 8041d54: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8041d58: f023 020c bic.w r2, r3, #12 - 8041d5c: 687b ldr r3, [r7, #4] - 8041d5e: 6c9b ldr r3, [r3, #72] ; 0x48 - 8041d60: 496f ldr r1, [pc, #444] ; (8041f20 ) - 8041d62: 4313 orrs r3, r2 - 8041d64: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8041d4e: 4b73 ldr r3, [pc, #460] ; (8041f1c ) + 8041d50: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8041d54: f023 020c bic.w r2, r3, #12 + 8041d58: 687b ldr r3, [r7, #4] + 8041d5a: 6c9b ldr r3, [r3, #72] ; 0x48 + 8041d5c: 496f ldr r1, [pc, #444] ; (8041f1c ) + 8041d5e: 4313 orrs r3, r2 + 8041d60: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- USART3 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) - 8041d68: 687b ldr r3, [r7, #4] - 8041d6a: 681b ldr r3, [r3, #0] - 8041d6c: f403 7380 and.w r3, r3, #256 ; 0x100 - 8041d70: 2b00 cmp r3, #0 - 8041d72: d00a beq.n 8041d8a + 8041d64: 687b ldr r3, [r7, #4] + 8041d66: 681b ldr r3, [r3, #0] + 8041d68: f403 7380 and.w r3, r3, #256 ; 0x100 + 8041d6c: 2b00 cmp r3, #0 + 8041d6e: d00a beq.n 8041d86 { /* Check the parameters */ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); /* Configure the USART3 clock source */ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); - 8041d74: 4b6a ldr r3, [pc, #424] ; (8041f20 ) - 8041d76: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8041d7a: f023 0230 bic.w r2, r3, #48 ; 0x30 - 8041d7e: 687b ldr r3, [r7, #4] - 8041d80: 6cdb ldr r3, [r3, #76] ; 0x4c - 8041d82: 4967 ldr r1, [pc, #412] ; (8041f20 ) - 8041d84: 4313 orrs r3, r2 - 8041d86: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8041d70: 4b6a ldr r3, [pc, #424] ; (8041f1c ) + 8041d72: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8041d76: f023 0230 bic.w r2, r3, #48 ; 0x30 + 8041d7a: 687b ldr r3, [r7, #4] + 8041d7c: 6cdb ldr r3, [r3, #76] ; 0x4c + 8041d7e: 4967 ldr r1, [pc, #412] ; (8041f1c ) + 8041d80: 4313 orrs r3, r2 + 8041d82: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- UART4 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) - 8041d8a: 687b ldr r3, [r7, #4] - 8041d8c: 681b ldr r3, [r3, #0] - 8041d8e: f403 7300 and.w r3, r3, #512 ; 0x200 - 8041d92: 2b00 cmp r3, #0 - 8041d94: d00a beq.n 8041dac + 8041d86: 687b ldr r3, [r7, #4] + 8041d88: 681b ldr r3, [r3, #0] + 8041d8a: f403 7300 and.w r3, r3, #512 ; 0x200 + 8041d8e: 2b00 cmp r3, #0 + 8041d90: d00a beq.n 8041da8 { /* Check the parameters */ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); /* Configure the UART4 clock source */ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); - 8041d96: 4b62 ldr r3, [pc, #392] ; (8041f20 ) - 8041d98: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8041d9c: f023 02c0 bic.w r2, r3, #192 ; 0xc0 - 8041da0: 687b ldr r3, [r7, #4] - 8041da2: 6d1b ldr r3, [r3, #80] ; 0x50 - 8041da4: 495e ldr r1, [pc, #376] ; (8041f20 ) - 8041da6: 4313 orrs r3, r2 - 8041da8: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8041d92: 4b62 ldr r3, [pc, #392] ; (8041f1c ) + 8041d94: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8041d98: f023 02c0 bic.w r2, r3, #192 ; 0xc0 + 8041d9c: 687b ldr r3, [r7, #4] + 8041d9e: 6d1b ldr r3, [r3, #80] ; 0x50 + 8041da0: 495e ldr r1, [pc, #376] ; (8041f1c ) + 8041da2: 4313 orrs r3, r2 + 8041da4: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- UART5 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) - 8041dac: 687b ldr r3, [r7, #4] - 8041dae: 681b ldr r3, [r3, #0] - 8041db0: f403 6380 and.w r3, r3, #1024 ; 0x400 - 8041db4: 2b00 cmp r3, #0 - 8041db6: d00a beq.n 8041dce + 8041da8: 687b ldr r3, [r7, #4] + 8041daa: 681b ldr r3, [r3, #0] + 8041dac: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8041db0: 2b00 cmp r3, #0 + 8041db2: d00a beq.n 8041dca { /* Check the parameters */ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); /* Configure the UART5 clock source */ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); - 8041db8: 4b59 ldr r3, [pc, #356] ; (8041f20 ) - 8041dba: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8041dbe: f423 7240 bic.w r2, r3, #768 ; 0x300 - 8041dc2: 687b ldr r3, [r7, #4] - 8041dc4: 6d5b ldr r3, [r3, #84] ; 0x54 - 8041dc6: 4956 ldr r1, [pc, #344] ; (8041f20 ) - 8041dc8: 4313 orrs r3, r2 - 8041dca: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8041db4: 4b59 ldr r3, [pc, #356] ; (8041f1c ) + 8041db6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8041dba: f423 7240 bic.w r2, r3, #768 ; 0x300 + 8041dbe: 687b ldr r3, [r7, #4] + 8041dc0: 6d5b ldr r3, [r3, #84] ; 0x54 + 8041dc2: 4956 ldr r1, [pc, #344] ; (8041f1c ) + 8041dc4: 4313 orrs r3, r2 + 8041dc6: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- USART6 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) - 8041dce: 687b ldr r3, [r7, #4] - 8041dd0: 681b ldr r3, [r3, #0] - 8041dd2: f403 6300 and.w r3, r3, #2048 ; 0x800 - 8041dd6: 2b00 cmp r3, #0 - 8041dd8: d00a beq.n 8041df0 + 8041dca: 687b ldr r3, [r7, #4] + 8041dcc: 681b ldr r3, [r3, #0] + 8041dce: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8041dd2: 2b00 cmp r3, #0 + 8041dd4: d00a beq.n 8041dec { /* Check the parameters */ assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); /* Configure the USART6 clock source */ __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); - 8041dda: 4b51 ldr r3, [pc, #324] ; (8041f20 ) - 8041ddc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8041de0: f423 6240 bic.w r2, r3, #3072 ; 0xc00 - 8041de4: 687b ldr r3, [r7, #4] - 8041de6: 6d9b ldr r3, [r3, #88] ; 0x58 - 8041de8: 494d ldr r1, [pc, #308] ; (8041f20 ) - 8041dea: 4313 orrs r3, r2 - 8041dec: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8041dd6: 4b51 ldr r3, [pc, #324] ; (8041f1c ) + 8041dd8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8041ddc: f423 6240 bic.w r2, r3, #3072 ; 0xc00 + 8041de0: 687b ldr r3, [r7, #4] + 8041de2: 6d9b ldr r3, [r3, #88] ; 0x58 + 8041de4: 494d ldr r1, [pc, #308] ; (8041f1c ) + 8041de6: 4313 orrs r3, r2 + 8041de8: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- UART7 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) - 8041df0: 687b ldr r3, [r7, #4] - 8041df2: 681b ldr r3, [r3, #0] - 8041df4: f403 5380 and.w r3, r3, #4096 ; 0x1000 - 8041df8: 2b00 cmp r3, #0 - 8041dfa: d00a beq.n 8041e12 + 8041dec: 687b ldr r3, [r7, #4] + 8041dee: 681b ldr r3, [r3, #0] + 8041df0: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8041df4: 2b00 cmp r3, #0 + 8041df6: d00a beq.n 8041e0e { /* Check the parameters */ assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); /* Configure the UART7 clock source */ __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); - 8041dfc: 4b48 ldr r3, [pc, #288] ; (8041f20 ) - 8041dfe: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8041e02: f423 5240 bic.w r2, r3, #12288 ; 0x3000 - 8041e06: 687b ldr r3, [r7, #4] - 8041e08: 6ddb ldr r3, [r3, #92] ; 0x5c - 8041e0a: 4945 ldr r1, [pc, #276] ; (8041f20 ) - 8041e0c: 4313 orrs r3, r2 - 8041e0e: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8041df8: 4b48 ldr r3, [pc, #288] ; (8041f1c ) + 8041dfa: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8041dfe: f423 5240 bic.w r2, r3, #12288 ; 0x3000 + 8041e02: 687b ldr r3, [r7, #4] + 8041e04: 6ddb ldr r3, [r3, #92] ; 0x5c + 8041e06: 4945 ldr r1, [pc, #276] ; (8041f1c ) + 8041e08: 4313 orrs r3, r2 + 8041e0a: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- UART8 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) - 8041e12: 687b ldr r3, [r7, #4] - 8041e14: 681b ldr r3, [r3, #0] - 8041e16: f403 5300 and.w r3, r3, #8192 ; 0x2000 - 8041e1a: 2b00 cmp r3, #0 - 8041e1c: d00a beq.n 8041e34 + 8041e0e: 687b ldr r3, [r7, #4] + 8041e10: 681b ldr r3, [r3, #0] + 8041e12: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 8041e16: 2b00 cmp r3, #0 + 8041e18: d00a beq.n 8041e30 { /* Check the parameters */ assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); /* Configure the UART8 clock source */ __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); - 8041e1e: 4b40 ldr r3, [pc, #256] ; (8041f20 ) - 8041e20: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8041e24: f423 4240 bic.w r2, r3, #49152 ; 0xc000 - 8041e28: 687b ldr r3, [r7, #4] - 8041e2a: 6e1b ldr r3, [r3, #96] ; 0x60 - 8041e2c: 493c ldr r1, [pc, #240] ; (8041f20 ) - 8041e2e: 4313 orrs r3, r2 - 8041e30: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8041e1a: 4b40 ldr r3, [pc, #256] ; (8041f1c ) + 8041e1c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8041e20: f423 4240 bic.w r2, r3, #49152 ; 0xc000 + 8041e24: 687b ldr r3, [r7, #4] + 8041e26: 6e1b ldr r3, [r3, #96] ; 0x60 + 8041e28: 493c ldr r1, [pc, #240] ; (8041f1c ) + 8041e2a: 4313 orrs r3, r2 + 8041e2c: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*--------------------------------------- CEC Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) - 8041e34: 687b ldr r3, [r7, #4] - 8041e36: 681b ldr r3, [r3, #0] - 8041e38: f403 0380 and.w r3, r3, #4194304 ; 0x400000 - 8041e3c: 2b00 cmp r3, #0 - 8041e3e: d00a beq.n 8041e56 + 8041e30: 687b ldr r3, [r7, #4] + 8041e32: 681b ldr r3, [r3, #0] + 8041e34: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8041e38: 2b00 cmp r3, #0 + 8041e3a: d00a beq.n 8041e52 { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); - 8041e40: 4b37 ldr r3, [pc, #220] ; (8041f20 ) - 8041e42: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8041e46: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000 - 8041e4a: 687b ldr r3, [r7, #4] - 8041e4c: 6f9b ldr r3, [r3, #120] ; 0x78 - 8041e4e: 4934 ldr r1, [pc, #208] ; (8041f20 ) - 8041e50: 4313 orrs r3, r2 - 8041e52: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8041e3c: 4b37 ldr r3, [pc, #220] ; (8041f1c ) + 8041e3e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8041e42: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000 + 8041e46: 687b ldr r3, [r7, #4] + 8041e48: 6f9b ldr r3, [r3, #120] ; 0x78 + 8041e4a: 4934 ldr r1, [pc, #208] ; (8041f1c ) + 8041e4c: 4313 orrs r3, r2 + 8041e4e: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- CK48 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) - 8041e56: 687b ldr r3, [r7, #4] - 8041e58: 681b ldr r3, [r3, #0] - 8041e5a: f403 1300 and.w r3, r3, #2097152 ; 0x200000 - 8041e5e: 2b00 cmp r3, #0 - 8041e60: d011 beq.n 8041e86 + 8041e52: 687b ldr r3, [r7, #4] + 8041e54: 681b ldr r3, [r3, #0] + 8041e56: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8041e5a: 2b00 cmp r3, #0 + 8041e5c: d011 beq.n 8041e82 { /* Check the parameters */ assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); /* Configure the CLK48 source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); - 8041e62: 4b2f ldr r3, [pc, #188] ; (8041f20 ) - 8041e64: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8041e68: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000 - 8041e6c: 687b ldr r3, [r7, #4] - 8041e6e: 6fdb ldr r3, [r3, #124] ; 0x7c - 8041e70: 492b ldr r1, [pc, #172] ; (8041f20 ) - 8041e72: 4313 orrs r3, r2 - 8041e74: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8041e5e: 4b2f ldr r3, [pc, #188] ; (8041f1c ) + 8041e60: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8041e64: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000 + 8041e68: 687b ldr r3, [r7, #4] + 8041e6a: 6fdb ldr r3, [r3, #124] ; 0x7c + 8041e6c: 492b ldr r1, [pc, #172] ; (8041f1c ) + 8041e6e: 4313 orrs r3, r2 + 8041e70: f8c1 3090 str.w r3, [r1, #144] ; 0x90 /* Enable the PLLSAI when it's used as clock source for CK48 */ if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) - 8041e78: 687b ldr r3, [r7, #4] - 8041e7a: 6fdb ldr r3, [r3, #124] ; 0x7c - 8041e7c: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 - 8041e80: d101 bne.n 8041e86 + 8041e74: 687b ldr r3, [r7, #4] + 8041e76: 6fdb ldr r3, [r3, #124] ; 0x7c + 8041e78: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 + 8041e7c: d101 bne.n 8041e82 { pllsaiused = 1; - 8041e82: 2301 movs r3, #1 - 8041e84: 61bb str r3, [r7, #24] + 8041e7e: 2301 movs r3, #1 + 8041e80: 61bb str r3, [r7, #24] } } /*-------------------------------------- LTDC Configuration -----------------------------------*/ #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) - 8041e86: 687b ldr r3, [r7, #4] - 8041e88: 681b ldr r3, [r3, #0] - 8041e8a: f003 0308 and.w r3, r3, #8 - 8041e8e: 2b00 cmp r3, #0 - 8041e90: d001 beq.n 8041e96 + 8041e82: 687b ldr r3, [r7, #4] + 8041e84: 681b ldr r3, [r3, #0] + 8041e86: f003 0308 and.w r3, r3, #8 + 8041e8a: 2b00 cmp r3, #0 + 8041e8c: d001 beq.n 8041e92 { pllsaiused = 1; - 8041e92: 2301 movs r3, #1 - 8041e94: 61bb str r3, [r7, #24] + 8041e8e: 2301 movs r3, #1 + 8041e90: 61bb str r3, [r7, #24] } #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) - 8041e96: 687b ldr r3, [r7, #4] - 8041e98: 681b ldr r3, [r3, #0] - 8041e9a: f403 2380 and.w r3, r3, #262144 ; 0x40000 - 8041e9e: 2b00 cmp r3, #0 - 8041ea0: d00a beq.n 8041eb8 + 8041e92: 687b ldr r3, [r7, #4] + 8041e94: 681b ldr r3, [r3, #0] + 8041e96: f403 2380 and.w r3, r3, #262144 ; 0x40000 + 8041e9a: 2b00 cmp r3, #0 + 8041e9c: d00a beq.n 8041eb4 { /* Check the parameters */ assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); /* Configure the LTPIM1 clock source */ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); - 8041ea2: 4b1f ldr r3, [pc, #124] ; (8041f20 ) - 8041ea4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8041ea8: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000 - 8041eac: 687b ldr r3, [r7, #4] - 8041eae: 6f5b ldr r3, [r3, #116] ; 0x74 - 8041eb0: 491b ldr r1, [pc, #108] ; (8041f20 ) - 8041eb2: 4313 orrs r3, r2 - 8041eb4: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8041e9e: 4b1f ldr r3, [pc, #124] ; (8041f1c ) + 8041ea0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8041ea4: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000 + 8041ea8: 687b ldr r3, [r7, #4] + 8041eaa: 6f5b ldr r3, [r3, #116] ; 0x74 + 8041eac: 491b ldr r1, [pc, #108] ; (8041f1c ) + 8041eae: 4313 orrs r3, r2 + 8041eb0: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) - 8041eb8: 687b ldr r3, [r7, #4] - 8041eba: 681b ldr r3, [r3, #0] - 8041ebc: f403 0300 and.w r3, r3, #8388608 ; 0x800000 - 8041ec0: 2b00 cmp r3, #0 - 8041ec2: d00b beq.n 8041edc + 8041eb4: 687b ldr r3, [r7, #4] + 8041eb6: 681b ldr r3, [r3, #0] + 8041eb8: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 8041ebc: 2b00 cmp r3, #0 + 8041ebe: d00b beq.n 8041ed8 { /* Check the parameters */ assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); /* Configure the SDMMC1 clock source */ __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); - 8041ec4: 4b16 ldr r3, [pc, #88] ; (8041f20 ) - 8041ec6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8041eca: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000 - 8041ece: 687b ldr r3, [r7, #4] - 8041ed0: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 - 8041ed4: 4912 ldr r1, [pc, #72] ; (8041f20 ) - 8041ed6: 4313 orrs r3, r2 - 8041ed8: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8041ec0: 4b16 ldr r3, [pc, #88] ; (8041f1c ) + 8041ec2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8041ec6: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000 + 8041eca: 687b ldr r3, [r7, #4] + 8041ecc: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 8041ed0: 4912 ldr r1, [pc, #72] ; (8041f1c ) + 8041ed2: 4313 orrs r3, r2 + 8041ed4: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) - 8041edc: 687b ldr r3, [r7, #4] - 8041ede: 681b ldr r3, [r3, #0] - 8041ee0: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 - 8041ee4: 2b00 cmp r3, #0 - 8041ee6: d00b beq.n 8041f00 + 8041ed8: 687b ldr r3, [r7, #4] + 8041eda: 681b ldr r3, [r3, #0] + 8041edc: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 + 8041ee0: 2b00 cmp r3, #0 + 8041ee2: d00b beq.n 8041efc { /* Check the parameters */ assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); /* Configure the SDMMC2 clock source */ __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); - 8041ee8: 4b0d ldr r3, [pc, #52] ; (8041f20 ) - 8041eea: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8041eee: f023 5200 bic.w r2, r3, #536870912 ; 0x20000000 - 8041ef2: 687b ldr r3, [r7, #4] - 8041ef4: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 8041ef8: 4909 ldr r1, [pc, #36] ; (8041f20 ) - 8041efa: 4313 orrs r3, r2 - 8041efc: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8041ee4: 4b0d ldr r3, [pc, #52] ; (8041f1c ) + 8041ee6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8041eea: f023 5200 bic.w r2, r3, #536870912 ; 0x20000000 + 8041eee: 687b ldr r3, [r7, #4] + 8041ef0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8041ef4: 4909 ldr r1, [pc, #36] ; (8041f1c ) + 8041ef6: 4313 orrs r3, r2 + 8041ef8: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*------------------------------------- DFSDM1 Configuration -------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) - 8041f00: 687b ldr r3, [r7, #4] - 8041f02: 681b ldr r3, [r3, #0] - 8041f04: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 - 8041f08: 2b00 cmp r3, #0 - 8041f0a: d00f beq.n 8041f2c + 8041efc: 687b ldr r3, [r7, #4] + 8041efe: 681b ldr r3, [r3, #0] + 8041f00: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 8041f04: 2b00 cmp r3, #0 + 8041f06: d00f beq.n 8041f28 { /* Check the parameters */ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); /* Configure the DFSDM1 interface clock source */ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); - 8041f0c: 4b04 ldr r3, [pc, #16] ; (8041f20 ) - 8041f0e: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c - 8041f12: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000 - 8041f16: 687b ldr r3, [r7, #4] - 8041f18: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8041f1c: e002 b.n 8041f24 - 8041f1e: bf00 nop - 8041f20: 40023800 .word 0x40023800 - 8041f24: 4986 ldr r1, [pc, #536] ; (8042140 ) - 8041f26: 4313 orrs r3, r2 - 8041f28: f8c1 308c str.w r3, [r1, #140] ; 0x8c + 8041f08: 4b04 ldr r3, [pc, #16] ; (8041f1c ) + 8041f0a: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8041f0e: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000 + 8041f12: 687b ldr r3, [r7, #4] + 8041f14: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8041f18: e002 b.n 8041f20 + 8041f1a: bf00 nop + 8041f1c: 40023800 .word 0x40023800 + 8041f20: 4986 ldr r1, [pc, #536] ; (804213c ) + 8041f22: 4313 orrs r3, r2 + 8041f24: f8c1 308c str.w r3, [r1, #140] ; 0x8c } /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) - 8041f2c: 687b ldr r3, [r7, #4] - 8041f2e: 681b ldr r3, [r3, #0] - 8041f30: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8041f34: 2b00 cmp r3, #0 - 8041f36: d00b beq.n 8041f50 + 8041f28: 687b ldr r3, [r7, #4] + 8041f2a: 681b ldr r3, [r3, #0] + 8041f2c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8041f30: 2b00 cmp r3, #0 + 8041f32: d00b beq.n 8041f4c { /* Check the parameters */ assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); /* Configure the DFSDM interface clock source */ __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); - 8041f38: 4b81 ldr r3, [pc, #516] ; (8042140 ) - 8041f3a: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c - 8041f3e: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000 - 8041f42: 687b ldr r3, [r7, #4] - 8041f44: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c - 8041f48: 497d ldr r1, [pc, #500] ; (8042140 ) - 8041f4a: 4313 orrs r3, r2 - 8041f4c: f8c1 308c str.w r3, [r1, #140] ; 0x8c + 8041f34: 4b81 ldr r3, [pc, #516] ; (804213c ) + 8041f36: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8041f3a: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000 + 8041f3e: 687b ldr r3, [r7, #4] + 8041f40: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8041f44: 497d ldr r1, [pc, #500] ; (804213c ) + 8041f46: 4313 orrs r3, r2 + 8041f48: f8c1 308c str.w r3, [r1, #140] ; 0x8c } #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */ if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) - 8041f50: 69fb ldr r3, [r7, #28] - 8041f52: 2b01 cmp r3, #1 - 8041f54: d006 beq.n 8041f64 - 8041f56: 687b ldr r3, [r7, #4] - 8041f58: 681b ldr r3, [r3, #0] - 8041f5a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 8041f5e: 2b00 cmp r3, #0 - 8041f60: f000 80d6 beq.w 8042110 + 8041f4c: 69fb ldr r3, [r7, #28] + 8041f4e: 2b01 cmp r3, #1 + 8041f50: d006 beq.n 8041f60 + 8041f52: 687b ldr r3, [r7, #4] + 8041f54: 681b ldr r3, [r3, #0] + 8041f56: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8041f5a: 2b00 cmp r3, #0 + 8041f5c: f000 80d6 beq.w 804210c { /* Disable the PLLI2S */ __HAL_RCC_PLLI2S_DISABLE(); - 8041f64: 4b76 ldr r3, [pc, #472] ; (8042140 ) - 8041f66: 681b ldr r3, [r3, #0] - 8041f68: 4a75 ldr r2, [pc, #468] ; (8042140 ) - 8041f6a: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 - 8041f6e: 6013 str r3, [r2, #0] + 8041f60: 4b76 ldr r3, [pc, #472] ; (804213c ) + 8041f62: 681b ldr r3, [r3, #0] + 8041f64: 4a75 ldr r2, [pc, #468] ; (804213c ) + 8041f66: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 + 8041f6a: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8041f70: f7fe fe20 bl 8040bb4 - 8041f74: 6178 str r0, [r7, #20] + 8041f6c: f7fe fe20 bl 8040bb0 + 8041f70: 6178 str r0, [r7, #20] /* Wait till PLLI2S is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) - 8041f76: e008 b.n 8041f8a + 8041f72: e008 b.n 8041f86 { if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) - 8041f78: f7fe fe1c bl 8040bb4 - 8041f7c: 4602 mov r2, r0 - 8041f7e: 697b ldr r3, [r7, #20] - 8041f80: 1ad3 subs r3, r2, r3 - 8041f82: 2b64 cmp r3, #100 ; 0x64 - 8041f84: d901 bls.n 8041f8a + 8041f74: f7fe fe1c bl 8040bb0 + 8041f78: 4602 mov r2, r0 + 8041f7a: 697b ldr r3, [r7, #20] + 8041f7c: 1ad3 subs r3, r2, r3 + 8041f7e: 2b64 cmp r3, #100 ; 0x64 + 8041f80: d901 bls.n 8041f86 { /* return in case of Timeout detected */ return HAL_TIMEOUT; - 8041f86: 2303 movs r3, #3 - 8041f88: e195 b.n 80422b6 + 8041f82: 2303 movs r3, #3 + 8041f84: e195 b.n 80422b2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) - 8041f8a: 4b6d ldr r3, [pc, #436] ; (8042140 ) - 8041f8c: 681b ldr r3, [r3, #0] - 8041f8e: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 - 8041f92: 2b00 cmp r3, #0 - 8041f94: d1f0 bne.n 8041f78 + 8041f86: 4b6d ldr r3, [pc, #436] ; (804213c ) + 8041f88: 681b ldr r3, [r3, #0] + 8041f8a: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 8041f8e: 2b00 cmp r3, #0 + 8041f90: d1f0 bne.n 8041f74 /* check for common PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) - 8041f96: 687b ldr r3, [r7, #4] - 8041f98: 681b ldr r3, [r3, #0] - 8041f9a: f003 0301 and.w r3, r3, #1 - 8041f9e: 2b00 cmp r3, #0 - 8041fa0: d021 beq.n 8041fe6 - 8041fa2: 687b ldr r3, [r7, #4] - 8041fa4: 6b5b ldr r3, [r3, #52] ; 0x34 - 8041fa6: 2b00 cmp r3, #0 - 8041fa8: d11d bne.n 8041fe6 + 8041f92: 687b ldr r3, [r7, #4] + 8041f94: 681b ldr r3, [r3, #0] + 8041f96: f003 0301 and.w r3, r3, #1 + 8041f9a: 2b00 cmp r3, #0 + 8041f9c: d021 beq.n 8041fe2 + 8041f9e: 687b ldr r3, [r7, #4] + 8041fa0: 6b5b ldr r3, [r3, #52] ; 0x34 + 8041fa2: 2b00 cmp r3, #0 + 8041fa4: d11d bne.n 8041fe2 { /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); - 8041faa: 4b65 ldr r3, [pc, #404] ; (8042140 ) - 8041fac: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 8041fb0: 0c1b lsrs r3, r3, #16 - 8041fb2: f003 0303 and.w r3, r3, #3 - 8041fb6: 613b str r3, [r7, #16] + 8041fa6: 4b65 ldr r3, [pc, #404] ; (804213c ) + 8041fa8: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8041fac: 0c1b lsrs r3, r3, #16 + 8041fae: f003 0303 and.w r3, r3, #3 + 8041fb2: 613b str r3, [r7, #16] tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); - 8041fb8: 4b61 ldr r3, [pc, #388] ; (8042140 ) - 8041fba: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 8041fbe: 0e1b lsrs r3, r3, #24 - 8041fc0: f003 030f and.w r3, r3, #15 - 8041fc4: 60fb str r3, [r7, #12] + 8041fb4: 4b61 ldr r3, [pc, #388] ; (804213c ) + 8041fb6: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8041fba: 0e1b lsrs r3, r3, #24 + 8041fbc: f003 030f and.w r3, r3, #15 + 8041fc0: 60fb str r3, [r7, #12] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR); - 8041fc6: 687b ldr r3, [r7, #4] - 8041fc8: 685b ldr r3, [r3, #4] - 8041fca: 019a lsls r2, r3, #6 - 8041fcc: 693b ldr r3, [r7, #16] - 8041fce: 041b lsls r3, r3, #16 - 8041fd0: 431a orrs r2, r3 - 8041fd2: 68fb ldr r3, [r7, #12] - 8041fd4: 061b lsls r3, r3, #24 - 8041fd6: 431a orrs r2, r3 - 8041fd8: 687b ldr r3, [r7, #4] - 8041fda: 689b ldr r3, [r3, #8] - 8041fdc: 071b lsls r3, r3, #28 - 8041fde: 4958 ldr r1, [pc, #352] ; (8042140 ) - 8041fe0: 4313 orrs r3, r2 - 8041fe2: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + 8041fc2: 687b ldr r3, [r7, #4] + 8041fc4: 685b ldr r3, [r3, #4] + 8041fc6: 019a lsls r2, r3, #6 + 8041fc8: 693b ldr r3, [r7, #16] + 8041fca: 041b lsls r3, r3, #16 + 8041fcc: 431a orrs r2, r3 + 8041fce: 68fb ldr r3, [r7, #12] + 8041fd0: 061b lsls r3, r3, #24 + 8041fd2: 431a orrs r2, r3 + 8041fd4: 687b ldr r3, [r7, #4] + 8041fd6: 689b ldr r3, [r3, #8] + 8041fd8: 071b lsls r3, r3, #28 + 8041fda: 4958 ldr r1, [pc, #352] ; (804213c ) + 8041fdc: 4313 orrs r3, r2 + 8041fde: f8c1 3084 str.w r3, [r1, #132] ; 0x84 } /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || - 8041fe6: 687b ldr r3, [r7, #4] - 8041fe8: 681b ldr r3, [r3, #0] - 8041fea: f403 2300 and.w r3, r3, #524288 ; 0x80000 - 8041fee: 2b00 cmp r3, #0 - 8041ff0: d004 beq.n 8041ffc - 8041ff2: 687b ldr r3, [r7, #4] - 8041ff4: 6bdb ldr r3, [r3, #60] ; 0x3c - 8041ff6: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 - 8041ffa: d00a beq.n 8042012 + 8041fe2: 687b ldr r3, [r7, #4] + 8041fe4: 681b ldr r3, [r3, #0] + 8041fe6: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 8041fea: 2b00 cmp r3, #0 + 8041fec: d004 beq.n 8041ff8 + 8041fee: 687b ldr r3, [r7, #4] + 8041ff0: 6bdb ldr r3, [r3, #60] ; 0x3c + 8041ff2: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 8041ff6: d00a beq.n 804200e ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) - 8041ffc: 687b ldr r3, [r7, #4] - 8041ffe: 681b ldr r3, [r3, #0] - 8042000: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 8041ff8: 687b ldr r3, [r7, #4] + 8041ffa: 681b ldr r3, [r3, #0] + 8041ffc: f403 1380 and.w r3, r3, #1048576 ; 0x100000 if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || - 8042004: 2b00 cmp r3, #0 - 8042006: d02e beq.n 8042066 + 8042000: 2b00 cmp r3, #0 + 8042002: d02e beq.n 8042062 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) - 8042008: 687b ldr r3, [r7, #4] - 804200a: 6c1b ldr r3, [r3, #64] ; 0x40 - 804200c: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 - 8042010: d129 bne.n 8042066 + 8042004: 687b ldr r3, [r7, #4] + 8042006: 6c1b ldr r3, [r3, #64] ; 0x40 + 8042008: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 804200c: d129 bne.n 8042062 assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Check for PLLI2S/DIVQ parameters */ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); - 8042012: 4b4b ldr r3, [pc, #300] ; (8042140 ) - 8042014: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 8042018: 0c1b lsrs r3, r3, #16 - 804201a: f003 0303 and.w r3, r3, #3 - 804201e: 613b str r3, [r7, #16] + 804200e: 4b4b ldr r3, [pc, #300] ; (804213c ) + 8042010: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8042014: 0c1b lsrs r3, r3, #16 + 8042016: f003 0303 and.w r3, r3, #3 + 804201a: 613b str r3, [r7, #16] tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - 8042020: 4b47 ldr r3, [pc, #284] ; (8042140 ) - 8042022: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 8042026: 0f1b lsrs r3, r3, #28 - 8042028: f003 0307 and.w r3, r3, #7 - 804202c: 60fb str r3, [r7, #12] + 804201c: 4b47 ldr r3, [pc, #284] ; (804213c ) + 804201e: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8042022: 0f1b lsrs r3, r3, #28 + 8042024: f003 0307 and.w r3, r3, #7 + 8042028: 60fb str r3, [r7, #12] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); - 804202e: 687b ldr r3, [r7, #4] - 8042030: 685b ldr r3, [r3, #4] - 8042032: 019a lsls r2, r3, #6 - 8042034: 693b ldr r3, [r7, #16] - 8042036: 041b lsls r3, r3, #16 - 8042038: 431a orrs r2, r3 - 804203a: 687b ldr r3, [r7, #4] - 804203c: 68db ldr r3, [r3, #12] - 804203e: 061b lsls r3, r3, #24 - 8042040: 431a orrs r2, r3 - 8042042: 68fb ldr r3, [r7, #12] - 8042044: 071b lsls r3, r3, #28 - 8042046: 493e ldr r1, [pc, #248] ; (8042140 ) - 8042048: 4313 orrs r3, r2 - 804204a: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + 804202a: 687b ldr r3, [r7, #4] + 804202c: 685b ldr r3, [r3, #4] + 804202e: 019a lsls r2, r3, #6 + 8042030: 693b ldr r3, [r7, #16] + 8042032: 041b lsls r3, r3, #16 + 8042034: 431a orrs r2, r3 + 8042036: 687b ldr r3, [r7, #4] + 8042038: 68db ldr r3, [r3, #12] + 804203a: 061b lsls r3, r3, #24 + 804203c: 431a orrs r2, r3 + 804203e: 68fb ldr r3, [r7, #12] + 8042040: 071b lsls r3, r3, #28 + 8042042: 493e ldr r1, [pc, #248] ; (804213c ) + 8042044: 4313 orrs r3, r2 + 8042046: f8c1 3084 str.w r3, [r1, #132] ; 0x84 /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); - 804204e: 4b3c ldr r3, [pc, #240] ; (8042140 ) - 8042050: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c - 8042054: f023 021f bic.w r2, r3, #31 - 8042058: 687b ldr r3, [r7, #4] - 804205a: 6a5b ldr r3, [r3, #36] ; 0x24 - 804205c: 3b01 subs r3, #1 - 804205e: 4938 ldr r1, [pc, #224] ; (8042140 ) - 8042060: 4313 orrs r3, r2 - 8042062: f8c1 308c str.w r3, [r1, #140] ; 0x8c + 804204a: 4b3c ldr r3, [pc, #240] ; (804213c ) + 804204c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8042050: f023 021f bic.w r2, r3, #31 + 8042054: 687b ldr r3, [r7, #4] + 8042056: 6a5b ldr r3, [r3, #36] ; 0x24 + 8042058: 3b01 subs r3, #1 + 804205a: 4938 ldr r1, [pc, #224] ; (804213c ) + 804205c: 4313 orrs r3, r2 + 804205e: f8c1 308c str.w r3, [r1, #140] ; 0x8c } /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) - 8042066: 687b ldr r3, [r7, #4] - 8042068: 681b ldr r3, [r3, #0] - 804206a: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 - 804206e: 2b00 cmp r3, #0 - 8042070: d01d beq.n 80420ae + 8042062: 687b ldr r3, [r7, #4] + 8042064: 681b ldr r3, [r3, #0] + 8042066: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 804206a: 2b00 cmp r3, #0 + 804206c: d01d beq.n 80420aa { /* check for Parameters */ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); - 8042072: 4b33 ldr r3, [pc, #204] ; (8042140 ) - 8042074: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 8042078: 0e1b lsrs r3, r3, #24 - 804207a: f003 030f and.w r3, r3, #15 - 804207e: 613b str r3, [r7, #16] + 804206e: 4b33 ldr r3, [pc, #204] ; (804213c ) + 8042070: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8042074: 0e1b lsrs r3, r3, #24 + 8042076: f003 030f and.w r3, r3, #15 + 804207a: 613b str r3, [r7, #16] tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - 8042080: 4b2f ldr r3, [pc, #188] ; (8042140 ) - 8042082: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 8042086: 0f1b lsrs r3, r3, #28 - 8042088: f003 0307 and.w r3, r3, #7 - 804208c: 60fb str r3, [r7, #12] + 804207c: 4b2f ldr r3, [pc, #188] ; (804213c ) + 804207e: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8042082: 0f1b lsrs r3, r3, #28 + 8042084: f003 0307 and.w r3, r3, #7 + 8042088: 60fb str r3, [r7, #12] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1); - 804208e: 687b ldr r3, [r7, #4] - 8042090: 685b ldr r3, [r3, #4] - 8042092: 019a lsls r2, r3, #6 - 8042094: 687b ldr r3, [r7, #4] - 8042096: 691b ldr r3, [r3, #16] - 8042098: 041b lsls r3, r3, #16 - 804209a: 431a orrs r2, r3 - 804209c: 693b ldr r3, [r7, #16] - 804209e: 061b lsls r3, r3, #24 - 80420a0: 431a orrs r2, r3 - 80420a2: 68fb ldr r3, [r7, #12] - 80420a4: 071b lsls r3, r3, #28 - 80420a6: 4926 ldr r1, [pc, #152] ; (8042140 ) - 80420a8: 4313 orrs r3, r2 - 80420aa: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + 804208a: 687b ldr r3, [r7, #4] + 804208c: 685b ldr r3, [r3, #4] + 804208e: 019a lsls r2, r3, #6 + 8042090: 687b ldr r3, [r7, #4] + 8042092: 691b ldr r3, [r3, #16] + 8042094: 041b lsls r3, r3, #16 + 8042096: 431a orrs r2, r3 + 8042098: 693b ldr r3, [r7, #16] + 804209a: 061b lsls r3, r3, #24 + 804209c: 431a orrs r2, r3 + 804209e: 68fb ldr r3, [r7, #12] + 80420a0: 071b lsls r3, r3, #28 + 80420a2: 4926 ldr r1, [pc, #152] ; (804213c ) + 80420a4: 4313 orrs r3, r2 + 80420a6: f8c1 3084 str.w r3, [r1, #132] ; 0x84 } /*----------------- In Case of PLLI2S is just selected -----------------*/ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) - 80420ae: 687b ldr r3, [r7, #4] - 80420b0: 681b ldr r3, [r3, #0] - 80420b2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 80420b6: 2b00 cmp r3, #0 - 80420b8: d011 beq.n 80420de + 80420aa: 687b ldr r3, [r7, #4] + 80420ac: 681b ldr r3, [r3, #0] + 80420ae: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 80420b2: 2b00 cmp r3, #0 + 80420b4: d011 beq.n 80420da assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); - 80420ba: 687b ldr r3, [r7, #4] - 80420bc: 685b ldr r3, [r3, #4] - 80420be: 019a lsls r2, r3, #6 - 80420c0: 687b ldr r3, [r7, #4] - 80420c2: 691b ldr r3, [r3, #16] - 80420c4: 041b lsls r3, r3, #16 - 80420c6: 431a orrs r2, r3 - 80420c8: 687b ldr r3, [r7, #4] - 80420ca: 68db ldr r3, [r3, #12] - 80420cc: 061b lsls r3, r3, #24 - 80420ce: 431a orrs r2, r3 - 80420d0: 687b ldr r3, [r7, #4] - 80420d2: 689b ldr r3, [r3, #8] - 80420d4: 071b lsls r3, r3, #28 - 80420d6: 491a ldr r1, [pc, #104] ; (8042140 ) - 80420d8: 4313 orrs r3, r2 - 80420da: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + 80420b6: 687b ldr r3, [r7, #4] + 80420b8: 685b ldr r3, [r3, #4] + 80420ba: 019a lsls r2, r3, #6 + 80420bc: 687b ldr r3, [r7, #4] + 80420be: 691b ldr r3, [r3, #16] + 80420c0: 041b lsls r3, r3, #16 + 80420c2: 431a orrs r2, r3 + 80420c4: 687b ldr r3, [r7, #4] + 80420c6: 68db ldr r3, [r3, #12] + 80420c8: 061b lsls r3, r3, #24 + 80420ca: 431a orrs r2, r3 + 80420cc: 687b ldr r3, [r7, #4] + 80420ce: 689b ldr r3, [r3, #8] + 80420d0: 071b lsls r3, r3, #28 + 80420d2: 491a ldr r1, [pc, #104] ; (804213c ) + 80420d4: 4313 orrs r3, r2 + 80420d6: f8c1 3084 str.w r3, [r1, #132] ; 0x84 } /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); - 80420de: 4b18 ldr r3, [pc, #96] ; (8042140 ) - 80420e0: 681b ldr r3, [r3, #0] - 80420e2: 4a17 ldr r2, [pc, #92] ; (8042140 ) - 80420e4: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 - 80420e8: 6013 str r3, [r2, #0] + 80420da: 4b18 ldr r3, [pc, #96] ; (804213c ) + 80420dc: 681b ldr r3, [r3, #0] + 80420de: 4a17 ldr r2, [pc, #92] ; (804213c ) + 80420e0: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 + 80420e4: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 80420ea: f7fe fd63 bl 8040bb4 - 80420ee: 6178 str r0, [r7, #20] + 80420e6: f7fe fd63 bl 8040bb0 + 80420ea: 6178 str r0, [r7, #20] /* Wait till PLLI2S is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) - 80420f0: e008 b.n 8042104 + 80420ec: e008 b.n 8042100 { if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) - 80420f2: f7fe fd5f bl 8040bb4 - 80420f6: 4602 mov r2, r0 - 80420f8: 697b ldr r3, [r7, #20] - 80420fa: 1ad3 subs r3, r2, r3 - 80420fc: 2b64 cmp r3, #100 ; 0x64 - 80420fe: d901 bls.n 8042104 + 80420ee: f7fe fd5f bl 8040bb0 + 80420f2: 4602 mov r2, r0 + 80420f4: 697b ldr r3, [r7, #20] + 80420f6: 1ad3 subs r3, r2, r3 + 80420f8: 2b64 cmp r3, #100 ; 0x64 + 80420fa: d901 bls.n 8042100 { /* return in case of Timeout detected */ return HAL_TIMEOUT; - 8042100: 2303 movs r3, #3 - 8042102: e0d8 b.n 80422b6 + 80420fc: 2303 movs r3, #3 + 80420fe: e0d8 b.n 80422b2 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) - 8042104: 4b0e ldr r3, [pc, #56] ; (8042140 ) - 8042106: 681b ldr r3, [r3, #0] - 8042108: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 - 804210c: 2b00 cmp r3, #0 - 804210e: d0f0 beq.n 80420f2 + 8042100: 4b0e ldr r3, [pc, #56] ; (804213c ) + 8042102: 681b ldr r3, [r3, #0] + 8042104: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 8042108: 2b00 cmp r3, #0 + 804210a: d0f0 beq.n 80420ee } } /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ if(pllsaiused == 1) - 8042110: 69bb ldr r3, [r7, #24] - 8042112: 2b01 cmp r3, #1 - 8042114: f040 80ce bne.w 80422b4 + 804210c: 69bb ldr r3, [r7, #24] + 804210e: 2b01 cmp r3, #1 + 8042110: f040 80ce bne.w 80422b0 { /* Disable PLLSAI Clock */ __HAL_RCC_PLLSAI_DISABLE(); - 8042118: 4b09 ldr r3, [pc, #36] ; (8042140 ) - 804211a: 681b ldr r3, [r3, #0] - 804211c: 4a08 ldr r2, [pc, #32] ; (8042140 ) - 804211e: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 - 8042122: 6013 str r3, [r2, #0] + 8042114: 4b09 ldr r3, [pc, #36] ; (804213c ) + 8042116: 681b ldr r3, [r3, #0] + 8042118: 4a08 ldr r2, [pc, #32] ; (804213c ) + 804211a: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 804211e: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8042124: f7fe fd46 bl 8040bb4 - 8042128: 6178 str r0, [r7, #20] + 8042120: f7fe fd46 bl 8040bb0 + 8042124: 6178 str r0, [r7, #20] /* Wait till PLLSAI is disabled */ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) - 804212a: e00b b.n 8042144 + 8042126: e00b b.n 8042140 { if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) - 804212c: f7fe fd42 bl 8040bb4 - 8042130: 4602 mov r2, r0 - 8042132: 697b ldr r3, [r7, #20] - 8042134: 1ad3 subs r3, r2, r3 - 8042136: 2b64 cmp r3, #100 ; 0x64 - 8042138: d904 bls.n 8042144 + 8042128: f7fe fd42 bl 8040bb0 + 804212c: 4602 mov r2, r0 + 804212e: 697b ldr r3, [r7, #20] + 8042130: 1ad3 subs r3, r2, r3 + 8042132: 2b64 cmp r3, #100 ; 0x64 + 8042134: d904 bls.n 8042140 { /* return in case of Timeout detected */ return HAL_TIMEOUT; - 804213a: 2303 movs r3, #3 - 804213c: e0bb b.n 80422b6 - 804213e: bf00 nop - 8042140: 40023800 .word 0x40023800 + 8042136: 2303 movs r3, #3 + 8042138: e0bb b.n 80422b2 + 804213a: bf00 nop + 804213c: 40023800 .word 0x40023800 while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) - 8042144: 4b5e ldr r3, [pc, #376] ; (80422c0 ) - 8042146: 681b ldr r3, [r3, #0] - 8042148: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 - 804214c: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 - 8042150: d0ec beq.n 804212c + 8042140: 4b5e ldr r3, [pc, #376] ; (80422bc ) + 8042142: 681b ldr r3, [r3, #0] + 8042144: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 + 8042148: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 + 804214c: d0ec beq.n 8042128 /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ - 8042152: 687b ldr r3, [r7, #4] - 8042154: 681b ldr r3, [r3, #0] - 8042156: f403 2300 and.w r3, r3, #524288 ; 0x80000 - 804215a: 2b00 cmp r3, #0 - 804215c: d003 beq.n 8042166 - 804215e: 687b ldr r3, [r7, #4] - 8042160: 6bdb ldr r3, [r3, #60] ; 0x3c - 8042162: 2b00 cmp r3, #0 - 8042164: d009 beq.n 804217a + 804214e: 687b ldr r3, [r7, #4] + 8042150: 681b ldr r3, [r3, #0] + 8042152: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 8042156: 2b00 cmp r3, #0 + 8042158: d003 beq.n 8042162 + 804215a: 687b ldr r3, [r7, #4] + 804215c: 6bdb ldr r3, [r3, #60] ; 0x3c + 804215e: 2b00 cmp r3, #0 + 8042160: d009 beq.n 8042176 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) - 8042166: 687b ldr r3, [r7, #4] - 8042168: 681b ldr r3, [r3, #0] - 804216a: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 8042162: 687b ldr r3, [r7, #4] + 8042164: 681b ldr r3, [r3, #0] + 8042166: f403 1380 and.w r3, r3, #1048576 ; 0x100000 if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ - 804216e: 2b00 cmp r3, #0 - 8042170: d02e beq.n 80421d0 + 804216a: 2b00 cmp r3, #0 + 804216c: d02e beq.n 80421cc ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) - 8042172: 687b ldr r3, [r7, #4] - 8042174: 6c1b ldr r3, [r3, #64] ; 0x40 - 8042176: 2b00 cmp r3, #0 - 8042178: d12a bne.n 80421d0 + 804216e: 687b ldr r3, [r7, #4] + 8042170: 6c1b ldr r3, [r3, #64] ; 0x40 + 8042172: 2b00 cmp r3, #0 + 8042174: d12a bne.n 80421cc assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); /* check for PLLSAI/DIVQ Parameter */ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); - 804217a: 4b51 ldr r3, [pc, #324] ; (80422c0 ) - 804217c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8042180: 0c1b lsrs r3, r3, #16 - 8042182: f003 0303 and.w r3, r3, #3 - 8042186: 613b str r3, [r7, #16] + 8042176: 4b51 ldr r3, [pc, #324] ; (80422bc ) + 8042178: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 804217c: 0c1b lsrs r3, r3, #16 + 804217e: f003 0303 and.w r3, r3, #3 + 8042182: 613b str r3, [r7, #16] tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); - 8042188: 4b4d ldr r3, [pc, #308] ; (80422c0 ) - 804218a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 804218e: 0f1b lsrs r3, r3, #28 - 8042190: f003 0307 and.w r3, r3, #7 - 8042194: 60fb str r3, [r7, #12] + 8042184: 4b4d ldr r3, [pc, #308] ; (80422bc ) + 8042186: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 804218a: 0f1b lsrs r3, r3, #28 + 804218c: f003 0307 and.w r3, r3, #7 + 8042190: 60fb str r3, [r7, #12] /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); - 8042196: 687b ldr r3, [r7, #4] - 8042198: 695b ldr r3, [r3, #20] - 804219a: 019a lsls r2, r3, #6 - 804219c: 693b ldr r3, [r7, #16] - 804219e: 041b lsls r3, r3, #16 - 80421a0: 431a orrs r2, r3 - 80421a2: 687b ldr r3, [r7, #4] - 80421a4: 699b ldr r3, [r3, #24] - 80421a6: 061b lsls r3, r3, #24 - 80421a8: 431a orrs r2, r3 - 80421aa: 68fb ldr r3, [r7, #12] - 80421ac: 071b lsls r3, r3, #28 - 80421ae: 4944 ldr r1, [pc, #272] ; (80422c0 ) - 80421b0: 4313 orrs r3, r2 - 80421b2: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + 8042192: 687b ldr r3, [r7, #4] + 8042194: 695b ldr r3, [r3, #20] + 8042196: 019a lsls r2, r3, #6 + 8042198: 693b ldr r3, [r7, #16] + 804219a: 041b lsls r3, r3, #16 + 804219c: 431a orrs r2, r3 + 804219e: 687b ldr r3, [r7, #4] + 80421a0: 699b ldr r3, [r3, #24] + 80421a2: 061b lsls r3, r3, #24 + 80421a4: 431a orrs r2, r3 + 80421a6: 68fb ldr r3, [r7, #12] + 80421a8: 071b lsls r3, r3, #28 + 80421aa: 4944 ldr r1, [pc, #272] ; (80422bc ) + 80421ac: 4313 orrs r3, r2 + 80421ae: f8c1 3088 str.w r3, [r1, #136] ; 0x88 /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); - 80421b6: 4b42 ldr r3, [pc, #264] ; (80422c0 ) - 80421b8: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c - 80421bc: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00 - 80421c0: 687b ldr r3, [r7, #4] - 80421c2: 6a9b ldr r3, [r3, #40] ; 0x28 - 80421c4: 3b01 subs r3, #1 - 80421c6: 021b lsls r3, r3, #8 - 80421c8: 493d ldr r1, [pc, #244] ; (80422c0 ) - 80421ca: 4313 orrs r3, r2 - 80421cc: f8c1 308c str.w r3, [r1, #140] ; 0x8c + 80421b2: 4b42 ldr r3, [pc, #264] ; (80422bc ) + 80421b4: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 80421b8: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00 + 80421bc: 687b ldr r3, [r7, #4] + 80421be: 6a9b ldr r3, [r3, #40] ; 0x28 + 80421c0: 3b01 subs r3, #1 + 80421c2: 021b lsls r3, r3, #8 + 80421c4: 493d ldr r1, [pc, #244] ; (80422bc ) + 80421c6: 4313 orrs r3, r2 + 80421c8: f8c1 308c str.w r3, [r1, #140] ; 0x8c } /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ /* In Case of PLLI2S is selected as source clock for CK48 */ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) - 80421d0: 687b ldr r3, [r7, #4] - 80421d2: 681b ldr r3, [r3, #0] - 80421d4: f403 1300 and.w r3, r3, #2097152 ; 0x200000 - 80421d8: 2b00 cmp r3, #0 - 80421da: d022 beq.n 8042222 - 80421dc: 687b ldr r3, [r7, #4] - 80421de: 6fdb ldr r3, [r3, #124] ; 0x7c - 80421e0: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 - 80421e4: d11d bne.n 8042222 + 80421cc: 687b ldr r3, [r7, #4] + 80421ce: 681b ldr r3, [r3, #0] + 80421d0: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 80421d4: 2b00 cmp r3, #0 + 80421d6: d022 beq.n 804221e + 80421d8: 687b ldr r3, [r7, #4] + 80421da: 6fdb ldr r3, [r3, #124] ; 0x7c + 80421dc: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 + 80421e0: d11d bne.n 804221e { /* check for Parameters */ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); - 80421e6: 4b36 ldr r3, [pc, #216] ; (80422c0 ) - 80421e8: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 80421ec: 0e1b lsrs r3, r3, #24 - 80421ee: f003 030f and.w r3, r3, #15 - 80421f2: 613b str r3, [r7, #16] + 80421e2: 4b36 ldr r3, [pc, #216] ; (80422bc ) + 80421e4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 80421e8: 0e1b lsrs r3, r3, #24 + 80421ea: f003 030f and.w r3, r3, #15 + 80421ee: 613b str r3, [r7, #16] tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); - 80421f4: 4b32 ldr r3, [pc, #200] ; (80422c0 ) - 80421f6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 80421fa: 0f1b lsrs r3, r3, #28 - 80421fc: f003 0307 and.w r3, r3, #7 - 8042200: 60fb str r3, [r7, #12] + 80421f0: 4b32 ldr r3, [pc, #200] ; (80422bc ) + 80421f2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 80421f6: 0f1b lsrs r3, r3, #28 + 80421f8: f003 0307 and.w r3, r3, #7 + 80421fc: 60fb str r3, [r7, #12] /* Configure the PLLSAI division factors */ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1); - 8042202: 687b ldr r3, [r7, #4] - 8042204: 695b ldr r3, [r3, #20] - 8042206: 019a lsls r2, r3, #6 - 8042208: 687b ldr r3, [r7, #4] - 804220a: 6a1b ldr r3, [r3, #32] - 804220c: 041b lsls r3, r3, #16 - 804220e: 431a orrs r2, r3 - 8042210: 693b ldr r3, [r7, #16] - 8042212: 061b lsls r3, r3, #24 - 8042214: 431a orrs r2, r3 - 8042216: 68fb ldr r3, [r7, #12] - 8042218: 071b lsls r3, r3, #28 - 804221a: 4929 ldr r1, [pc, #164] ; (80422c0 ) - 804221c: 4313 orrs r3, r2 - 804221e: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + 80421fe: 687b ldr r3, [r7, #4] + 8042200: 695b ldr r3, [r3, #20] + 8042202: 019a lsls r2, r3, #6 + 8042204: 687b ldr r3, [r7, #4] + 8042206: 6a1b ldr r3, [r3, #32] + 8042208: 041b lsls r3, r3, #16 + 804220a: 431a orrs r2, r3 + 804220c: 693b ldr r3, [r7, #16] + 804220e: 061b lsls r3, r3, #24 + 8042210: 431a orrs r2, r3 + 8042212: 68fb ldr r3, [r7, #12] + 8042214: 071b lsls r3, r3, #28 + 8042216: 4929 ldr r1, [pc, #164] ; (80422bc ) + 8042218: 4313 orrs r3, r2 + 804221a: f8c1 3088 str.w r3, [r1, #136] ; 0x88 } #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) /*---------------------------- LTDC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) - 8042222: 687b ldr r3, [r7, #4] - 8042224: 681b ldr r3, [r3, #0] - 8042226: f003 0308 and.w r3, r3, #8 - 804222a: 2b00 cmp r3, #0 - 804222c: d028 beq.n 8042280 + 804221e: 687b ldr r3, [r7, #4] + 8042220: 681b ldr r3, [r3, #0] + 8042222: f003 0308 and.w r3, r3, #8 + 8042226: 2b00 cmp r3, #0 + 8042228: d028 beq.n 804227c { assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); - 804222e: 4b24 ldr r3, [pc, #144] ; (80422c0 ) - 8042230: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8042234: 0e1b lsrs r3, r3, #24 - 8042236: f003 030f and.w r3, r3, #15 - 804223a: 613b str r3, [r7, #16] + 804222a: 4b24 ldr r3, [pc, #144] ; (80422bc ) + 804222c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8042230: 0e1b lsrs r3, r3, #24 + 8042232: f003 030f and.w r3, r3, #15 + 8042236: 613b str r3, [r7, #16] tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); - 804223c: 4b20 ldr r3, [pc, #128] ; (80422c0 ) - 804223e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8042242: 0c1b lsrs r3, r3, #16 - 8042244: f003 0303 and.w r3, r3, #3 - 8042248: 60fb str r3, [r7, #12] + 8042238: 4b20 ldr r3, [pc, #128] ; (80422bc ) + 804223a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 804223e: 0c1b lsrs r3, r3, #16 + 8042240: f003 0303 and.w r3, r3, #3 + 8042244: 60fb str r3, [r7, #12] /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR); - 804224a: 687b ldr r3, [r7, #4] - 804224c: 695b ldr r3, [r3, #20] - 804224e: 019a lsls r2, r3, #6 - 8042250: 68fb ldr r3, [r7, #12] - 8042252: 041b lsls r3, r3, #16 - 8042254: 431a orrs r2, r3 - 8042256: 693b ldr r3, [r7, #16] - 8042258: 061b lsls r3, r3, #24 - 804225a: 431a orrs r2, r3 - 804225c: 687b ldr r3, [r7, #4] - 804225e: 69db ldr r3, [r3, #28] - 8042260: 071b lsls r3, r3, #28 - 8042262: 4917 ldr r1, [pc, #92] ; (80422c0 ) - 8042264: 4313 orrs r3, r2 - 8042266: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + 8042246: 687b ldr r3, [r7, #4] + 8042248: 695b ldr r3, [r3, #20] + 804224a: 019a lsls r2, r3, #6 + 804224c: 68fb ldr r3, [r7, #12] + 804224e: 041b lsls r3, r3, #16 + 8042250: 431a orrs r2, r3 + 8042252: 693b ldr r3, [r7, #16] + 8042254: 061b lsls r3, r3, #24 + 8042256: 431a orrs r2, r3 + 8042258: 687b ldr r3, [r7, #4] + 804225a: 69db ldr r3, [r3, #28] + 804225c: 071b lsls r3, r3, #28 + 804225e: 4917 ldr r1, [pc, #92] ; (80422bc ) + 8042260: 4313 orrs r3, r2 + 8042262: f8c1 3088 str.w r3, [r1, #136] ; 0x88 /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); - 804226a: 4b15 ldr r3, [pc, #84] ; (80422c0 ) - 804226c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c - 8042270: f423 3240 bic.w r2, r3, #196608 ; 0x30000 - 8042274: 687b ldr r3, [r7, #4] - 8042276: 6adb ldr r3, [r3, #44] ; 0x2c - 8042278: 4911 ldr r1, [pc, #68] ; (80422c0 ) - 804227a: 4313 orrs r3, r2 - 804227c: f8c1 308c str.w r3, [r1, #140] ; 0x8c + 8042266: 4b15 ldr r3, [pc, #84] ; (80422bc ) + 8042268: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 804226c: f423 3240 bic.w r2, r3, #196608 ; 0x30000 + 8042270: 687b ldr r3, [r7, #4] + 8042272: 6adb ldr r3, [r3, #44] ; 0x2c + 8042274: 4911 ldr r1, [pc, #68] ; (80422bc ) + 8042276: 4313 orrs r3, r2 + 8042278: f8c1 308c str.w r3, [r1, #140] ; 0x8c } #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); - 8042280: 4b0f ldr r3, [pc, #60] ; (80422c0 ) - 8042282: 681b ldr r3, [r3, #0] - 8042284: 4a0e ldr r2, [pc, #56] ; (80422c0 ) - 8042286: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 804228a: 6013 str r3, [r2, #0] + 804227c: 4b0f ldr r3, [pc, #60] ; (80422bc ) + 804227e: 681b ldr r3, [r3, #0] + 8042280: 4a0e ldr r2, [pc, #56] ; (80422bc ) + 8042282: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8042286: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 804228c: f7fe fc92 bl 8040bb4 - 8042290: 6178 str r0, [r7, #20] + 8042288: f7fe fc92 bl 8040bb0 + 804228c: 6178 str r0, [r7, #20] /* Wait till PLLSAI is ready */ while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) - 8042292: e008 b.n 80422a6 + 804228e: e008 b.n 80422a2 { if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) - 8042294: f7fe fc8e bl 8040bb4 - 8042298: 4602 mov r2, r0 - 804229a: 697b ldr r3, [r7, #20] - 804229c: 1ad3 subs r3, r2, r3 - 804229e: 2b64 cmp r3, #100 ; 0x64 - 80422a0: d901 bls.n 80422a6 + 8042290: f7fe fc8e bl 8040bb0 + 8042294: 4602 mov r2, r0 + 8042296: 697b ldr r3, [r7, #20] + 8042298: 1ad3 subs r3, r2, r3 + 804229a: 2b64 cmp r3, #100 ; 0x64 + 804229c: d901 bls.n 80422a2 { /* return in case of Timeout detected */ return HAL_TIMEOUT; - 80422a2: 2303 movs r3, #3 - 80422a4: e007 b.n 80422b6 + 804229e: 2303 movs r3, #3 + 80422a0: e007 b.n 80422b2 while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) - 80422a6: 4b06 ldr r3, [pc, #24] ; (80422c0 ) - 80422a8: 681b ldr r3, [r3, #0] - 80422aa: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 - 80422ae: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 - 80422b2: d1ef bne.n 8042294 + 80422a2: 4b06 ldr r3, [pc, #24] ; (80422bc ) + 80422a4: 681b ldr r3, [r3, #0] + 80422a6: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 + 80422aa: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 + 80422ae: d1ef bne.n 8042290 } } } return HAL_OK; - 80422b4: 2300 movs r3, #0 + 80422b0: 2300 movs r3, #0 } - 80422b6: 4618 mov r0, r3 - 80422b8: 3720 adds r7, #32 - 80422ba: 46bd mov sp, r7 - 80422bc: bd80 pop {r7, pc} - 80422be: bf00 nop - 80422c0: 40023800 .word 0x40023800 - -080422c4 : + 80422b2: 4618 mov r0, r3 + 80422b4: 3720 adds r7, #32 + 80422b6: 46bd mov sp, r7 + 80422b8: bd80 pop {r7, pc} + 80422ba: bf00 nop + 80422bc: 40023800 .word 0x40023800 + +080422c0 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { - 80422c4: b580 push {r7, lr} - 80422c6: b082 sub sp, #8 - 80422c8: af00 add r7, sp, #0 - 80422ca: 6078 str r0, [r7, #4] + 80422c0: b580 push {r7, lr} + 80422c2: b082 sub sp, #8 + 80422c4: af00 add r7, sp, #0 + 80422c6: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) - 80422cc: 687b ldr r3, [r7, #4] - 80422ce: 2b00 cmp r3, #0 - 80422d0: d101 bne.n 80422d6 + 80422c8: 687b ldr r3, [r7, #4] + 80422ca: 2b00 cmp r3, #0 + 80422cc: d101 bne.n 80422d2 { return HAL_ERROR; - 80422d2: 2301 movs r3, #1 - 80422d4: e040 b.n 8042358 + 80422ce: 2301 movs r3, #1 + 80422d0: e040 b.n 8042354 { /* Check the parameters */ assert_param(IS_UART_INSTANCE(huart->Instance)); } if (huart->gState == HAL_UART_STATE_RESET) - 80422d6: 687b ldr r3, [r7, #4] - 80422d8: 6f9b ldr r3, [r3, #120] ; 0x78 - 80422da: 2b00 cmp r3, #0 - 80422dc: d106 bne.n 80422ec + 80422d2: 687b ldr r3, [r7, #4] + 80422d4: 6f9b ldr r3, [r3, #120] ; 0x78 + 80422d6: 2b00 cmp r3, #0 + 80422d8: d106 bne.n 80422e8 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - 80422de: 687b ldr r3, [r7, #4] - 80422e0: 2200 movs r2, #0 - 80422e2: f883 2074 strb.w r2, [r3, #116] ; 0x74 + 80422da: 687b ldr r3, [r7, #4] + 80422dc: 2200 movs r2, #0 + 80422de: f883 2074 strb.w r2, [r3, #116] ; 0x74 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); - 80422e6: 6878 ldr r0, [r7, #4] - 80422e8: f7fe fac2 bl 8040870 + 80422e2: 6878 ldr r0, [r7, #4] + 80422e4: f7fe fac2 bl 804086c #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; - 80422ec: 687b ldr r3, [r7, #4] - 80422ee: 2224 movs r2, #36 ; 0x24 - 80422f0: 679a str r2, [r3, #120] ; 0x78 + 80422e8: 687b ldr r3, [r7, #4] + 80422ea: 2224 movs r2, #36 ; 0x24 + 80422ec: 679a str r2, [r3, #120] ; 0x78 __HAL_UART_DISABLE(huart); - 80422f2: 687b ldr r3, [r7, #4] - 80422f4: 681b ldr r3, [r3, #0] - 80422f6: 681a ldr r2, [r3, #0] - 80422f8: 687b ldr r3, [r7, #4] - 80422fa: 681b ldr r3, [r3, #0] - 80422fc: f022 0201 bic.w r2, r2, #1 - 8042300: 601a str r2, [r3, #0] + 80422ee: 687b ldr r3, [r7, #4] + 80422f0: 681b ldr r3, [r3, #0] + 80422f2: 681a ldr r2, [r3, #0] + 80422f4: 687b ldr r3, [r7, #4] + 80422f6: 681b ldr r3, [r3, #0] + 80422f8: f022 0201 bic.w r2, r2, #1 + 80422fc: 601a str r2, [r3, #0] /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) - 8042302: 6878 ldr r0, [r7, #4] - 8042304: f000 f8c0 bl 8042488 - 8042308: 4603 mov r3, r0 - 804230a: 2b01 cmp r3, #1 - 804230c: d101 bne.n 8042312 + 80422fe: 6878 ldr r0, [r7, #4] + 8042300: f000 f8c0 bl 8042484 + 8042304: 4603 mov r3, r0 + 8042306: 2b01 cmp r3, #1 + 8042308: d101 bne.n 804230e { return HAL_ERROR; - 804230e: 2301 movs r3, #1 - 8042310: e022 b.n 8042358 + 804230a: 2301 movs r3, #1 + 804230c: e022 b.n 8042354 } if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - 8042312: 687b ldr r3, [r7, #4] - 8042314: 6a5b ldr r3, [r3, #36] ; 0x24 - 8042316: 2b00 cmp r3, #0 - 8042318: d002 beq.n 8042320 + 804230e: 687b ldr r3, [r7, #4] + 8042310: 6a5b ldr r3, [r3, #36] ; 0x24 + 8042312: 2b00 cmp r3, #0 + 8042314: d002 beq.n 804231c { UART_AdvFeatureConfig(huart); - 804231a: 6878 ldr r0, [r7, #4] - 804231c: f000 fb16 bl 804294c + 8042316: 6878 ldr r0, [r7, #4] + 8042318: f000 fb16 bl 8042948 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - 8042320: 687b ldr r3, [r7, #4] - 8042322: 681b ldr r3, [r3, #0] - 8042324: 685a ldr r2, [r3, #4] - 8042326: 687b ldr r3, [r7, #4] - 8042328: 681b ldr r3, [r3, #0] - 804232a: f422 4290 bic.w r2, r2, #18432 ; 0x4800 - 804232e: 605a str r2, [r3, #4] + 804231c: 687b ldr r3, [r7, #4] + 804231e: 681b ldr r3, [r3, #0] + 8042320: 685a ldr r2, [r3, #4] + 8042322: 687b ldr r3, [r7, #4] + 8042324: 681b ldr r3, [r3, #0] + 8042326: f422 4290 bic.w r2, r2, #18432 ; 0x4800 + 804232a: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - 8042330: 687b ldr r3, [r7, #4] - 8042332: 681b ldr r3, [r3, #0] - 8042334: 689a ldr r2, [r3, #8] - 8042336: 687b ldr r3, [r7, #4] - 8042338: 681b ldr r3, [r3, #0] - 804233a: f022 022a bic.w r2, r2, #42 ; 0x2a - 804233e: 609a str r2, [r3, #8] + 804232c: 687b ldr r3, [r7, #4] + 804232e: 681b ldr r3, [r3, #0] + 8042330: 689a ldr r2, [r3, #8] + 8042332: 687b ldr r3, [r7, #4] + 8042334: 681b ldr r3, [r3, #0] + 8042336: f022 022a bic.w r2, r2, #42 ; 0x2a + 804233a: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); - 8042340: 687b ldr r3, [r7, #4] - 8042342: 681b ldr r3, [r3, #0] - 8042344: 681a ldr r2, [r3, #0] - 8042346: 687b ldr r3, [r7, #4] - 8042348: 681b ldr r3, [r3, #0] - 804234a: f042 0201 orr.w r2, r2, #1 - 804234e: 601a str r2, [r3, #0] + 804233c: 687b ldr r3, [r7, #4] + 804233e: 681b ldr r3, [r3, #0] + 8042340: 681a ldr r2, [r3, #0] + 8042342: 687b ldr r3, [r7, #4] + 8042344: 681b ldr r3, [r3, #0] + 8042346: f042 0201 orr.w r2, r2, #1 + 804234a: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); - 8042350: 6878 ldr r0, [r7, #4] - 8042352: f000 fb9d bl 8042a90 - 8042356: 4603 mov r3, r0 + 804234c: 6878 ldr r0, [r7, #4] + 804234e: f000 fb9d bl 8042a8c + 8042352: 4603 mov r3, r0 } - 8042358: 4618 mov r0, r3 - 804235a: 3708 adds r7, #8 - 804235c: 46bd mov sp, r7 - 804235e: bd80 pop {r7, pc} + 8042354: 4618 mov r0, r3 + 8042356: 3708 adds r7, #8 + 8042358: 46bd mov sp, r7 + 804235a: bd80 pop {r7, pc} -08042360 : +0804235c : * @param Size Amount of data elements (u8 or u16) to be sent. * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - 8042360: b580 push {r7, lr} - 8042362: b08a sub sp, #40 ; 0x28 - 8042364: af02 add r7, sp, #8 - 8042366: 60f8 str r0, [r7, #12] - 8042368: 60b9 str r1, [r7, #8] - 804236a: 603b str r3, [r7, #0] - 804236c: 4613 mov r3, r2 - 804236e: 80fb strh r3, [r7, #6] + 804235c: b580 push {r7, lr} + 804235e: b08a sub sp, #40 ; 0x28 + 8042360: af02 add r7, sp, #8 + 8042362: 60f8 str r0, [r7, #12] + 8042364: 60b9 str r1, [r7, #8] + 8042366: 603b str r3, [r7, #0] + 8042368: 4613 mov r3, r2 + 804236a: 80fb strh r3, [r7, #6] uint8_t *pdata8bits; uint16_t *pdata16bits; uint32_t tickstart; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) - 8042370: 68fb ldr r3, [r7, #12] - 8042372: 6f9b ldr r3, [r3, #120] ; 0x78 - 8042374: 2b20 cmp r3, #32 - 8042376: f040 8081 bne.w 804247c + 804236c: 68fb ldr r3, [r7, #12] + 804236e: 6f9b ldr r3, [r3, #120] ; 0x78 + 8042370: 2b20 cmp r3, #32 + 8042372: f040 8081 bne.w 8042478 { if ((pData == NULL) || (Size == 0U)) - 804237a: 68bb ldr r3, [r7, #8] - 804237c: 2b00 cmp r3, #0 - 804237e: d002 beq.n 8042386 - 8042380: 88fb ldrh r3, [r7, #6] - 8042382: 2b00 cmp r3, #0 - 8042384: d101 bne.n 804238a + 8042376: 68bb ldr r3, [r7, #8] + 8042378: 2b00 cmp r3, #0 + 804237a: d002 beq.n 8042382 + 804237c: 88fb ldrh r3, [r7, #6] + 804237e: 2b00 cmp r3, #0 + 8042380: d101 bne.n 8042386 { return HAL_ERROR; - 8042386: 2301 movs r3, #1 - 8042388: e079 b.n 804247e + 8042382: 2301 movs r3, #1 + 8042384: e079 b.n 804247a } __HAL_LOCK(huart); - 804238a: 68fb ldr r3, [r7, #12] - 804238c: f893 3074 ldrb.w r3, [r3, #116] ; 0x74 - 8042390: 2b01 cmp r3, #1 - 8042392: d101 bne.n 8042398 - 8042394: 2302 movs r3, #2 - 8042396: e072 b.n 804247e - 8042398: 68fb ldr r3, [r7, #12] - 804239a: 2201 movs r2, #1 - 804239c: f883 2074 strb.w r2, [r3, #116] ; 0x74 + 8042386: 68fb ldr r3, [r7, #12] + 8042388: f893 3074 ldrb.w r3, [r3, #116] ; 0x74 + 804238c: 2b01 cmp r3, #1 + 804238e: d101 bne.n 8042394 + 8042390: 2302 movs r3, #2 + 8042392: e072 b.n 804247a + 8042394: 68fb ldr r3, [r7, #12] + 8042396: 2201 movs r2, #1 + 8042398: f883 2074 strb.w r2, [r3, #116] ; 0x74 huart->ErrorCode = HAL_UART_ERROR_NONE; - 80423a0: 68fb ldr r3, [r7, #12] - 80423a2: 2200 movs r2, #0 - 80423a4: f8c3 2080 str.w r2, [r3, #128] ; 0x80 + 804239c: 68fb ldr r3, [r7, #12] + 804239e: 2200 movs r2, #0 + 80423a0: f8c3 2080 str.w r2, [r3, #128] ; 0x80 huart->gState = HAL_UART_STATE_BUSY_TX; - 80423a8: 68fb ldr r3, [r7, #12] - 80423aa: 2221 movs r2, #33 ; 0x21 - 80423ac: 679a str r2, [r3, #120] ; 0x78 + 80423a4: 68fb ldr r3, [r7, #12] + 80423a6: 2221 movs r2, #33 ; 0x21 + 80423a8: 679a str r2, [r3, #120] ; 0x78 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - 80423ae: f7fe fc01 bl 8040bb4 - 80423b2: 6178 str r0, [r7, #20] + 80423aa: f7fe fc01 bl 8040bb0 + 80423ae: 6178 str r0, [r7, #20] huart->TxXferSize = Size; - 80423b4: 68fb ldr r3, [r7, #12] - 80423b6: 88fa ldrh r2, [r7, #6] - 80423b8: f8a3 2050 strh.w r2, [r3, #80] ; 0x50 + 80423b0: 68fb ldr r3, [r7, #12] + 80423b2: 88fa ldrh r2, [r7, #6] + 80423b4: f8a3 2050 strh.w r2, [r3, #80] ; 0x50 huart->TxXferCount = Size; - 80423bc: 68fb ldr r3, [r7, #12] - 80423be: 88fa ldrh r2, [r7, #6] - 80423c0: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 + 80423b8: 68fb ldr r3, [r7, #12] + 80423ba: 88fa ldrh r2, [r7, #6] + 80423bc: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - 80423c4: 68fb ldr r3, [r7, #12] - 80423c6: 689b ldr r3, [r3, #8] - 80423c8: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 - 80423cc: d108 bne.n 80423e0 - 80423ce: 68fb ldr r3, [r7, #12] - 80423d0: 691b ldr r3, [r3, #16] - 80423d2: 2b00 cmp r3, #0 - 80423d4: d104 bne.n 80423e0 + 80423c0: 68fb ldr r3, [r7, #12] + 80423c2: 689b ldr r3, [r3, #8] + 80423c4: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 80423c8: d108 bne.n 80423dc + 80423ca: 68fb ldr r3, [r7, #12] + 80423cc: 691b ldr r3, [r3, #16] + 80423ce: 2b00 cmp r3, #0 + 80423d0: d104 bne.n 80423dc { pdata8bits = NULL; - 80423d6: 2300 movs r3, #0 - 80423d8: 61fb str r3, [r7, #28] + 80423d2: 2300 movs r3, #0 + 80423d4: 61fb str r3, [r7, #28] pdata16bits = (uint16_t *) pData; - 80423da: 68bb ldr r3, [r7, #8] - 80423dc: 61bb str r3, [r7, #24] - 80423de: e003 b.n 80423e8 + 80423d6: 68bb ldr r3, [r7, #8] + 80423d8: 61bb str r3, [r7, #24] + 80423da: e003 b.n 80423e4 } else { pdata8bits = pData; - 80423e0: 68bb ldr r3, [r7, #8] - 80423e2: 61fb str r3, [r7, #28] + 80423dc: 68bb ldr r3, [r7, #8] + 80423de: 61fb str r3, [r7, #28] pdata16bits = NULL; - 80423e4: 2300 movs r3, #0 - 80423e6: 61bb str r3, [r7, #24] + 80423e0: 2300 movs r3, #0 + 80423e2: 61bb str r3, [r7, #24] } __HAL_UNLOCK(huart); - 80423e8: 68fb ldr r3, [r7, #12] - 80423ea: 2200 movs r2, #0 - 80423ec: f883 2074 strb.w r2, [r3, #116] ; 0x74 + 80423e4: 68fb ldr r3, [r7, #12] + 80423e6: 2200 movs r2, #0 + 80423e8: f883 2074 strb.w r2, [r3, #116] ; 0x74 while (huart->TxXferCount > 0U) - 80423f0: e02c b.n 804244c + 80423ec: e02c b.n 8042448 { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - 80423f2: 683b ldr r3, [r7, #0] - 80423f4: 9300 str r3, [sp, #0] - 80423f6: 697b ldr r3, [r7, #20] - 80423f8: 2200 movs r2, #0 - 80423fa: 2180 movs r1, #128 ; 0x80 - 80423fc: 68f8 ldr r0, [r7, #12] - 80423fe: f000 fb90 bl 8042b22 - 8042402: 4603 mov r3, r0 - 8042404: 2b00 cmp r3, #0 - 8042406: d001 beq.n 804240c + 80423ee: 683b ldr r3, [r7, #0] + 80423f0: 9300 str r3, [sp, #0] + 80423f2: 697b ldr r3, [r7, #20] + 80423f4: 2200 movs r2, #0 + 80423f6: 2180 movs r1, #128 ; 0x80 + 80423f8: 68f8 ldr r0, [r7, #12] + 80423fa: f000 fb90 bl 8042b1e + 80423fe: 4603 mov r3, r0 + 8042400: 2b00 cmp r3, #0 + 8042402: d001 beq.n 8042408 { return HAL_TIMEOUT; - 8042408: 2303 movs r3, #3 - 804240a: e038 b.n 804247e + 8042404: 2303 movs r3, #3 + 8042406: e038 b.n 804247a } if (pdata8bits == NULL) - 804240c: 69fb ldr r3, [r7, #28] - 804240e: 2b00 cmp r3, #0 - 8042410: d10b bne.n 804242a + 8042408: 69fb ldr r3, [r7, #28] + 804240a: 2b00 cmp r3, #0 + 804240c: d10b bne.n 8042426 { huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); - 8042412: 69bb ldr r3, [r7, #24] - 8042414: 881b ldrh r3, [r3, #0] - 8042416: 461a mov r2, r3 - 8042418: 68fb ldr r3, [r7, #12] - 804241a: 681b ldr r3, [r3, #0] - 804241c: f3c2 0208 ubfx r2, r2, #0, #9 - 8042420: 629a str r2, [r3, #40] ; 0x28 + 804240e: 69bb ldr r3, [r7, #24] + 8042410: 881b ldrh r3, [r3, #0] + 8042412: 461a mov r2, r3 + 8042414: 68fb ldr r3, [r7, #12] + 8042416: 681b ldr r3, [r3, #0] + 8042418: f3c2 0208 ubfx r2, r2, #0, #9 + 804241c: 629a str r2, [r3, #40] ; 0x28 pdata16bits++; - 8042422: 69bb ldr r3, [r7, #24] - 8042424: 3302 adds r3, #2 - 8042426: 61bb str r3, [r7, #24] - 8042428: e007 b.n 804243a + 804241e: 69bb ldr r3, [r7, #24] + 8042420: 3302 adds r3, #2 + 8042422: 61bb str r3, [r7, #24] + 8042424: e007 b.n 8042436 } else { huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); - 804242a: 69fb ldr r3, [r7, #28] - 804242c: 781a ldrb r2, [r3, #0] - 804242e: 68fb ldr r3, [r7, #12] - 8042430: 681b ldr r3, [r3, #0] - 8042432: 629a str r2, [r3, #40] ; 0x28 + 8042426: 69fb ldr r3, [r7, #28] + 8042428: 781a ldrb r2, [r3, #0] + 804242a: 68fb ldr r3, [r7, #12] + 804242c: 681b ldr r3, [r3, #0] + 804242e: 629a str r2, [r3, #40] ; 0x28 pdata8bits++; - 8042434: 69fb ldr r3, [r7, #28] - 8042436: 3301 adds r3, #1 - 8042438: 61fb str r3, [r7, #28] + 8042430: 69fb ldr r3, [r7, #28] + 8042432: 3301 adds r3, #1 + 8042434: 61fb str r3, [r7, #28] } huart->TxXferCount--; - 804243a: 68fb ldr r3, [r7, #12] - 804243c: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52 - 8042440: b29b uxth r3, r3 - 8042442: 3b01 subs r3, #1 - 8042444: b29a uxth r2, r3 - 8042446: 68fb ldr r3, [r7, #12] - 8042448: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 + 8042436: 68fb ldr r3, [r7, #12] + 8042438: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52 + 804243c: b29b uxth r3, r3 + 804243e: 3b01 subs r3, #1 + 8042440: b29a uxth r2, r3 + 8042442: 68fb ldr r3, [r7, #12] + 8042444: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 while (huart->TxXferCount > 0U) - 804244c: 68fb ldr r3, [r7, #12] - 804244e: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52 - 8042452: b29b uxth r3, r3 - 8042454: 2b00 cmp r3, #0 - 8042456: d1cc bne.n 80423f2 + 8042448: 68fb ldr r3, [r7, #12] + 804244a: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52 + 804244e: b29b uxth r3, r3 + 8042450: 2b00 cmp r3, #0 + 8042452: d1cc bne.n 80423ee } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) - 8042458: 683b ldr r3, [r7, #0] - 804245a: 9300 str r3, [sp, #0] - 804245c: 697b ldr r3, [r7, #20] - 804245e: 2200 movs r2, #0 - 8042460: 2140 movs r1, #64 ; 0x40 - 8042462: 68f8 ldr r0, [r7, #12] - 8042464: f000 fb5d bl 8042b22 - 8042468: 4603 mov r3, r0 - 804246a: 2b00 cmp r3, #0 - 804246c: d001 beq.n 8042472 + 8042454: 683b ldr r3, [r7, #0] + 8042456: 9300 str r3, [sp, #0] + 8042458: 697b ldr r3, [r7, #20] + 804245a: 2200 movs r2, #0 + 804245c: 2140 movs r1, #64 ; 0x40 + 804245e: 68f8 ldr r0, [r7, #12] + 8042460: f000 fb5d bl 8042b1e + 8042464: 4603 mov r3, r0 + 8042466: 2b00 cmp r3, #0 + 8042468: d001 beq.n 804246e { return HAL_TIMEOUT; - 804246e: 2303 movs r3, #3 - 8042470: e005 b.n 804247e + 804246a: 2303 movs r3, #3 + 804246c: e005 b.n 804247a } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - 8042472: 68fb ldr r3, [r7, #12] - 8042474: 2220 movs r2, #32 - 8042476: 679a str r2, [r3, #120] ; 0x78 + 804246e: 68fb ldr r3, [r7, #12] + 8042470: 2220 movs r2, #32 + 8042472: 679a str r2, [r3, #120] ; 0x78 return HAL_OK; - 8042478: 2300 movs r3, #0 - 804247a: e000 b.n 804247e + 8042474: 2300 movs r3, #0 + 8042476: e000 b.n 804247a } else { return HAL_BUSY; - 804247c: 2302 movs r3, #2 + 8042478: 2302 movs r3, #2 } } - 804247e: 4618 mov r0, r3 - 8042480: 3720 adds r7, #32 - 8042482: 46bd mov sp, r7 - 8042484: bd80 pop {r7, pc} + 804247a: 4618 mov r0, r3 + 804247c: 3720 adds r7, #32 + 804247e: 46bd mov sp, r7 + 8042480: bd80 pop {r7, pc} ... -08042488 : +08042484 : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { - 8042488: b580 push {r7, lr} - 804248a: b088 sub sp, #32 - 804248c: af00 add r7, sp, #0 - 804248e: 6078 str r0, [r7, #4] + 8042484: b580 push {r7, lr} + 8042486: b088 sub sp, #32 + 8042488: af00 add r7, sp, #0 + 804248a: 6078 str r0, [r7, #4] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; - 8042490: 2300 movs r3, #0 - 8042492: 77bb strb r3, [r7, #30] + 804248c: 2300 movs r3, #0 + 804248e: 77bb strb r3, [r7, #30] * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + 8042490: 687b ldr r3, [r7, #4] + 8042492: 689a ldr r2, [r3, #8] 8042494: 687b ldr r3, [r7, #4] - 8042496: 689a ldr r2, [r3, #8] - 8042498: 687b ldr r3, [r7, #4] - 804249a: 691b ldr r3, [r3, #16] - 804249c: 431a orrs r2, r3 - 804249e: 687b ldr r3, [r7, #4] - 80424a0: 695b ldr r3, [r3, #20] - 80424a2: 431a orrs r2, r3 - 80424a4: 687b ldr r3, [r7, #4] - 80424a6: 69db ldr r3, [r3, #28] - 80424a8: 4313 orrs r3, r2 - 80424aa: 617b str r3, [r7, #20] + 8042496: 691b ldr r3, [r3, #16] + 8042498: 431a orrs r2, r3 + 804249a: 687b ldr r3, [r7, #4] + 804249c: 695b ldr r3, [r3, #20] + 804249e: 431a orrs r2, r3 + 80424a0: 687b ldr r3, [r7, #4] + 80424a2: 69db ldr r3, [r3, #28] + 80424a4: 4313 orrs r3, r2 + 80424a6: 617b str r3, [r7, #20] MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); - 80424ac: 687b ldr r3, [r7, #4] - 80424ae: 681b ldr r3, [r3, #0] - 80424b0: 681a ldr r2, [r3, #0] - 80424b2: 4ba7 ldr r3, [pc, #668] ; (8042750 ) - 80424b4: 4013 ands r3, r2 - 80424b6: 687a ldr r2, [r7, #4] - 80424b8: 6812 ldr r2, [r2, #0] - 80424ba: 6979 ldr r1, [r7, #20] - 80424bc: 430b orrs r3, r1 - 80424be: 6013 str r3, [r2, #0] + 80424a8: 687b ldr r3, [r7, #4] + 80424aa: 681b ldr r3, [r3, #0] + 80424ac: 681a ldr r2, [r3, #0] + 80424ae: 4ba7 ldr r3, [pc, #668] ; (804274c ) + 80424b0: 4013 ands r3, r2 + 80424b2: 687a ldr r2, [r7, #4] + 80424b4: 6812 ldr r2, [r2, #0] + 80424b6: 6979 ldr r1, [r7, #20] + 80424b8: 430b orrs r3, r1 + 80424ba: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - 80424c0: 687b ldr r3, [r7, #4] - 80424c2: 681b ldr r3, [r3, #0] - 80424c4: 685b ldr r3, [r3, #4] - 80424c6: f423 5140 bic.w r1, r3, #12288 ; 0x3000 + 80424bc: 687b ldr r3, [r7, #4] + 80424be: 681b ldr r3, [r3, #0] + 80424c0: 685b ldr r3, [r3, #4] + 80424c2: f423 5140 bic.w r1, r3, #12288 ; 0x3000 + 80424c6: 687b ldr r3, [r7, #4] + 80424c8: 68da ldr r2, [r3, #12] 80424ca: 687b ldr r3, [r7, #4] - 80424cc: 68da ldr r2, [r3, #12] - 80424ce: 687b ldr r3, [r7, #4] - 80424d0: 681b ldr r3, [r3, #0] - 80424d2: 430a orrs r2, r1 - 80424d4: 605a str r2, [r3, #4] + 80424cc: 681b ldr r3, [r3, #0] + 80424ce: 430a orrs r2, r1 + 80424d0: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; - 80424d6: 687b ldr r3, [r7, #4] - 80424d8: 699b ldr r3, [r3, #24] - 80424da: 617b str r3, [r7, #20] + 80424d2: 687b ldr r3, [r7, #4] + 80424d4: 699b ldr r3, [r3, #24] + 80424d6: 617b str r3, [r7, #20] tmpreg |= huart->Init.OneBitSampling; - 80424dc: 687b ldr r3, [r7, #4] - 80424de: 6a1b ldr r3, [r3, #32] - 80424e0: 697a ldr r2, [r7, #20] - 80424e2: 4313 orrs r3, r2 - 80424e4: 617b str r3, [r7, #20] + 80424d8: 687b ldr r3, [r7, #4] + 80424da: 6a1b ldr r3, [r3, #32] + 80424dc: 697a ldr r2, [r7, #20] + 80424de: 4313 orrs r3, r2 + 80424e0: 617b str r3, [r7, #20] MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); - 80424e6: 687b ldr r3, [r7, #4] - 80424e8: 681b ldr r3, [r3, #0] - 80424ea: 689b ldr r3, [r3, #8] - 80424ec: f423 6130 bic.w r1, r3, #2816 ; 0xb00 - 80424f0: 687b ldr r3, [r7, #4] - 80424f2: 681b ldr r3, [r3, #0] - 80424f4: 697a ldr r2, [r7, #20] - 80424f6: 430a orrs r2, r1 - 80424f8: 609a str r2, [r3, #8] + 80424e2: 687b ldr r3, [r7, #4] + 80424e4: 681b ldr r3, [r3, #0] + 80424e6: 689b ldr r3, [r3, #8] + 80424e8: f423 6130 bic.w r1, r3, #2816 ; 0xb00 + 80424ec: 687b ldr r3, [r7, #4] + 80424ee: 681b ldr r3, [r3, #0] + 80424f0: 697a ldr r2, [r7, #20] + 80424f2: 430a orrs r2, r1 + 80424f4: 609a str r2, [r3, #8] /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); - 80424fa: 687b ldr r3, [r7, #4] - 80424fc: 681b ldr r3, [r3, #0] - 80424fe: 4a95 ldr r2, [pc, #596] ; (8042754 ) - 8042500: 4293 cmp r3, r2 - 8042502: d120 bne.n 8042546 - 8042504: 4b94 ldr r3, [pc, #592] ; (8042758 ) - 8042506: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 804250a: f003 0303 and.w r3, r3, #3 - 804250e: 2b03 cmp r3, #3 - 8042510: d816 bhi.n 8042540 - 8042512: a201 add r2, pc, #4 ; (adr r2, 8042518 ) - 8042514: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8042518: 08042529 .word 0x08042529 - 804251c: 08042535 .word 0x08042535 - 8042520: 0804252f .word 0x0804252f - 8042524: 0804253b .word 0x0804253b - 8042528: 2301 movs r3, #1 - 804252a: 77fb strb r3, [r7, #31] - 804252c: e14f b.n 80427ce - 804252e: 2302 movs r3, #2 - 8042530: 77fb strb r3, [r7, #31] - 8042532: e14c b.n 80427ce - 8042534: 2304 movs r3, #4 - 8042536: 77fb strb r3, [r7, #31] - 8042538: e149 b.n 80427ce - 804253a: 2308 movs r3, #8 - 804253c: 77fb strb r3, [r7, #31] - 804253e: e146 b.n 80427ce - 8042540: 2310 movs r3, #16 - 8042542: 77fb strb r3, [r7, #31] - 8042544: e143 b.n 80427ce - 8042546: 687b ldr r3, [r7, #4] - 8042548: 681b ldr r3, [r3, #0] - 804254a: 4a84 ldr r2, [pc, #528] ; (804275c ) - 804254c: 4293 cmp r3, r2 - 804254e: d132 bne.n 80425b6 - 8042550: 4b81 ldr r3, [pc, #516] ; (8042758 ) - 8042552: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8042556: f003 030c and.w r3, r3, #12 - 804255a: 2b0c cmp r3, #12 - 804255c: d828 bhi.n 80425b0 - 804255e: a201 add r2, pc, #4 ; (adr r2, 8042564 ) - 8042560: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8042564: 08042599 .word 0x08042599 - 8042568: 080425b1 .word 0x080425b1 - 804256c: 080425b1 .word 0x080425b1 - 8042570: 080425b1 .word 0x080425b1 - 8042574: 080425a5 .word 0x080425a5 - 8042578: 080425b1 .word 0x080425b1 - 804257c: 080425b1 .word 0x080425b1 - 8042580: 080425b1 .word 0x080425b1 - 8042584: 0804259f .word 0x0804259f - 8042588: 080425b1 .word 0x080425b1 - 804258c: 080425b1 .word 0x080425b1 - 8042590: 080425b1 .word 0x080425b1 - 8042594: 080425ab .word 0x080425ab - 8042598: 2300 movs r3, #0 - 804259a: 77fb strb r3, [r7, #31] - 804259c: e117 b.n 80427ce - 804259e: 2302 movs r3, #2 - 80425a0: 77fb strb r3, [r7, #31] - 80425a2: e114 b.n 80427ce - 80425a4: 2304 movs r3, #4 - 80425a6: 77fb strb r3, [r7, #31] - 80425a8: e111 b.n 80427ce - 80425aa: 2308 movs r3, #8 - 80425ac: 77fb strb r3, [r7, #31] - 80425ae: e10e b.n 80427ce - 80425b0: 2310 movs r3, #16 - 80425b2: 77fb strb r3, [r7, #31] - 80425b4: e10b b.n 80427ce - 80425b6: 687b ldr r3, [r7, #4] - 80425b8: 681b ldr r3, [r3, #0] - 80425ba: 4a69 ldr r2, [pc, #420] ; (8042760 ) - 80425bc: 4293 cmp r3, r2 - 80425be: d120 bne.n 8042602 - 80425c0: 4b65 ldr r3, [pc, #404] ; (8042758 ) - 80425c2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 80425c6: f003 0330 and.w r3, r3, #48 ; 0x30 + 80424f6: 687b ldr r3, [r7, #4] + 80424f8: 681b ldr r3, [r3, #0] + 80424fa: 4a95 ldr r2, [pc, #596] ; (8042750 ) + 80424fc: 4293 cmp r3, r2 + 80424fe: d120 bne.n 8042542 + 8042500: 4b94 ldr r3, [pc, #592] ; (8042754 ) + 8042502: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8042506: f003 0303 and.w r3, r3, #3 + 804250a: 2b03 cmp r3, #3 + 804250c: d816 bhi.n 804253c + 804250e: a201 add r2, pc, #4 ; (adr r2, 8042514 ) + 8042510: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8042514: 08042525 .word 0x08042525 + 8042518: 08042531 .word 0x08042531 + 804251c: 0804252b .word 0x0804252b + 8042520: 08042537 .word 0x08042537 + 8042524: 2301 movs r3, #1 + 8042526: 77fb strb r3, [r7, #31] + 8042528: e14f b.n 80427ca + 804252a: 2302 movs r3, #2 + 804252c: 77fb strb r3, [r7, #31] + 804252e: e14c b.n 80427ca + 8042530: 2304 movs r3, #4 + 8042532: 77fb strb r3, [r7, #31] + 8042534: e149 b.n 80427ca + 8042536: 2308 movs r3, #8 + 8042538: 77fb strb r3, [r7, #31] + 804253a: e146 b.n 80427ca + 804253c: 2310 movs r3, #16 + 804253e: 77fb strb r3, [r7, #31] + 8042540: e143 b.n 80427ca + 8042542: 687b ldr r3, [r7, #4] + 8042544: 681b ldr r3, [r3, #0] + 8042546: 4a84 ldr r2, [pc, #528] ; (8042758 ) + 8042548: 4293 cmp r3, r2 + 804254a: d132 bne.n 80425b2 + 804254c: 4b81 ldr r3, [pc, #516] ; (8042754 ) + 804254e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8042552: f003 030c and.w r3, r3, #12 + 8042556: 2b0c cmp r3, #12 + 8042558: d828 bhi.n 80425ac + 804255a: a201 add r2, pc, #4 ; (adr r2, 8042560 ) + 804255c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8042560: 08042595 .word 0x08042595 + 8042564: 080425ad .word 0x080425ad + 8042568: 080425ad .word 0x080425ad + 804256c: 080425ad .word 0x080425ad + 8042570: 080425a1 .word 0x080425a1 + 8042574: 080425ad .word 0x080425ad + 8042578: 080425ad .word 0x080425ad + 804257c: 080425ad .word 0x080425ad + 8042580: 0804259b .word 0x0804259b + 8042584: 080425ad .word 0x080425ad + 8042588: 080425ad .word 0x080425ad + 804258c: 080425ad .word 0x080425ad + 8042590: 080425a7 .word 0x080425a7 + 8042594: 2300 movs r3, #0 + 8042596: 77fb strb r3, [r7, #31] + 8042598: e117 b.n 80427ca + 804259a: 2302 movs r3, #2 + 804259c: 77fb strb r3, [r7, #31] + 804259e: e114 b.n 80427ca + 80425a0: 2304 movs r3, #4 + 80425a2: 77fb strb r3, [r7, #31] + 80425a4: e111 b.n 80427ca + 80425a6: 2308 movs r3, #8 + 80425a8: 77fb strb r3, [r7, #31] + 80425aa: e10e b.n 80427ca + 80425ac: 2310 movs r3, #16 + 80425ae: 77fb strb r3, [r7, #31] + 80425b0: e10b b.n 80427ca + 80425b2: 687b ldr r3, [r7, #4] + 80425b4: 681b ldr r3, [r3, #0] + 80425b6: 4a69 ldr r2, [pc, #420] ; (804275c ) + 80425b8: 4293 cmp r3, r2 + 80425ba: d120 bne.n 80425fe + 80425bc: 4b65 ldr r3, [pc, #404] ; (8042754 ) + 80425be: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80425c2: f003 0330 and.w r3, r3, #48 ; 0x30 + 80425c6: 2b30 cmp r3, #48 ; 0x30 + 80425c8: d013 beq.n 80425f2 80425ca: 2b30 cmp r3, #48 ; 0x30 - 80425cc: d013 beq.n 80425f6 - 80425ce: 2b30 cmp r3, #48 ; 0x30 - 80425d0: d814 bhi.n 80425fc + 80425cc: d814 bhi.n 80425f8 + 80425ce: 2b20 cmp r3, #32 + 80425d0: d009 beq.n 80425e6 80425d2: 2b20 cmp r3, #32 - 80425d4: d009 beq.n 80425ea - 80425d6: 2b20 cmp r3, #32 - 80425d8: d810 bhi.n 80425fc - 80425da: 2b00 cmp r3, #0 - 80425dc: d002 beq.n 80425e4 - 80425de: 2b10 cmp r3, #16 - 80425e0: d006 beq.n 80425f0 - 80425e2: e00b b.n 80425fc - 80425e4: 2300 movs r3, #0 - 80425e6: 77fb strb r3, [r7, #31] - 80425e8: e0f1 b.n 80427ce - 80425ea: 2302 movs r3, #2 - 80425ec: 77fb strb r3, [r7, #31] - 80425ee: e0ee b.n 80427ce - 80425f0: 2304 movs r3, #4 - 80425f2: 77fb strb r3, [r7, #31] - 80425f4: e0eb b.n 80427ce - 80425f6: 2308 movs r3, #8 - 80425f8: 77fb strb r3, [r7, #31] - 80425fa: e0e8 b.n 80427ce - 80425fc: 2310 movs r3, #16 - 80425fe: 77fb strb r3, [r7, #31] - 8042600: e0e5 b.n 80427ce - 8042602: 687b ldr r3, [r7, #4] - 8042604: 681b ldr r3, [r3, #0] - 8042606: 4a57 ldr r2, [pc, #348] ; (8042764 ) - 8042608: 4293 cmp r3, r2 - 804260a: d120 bne.n 804264e - 804260c: 4b52 ldr r3, [pc, #328] ; (8042758 ) - 804260e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8042612: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 80425d4: d810 bhi.n 80425f8 + 80425d6: 2b00 cmp r3, #0 + 80425d8: d002 beq.n 80425e0 + 80425da: 2b10 cmp r3, #16 + 80425dc: d006 beq.n 80425ec + 80425de: e00b b.n 80425f8 + 80425e0: 2300 movs r3, #0 + 80425e2: 77fb strb r3, [r7, #31] + 80425e4: e0f1 b.n 80427ca + 80425e6: 2302 movs r3, #2 + 80425e8: 77fb strb r3, [r7, #31] + 80425ea: e0ee b.n 80427ca + 80425ec: 2304 movs r3, #4 + 80425ee: 77fb strb r3, [r7, #31] + 80425f0: e0eb b.n 80427ca + 80425f2: 2308 movs r3, #8 + 80425f4: 77fb strb r3, [r7, #31] + 80425f6: e0e8 b.n 80427ca + 80425f8: 2310 movs r3, #16 + 80425fa: 77fb strb r3, [r7, #31] + 80425fc: e0e5 b.n 80427ca + 80425fe: 687b ldr r3, [r7, #4] + 8042600: 681b ldr r3, [r3, #0] + 8042602: 4a57 ldr r2, [pc, #348] ; (8042760 ) + 8042604: 4293 cmp r3, r2 + 8042606: d120 bne.n 804264a + 8042608: 4b52 ldr r3, [pc, #328] ; (8042754 ) + 804260a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 804260e: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 8042612: 2bc0 cmp r3, #192 ; 0xc0 + 8042614: d013 beq.n 804263e 8042616: 2bc0 cmp r3, #192 ; 0xc0 - 8042618: d013 beq.n 8042642 - 804261a: 2bc0 cmp r3, #192 ; 0xc0 - 804261c: d814 bhi.n 8042648 + 8042618: d814 bhi.n 8042644 + 804261a: 2b80 cmp r3, #128 ; 0x80 + 804261c: d009 beq.n 8042632 804261e: 2b80 cmp r3, #128 ; 0x80 - 8042620: d009 beq.n 8042636 - 8042622: 2b80 cmp r3, #128 ; 0x80 - 8042624: d810 bhi.n 8042648 - 8042626: 2b00 cmp r3, #0 - 8042628: d002 beq.n 8042630 - 804262a: 2b40 cmp r3, #64 ; 0x40 - 804262c: d006 beq.n 804263c - 804262e: e00b b.n 8042648 - 8042630: 2300 movs r3, #0 - 8042632: 77fb strb r3, [r7, #31] - 8042634: e0cb b.n 80427ce - 8042636: 2302 movs r3, #2 - 8042638: 77fb strb r3, [r7, #31] - 804263a: e0c8 b.n 80427ce - 804263c: 2304 movs r3, #4 - 804263e: 77fb strb r3, [r7, #31] - 8042640: e0c5 b.n 80427ce - 8042642: 2308 movs r3, #8 - 8042644: 77fb strb r3, [r7, #31] - 8042646: e0c2 b.n 80427ce - 8042648: 2310 movs r3, #16 - 804264a: 77fb strb r3, [r7, #31] - 804264c: e0bf b.n 80427ce - 804264e: 687b ldr r3, [r7, #4] - 8042650: 681b ldr r3, [r3, #0] - 8042652: 4a45 ldr r2, [pc, #276] ; (8042768 ) - 8042654: 4293 cmp r3, r2 - 8042656: d125 bne.n 80426a4 - 8042658: 4b3f ldr r3, [pc, #252] ; (8042758 ) - 804265a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 804265e: f403 7340 and.w r3, r3, #768 ; 0x300 - 8042662: f5b3 7f40 cmp.w r3, #768 ; 0x300 - 8042666: d017 beq.n 8042698 - 8042668: f5b3 7f40 cmp.w r3, #768 ; 0x300 - 804266c: d817 bhi.n 804269e - 804266e: f5b3 7f00 cmp.w r3, #512 ; 0x200 - 8042672: d00b beq.n 804268c - 8042674: f5b3 7f00 cmp.w r3, #512 ; 0x200 - 8042678: d811 bhi.n 804269e - 804267a: 2b00 cmp r3, #0 - 804267c: d003 beq.n 8042686 - 804267e: f5b3 7f80 cmp.w r3, #256 ; 0x100 - 8042682: d006 beq.n 8042692 - 8042684: e00b b.n 804269e - 8042686: 2300 movs r3, #0 - 8042688: 77fb strb r3, [r7, #31] - 804268a: e0a0 b.n 80427ce - 804268c: 2302 movs r3, #2 - 804268e: 77fb strb r3, [r7, #31] - 8042690: e09d b.n 80427ce - 8042692: 2304 movs r3, #4 - 8042694: 77fb strb r3, [r7, #31] - 8042696: e09a b.n 80427ce - 8042698: 2308 movs r3, #8 - 804269a: 77fb strb r3, [r7, #31] - 804269c: e097 b.n 80427ce - 804269e: 2310 movs r3, #16 - 80426a0: 77fb strb r3, [r7, #31] - 80426a2: e094 b.n 80427ce - 80426a4: 687b ldr r3, [r7, #4] - 80426a6: 681b ldr r3, [r3, #0] - 80426a8: 4a30 ldr r2, [pc, #192] ; (804276c ) - 80426aa: 4293 cmp r3, r2 - 80426ac: d125 bne.n 80426fa - 80426ae: 4b2a ldr r3, [pc, #168] ; (8042758 ) - 80426b0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 80426b4: f403 6340 and.w r3, r3, #3072 ; 0xc00 - 80426b8: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 - 80426bc: d017 beq.n 80426ee - 80426be: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 - 80426c2: d817 bhi.n 80426f4 - 80426c4: f5b3 6f00 cmp.w r3, #2048 ; 0x800 - 80426c8: d00b beq.n 80426e2 - 80426ca: f5b3 6f00 cmp.w r3, #2048 ; 0x800 - 80426ce: d811 bhi.n 80426f4 - 80426d0: 2b00 cmp r3, #0 - 80426d2: d003 beq.n 80426dc - 80426d4: f5b3 6f80 cmp.w r3, #1024 ; 0x400 - 80426d8: d006 beq.n 80426e8 - 80426da: e00b b.n 80426f4 - 80426dc: 2301 movs r3, #1 - 80426de: 77fb strb r3, [r7, #31] - 80426e0: e075 b.n 80427ce - 80426e2: 2302 movs r3, #2 - 80426e4: 77fb strb r3, [r7, #31] - 80426e6: e072 b.n 80427ce - 80426e8: 2304 movs r3, #4 - 80426ea: 77fb strb r3, [r7, #31] - 80426ec: e06f b.n 80427ce - 80426ee: 2308 movs r3, #8 - 80426f0: 77fb strb r3, [r7, #31] - 80426f2: e06c b.n 80427ce - 80426f4: 2310 movs r3, #16 - 80426f6: 77fb strb r3, [r7, #31] - 80426f8: e069 b.n 80427ce - 80426fa: 687b ldr r3, [r7, #4] - 80426fc: 681b ldr r3, [r3, #0] - 80426fe: 4a1c ldr r2, [pc, #112] ; (8042770 ) - 8042700: 4293 cmp r3, r2 - 8042702: d137 bne.n 8042774 - 8042704: 4b14 ldr r3, [pc, #80] ; (8042758 ) - 8042706: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 804270a: f403 5340 and.w r3, r3, #12288 ; 0x3000 - 804270e: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 - 8042712: d017 beq.n 8042744 - 8042714: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 - 8042718: d817 bhi.n 804274a - 804271a: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 - 804271e: d00b beq.n 8042738 - 8042720: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 - 8042724: d811 bhi.n 804274a - 8042726: 2b00 cmp r3, #0 - 8042728: d003 beq.n 8042732 - 804272a: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 - 804272e: d006 beq.n 804273e - 8042730: e00b b.n 804274a - 8042732: 2300 movs r3, #0 - 8042734: 77fb strb r3, [r7, #31] - 8042736: e04a b.n 80427ce - 8042738: 2302 movs r3, #2 - 804273a: 77fb strb r3, [r7, #31] - 804273c: e047 b.n 80427ce - 804273e: 2304 movs r3, #4 - 8042740: 77fb strb r3, [r7, #31] - 8042742: e044 b.n 80427ce - 8042744: 2308 movs r3, #8 - 8042746: 77fb strb r3, [r7, #31] - 8042748: e041 b.n 80427ce - 804274a: 2310 movs r3, #16 - 804274c: 77fb strb r3, [r7, #31] - 804274e: e03e b.n 80427ce - 8042750: efff69f3 .word 0xefff69f3 - 8042754: 40011000 .word 0x40011000 - 8042758: 40023800 .word 0x40023800 - 804275c: 40004400 .word 0x40004400 - 8042760: 40004800 .word 0x40004800 - 8042764: 40004c00 .word 0x40004c00 - 8042768: 40005000 .word 0x40005000 - 804276c: 40011400 .word 0x40011400 - 8042770: 40007800 .word 0x40007800 - 8042774: 687b ldr r3, [r7, #4] - 8042776: 681b ldr r3, [r3, #0] - 8042778: 4a71 ldr r2, [pc, #452] ; (8042940 ) - 804277a: 4293 cmp r3, r2 - 804277c: d125 bne.n 80427ca - 804277e: 4b71 ldr r3, [pc, #452] ; (8042944 ) - 8042780: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8042784: f403 4340 and.w r3, r3, #49152 ; 0xc000 - 8042788: f5b3 4f40 cmp.w r3, #49152 ; 0xc000 - 804278c: d017 beq.n 80427be - 804278e: f5b3 4f40 cmp.w r3, #49152 ; 0xc000 - 8042792: d817 bhi.n 80427c4 - 8042794: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 - 8042798: d00b beq.n 80427b2 - 804279a: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 - 804279e: d811 bhi.n 80427c4 - 80427a0: 2b00 cmp r3, #0 - 80427a2: d003 beq.n 80427ac - 80427a4: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 - 80427a8: d006 beq.n 80427b8 - 80427aa: e00b b.n 80427c4 - 80427ac: 2300 movs r3, #0 - 80427ae: 77fb strb r3, [r7, #31] - 80427b0: e00d b.n 80427ce - 80427b2: 2302 movs r3, #2 - 80427b4: 77fb strb r3, [r7, #31] - 80427b6: e00a b.n 80427ce - 80427b8: 2304 movs r3, #4 - 80427ba: 77fb strb r3, [r7, #31] - 80427bc: e007 b.n 80427ce - 80427be: 2308 movs r3, #8 - 80427c0: 77fb strb r3, [r7, #31] - 80427c2: e004 b.n 80427ce - 80427c4: 2310 movs r3, #16 - 80427c6: 77fb strb r3, [r7, #31] - 80427c8: e001 b.n 80427ce - 80427ca: 2310 movs r3, #16 - 80427cc: 77fb strb r3, [r7, #31] + 8042620: d810 bhi.n 8042644 + 8042622: 2b00 cmp r3, #0 + 8042624: d002 beq.n 804262c + 8042626: 2b40 cmp r3, #64 ; 0x40 + 8042628: d006 beq.n 8042638 + 804262a: e00b b.n 8042644 + 804262c: 2300 movs r3, #0 + 804262e: 77fb strb r3, [r7, #31] + 8042630: e0cb b.n 80427ca + 8042632: 2302 movs r3, #2 + 8042634: 77fb strb r3, [r7, #31] + 8042636: e0c8 b.n 80427ca + 8042638: 2304 movs r3, #4 + 804263a: 77fb strb r3, [r7, #31] + 804263c: e0c5 b.n 80427ca + 804263e: 2308 movs r3, #8 + 8042640: 77fb strb r3, [r7, #31] + 8042642: e0c2 b.n 80427ca + 8042644: 2310 movs r3, #16 + 8042646: 77fb strb r3, [r7, #31] + 8042648: e0bf b.n 80427ca + 804264a: 687b ldr r3, [r7, #4] + 804264c: 681b ldr r3, [r3, #0] + 804264e: 4a45 ldr r2, [pc, #276] ; (8042764 ) + 8042650: 4293 cmp r3, r2 + 8042652: d125 bne.n 80426a0 + 8042654: 4b3f ldr r3, [pc, #252] ; (8042754 ) + 8042656: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 804265a: f403 7340 and.w r3, r3, #768 ; 0x300 + 804265e: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 8042662: d017 beq.n 8042694 + 8042664: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 8042668: d817 bhi.n 804269a + 804266a: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 804266e: d00b beq.n 8042688 + 8042670: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 8042674: d811 bhi.n 804269a + 8042676: 2b00 cmp r3, #0 + 8042678: d003 beq.n 8042682 + 804267a: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 804267e: d006 beq.n 804268e + 8042680: e00b b.n 804269a + 8042682: 2300 movs r3, #0 + 8042684: 77fb strb r3, [r7, #31] + 8042686: e0a0 b.n 80427ca + 8042688: 2302 movs r3, #2 + 804268a: 77fb strb r3, [r7, #31] + 804268c: e09d b.n 80427ca + 804268e: 2304 movs r3, #4 + 8042690: 77fb strb r3, [r7, #31] + 8042692: e09a b.n 80427ca + 8042694: 2308 movs r3, #8 + 8042696: 77fb strb r3, [r7, #31] + 8042698: e097 b.n 80427ca + 804269a: 2310 movs r3, #16 + 804269c: 77fb strb r3, [r7, #31] + 804269e: e094 b.n 80427ca + 80426a0: 687b ldr r3, [r7, #4] + 80426a2: 681b ldr r3, [r3, #0] + 80426a4: 4a30 ldr r2, [pc, #192] ; (8042768 ) + 80426a6: 4293 cmp r3, r2 + 80426a8: d125 bne.n 80426f6 + 80426aa: 4b2a ldr r3, [pc, #168] ; (8042754 ) + 80426ac: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80426b0: f403 6340 and.w r3, r3, #3072 ; 0xc00 + 80426b4: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 + 80426b8: d017 beq.n 80426ea + 80426ba: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 + 80426be: d817 bhi.n 80426f0 + 80426c0: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 80426c4: d00b beq.n 80426de + 80426c6: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 80426ca: d811 bhi.n 80426f0 + 80426cc: 2b00 cmp r3, #0 + 80426ce: d003 beq.n 80426d8 + 80426d0: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 80426d4: d006 beq.n 80426e4 + 80426d6: e00b b.n 80426f0 + 80426d8: 2301 movs r3, #1 + 80426da: 77fb strb r3, [r7, #31] + 80426dc: e075 b.n 80427ca + 80426de: 2302 movs r3, #2 + 80426e0: 77fb strb r3, [r7, #31] + 80426e2: e072 b.n 80427ca + 80426e4: 2304 movs r3, #4 + 80426e6: 77fb strb r3, [r7, #31] + 80426e8: e06f b.n 80427ca + 80426ea: 2308 movs r3, #8 + 80426ec: 77fb strb r3, [r7, #31] + 80426ee: e06c b.n 80427ca + 80426f0: 2310 movs r3, #16 + 80426f2: 77fb strb r3, [r7, #31] + 80426f4: e069 b.n 80427ca + 80426f6: 687b ldr r3, [r7, #4] + 80426f8: 681b ldr r3, [r3, #0] + 80426fa: 4a1c ldr r2, [pc, #112] ; (804276c ) + 80426fc: 4293 cmp r3, r2 + 80426fe: d137 bne.n 8042770 + 8042700: 4b14 ldr r3, [pc, #80] ; (8042754 ) + 8042702: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8042706: f403 5340 and.w r3, r3, #12288 ; 0x3000 + 804270a: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 + 804270e: d017 beq.n 8042740 + 8042710: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 + 8042714: d817 bhi.n 8042746 + 8042716: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 804271a: d00b beq.n 8042734 + 804271c: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 8042720: d811 bhi.n 8042746 + 8042722: 2b00 cmp r3, #0 + 8042724: d003 beq.n 804272e + 8042726: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 804272a: d006 beq.n 804273a + 804272c: e00b b.n 8042746 + 804272e: 2300 movs r3, #0 + 8042730: 77fb strb r3, [r7, #31] + 8042732: e04a b.n 80427ca + 8042734: 2302 movs r3, #2 + 8042736: 77fb strb r3, [r7, #31] + 8042738: e047 b.n 80427ca + 804273a: 2304 movs r3, #4 + 804273c: 77fb strb r3, [r7, #31] + 804273e: e044 b.n 80427ca + 8042740: 2308 movs r3, #8 + 8042742: 77fb strb r3, [r7, #31] + 8042744: e041 b.n 80427ca + 8042746: 2310 movs r3, #16 + 8042748: 77fb strb r3, [r7, #31] + 804274a: e03e b.n 80427ca + 804274c: efff69f3 .word 0xefff69f3 + 8042750: 40011000 .word 0x40011000 + 8042754: 40023800 .word 0x40023800 + 8042758: 40004400 .word 0x40004400 + 804275c: 40004800 .word 0x40004800 + 8042760: 40004c00 .word 0x40004c00 + 8042764: 40005000 .word 0x40005000 + 8042768: 40011400 .word 0x40011400 + 804276c: 40007800 .word 0x40007800 + 8042770: 687b ldr r3, [r7, #4] + 8042772: 681b ldr r3, [r3, #0] + 8042774: 4a71 ldr r2, [pc, #452] ; (804293c ) + 8042776: 4293 cmp r3, r2 + 8042778: d125 bne.n 80427c6 + 804277a: 4b71 ldr r3, [pc, #452] ; (8042940 ) + 804277c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8042780: f403 4340 and.w r3, r3, #49152 ; 0xc000 + 8042784: f5b3 4f40 cmp.w r3, #49152 ; 0xc000 + 8042788: d017 beq.n 80427ba + 804278a: f5b3 4f40 cmp.w r3, #49152 ; 0xc000 + 804278e: d817 bhi.n 80427c0 + 8042790: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8042794: d00b beq.n 80427ae + 8042796: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 804279a: d811 bhi.n 80427c0 + 804279c: 2b00 cmp r3, #0 + 804279e: d003 beq.n 80427a8 + 80427a0: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 80427a4: d006 beq.n 80427b4 + 80427a6: e00b b.n 80427c0 + 80427a8: 2300 movs r3, #0 + 80427aa: 77fb strb r3, [r7, #31] + 80427ac: e00d b.n 80427ca + 80427ae: 2302 movs r3, #2 + 80427b0: 77fb strb r3, [r7, #31] + 80427b2: e00a b.n 80427ca + 80427b4: 2304 movs r3, #4 + 80427b6: 77fb strb r3, [r7, #31] + 80427b8: e007 b.n 80427ca + 80427ba: 2308 movs r3, #8 + 80427bc: 77fb strb r3, [r7, #31] + 80427be: e004 b.n 80427ca + 80427c0: 2310 movs r3, #16 + 80427c2: 77fb strb r3, [r7, #31] + 80427c4: e001 b.n 80427ca + 80427c6: 2310 movs r3, #16 + 80427c8: 77fb strb r3, [r7, #31] if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - 80427ce: 687b ldr r3, [r7, #4] - 80427d0: 69db ldr r3, [r3, #28] - 80427d2: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 - 80427d6: d15b bne.n 8042890 + 80427ca: 687b ldr r3, [r7, #4] + 80427cc: 69db ldr r3, [r3, #28] + 80427ce: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 80427d2: d15b bne.n 804288c { switch (clocksource) - 80427d8: 7ffb ldrb r3, [r7, #31] - 80427da: 2b08 cmp r3, #8 - 80427dc: d827 bhi.n 804282e - 80427de: a201 add r2, pc, #4 ; (adr r2, 80427e4 ) - 80427e0: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 80427e4: 08042809 .word 0x08042809 - 80427e8: 08042811 .word 0x08042811 - 80427ec: 08042819 .word 0x08042819 - 80427f0: 0804282f .word 0x0804282f - 80427f4: 0804281f .word 0x0804281f - 80427f8: 0804282f .word 0x0804282f - 80427fc: 0804282f .word 0x0804282f - 8042800: 0804282f .word 0x0804282f - 8042804: 08042827 .word 0x08042827 + 80427d4: 7ffb ldrb r3, [r7, #31] + 80427d6: 2b08 cmp r3, #8 + 80427d8: d827 bhi.n 804282a + 80427da: a201 add r2, pc, #4 ; (adr r2, 80427e0 ) + 80427dc: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80427e0: 08042805 .word 0x08042805 + 80427e4: 0804280d .word 0x0804280d + 80427e8: 08042815 .word 0x08042815 + 80427ec: 0804282b .word 0x0804282b + 80427f0: 0804281b .word 0x0804281b + 80427f4: 0804282b .word 0x0804282b + 80427f8: 0804282b .word 0x0804282b + 80427fc: 0804282b .word 0x0804282b + 8042800: 08042823 .word 0x08042823 { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - 8042808: f7ff f90c bl 8041a24 - 804280c: 61b8 str r0, [r7, #24] + 8042804: f7ff f90c bl 8041a20 + 8042808: 61b8 str r0, [r7, #24] break; - 804280e: e013 b.n 8042838 + 804280a: e013 b.n 8042834 case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - 8042810: f7ff f91c bl 8041a4c - 8042814: 61b8 str r0, [r7, #24] + 804280c: f7ff f91c bl 8041a48 + 8042810: 61b8 str r0, [r7, #24] break; - 8042816: e00f b.n 8042838 + 8042812: e00f b.n 8042834 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; - 8042818: 4b4b ldr r3, [pc, #300] ; (8042948 ) - 804281a: 61bb str r3, [r7, #24] + 8042814: 4b4b ldr r3, [pc, #300] ; (8042944 ) + 8042816: 61bb str r3, [r7, #24] break; - 804281c: e00c b.n 8042838 + 8042818: e00c b.n 8042834 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - 804281e: f7ff f83f bl 80418a0 - 8042822: 61b8 str r0, [r7, #24] + 804281a: f7ff f83f bl 804189c + 804281e: 61b8 str r0, [r7, #24] break; - 8042824: e008 b.n 8042838 + 8042820: e008 b.n 8042834 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; - 8042826: f44f 4300 mov.w r3, #32768 ; 0x8000 - 804282a: 61bb str r3, [r7, #24] + 8042822: f44f 4300 mov.w r3, #32768 ; 0x8000 + 8042826: 61bb str r3, [r7, #24] break; - 804282c: e004 b.n 8042838 + 8042828: e004 b.n 8042834 default: pclk = 0U; - 804282e: 2300 movs r3, #0 - 8042830: 61bb str r3, [r7, #24] + 804282a: 2300 movs r3, #0 + 804282c: 61bb str r3, [r7, #24] ret = HAL_ERROR; - 8042832: 2301 movs r3, #1 - 8042834: 77bb strb r3, [r7, #30] + 804282e: 2301 movs r3, #1 + 8042830: 77bb strb r3, [r7, #30] break; - 8042836: bf00 nop + 8042832: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) - 8042838: 69bb ldr r3, [r7, #24] - 804283a: 2b00 cmp r3, #0 - 804283c: d074 beq.n 8042928 + 8042834: 69bb ldr r3, [r7, #24] + 8042836: 2b00 cmp r3, #0 + 8042838: d074 beq.n 8042924 { usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); - 804283e: 69bb ldr r3, [r7, #24] - 8042840: 005a lsls r2, r3, #1 - 8042842: 687b ldr r3, [r7, #4] - 8042844: 685b ldr r3, [r3, #4] - 8042846: 085b lsrs r3, r3, #1 - 8042848: 441a add r2, r3 - 804284a: 687b ldr r3, [r7, #4] - 804284c: 685b ldr r3, [r3, #4] - 804284e: fbb2 f3f3 udiv r3, r2, r3 - 8042852: b29b uxth r3, r3 - 8042854: 613b str r3, [r7, #16] + 804283a: 69bb ldr r3, [r7, #24] + 804283c: 005a lsls r2, r3, #1 + 804283e: 687b ldr r3, [r7, #4] + 8042840: 685b ldr r3, [r3, #4] + 8042842: 085b lsrs r3, r3, #1 + 8042844: 441a add r2, r3 + 8042846: 687b ldr r3, [r7, #4] + 8042848: 685b ldr r3, [r3, #4] + 804284a: fbb2 f3f3 udiv r3, r2, r3 + 804284e: b29b uxth r3, r3 + 8042850: 613b str r3, [r7, #16] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - 8042856: 693b ldr r3, [r7, #16] - 8042858: 2b0f cmp r3, #15 - 804285a: d916 bls.n 804288a - 804285c: 693b ldr r3, [r7, #16] - 804285e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 - 8042862: d212 bcs.n 804288a + 8042852: 693b ldr r3, [r7, #16] + 8042854: 2b0f cmp r3, #15 + 8042856: d916 bls.n 8042886 + 8042858: 693b ldr r3, [r7, #16] + 804285a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 804285e: d212 bcs.n 8042886 { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); - 8042864: 693b ldr r3, [r7, #16] - 8042866: b29b uxth r3, r3 - 8042868: f023 030f bic.w r3, r3, #15 - 804286c: 81fb strh r3, [r7, #14] + 8042860: 693b ldr r3, [r7, #16] + 8042862: b29b uxth r3, r3 + 8042864: f023 030f bic.w r3, r3, #15 + 8042868: 81fb strh r3, [r7, #14] brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - 804286e: 693b ldr r3, [r7, #16] - 8042870: 085b lsrs r3, r3, #1 - 8042872: b29b uxth r3, r3 - 8042874: f003 0307 and.w r3, r3, #7 - 8042878: b29a uxth r2, r3 - 804287a: 89fb ldrh r3, [r7, #14] - 804287c: 4313 orrs r3, r2 - 804287e: 81fb strh r3, [r7, #14] + 804286a: 693b ldr r3, [r7, #16] + 804286c: 085b lsrs r3, r3, #1 + 804286e: b29b uxth r3, r3 + 8042870: f003 0307 and.w r3, r3, #7 + 8042874: b29a uxth r2, r3 + 8042876: 89fb ldrh r3, [r7, #14] + 8042878: 4313 orrs r3, r2 + 804287a: 81fb strh r3, [r7, #14] huart->Instance->BRR = brrtemp; - 8042880: 687b ldr r3, [r7, #4] - 8042882: 681b ldr r3, [r3, #0] - 8042884: 89fa ldrh r2, [r7, #14] - 8042886: 60da str r2, [r3, #12] - 8042888: e04e b.n 8042928 + 804287c: 687b ldr r3, [r7, #4] + 804287e: 681b ldr r3, [r3, #0] + 8042880: 89fa ldrh r2, [r7, #14] + 8042882: 60da str r2, [r3, #12] + 8042884: e04e b.n 8042924 } else { ret = HAL_ERROR; - 804288a: 2301 movs r3, #1 - 804288c: 77bb strb r3, [r7, #30] - 804288e: e04b b.n 8042928 + 8042886: 2301 movs r3, #1 + 8042888: 77bb strb r3, [r7, #30] + 804288a: e04b b.n 8042924 } } } else { switch (clocksource) - 8042890: 7ffb ldrb r3, [r7, #31] - 8042892: 2b08 cmp r3, #8 - 8042894: d827 bhi.n 80428e6 - 8042896: a201 add r2, pc, #4 ; (adr r2, 804289c ) - 8042898: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 804289c: 080428c1 .word 0x080428c1 - 80428a0: 080428c9 .word 0x080428c9 - 80428a4: 080428d1 .word 0x080428d1 - 80428a8: 080428e7 .word 0x080428e7 - 80428ac: 080428d7 .word 0x080428d7 - 80428b0: 080428e7 .word 0x080428e7 - 80428b4: 080428e7 .word 0x080428e7 - 80428b8: 080428e7 .word 0x080428e7 - 80428bc: 080428df .word 0x080428df + 804288c: 7ffb ldrb r3, [r7, #31] + 804288e: 2b08 cmp r3, #8 + 8042890: d827 bhi.n 80428e2 + 8042892: a201 add r2, pc, #4 ; (adr r2, 8042898 ) + 8042894: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8042898: 080428bd .word 0x080428bd + 804289c: 080428c5 .word 0x080428c5 + 80428a0: 080428cd .word 0x080428cd + 80428a4: 080428e3 .word 0x080428e3 + 80428a8: 080428d3 .word 0x080428d3 + 80428ac: 080428e3 .word 0x080428e3 + 80428b0: 080428e3 .word 0x080428e3 + 80428b4: 080428e3 .word 0x080428e3 + 80428b8: 080428db .word 0x080428db { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - 80428c0: f7ff f8b0 bl 8041a24 - 80428c4: 61b8 str r0, [r7, #24] + 80428bc: f7ff f8b0 bl 8041a20 + 80428c0: 61b8 str r0, [r7, #24] break; - 80428c6: e013 b.n 80428f0 + 80428c2: e013 b.n 80428ec case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - 80428c8: f7ff f8c0 bl 8041a4c - 80428cc: 61b8 str r0, [r7, #24] + 80428c4: f7ff f8c0 bl 8041a48 + 80428c8: 61b8 str r0, [r7, #24] break; - 80428ce: e00f b.n 80428f0 + 80428ca: e00f b.n 80428ec case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; - 80428d0: 4b1d ldr r3, [pc, #116] ; (8042948 ) - 80428d2: 61bb str r3, [r7, #24] + 80428cc: 4b1d ldr r3, [pc, #116] ; (8042944 ) + 80428ce: 61bb str r3, [r7, #24] break; - 80428d4: e00c b.n 80428f0 + 80428d0: e00c b.n 80428ec case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - 80428d6: f7fe ffe3 bl 80418a0 - 80428da: 61b8 str r0, [r7, #24] + 80428d2: f7fe ffe3 bl 804189c + 80428d6: 61b8 str r0, [r7, #24] break; - 80428dc: e008 b.n 80428f0 + 80428d8: e008 b.n 80428ec case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; - 80428de: f44f 4300 mov.w r3, #32768 ; 0x8000 - 80428e2: 61bb str r3, [r7, #24] + 80428da: f44f 4300 mov.w r3, #32768 ; 0x8000 + 80428de: 61bb str r3, [r7, #24] break; - 80428e4: e004 b.n 80428f0 + 80428e0: e004 b.n 80428ec default: pclk = 0U; - 80428e6: 2300 movs r3, #0 - 80428e8: 61bb str r3, [r7, #24] + 80428e2: 2300 movs r3, #0 + 80428e4: 61bb str r3, [r7, #24] ret = HAL_ERROR; - 80428ea: 2301 movs r3, #1 - 80428ec: 77bb strb r3, [r7, #30] + 80428e6: 2301 movs r3, #1 + 80428e8: 77bb strb r3, [r7, #30] break; - 80428ee: bf00 nop + 80428ea: bf00 nop } if (pclk != 0U) - 80428f0: 69bb ldr r3, [r7, #24] - 80428f2: 2b00 cmp r3, #0 - 80428f4: d018 beq.n 8042928 + 80428ec: 69bb ldr r3, [r7, #24] + 80428ee: 2b00 cmp r3, #0 + 80428f0: d018 beq.n 8042924 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); - 80428f6: 687b ldr r3, [r7, #4] - 80428f8: 685b ldr r3, [r3, #4] - 80428fa: 085a lsrs r2, r3, #1 - 80428fc: 69bb ldr r3, [r7, #24] - 80428fe: 441a add r2, r3 - 8042900: 687b ldr r3, [r7, #4] - 8042902: 685b ldr r3, [r3, #4] - 8042904: fbb2 f3f3 udiv r3, r2, r3 - 8042908: b29b uxth r3, r3 - 804290a: 613b str r3, [r7, #16] + 80428f2: 687b ldr r3, [r7, #4] + 80428f4: 685b ldr r3, [r3, #4] + 80428f6: 085a lsrs r2, r3, #1 + 80428f8: 69bb ldr r3, [r7, #24] + 80428fa: 441a add r2, r3 + 80428fc: 687b ldr r3, [r7, #4] + 80428fe: 685b ldr r3, [r3, #4] + 8042900: fbb2 f3f3 udiv r3, r2, r3 + 8042904: b29b uxth r3, r3 + 8042906: 613b str r3, [r7, #16] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - 804290c: 693b ldr r3, [r7, #16] - 804290e: 2b0f cmp r3, #15 - 8042910: d908 bls.n 8042924 - 8042912: 693b ldr r3, [r7, #16] - 8042914: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 - 8042918: d204 bcs.n 8042924 + 8042908: 693b ldr r3, [r7, #16] + 804290a: 2b0f cmp r3, #15 + 804290c: d908 bls.n 8042920 + 804290e: 693b ldr r3, [r7, #16] + 8042910: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8042914: d204 bcs.n 8042920 { huart->Instance->BRR = usartdiv; - 804291a: 687b ldr r3, [r7, #4] - 804291c: 681b ldr r3, [r3, #0] - 804291e: 693a ldr r2, [r7, #16] - 8042920: 60da str r2, [r3, #12] - 8042922: e001 b.n 8042928 + 8042916: 687b ldr r3, [r7, #4] + 8042918: 681b ldr r3, [r3, #0] + 804291a: 693a ldr r2, [r7, #16] + 804291c: 60da str r2, [r3, #12] + 804291e: e001 b.n 8042924 } else { ret = HAL_ERROR; - 8042924: 2301 movs r3, #1 - 8042926: 77bb strb r3, [r7, #30] + 8042920: 2301 movs r3, #1 + 8042922: 77bb strb r3, [r7, #30] } } /* Clear ISR function pointers */ huart->RxISR = NULL; - 8042928: 687b ldr r3, [r7, #4] - 804292a: 2200 movs r2, #0 - 804292c: 665a str r2, [r3, #100] ; 0x64 + 8042924: 687b ldr r3, [r7, #4] + 8042926: 2200 movs r2, #0 + 8042928: 665a str r2, [r3, #100] ; 0x64 huart->TxISR = NULL; - 804292e: 687b ldr r3, [r7, #4] - 8042930: 2200 movs r2, #0 - 8042932: 669a str r2, [r3, #104] ; 0x68 + 804292a: 687b ldr r3, [r7, #4] + 804292c: 2200 movs r2, #0 + 804292e: 669a str r2, [r3, #104] ; 0x68 return ret; - 8042934: 7fbb ldrb r3, [r7, #30] + 8042930: 7fbb ldrb r3, [r7, #30] } - 8042936: 4618 mov r0, r3 - 8042938: 3720 adds r7, #32 - 804293a: 46bd mov sp, r7 - 804293c: bd80 pop {r7, pc} - 804293e: bf00 nop - 8042940: 40007c00 .word 0x40007c00 - 8042944: 40023800 .word 0x40023800 - 8042948: 00f42400 .word 0x00f42400 - -0804294c : + 8042932: 4618 mov r0, r3 + 8042934: 3720 adds r7, #32 + 8042936: 46bd mov sp, r7 + 8042938: bd80 pop {r7, pc} + 804293a: bf00 nop + 804293c: 40007c00 .word 0x40007c00 + 8042940: 40023800 .word 0x40023800 + 8042944: 00f42400 .word 0x00f42400 + +08042948 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { - 804294c: b480 push {r7} - 804294e: b083 sub sp, #12 - 8042950: af00 add r7, sp, #0 - 8042952: 6078 str r0, [r7, #4] + 8042948: b480 push {r7} + 804294a: b083 sub sp, #12 + 804294c: af00 add r7, sp, #0 + 804294e: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) - 8042954: 687b ldr r3, [r7, #4] - 8042956: 6a5b ldr r3, [r3, #36] ; 0x24 - 8042958: f003 0301 and.w r3, r3, #1 - 804295c: 2b00 cmp r3, #0 - 804295e: d00a beq.n 8042976 + 8042950: 687b ldr r3, [r7, #4] + 8042952: 6a5b ldr r3, [r3, #36] ; 0x24 + 8042954: f003 0301 and.w r3, r3, #1 + 8042958: 2b00 cmp r3, #0 + 804295a: d00a beq.n 8042972 { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); - 8042960: 687b ldr r3, [r7, #4] - 8042962: 681b ldr r3, [r3, #0] - 8042964: 685b ldr r3, [r3, #4] - 8042966: f423 3100 bic.w r1, r3, #131072 ; 0x20000 + 804295c: 687b ldr r3, [r7, #4] + 804295e: 681b ldr r3, [r3, #0] + 8042960: 685b ldr r3, [r3, #4] + 8042962: f423 3100 bic.w r1, r3, #131072 ; 0x20000 + 8042966: 687b ldr r3, [r7, #4] + 8042968: 6a9a ldr r2, [r3, #40] ; 0x28 804296a: 687b ldr r3, [r7, #4] - 804296c: 6a9a ldr r2, [r3, #40] ; 0x28 - 804296e: 687b ldr r3, [r7, #4] - 8042970: 681b ldr r3, [r3, #0] - 8042972: 430a orrs r2, r1 - 8042974: 605a str r2, [r3, #4] + 804296c: 681b ldr r3, [r3, #0] + 804296e: 430a orrs r2, r1 + 8042970: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) - 8042976: 687b ldr r3, [r7, #4] - 8042978: 6a5b ldr r3, [r3, #36] ; 0x24 - 804297a: f003 0302 and.w r3, r3, #2 - 804297e: 2b00 cmp r3, #0 - 8042980: d00a beq.n 8042998 + 8042972: 687b ldr r3, [r7, #4] + 8042974: 6a5b ldr r3, [r3, #36] ; 0x24 + 8042976: f003 0302 and.w r3, r3, #2 + 804297a: 2b00 cmp r3, #0 + 804297c: d00a beq.n 8042994 { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); - 8042982: 687b ldr r3, [r7, #4] - 8042984: 681b ldr r3, [r3, #0] - 8042986: 685b ldr r3, [r3, #4] - 8042988: f423 3180 bic.w r1, r3, #65536 ; 0x10000 + 804297e: 687b ldr r3, [r7, #4] + 8042980: 681b ldr r3, [r3, #0] + 8042982: 685b ldr r3, [r3, #4] + 8042984: f423 3180 bic.w r1, r3, #65536 ; 0x10000 + 8042988: 687b ldr r3, [r7, #4] + 804298a: 6ada ldr r2, [r3, #44] ; 0x2c 804298c: 687b ldr r3, [r7, #4] - 804298e: 6ada ldr r2, [r3, #44] ; 0x2c - 8042990: 687b ldr r3, [r7, #4] - 8042992: 681b ldr r3, [r3, #0] - 8042994: 430a orrs r2, r1 - 8042996: 605a str r2, [r3, #4] + 804298e: 681b ldr r3, [r3, #0] + 8042990: 430a orrs r2, r1 + 8042992: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) - 8042998: 687b ldr r3, [r7, #4] - 804299a: 6a5b ldr r3, [r3, #36] ; 0x24 - 804299c: f003 0304 and.w r3, r3, #4 - 80429a0: 2b00 cmp r3, #0 - 80429a2: d00a beq.n 80429ba + 8042994: 687b ldr r3, [r7, #4] + 8042996: 6a5b ldr r3, [r3, #36] ; 0x24 + 8042998: f003 0304 and.w r3, r3, #4 + 804299c: 2b00 cmp r3, #0 + 804299e: d00a beq.n 80429b6 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); - 80429a4: 687b ldr r3, [r7, #4] - 80429a6: 681b ldr r3, [r3, #0] - 80429a8: 685b ldr r3, [r3, #4] - 80429aa: f423 2180 bic.w r1, r3, #262144 ; 0x40000 + 80429a0: 687b ldr r3, [r7, #4] + 80429a2: 681b ldr r3, [r3, #0] + 80429a4: 685b ldr r3, [r3, #4] + 80429a6: f423 2180 bic.w r1, r3, #262144 ; 0x40000 + 80429aa: 687b ldr r3, [r7, #4] + 80429ac: 6b1a ldr r2, [r3, #48] ; 0x30 80429ae: 687b ldr r3, [r7, #4] - 80429b0: 6b1a ldr r2, [r3, #48] ; 0x30 - 80429b2: 687b ldr r3, [r7, #4] - 80429b4: 681b ldr r3, [r3, #0] - 80429b6: 430a orrs r2, r1 - 80429b8: 605a str r2, [r3, #4] + 80429b0: 681b ldr r3, [r3, #0] + 80429b2: 430a orrs r2, r1 + 80429b4: 605a str r2, [r3, #4] } /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) - 80429ba: 687b ldr r3, [r7, #4] - 80429bc: 6a5b ldr r3, [r3, #36] ; 0x24 - 80429be: f003 0308 and.w r3, r3, #8 - 80429c2: 2b00 cmp r3, #0 - 80429c4: d00a beq.n 80429dc + 80429b6: 687b ldr r3, [r7, #4] + 80429b8: 6a5b ldr r3, [r3, #36] ; 0x24 + 80429ba: f003 0308 and.w r3, r3, #8 + 80429be: 2b00 cmp r3, #0 + 80429c0: d00a beq.n 80429d8 { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); - 80429c6: 687b ldr r3, [r7, #4] - 80429c8: 681b ldr r3, [r3, #0] - 80429ca: 685b ldr r3, [r3, #4] - 80429cc: f423 4100 bic.w r1, r3, #32768 ; 0x8000 + 80429c2: 687b ldr r3, [r7, #4] + 80429c4: 681b ldr r3, [r3, #0] + 80429c6: 685b ldr r3, [r3, #4] + 80429c8: f423 4100 bic.w r1, r3, #32768 ; 0x8000 + 80429cc: 687b ldr r3, [r7, #4] + 80429ce: 6b5a ldr r2, [r3, #52] ; 0x34 80429d0: 687b ldr r3, [r7, #4] - 80429d2: 6b5a ldr r2, [r3, #52] ; 0x34 - 80429d4: 687b ldr r3, [r7, #4] - 80429d6: 681b ldr r3, [r3, #0] - 80429d8: 430a orrs r2, r1 - 80429da: 605a str r2, [r3, #4] + 80429d2: 681b ldr r3, [r3, #0] + 80429d4: 430a orrs r2, r1 + 80429d6: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) - 80429dc: 687b ldr r3, [r7, #4] - 80429de: 6a5b ldr r3, [r3, #36] ; 0x24 - 80429e0: f003 0310 and.w r3, r3, #16 - 80429e4: 2b00 cmp r3, #0 - 80429e6: d00a beq.n 80429fe + 80429d8: 687b ldr r3, [r7, #4] + 80429da: 6a5b ldr r3, [r3, #36] ; 0x24 + 80429dc: f003 0310 and.w r3, r3, #16 + 80429e0: 2b00 cmp r3, #0 + 80429e2: d00a beq.n 80429fa { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); - 80429e8: 687b ldr r3, [r7, #4] - 80429ea: 681b ldr r3, [r3, #0] - 80429ec: 689b ldr r3, [r3, #8] - 80429ee: f423 5180 bic.w r1, r3, #4096 ; 0x1000 + 80429e4: 687b ldr r3, [r7, #4] + 80429e6: 681b ldr r3, [r3, #0] + 80429e8: 689b ldr r3, [r3, #8] + 80429ea: f423 5180 bic.w r1, r3, #4096 ; 0x1000 + 80429ee: 687b ldr r3, [r7, #4] + 80429f0: 6b9a ldr r2, [r3, #56] ; 0x38 80429f2: 687b ldr r3, [r7, #4] - 80429f4: 6b9a ldr r2, [r3, #56] ; 0x38 - 80429f6: 687b ldr r3, [r7, #4] - 80429f8: 681b ldr r3, [r3, #0] - 80429fa: 430a orrs r2, r1 - 80429fc: 609a str r2, [r3, #8] + 80429f4: 681b ldr r3, [r3, #0] + 80429f6: 430a orrs r2, r1 + 80429f8: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) - 80429fe: 687b ldr r3, [r7, #4] - 8042a00: 6a5b ldr r3, [r3, #36] ; 0x24 - 8042a02: f003 0320 and.w r3, r3, #32 - 8042a06: 2b00 cmp r3, #0 - 8042a08: d00a beq.n 8042a20 + 80429fa: 687b ldr r3, [r7, #4] + 80429fc: 6a5b ldr r3, [r3, #36] ; 0x24 + 80429fe: f003 0320 and.w r3, r3, #32 + 8042a02: 2b00 cmp r3, #0 + 8042a04: d00a beq.n 8042a1c { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); - 8042a0a: 687b ldr r3, [r7, #4] - 8042a0c: 681b ldr r3, [r3, #0] - 8042a0e: 689b ldr r3, [r3, #8] - 8042a10: f423 5100 bic.w r1, r3, #8192 ; 0x2000 + 8042a06: 687b ldr r3, [r7, #4] + 8042a08: 681b ldr r3, [r3, #0] + 8042a0a: 689b ldr r3, [r3, #8] + 8042a0c: f423 5100 bic.w r1, r3, #8192 ; 0x2000 + 8042a10: 687b ldr r3, [r7, #4] + 8042a12: 6bda ldr r2, [r3, #60] ; 0x3c 8042a14: 687b ldr r3, [r7, #4] - 8042a16: 6bda ldr r2, [r3, #60] ; 0x3c - 8042a18: 687b ldr r3, [r7, #4] - 8042a1a: 681b ldr r3, [r3, #0] - 8042a1c: 430a orrs r2, r1 - 8042a1e: 609a str r2, [r3, #8] + 8042a16: 681b ldr r3, [r3, #0] + 8042a18: 430a orrs r2, r1 + 8042a1a: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) - 8042a20: 687b ldr r3, [r7, #4] - 8042a22: 6a5b ldr r3, [r3, #36] ; 0x24 - 8042a24: f003 0340 and.w r3, r3, #64 ; 0x40 - 8042a28: 2b00 cmp r3, #0 - 8042a2a: d01a beq.n 8042a62 + 8042a1c: 687b ldr r3, [r7, #4] + 8042a1e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8042a20: f003 0340 and.w r3, r3, #64 ; 0x40 + 8042a24: 2b00 cmp r3, #0 + 8042a26: d01a beq.n 8042a5e { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); - 8042a2c: 687b ldr r3, [r7, #4] - 8042a2e: 681b ldr r3, [r3, #0] - 8042a30: 685b ldr r3, [r3, #4] - 8042a32: f423 1180 bic.w r1, r3, #1048576 ; 0x100000 + 8042a28: 687b ldr r3, [r7, #4] + 8042a2a: 681b ldr r3, [r3, #0] + 8042a2c: 685b ldr r3, [r3, #4] + 8042a2e: f423 1180 bic.w r1, r3, #1048576 ; 0x100000 + 8042a32: 687b ldr r3, [r7, #4] + 8042a34: 6c1a ldr r2, [r3, #64] ; 0x40 8042a36: 687b ldr r3, [r7, #4] - 8042a38: 6c1a ldr r2, [r3, #64] ; 0x40 - 8042a3a: 687b ldr r3, [r7, #4] - 8042a3c: 681b ldr r3, [r3, #0] - 8042a3e: 430a orrs r2, r1 - 8042a40: 605a str r2, [r3, #4] + 8042a38: 681b ldr r3, [r3, #0] + 8042a3a: 430a orrs r2, r1 + 8042a3c: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) - 8042a42: 687b ldr r3, [r7, #4] - 8042a44: 6c1b ldr r3, [r3, #64] ; 0x40 - 8042a46: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 - 8042a4a: d10a bne.n 8042a62 + 8042a3e: 687b ldr r3, [r7, #4] + 8042a40: 6c1b ldr r3, [r3, #64] ; 0x40 + 8042a42: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 8042a46: d10a bne.n 8042a5e { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); - 8042a4c: 687b ldr r3, [r7, #4] - 8042a4e: 681b ldr r3, [r3, #0] - 8042a50: 685b ldr r3, [r3, #4] - 8042a52: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000 + 8042a48: 687b ldr r3, [r7, #4] + 8042a4a: 681b ldr r3, [r3, #0] + 8042a4c: 685b ldr r3, [r3, #4] + 8042a4e: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000 + 8042a52: 687b ldr r3, [r7, #4] + 8042a54: 6c5a ldr r2, [r3, #68] ; 0x44 8042a56: 687b ldr r3, [r7, #4] - 8042a58: 6c5a ldr r2, [r3, #68] ; 0x44 - 8042a5a: 687b ldr r3, [r7, #4] - 8042a5c: 681b ldr r3, [r3, #0] - 8042a5e: 430a orrs r2, r1 - 8042a60: 605a str r2, [r3, #4] + 8042a58: 681b ldr r3, [r3, #0] + 8042a5a: 430a orrs r2, r1 + 8042a5c: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) - 8042a62: 687b ldr r3, [r7, #4] - 8042a64: 6a5b ldr r3, [r3, #36] ; 0x24 - 8042a66: f003 0380 and.w r3, r3, #128 ; 0x80 - 8042a6a: 2b00 cmp r3, #0 - 8042a6c: d00a beq.n 8042a84 + 8042a5e: 687b ldr r3, [r7, #4] + 8042a60: 6a5b ldr r3, [r3, #36] ; 0x24 + 8042a62: f003 0380 and.w r3, r3, #128 ; 0x80 + 8042a66: 2b00 cmp r3, #0 + 8042a68: d00a beq.n 8042a80 { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); - 8042a6e: 687b ldr r3, [r7, #4] - 8042a70: 681b ldr r3, [r3, #0] - 8042a72: 685b ldr r3, [r3, #4] - 8042a74: f423 2100 bic.w r1, r3, #524288 ; 0x80000 + 8042a6a: 687b ldr r3, [r7, #4] + 8042a6c: 681b ldr r3, [r3, #0] + 8042a6e: 685b ldr r3, [r3, #4] + 8042a70: f423 2100 bic.w r1, r3, #524288 ; 0x80000 + 8042a74: 687b ldr r3, [r7, #4] + 8042a76: 6c9a ldr r2, [r3, #72] ; 0x48 8042a78: 687b ldr r3, [r7, #4] - 8042a7a: 6c9a ldr r2, [r3, #72] ; 0x48 - 8042a7c: 687b ldr r3, [r7, #4] - 8042a7e: 681b ldr r3, [r3, #0] - 8042a80: 430a orrs r2, r1 - 8042a82: 605a str r2, [r3, #4] + 8042a7a: 681b ldr r3, [r3, #0] + 8042a7c: 430a orrs r2, r1 + 8042a7e: 605a str r2, [r3, #4] } } - 8042a84: bf00 nop - 8042a86: 370c adds r7, #12 - 8042a88: 46bd mov sp, r7 - 8042a8a: f85d 7b04 ldr.w r7, [sp], #4 - 8042a8e: 4770 bx lr + 8042a80: bf00 nop + 8042a82: 370c adds r7, #12 + 8042a84: 46bd mov sp, r7 + 8042a86: f85d 7b04 ldr.w r7, [sp], #4 + 8042a8a: 4770 bx lr -08042a90 : +08042a8c : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { - 8042a90: b580 push {r7, lr} - 8042a92: b086 sub sp, #24 - 8042a94: af02 add r7, sp, #8 - 8042a96: 6078 str r0, [r7, #4] + 8042a8c: b580 push {r7, lr} + 8042a8e: b086 sub sp, #24 + 8042a90: af02 add r7, sp, #8 + 8042a92: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - 8042a98: 687b ldr r3, [r7, #4] - 8042a9a: 2200 movs r2, #0 - 8042a9c: f8c3 2080 str.w r2, [r3, #128] ; 0x80 + 8042a94: 687b ldr r3, [r7, #4] + 8042a96: 2200 movs r2, #0 + 8042a98: f8c3 2080 str.w r2, [r3, #128] ; 0x80 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - 8042aa0: f7fe f888 bl 8040bb4 - 8042aa4: 60f8 str r0, [r7, #12] + 8042a9c: f7fe f888 bl 8040bb0 + 8042aa0: 60f8 str r0, [r7, #12] /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - 8042aa6: 687b ldr r3, [r7, #4] - 8042aa8: 681b ldr r3, [r3, #0] - 8042aaa: 681b ldr r3, [r3, #0] - 8042aac: f003 0308 and.w r3, r3, #8 - 8042ab0: 2b08 cmp r3, #8 - 8042ab2: d10e bne.n 8042ad2 + 8042aa2: 687b ldr r3, [r7, #4] + 8042aa4: 681b ldr r3, [r3, #0] + 8042aa6: 681b ldr r3, [r3, #0] + 8042aa8: f003 0308 and.w r3, r3, #8 + 8042aac: 2b08 cmp r3, #8 + 8042aae: d10e bne.n 8042ace { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - 8042ab4: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 - 8042ab8: 9300 str r3, [sp, #0] - 8042aba: 68fb ldr r3, [r7, #12] - 8042abc: 2200 movs r2, #0 - 8042abe: f44f 1100 mov.w r1, #2097152 ; 0x200000 - 8042ac2: 6878 ldr r0, [r7, #4] - 8042ac4: f000 f82d bl 8042b22 - 8042ac8: 4603 mov r3, r0 - 8042aca: 2b00 cmp r3, #0 - 8042acc: d001 beq.n 8042ad2 + 8042ab0: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 + 8042ab4: 9300 str r3, [sp, #0] + 8042ab6: 68fb ldr r3, [r7, #12] + 8042ab8: 2200 movs r2, #0 + 8042aba: f44f 1100 mov.w r1, #2097152 ; 0x200000 + 8042abe: 6878 ldr r0, [r7, #4] + 8042ac0: f000 f82d bl 8042b1e + 8042ac4: 4603 mov r3, r0 + 8042ac6: 2b00 cmp r3, #0 + 8042ac8: d001 beq.n 8042ace { /* Timeout occurred */ return HAL_TIMEOUT; - 8042ace: 2303 movs r3, #3 - 8042ad0: e023 b.n 8042b1a + 8042aca: 2303 movs r3, #3 + 8042acc: e023 b.n 8042b16 } } #if defined(USART_ISR_REACK) /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - 8042ad2: 687b ldr r3, [r7, #4] - 8042ad4: 681b ldr r3, [r3, #0] - 8042ad6: 681b ldr r3, [r3, #0] - 8042ad8: f003 0304 and.w r3, r3, #4 - 8042adc: 2b04 cmp r3, #4 - 8042ade: d10e bne.n 8042afe + 8042ace: 687b ldr r3, [r7, #4] + 8042ad0: 681b ldr r3, [r3, #0] + 8042ad2: 681b ldr r3, [r3, #0] + 8042ad4: f003 0304 and.w r3, r3, #4 + 8042ad8: 2b04 cmp r3, #4 + 8042ada: d10e bne.n 8042afa { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - 8042ae0: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 - 8042ae4: 9300 str r3, [sp, #0] - 8042ae6: 68fb ldr r3, [r7, #12] - 8042ae8: 2200 movs r2, #0 - 8042aea: f44f 0180 mov.w r1, #4194304 ; 0x400000 - 8042aee: 6878 ldr r0, [r7, #4] - 8042af0: f000 f817 bl 8042b22 - 8042af4: 4603 mov r3, r0 - 8042af6: 2b00 cmp r3, #0 - 8042af8: d001 beq.n 8042afe + 8042adc: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 + 8042ae0: 9300 str r3, [sp, #0] + 8042ae2: 68fb ldr r3, [r7, #12] + 8042ae4: 2200 movs r2, #0 + 8042ae6: f44f 0180 mov.w r1, #4194304 ; 0x400000 + 8042aea: 6878 ldr r0, [r7, #4] + 8042aec: f000 f817 bl 8042b1e + 8042af0: 4603 mov r3, r0 + 8042af2: 2b00 cmp r3, #0 + 8042af4: d001 beq.n 8042afa { /* Timeout occurred */ return HAL_TIMEOUT; - 8042afa: 2303 movs r3, #3 - 8042afc: e00d b.n 8042b1a + 8042af6: 2303 movs r3, #3 + 8042af8: e00d b.n 8042b16 } } #endif /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; - 8042afe: 687b ldr r3, [r7, #4] - 8042b00: 2220 movs r2, #32 - 8042b02: 679a str r2, [r3, #120] ; 0x78 + 8042afa: 687b ldr r3, [r7, #4] + 8042afc: 2220 movs r2, #32 + 8042afe: 679a str r2, [r3, #120] ; 0x78 huart->RxState = HAL_UART_STATE_READY; - 8042b04: 687b ldr r3, [r7, #4] - 8042b06: 2220 movs r2, #32 - 8042b08: 67da str r2, [r3, #124] ; 0x7c + 8042b00: 687b ldr r3, [r7, #4] + 8042b02: 2220 movs r2, #32 + 8042b04: 67da str r2, [r3, #124] ; 0x7c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 8042b0a: 687b ldr r3, [r7, #4] - 8042b0c: 2200 movs r2, #0 - 8042b0e: 661a str r2, [r3, #96] ; 0x60 + 8042b06: 687b ldr r3, [r7, #4] + 8042b08: 2200 movs r2, #0 + 8042b0a: 661a str r2, [r3, #96] ; 0x60 __HAL_UNLOCK(huart); - 8042b10: 687b ldr r3, [r7, #4] - 8042b12: 2200 movs r2, #0 - 8042b14: f883 2074 strb.w r2, [r3, #116] ; 0x74 + 8042b0c: 687b ldr r3, [r7, #4] + 8042b0e: 2200 movs r2, #0 + 8042b10: f883 2074 strb.w r2, [r3, #116] ; 0x74 return HAL_OK; - 8042b18: 2300 movs r3, #0 + 8042b14: 2300 movs r3, #0 } - 8042b1a: 4618 mov r0, r3 - 8042b1c: 3710 adds r7, #16 - 8042b1e: 46bd mov sp, r7 - 8042b20: bd80 pop {r7, pc} + 8042b16: 4618 mov r0, r3 + 8042b18: 3710 adds r7, #16 + 8042b1a: 46bd mov sp, r7 + 8042b1c: bd80 pop {r7, pc} -08042b22 : +08042b1e : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { - 8042b22: b580 push {r7, lr} - 8042b24: b084 sub sp, #16 - 8042b26: af00 add r7, sp, #0 - 8042b28: 60f8 str r0, [r7, #12] - 8042b2a: 60b9 str r1, [r7, #8] - 8042b2c: 603b str r3, [r7, #0] - 8042b2e: 4613 mov r3, r2 - 8042b30: 71fb strb r3, [r7, #7] + 8042b1e: b580 push {r7, lr} + 8042b20: b084 sub sp, #16 + 8042b22: af00 add r7, sp, #0 + 8042b24: 60f8 str r0, [r7, #12] + 8042b26: 60b9 str r1, [r7, #8] + 8042b28: 603b str r3, [r7, #0] + 8042b2a: 4613 mov r3, r2 + 8042b2c: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - 8042b32: e05e b.n 8042bf2 + 8042b2e: e05e b.n 8042bee { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) - 8042b34: 69bb ldr r3, [r7, #24] - 8042b36: f1b3 3fff cmp.w r3, #4294967295 - 8042b3a: d05a beq.n 8042bf2 + 8042b30: 69bb ldr r3, [r7, #24] + 8042b32: f1b3 3fff cmp.w r3, #4294967295 + 8042b36: d05a beq.n 8042bee { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - 8042b3c: f7fe f83a bl 8040bb4 - 8042b40: 4602 mov r2, r0 - 8042b42: 683b ldr r3, [r7, #0] - 8042b44: 1ad3 subs r3, r2, r3 - 8042b46: 69ba ldr r2, [r7, #24] - 8042b48: 429a cmp r2, r3 - 8042b4a: d302 bcc.n 8042b52 - 8042b4c: 69bb ldr r3, [r7, #24] - 8042b4e: 2b00 cmp r3, #0 - 8042b50: d11b bne.n 8042b8a + 8042b38: f7fe f83a bl 8040bb0 + 8042b3c: 4602 mov r2, r0 + 8042b3e: 683b ldr r3, [r7, #0] + 8042b40: 1ad3 subs r3, r2, r3 + 8042b42: 69ba ldr r2, [r7, #24] + 8042b44: 429a cmp r2, r3 + 8042b46: d302 bcc.n 8042b4e + 8042b48: 69bb ldr r3, [r7, #24] + 8042b4a: 2b00 cmp r3, #0 + 8042b4c: d11b bne.n 8042b86 { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); - 8042b52: 68fb ldr r3, [r7, #12] - 8042b54: 681b ldr r3, [r3, #0] - 8042b56: 681a ldr r2, [r3, #0] - 8042b58: 68fb ldr r3, [r7, #12] - 8042b5a: 681b ldr r3, [r3, #0] - 8042b5c: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 - 8042b60: 601a str r2, [r3, #0] + 8042b4e: 68fb ldr r3, [r7, #12] + 8042b50: 681b ldr r3, [r3, #0] + 8042b52: 681a ldr r2, [r3, #0] + 8042b54: 68fb ldr r3, [r7, #12] + 8042b56: 681b ldr r3, [r3, #0] + 8042b58: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 + 8042b5c: 601a str r2, [r3, #0] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 8042b62: 68fb ldr r3, [r7, #12] - 8042b64: 681b ldr r3, [r3, #0] - 8042b66: 689a ldr r2, [r3, #8] - 8042b68: 68fb ldr r3, [r7, #12] - 8042b6a: 681b ldr r3, [r3, #0] - 8042b6c: f022 0201 bic.w r2, r2, #1 - 8042b70: 609a str r2, [r3, #8] + 8042b5e: 68fb ldr r3, [r7, #12] + 8042b60: 681b ldr r3, [r3, #0] + 8042b62: 689a ldr r2, [r3, #8] + 8042b64: 68fb ldr r3, [r7, #12] + 8042b66: 681b ldr r3, [r3, #0] + 8042b68: f022 0201 bic.w r2, r2, #1 + 8042b6c: 609a str r2, [r3, #8] huart->gState = HAL_UART_STATE_READY; - 8042b72: 68fb ldr r3, [r7, #12] - 8042b74: 2220 movs r2, #32 - 8042b76: 679a str r2, [r3, #120] ; 0x78 + 8042b6e: 68fb ldr r3, [r7, #12] + 8042b70: 2220 movs r2, #32 + 8042b72: 679a str r2, [r3, #120] ; 0x78 huart->RxState = HAL_UART_STATE_READY; - 8042b78: 68fb ldr r3, [r7, #12] - 8042b7a: 2220 movs r2, #32 - 8042b7c: 67da str r2, [r3, #124] ; 0x7c + 8042b74: 68fb ldr r3, [r7, #12] + 8042b76: 2220 movs r2, #32 + 8042b78: 67da str r2, [r3, #124] ; 0x7c __HAL_UNLOCK(huart); - 8042b7e: 68fb ldr r3, [r7, #12] - 8042b80: 2200 movs r2, #0 - 8042b82: f883 2074 strb.w r2, [r3, #116] ; 0x74 + 8042b7a: 68fb ldr r3, [r7, #12] + 8042b7c: 2200 movs r2, #0 + 8042b7e: f883 2074 strb.w r2, [r3, #116] ; 0x74 return HAL_TIMEOUT; - 8042b86: 2303 movs r3, #3 - 8042b88: e043 b.n 8042c12 + 8042b82: 2303 movs r3, #3 + 8042b84: e043 b.n 8042c0e } if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) - 8042b8a: 68fb ldr r3, [r7, #12] - 8042b8c: 681b ldr r3, [r3, #0] - 8042b8e: 681b ldr r3, [r3, #0] - 8042b90: f003 0304 and.w r3, r3, #4 - 8042b94: 2b00 cmp r3, #0 - 8042b96: d02c beq.n 8042bf2 + 8042b86: 68fb ldr r3, [r7, #12] + 8042b88: 681b ldr r3, [r3, #0] + 8042b8a: 681b ldr r3, [r3, #0] + 8042b8c: f003 0304 and.w r3, r3, #4 + 8042b90: 2b00 cmp r3, #0 + 8042b92: d02c beq.n 8042bee { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) - 8042b98: 68fb ldr r3, [r7, #12] - 8042b9a: 681b ldr r3, [r3, #0] - 8042b9c: 69db ldr r3, [r3, #28] - 8042b9e: f403 6300 and.w r3, r3, #2048 ; 0x800 - 8042ba2: f5b3 6f00 cmp.w r3, #2048 ; 0x800 - 8042ba6: d124 bne.n 8042bf2 + 8042b94: 68fb ldr r3, [r7, #12] + 8042b96: 681b ldr r3, [r3, #0] + 8042b98: 69db ldr r3, [r3, #28] + 8042b9a: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8042b9e: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 8042ba2: d124 bne.n 8042bee { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - 8042ba8: 68fb ldr r3, [r7, #12] - 8042baa: 681b ldr r3, [r3, #0] - 8042bac: f44f 6200 mov.w r2, #2048 ; 0x800 - 8042bb0: 621a str r2, [r3, #32] + 8042ba4: 68fb ldr r3, [r7, #12] + 8042ba6: 681b ldr r3, [r3, #0] + 8042ba8: f44f 6200 mov.w r2, #2048 ; 0x800 + 8042bac: 621a str r2, [r3, #32] /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); - 8042bb2: 68fb ldr r3, [r7, #12] - 8042bb4: 681b ldr r3, [r3, #0] - 8042bb6: 681a ldr r2, [r3, #0] - 8042bb8: 68fb ldr r3, [r7, #12] - 8042bba: 681b ldr r3, [r3, #0] - 8042bbc: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 - 8042bc0: 601a str r2, [r3, #0] + 8042bae: 68fb ldr r3, [r7, #12] + 8042bb0: 681b ldr r3, [r3, #0] + 8042bb2: 681a ldr r2, [r3, #0] + 8042bb4: 68fb ldr r3, [r7, #12] + 8042bb6: 681b ldr r3, [r3, #0] + 8042bb8: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 + 8042bbc: 601a str r2, [r3, #0] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 8042bc2: 68fb ldr r3, [r7, #12] - 8042bc4: 681b ldr r3, [r3, #0] - 8042bc6: 689a ldr r2, [r3, #8] - 8042bc8: 68fb ldr r3, [r7, #12] - 8042bca: 681b ldr r3, [r3, #0] - 8042bcc: f022 0201 bic.w r2, r2, #1 - 8042bd0: 609a str r2, [r3, #8] + 8042bbe: 68fb ldr r3, [r7, #12] + 8042bc0: 681b ldr r3, [r3, #0] + 8042bc2: 689a ldr r2, [r3, #8] + 8042bc4: 68fb ldr r3, [r7, #12] + 8042bc6: 681b ldr r3, [r3, #0] + 8042bc8: f022 0201 bic.w r2, r2, #1 + 8042bcc: 609a str r2, [r3, #8] huart->gState = HAL_UART_STATE_READY; - 8042bd2: 68fb ldr r3, [r7, #12] - 8042bd4: 2220 movs r2, #32 - 8042bd6: 679a str r2, [r3, #120] ; 0x78 + 8042bce: 68fb ldr r3, [r7, #12] + 8042bd0: 2220 movs r2, #32 + 8042bd2: 679a str r2, [r3, #120] ; 0x78 huart->RxState = HAL_UART_STATE_READY; - 8042bd8: 68fb ldr r3, [r7, #12] - 8042bda: 2220 movs r2, #32 - 8042bdc: 67da str r2, [r3, #124] ; 0x7c + 8042bd4: 68fb ldr r3, [r7, #12] + 8042bd6: 2220 movs r2, #32 + 8042bd8: 67da str r2, [r3, #124] ; 0x7c huart->ErrorCode = HAL_UART_ERROR_RTO; - 8042bde: 68fb ldr r3, [r7, #12] - 8042be0: 2220 movs r2, #32 - 8042be2: f8c3 2080 str.w r2, [r3, #128] ; 0x80 + 8042bda: 68fb ldr r3, [r7, #12] + 8042bdc: 2220 movs r2, #32 + 8042bde: f8c3 2080 str.w r2, [r3, #128] ; 0x80 /* Process Unlocked */ __HAL_UNLOCK(huart); - 8042be6: 68fb ldr r3, [r7, #12] - 8042be8: 2200 movs r2, #0 - 8042bea: f883 2074 strb.w r2, [r3, #116] ; 0x74 + 8042be2: 68fb ldr r3, [r7, #12] + 8042be4: 2200 movs r2, #0 + 8042be6: f883 2074 strb.w r2, [r3, #116] ; 0x74 return HAL_TIMEOUT; - 8042bee: 2303 movs r3, #3 - 8042bf0: e00f b.n 8042c12 + 8042bea: 2303 movs r3, #3 + 8042bec: e00f b.n 8042c0e while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - 8042bf2: 68fb ldr r3, [r7, #12] - 8042bf4: 681b ldr r3, [r3, #0] - 8042bf6: 69da ldr r2, [r3, #28] - 8042bf8: 68bb ldr r3, [r7, #8] - 8042bfa: 4013 ands r3, r2 - 8042bfc: 68ba ldr r2, [r7, #8] - 8042bfe: 429a cmp r2, r3 - 8042c00: bf0c ite eq - 8042c02: 2301 moveq r3, #1 - 8042c04: 2300 movne r3, #0 - 8042c06: b2db uxtb r3, r3 - 8042c08: 461a mov r2, r3 - 8042c0a: 79fb ldrb r3, [r7, #7] - 8042c0c: 429a cmp r2, r3 - 8042c0e: d091 beq.n 8042b34 + 8042bee: 68fb ldr r3, [r7, #12] + 8042bf0: 681b ldr r3, [r3, #0] + 8042bf2: 69da ldr r2, [r3, #28] + 8042bf4: 68bb ldr r3, [r7, #8] + 8042bf6: 4013 ands r3, r2 + 8042bf8: 68ba ldr r2, [r7, #8] + 8042bfa: 429a cmp r2, r3 + 8042bfc: bf0c ite eq + 8042bfe: 2301 moveq r3, #1 + 8042c00: 2300 movne r3, #0 + 8042c02: b2db uxtb r3, r3 + 8042c04: 461a mov r2, r3 + 8042c06: 79fb ldrb r3, [r7, #7] + 8042c08: 429a cmp r2, r3 + 8042c0a: d091 beq.n 8042b30 } } } } return HAL_OK; - 8042c10: 2300 movs r3, #0 + 8042c0c: 2300 movs r3, #0 } - 8042c12: 4618 mov r0, r3 - 8042c14: 3710 adds r7, #16 - 8042c16: 46bd mov sp, r7 - 8042c18: bd80 pop {r7, pc} + 8042c0e: 4618 mov r0, r3 + 8042c10: 3710 adds r7, #16 + 8042c12: 46bd mov sp, r7 + 8042c14: bd80 pop {r7, pc} ... -08042c1c <__errno>: - 8042c1c: 4b01 ldr r3, [pc, #4] ; (8042c24 <__errno+0x8>) - 8042c1e: 6818 ldr r0, [r3, #0] - 8042c20: 4770 bx lr - 8042c22: bf00 nop - 8042c24: 2000000c .word 0x2000000c - -08042c28 <__libc_init_array>: - 8042c28: b570 push {r4, r5, r6, lr} - 8042c2a: 4d0d ldr r5, [pc, #52] ; (8042c60 <__libc_init_array+0x38>) - 8042c2c: 4c0d ldr r4, [pc, #52] ; (8042c64 <__libc_init_array+0x3c>) - 8042c2e: 1b64 subs r4, r4, r5 - 8042c30: 10a4 asrs r4, r4, #2 - 8042c32: 2600 movs r6, #0 - 8042c34: 42a6 cmp r6, r4 - 8042c36: d109 bne.n 8042c4c <__libc_init_array+0x24> - 8042c38: 4d0b ldr r5, [pc, #44] ; (8042c68 <__libc_init_array+0x40>) - 8042c3a: 4c0c ldr r4, [pc, #48] ; (8042c6c <__libc_init_array+0x44>) - 8042c3c: f000 ff76 bl 8043b2c <_init> - 8042c40: 1b64 subs r4, r4, r5 - 8042c42: 10a4 asrs r4, r4, #2 - 8042c44: 2600 movs r6, #0 - 8042c46: 42a6 cmp r6, r4 - 8042c48: d105 bne.n 8042c56 <__libc_init_array+0x2e> - 8042c4a: bd70 pop {r4, r5, r6, pc} - 8042c4c: f855 3b04 ldr.w r3, [r5], #4 - 8042c50: 4798 blx r3 - 8042c52: 3601 adds r6, #1 - 8042c54: e7ee b.n 8042c34 <__libc_init_array+0xc> - 8042c56: f855 3b04 ldr.w r3, [r5], #4 - 8042c5a: 4798 blx r3 - 8042c5c: 3601 adds r6, #1 - 8042c5e: e7f2 b.n 8042c46 <__libc_init_array+0x1e> - 8042c60: 08043c1c .word 0x08043c1c - 8042c64: 08043c1c .word 0x08043c1c +08042c18 <__errno>: + 8042c18: 4b01 ldr r3, [pc, #4] ; (8042c20 <__errno+0x8>) + 8042c1a: 6818 ldr r0, [r3, #0] + 8042c1c: 4770 bx lr + 8042c1e: bf00 nop + 8042c20: 2000000c .word 0x2000000c + +08042c24 <__libc_init_array>: + 8042c24: b570 push {r4, r5, r6, lr} + 8042c26: 4d0d ldr r5, [pc, #52] ; (8042c5c <__libc_init_array+0x38>) + 8042c28: 4c0d ldr r4, [pc, #52] ; (8042c60 <__libc_init_array+0x3c>) + 8042c2a: 1b64 subs r4, r4, r5 + 8042c2c: 10a4 asrs r4, r4, #2 + 8042c2e: 2600 movs r6, #0 + 8042c30: 42a6 cmp r6, r4 + 8042c32: d109 bne.n 8042c48 <__libc_init_array+0x24> + 8042c34: 4d0b ldr r5, [pc, #44] ; (8042c64 <__libc_init_array+0x40>) + 8042c36: 4c0c ldr r4, [pc, #48] ; (8042c68 <__libc_init_array+0x44>) + 8042c38: f000 ff76 bl 8043b28 <_init> + 8042c3c: 1b64 subs r4, r4, r5 + 8042c3e: 10a4 asrs r4, r4, #2 + 8042c40: 2600 movs r6, #0 + 8042c42: 42a6 cmp r6, r4 + 8042c44: d105 bne.n 8042c52 <__libc_init_array+0x2e> + 8042c46: bd70 pop {r4, r5, r6, pc} + 8042c48: f855 3b04 ldr.w r3, [r5], #4 + 8042c4c: 4798 blx r3 + 8042c4e: 3601 adds r6, #1 + 8042c50: e7ee b.n 8042c30 <__libc_init_array+0xc> + 8042c52: f855 3b04 ldr.w r3, [r5], #4 + 8042c56: 4798 blx r3 + 8042c58: 3601 adds r6, #1 + 8042c5a: e7f2 b.n 8042c42 <__libc_init_array+0x1e> + 8042c5c: 08043c18 .word 0x08043c18 + 8042c60: 08043c18 .word 0x08043c18 + 8042c64: 08043c18 .word 0x08043c18 8042c68: 08043c1c .word 0x08043c1c - 8042c6c: 08043c20 .word 0x08043c20 - -08042c70 : - 8042c70: 4402 add r2, r0 - 8042c72: 4603 mov r3, r0 - 8042c74: 4293 cmp r3, r2 - 8042c76: d100 bne.n 8042c7a - 8042c78: 4770 bx lr - 8042c7a: f803 1b01 strb.w r1, [r3], #1 - 8042c7e: e7f9 b.n 8042c74 - -08042c80 : - 8042c80: b40f push {r0, r1, r2, r3} - 8042c82: 4b0a ldr r3, [pc, #40] ; (8042cac ) - 8042c84: b513 push {r0, r1, r4, lr} - 8042c86: 681c ldr r4, [r3, #0] - 8042c88: b124 cbz r4, 8042c94 - 8042c8a: 69a3 ldr r3, [r4, #24] - 8042c8c: b913 cbnz r3, 8042c94 - 8042c8e: 4620 mov r0, r4 - 8042c90: f000 f866 bl 8042d60 <__sinit> - 8042c94: ab05 add r3, sp, #20 - 8042c96: 9a04 ldr r2, [sp, #16] - 8042c98: 68a1 ldr r1, [r4, #8] - 8042c9a: 9301 str r3, [sp, #4] - 8042c9c: 4620 mov r0, r4 - 8042c9e: f000 f983 bl 8042fa8 <_vfiprintf_r> - 8042ca2: b002 add sp, #8 - 8042ca4: e8bd 4010 ldmia.w sp!, {r4, lr} - 8042ca8: b004 add sp, #16 - 8042caa: 4770 bx lr - 8042cac: 2000000c .word 0x2000000c - -08042cb0 : - 8042cb0: 2300 movs r3, #0 - 8042cb2: b510 push {r4, lr} - 8042cb4: 4604 mov r4, r0 - 8042cb6: e9c0 3300 strd r3, r3, [r0] - 8042cba: e9c0 3304 strd r3, r3, [r0, #16] - 8042cbe: 6083 str r3, [r0, #8] - 8042cc0: 8181 strh r1, [r0, #12] - 8042cc2: 6643 str r3, [r0, #100] ; 0x64 - 8042cc4: 81c2 strh r2, [r0, #14] - 8042cc6: 6183 str r3, [r0, #24] - 8042cc8: 4619 mov r1, r3 - 8042cca: 2208 movs r2, #8 - 8042ccc: 305c adds r0, #92 ; 0x5c - 8042cce: f7ff ffcf bl 8042c70 - 8042cd2: 4b05 ldr r3, [pc, #20] ; (8042ce8 ) - 8042cd4: 6263 str r3, [r4, #36] ; 0x24 - 8042cd6: 4b05 ldr r3, [pc, #20] ; (8042cec ) - 8042cd8: 62a3 str r3, [r4, #40] ; 0x28 - 8042cda: 4b05 ldr r3, [pc, #20] ; (8042cf0 ) - 8042cdc: 62e3 str r3, [r4, #44] ; 0x2c - 8042cde: 4b05 ldr r3, [pc, #20] ; (8042cf4 ) - 8042ce0: 6224 str r4, [r4, #32] - 8042ce2: 6323 str r3, [r4, #48] ; 0x30 - 8042ce4: bd10 pop {r4, pc} - 8042ce6: bf00 nop - 8042ce8: 08043551 .word 0x08043551 - 8042cec: 08043573 .word 0x08043573 - 8042cf0: 080435ab .word 0x080435ab - 8042cf4: 080435cf .word 0x080435cf - -08042cf8 <_cleanup_r>: - 8042cf8: 4901 ldr r1, [pc, #4] ; (8042d00 <_cleanup_r+0x8>) - 8042cfa: f000 b8af b.w 8042e5c <_fwalk_reent> - 8042cfe: bf00 nop - 8042d00: 080438a9 .word 0x080438a9 - -08042d04 <__sfmoreglue>: - 8042d04: b570 push {r4, r5, r6, lr} - 8042d06: 1e4a subs r2, r1, #1 - 8042d08: 2568 movs r5, #104 ; 0x68 - 8042d0a: 4355 muls r5, r2 - 8042d0c: 460e mov r6, r1 - 8042d0e: f105 0174 add.w r1, r5, #116 ; 0x74 - 8042d12: f000 f8c5 bl 8042ea0 <_malloc_r> - 8042d16: 4604 mov r4, r0 - 8042d18: b140 cbz r0, 8042d2c <__sfmoreglue+0x28> - 8042d1a: 2100 movs r1, #0 - 8042d1c: e9c0 1600 strd r1, r6, [r0] - 8042d20: 300c adds r0, #12 - 8042d22: 60a0 str r0, [r4, #8] - 8042d24: f105 0268 add.w r2, r5, #104 ; 0x68 - 8042d28: f7ff ffa2 bl 8042c70 - 8042d2c: 4620 mov r0, r4 - 8042d2e: bd70 pop {r4, r5, r6, pc} - -08042d30 <__sfp_lock_acquire>: - 8042d30: 4801 ldr r0, [pc, #4] ; (8042d38 <__sfp_lock_acquire+0x8>) - 8042d32: f000 b8b3 b.w 8042e9c <__retarget_lock_acquire_recursive> - 8042d36: bf00 nop - 8042d38: 20000128 .word 0x20000128 - -08042d3c <__sfp_lock_release>: - 8042d3c: 4801 ldr r0, [pc, #4] ; (8042d44 <__sfp_lock_release+0x8>) - 8042d3e: f000 b8ae b.w 8042e9e <__retarget_lock_release_recursive> - 8042d42: bf00 nop - 8042d44: 20000128 .word 0x20000128 - -08042d48 <__sinit_lock_acquire>: - 8042d48: 4801 ldr r0, [pc, #4] ; (8042d50 <__sinit_lock_acquire+0x8>) - 8042d4a: f000 b8a7 b.w 8042e9c <__retarget_lock_acquire_recursive> - 8042d4e: bf00 nop - 8042d50: 20000123 .word 0x20000123 - -08042d54 <__sinit_lock_release>: - 8042d54: 4801 ldr r0, [pc, #4] ; (8042d5c <__sinit_lock_release+0x8>) - 8042d56: f000 b8a2 b.w 8042e9e <__retarget_lock_release_recursive> - 8042d5a: bf00 nop - 8042d5c: 20000123 .word 0x20000123 - -08042d60 <__sinit>: - 8042d60: b510 push {r4, lr} - 8042d62: 4604 mov r4, r0 - 8042d64: f7ff fff0 bl 8042d48 <__sinit_lock_acquire> - 8042d68: 69a3 ldr r3, [r4, #24] - 8042d6a: b11b cbz r3, 8042d74 <__sinit+0x14> - 8042d6c: e8bd 4010 ldmia.w sp!, {r4, lr} - 8042d70: f7ff bff0 b.w 8042d54 <__sinit_lock_release> - 8042d74: e9c4 3312 strd r3, r3, [r4, #72] ; 0x48 - 8042d78: 6523 str r3, [r4, #80] ; 0x50 - 8042d7a: 4b13 ldr r3, [pc, #76] ; (8042dc8 <__sinit+0x68>) - 8042d7c: 4a13 ldr r2, [pc, #76] ; (8042dcc <__sinit+0x6c>) - 8042d7e: 681b ldr r3, [r3, #0] - 8042d80: 62a2 str r2, [r4, #40] ; 0x28 - 8042d82: 42a3 cmp r3, r4 - 8042d84: bf04 itt eq - 8042d86: 2301 moveq r3, #1 - 8042d88: 61a3 streq r3, [r4, #24] - 8042d8a: 4620 mov r0, r4 - 8042d8c: f000 f820 bl 8042dd0 <__sfp> - 8042d90: 6060 str r0, [r4, #4] - 8042d92: 4620 mov r0, r4 - 8042d94: f000 f81c bl 8042dd0 <__sfp> - 8042d98: 60a0 str r0, [r4, #8] - 8042d9a: 4620 mov r0, r4 - 8042d9c: f000 f818 bl 8042dd0 <__sfp> - 8042da0: 2200 movs r2, #0 - 8042da2: 60e0 str r0, [r4, #12] - 8042da4: 2104 movs r1, #4 - 8042da6: 6860 ldr r0, [r4, #4] - 8042da8: f7ff ff82 bl 8042cb0 - 8042dac: 68a0 ldr r0, [r4, #8] - 8042dae: 2201 movs r2, #1 - 8042db0: 2109 movs r1, #9 - 8042db2: f7ff ff7d bl 8042cb0 - 8042db6: 68e0 ldr r0, [r4, #12] - 8042db8: 2202 movs r2, #2 - 8042dba: 2112 movs r1, #18 - 8042dbc: f7ff ff78 bl 8042cb0 - 8042dc0: 2301 movs r3, #1 - 8042dc2: 61a3 str r3, [r4, #24] - 8042dc4: e7d2 b.n 8042d6c <__sinit+0xc> - 8042dc6: bf00 nop - 8042dc8: 08043b7c .word 0x08043b7c - 8042dcc: 08042cf9 .word 0x08042cf9 - -08042dd0 <__sfp>: - 8042dd0: b5f8 push {r3, r4, r5, r6, r7, lr} - 8042dd2: 4607 mov r7, r0 - 8042dd4: f7ff ffac bl 8042d30 <__sfp_lock_acquire> - 8042dd8: 4b1e ldr r3, [pc, #120] ; (8042e54 <__sfp+0x84>) - 8042dda: 681e ldr r6, [r3, #0] - 8042ddc: 69b3 ldr r3, [r6, #24] - 8042dde: b913 cbnz r3, 8042de6 <__sfp+0x16> - 8042de0: 4630 mov r0, r6 - 8042de2: f7ff ffbd bl 8042d60 <__sinit> - 8042de6: 3648 adds r6, #72 ; 0x48 - 8042de8: e9d6 3401 ldrd r3, r4, [r6, #4] - 8042dec: 3b01 subs r3, #1 - 8042dee: d503 bpl.n 8042df8 <__sfp+0x28> - 8042df0: 6833 ldr r3, [r6, #0] - 8042df2: b30b cbz r3, 8042e38 <__sfp+0x68> - 8042df4: 6836 ldr r6, [r6, #0] - 8042df6: e7f7 b.n 8042de8 <__sfp+0x18> - 8042df8: f9b4 500c ldrsh.w r5, [r4, #12] - 8042dfc: b9d5 cbnz r5, 8042e34 <__sfp+0x64> - 8042dfe: 4b16 ldr r3, [pc, #88] ; (8042e58 <__sfp+0x88>) - 8042e00: 60e3 str r3, [r4, #12] - 8042e02: f104 0058 add.w r0, r4, #88 ; 0x58 - 8042e06: 6665 str r5, [r4, #100] ; 0x64 - 8042e08: f000 f847 bl 8042e9a <__retarget_lock_init_recursive> - 8042e0c: f7ff ff96 bl 8042d3c <__sfp_lock_release> - 8042e10: e9c4 5501 strd r5, r5, [r4, #4] - 8042e14: e9c4 5504 strd r5, r5, [r4, #16] - 8042e18: 6025 str r5, [r4, #0] - 8042e1a: 61a5 str r5, [r4, #24] - 8042e1c: 2208 movs r2, #8 - 8042e1e: 4629 mov r1, r5 - 8042e20: f104 005c add.w r0, r4, #92 ; 0x5c - 8042e24: f7ff ff24 bl 8042c70 - 8042e28: e9c4 550d strd r5, r5, [r4, #52] ; 0x34 - 8042e2c: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48 - 8042e30: 4620 mov r0, r4 - 8042e32: bdf8 pop {r3, r4, r5, r6, r7, pc} - 8042e34: 3468 adds r4, #104 ; 0x68 - 8042e36: e7d9 b.n 8042dec <__sfp+0x1c> - 8042e38: 2104 movs r1, #4 - 8042e3a: 4638 mov r0, r7 - 8042e3c: f7ff ff62 bl 8042d04 <__sfmoreglue> - 8042e40: 4604 mov r4, r0 - 8042e42: 6030 str r0, [r6, #0] - 8042e44: 2800 cmp r0, #0 - 8042e46: d1d5 bne.n 8042df4 <__sfp+0x24> - 8042e48: f7ff ff78 bl 8042d3c <__sfp_lock_release> - 8042e4c: 230c movs r3, #12 - 8042e4e: 603b str r3, [r7, #0] - 8042e50: e7ee b.n 8042e30 <__sfp+0x60> - 8042e52: bf00 nop - 8042e54: 08043b7c .word 0x08043b7c - 8042e58: ffff0001 .word 0xffff0001 - -08042e5c <_fwalk_reent>: - 8042e5c: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} - 8042e60: 4606 mov r6, r0 - 8042e62: 4688 mov r8, r1 - 8042e64: f100 0448 add.w r4, r0, #72 ; 0x48 - 8042e68: 2700 movs r7, #0 - 8042e6a: e9d4 9501 ldrd r9, r5, [r4, #4] - 8042e6e: f1b9 0901 subs.w r9, r9, #1 - 8042e72: d505 bpl.n 8042e80 <_fwalk_reent+0x24> - 8042e74: 6824 ldr r4, [r4, #0] - 8042e76: 2c00 cmp r4, #0 - 8042e78: d1f7 bne.n 8042e6a <_fwalk_reent+0xe> - 8042e7a: 4638 mov r0, r7 - 8042e7c: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} - 8042e80: 89ab ldrh r3, [r5, #12] - 8042e82: 2b01 cmp r3, #1 - 8042e84: d907 bls.n 8042e96 <_fwalk_reent+0x3a> - 8042e86: f9b5 300e ldrsh.w r3, [r5, #14] - 8042e8a: 3301 adds r3, #1 - 8042e8c: d003 beq.n 8042e96 <_fwalk_reent+0x3a> - 8042e8e: 4629 mov r1, r5 - 8042e90: 4630 mov r0, r6 - 8042e92: 47c0 blx r8 - 8042e94: 4307 orrs r7, r0 - 8042e96: 3568 adds r5, #104 ; 0x68 - 8042e98: e7e9 b.n 8042e6e <_fwalk_reent+0x12> - -08042e9a <__retarget_lock_init_recursive>: + +08042c6c : + 8042c6c: 4402 add r2, r0 + 8042c6e: 4603 mov r3, r0 + 8042c70: 4293 cmp r3, r2 + 8042c72: d100 bne.n 8042c76 + 8042c74: 4770 bx lr + 8042c76: f803 1b01 strb.w r1, [r3], #1 + 8042c7a: e7f9 b.n 8042c70 + +08042c7c : + 8042c7c: b40f push {r0, r1, r2, r3} + 8042c7e: 4b0a ldr r3, [pc, #40] ; (8042ca8 ) + 8042c80: b513 push {r0, r1, r4, lr} + 8042c82: 681c ldr r4, [r3, #0] + 8042c84: b124 cbz r4, 8042c90 + 8042c86: 69a3 ldr r3, [r4, #24] + 8042c88: b913 cbnz r3, 8042c90 + 8042c8a: 4620 mov r0, r4 + 8042c8c: f000 f866 bl 8042d5c <__sinit> + 8042c90: ab05 add r3, sp, #20 + 8042c92: 9a04 ldr r2, [sp, #16] + 8042c94: 68a1 ldr r1, [r4, #8] + 8042c96: 9301 str r3, [sp, #4] + 8042c98: 4620 mov r0, r4 + 8042c9a: f000 f983 bl 8042fa4 <_vfiprintf_r> + 8042c9e: b002 add sp, #8 + 8042ca0: e8bd 4010 ldmia.w sp!, {r4, lr} + 8042ca4: b004 add sp, #16 + 8042ca6: 4770 bx lr + 8042ca8: 2000000c .word 0x2000000c + +08042cac : + 8042cac: 2300 movs r3, #0 + 8042cae: b510 push {r4, lr} + 8042cb0: 4604 mov r4, r0 + 8042cb2: e9c0 3300 strd r3, r3, [r0] + 8042cb6: e9c0 3304 strd r3, r3, [r0, #16] + 8042cba: 6083 str r3, [r0, #8] + 8042cbc: 8181 strh r1, [r0, #12] + 8042cbe: 6643 str r3, [r0, #100] ; 0x64 + 8042cc0: 81c2 strh r2, [r0, #14] + 8042cc2: 6183 str r3, [r0, #24] + 8042cc4: 4619 mov r1, r3 + 8042cc6: 2208 movs r2, #8 + 8042cc8: 305c adds r0, #92 ; 0x5c + 8042cca: f7ff ffcf bl 8042c6c + 8042cce: 4b05 ldr r3, [pc, #20] ; (8042ce4 ) + 8042cd0: 6263 str r3, [r4, #36] ; 0x24 + 8042cd2: 4b05 ldr r3, [pc, #20] ; (8042ce8 ) + 8042cd4: 62a3 str r3, [r4, #40] ; 0x28 + 8042cd6: 4b05 ldr r3, [pc, #20] ; (8042cec ) + 8042cd8: 62e3 str r3, [r4, #44] ; 0x2c + 8042cda: 4b05 ldr r3, [pc, #20] ; (8042cf0 ) + 8042cdc: 6224 str r4, [r4, #32] + 8042cde: 6323 str r3, [r4, #48] ; 0x30 + 8042ce0: bd10 pop {r4, pc} + 8042ce2: bf00 nop + 8042ce4: 0804354d .word 0x0804354d + 8042ce8: 0804356f .word 0x0804356f + 8042cec: 080435a7 .word 0x080435a7 + 8042cf0: 080435cb .word 0x080435cb + +08042cf4 <_cleanup_r>: + 8042cf4: 4901 ldr r1, [pc, #4] ; (8042cfc <_cleanup_r+0x8>) + 8042cf6: f000 b8af b.w 8042e58 <_fwalk_reent> + 8042cfa: bf00 nop + 8042cfc: 080438a5 .word 0x080438a5 + +08042d00 <__sfmoreglue>: + 8042d00: b570 push {r4, r5, r6, lr} + 8042d02: 1e4a subs r2, r1, #1 + 8042d04: 2568 movs r5, #104 ; 0x68 + 8042d06: 4355 muls r5, r2 + 8042d08: 460e mov r6, r1 + 8042d0a: f105 0174 add.w r1, r5, #116 ; 0x74 + 8042d0e: f000 f8c5 bl 8042e9c <_malloc_r> + 8042d12: 4604 mov r4, r0 + 8042d14: b140 cbz r0, 8042d28 <__sfmoreglue+0x28> + 8042d16: 2100 movs r1, #0 + 8042d18: e9c0 1600 strd r1, r6, [r0] + 8042d1c: 300c adds r0, #12 + 8042d1e: 60a0 str r0, [r4, #8] + 8042d20: f105 0268 add.w r2, r5, #104 ; 0x68 + 8042d24: f7ff ffa2 bl 8042c6c + 8042d28: 4620 mov r0, r4 + 8042d2a: bd70 pop {r4, r5, r6, pc} + +08042d2c <__sfp_lock_acquire>: + 8042d2c: 4801 ldr r0, [pc, #4] ; (8042d34 <__sfp_lock_acquire+0x8>) + 8042d2e: f000 b8b3 b.w 8042e98 <__retarget_lock_acquire_recursive> + 8042d32: bf00 nop + 8042d34: 20000128 .word 0x20000128 + +08042d38 <__sfp_lock_release>: + 8042d38: 4801 ldr r0, [pc, #4] ; (8042d40 <__sfp_lock_release+0x8>) + 8042d3a: f000 b8ae b.w 8042e9a <__retarget_lock_release_recursive> + 8042d3e: bf00 nop + 8042d40: 20000128 .word 0x20000128 + +08042d44 <__sinit_lock_acquire>: + 8042d44: 4801 ldr r0, [pc, #4] ; (8042d4c <__sinit_lock_acquire+0x8>) + 8042d46: f000 b8a7 b.w 8042e98 <__retarget_lock_acquire_recursive> + 8042d4a: bf00 nop + 8042d4c: 20000123 .word 0x20000123 + +08042d50 <__sinit_lock_release>: + 8042d50: 4801 ldr r0, [pc, #4] ; (8042d58 <__sinit_lock_release+0x8>) + 8042d52: f000 b8a2 b.w 8042e9a <__retarget_lock_release_recursive> + 8042d56: bf00 nop + 8042d58: 20000123 .word 0x20000123 + +08042d5c <__sinit>: + 8042d5c: b510 push {r4, lr} + 8042d5e: 4604 mov r4, r0 + 8042d60: f7ff fff0 bl 8042d44 <__sinit_lock_acquire> + 8042d64: 69a3 ldr r3, [r4, #24] + 8042d66: b11b cbz r3, 8042d70 <__sinit+0x14> + 8042d68: e8bd 4010 ldmia.w sp!, {r4, lr} + 8042d6c: f7ff bff0 b.w 8042d50 <__sinit_lock_release> + 8042d70: e9c4 3312 strd r3, r3, [r4, #72] ; 0x48 + 8042d74: 6523 str r3, [r4, #80] ; 0x50 + 8042d76: 4b13 ldr r3, [pc, #76] ; (8042dc4 <__sinit+0x68>) + 8042d78: 4a13 ldr r2, [pc, #76] ; (8042dc8 <__sinit+0x6c>) + 8042d7a: 681b ldr r3, [r3, #0] + 8042d7c: 62a2 str r2, [r4, #40] ; 0x28 + 8042d7e: 42a3 cmp r3, r4 + 8042d80: bf04 itt eq + 8042d82: 2301 moveq r3, #1 + 8042d84: 61a3 streq r3, [r4, #24] + 8042d86: 4620 mov r0, r4 + 8042d88: f000 f820 bl 8042dcc <__sfp> + 8042d8c: 6060 str r0, [r4, #4] + 8042d8e: 4620 mov r0, r4 + 8042d90: f000 f81c bl 8042dcc <__sfp> + 8042d94: 60a0 str r0, [r4, #8] + 8042d96: 4620 mov r0, r4 + 8042d98: f000 f818 bl 8042dcc <__sfp> + 8042d9c: 2200 movs r2, #0 + 8042d9e: 60e0 str r0, [r4, #12] + 8042da0: 2104 movs r1, #4 + 8042da2: 6860 ldr r0, [r4, #4] + 8042da4: f7ff ff82 bl 8042cac + 8042da8: 68a0 ldr r0, [r4, #8] + 8042daa: 2201 movs r2, #1 + 8042dac: 2109 movs r1, #9 + 8042dae: f7ff ff7d bl 8042cac + 8042db2: 68e0 ldr r0, [r4, #12] + 8042db4: 2202 movs r2, #2 + 8042db6: 2112 movs r1, #18 + 8042db8: f7ff ff78 bl 8042cac + 8042dbc: 2301 movs r3, #1 + 8042dbe: 61a3 str r3, [r4, #24] + 8042dc0: e7d2 b.n 8042d68 <__sinit+0xc> + 8042dc2: bf00 nop + 8042dc4: 08043b78 .word 0x08043b78 + 8042dc8: 08042cf5 .word 0x08042cf5 + +08042dcc <__sfp>: + 8042dcc: b5f8 push {r3, r4, r5, r6, r7, lr} + 8042dce: 4607 mov r7, r0 + 8042dd0: f7ff ffac bl 8042d2c <__sfp_lock_acquire> + 8042dd4: 4b1e ldr r3, [pc, #120] ; (8042e50 <__sfp+0x84>) + 8042dd6: 681e ldr r6, [r3, #0] + 8042dd8: 69b3 ldr r3, [r6, #24] + 8042dda: b913 cbnz r3, 8042de2 <__sfp+0x16> + 8042ddc: 4630 mov r0, r6 + 8042dde: f7ff ffbd bl 8042d5c <__sinit> + 8042de2: 3648 adds r6, #72 ; 0x48 + 8042de4: e9d6 3401 ldrd r3, r4, [r6, #4] + 8042de8: 3b01 subs r3, #1 + 8042dea: d503 bpl.n 8042df4 <__sfp+0x28> + 8042dec: 6833 ldr r3, [r6, #0] + 8042dee: b30b cbz r3, 8042e34 <__sfp+0x68> + 8042df0: 6836 ldr r6, [r6, #0] + 8042df2: e7f7 b.n 8042de4 <__sfp+0x18> + 8042df4: f9b4 500c ldrsh.w r5, [r4, #12] + 8042df8: b9d5 cbnz r5, 8042e30 <__sfp+0x64> + 8042dfa: 4b16 ldr r3, [pc, #88] ; (8042e54 <__sfp+0x88>) + 8042dfc: 60e3 str r3, [r4, #12] + 8042dfe: f104 0058 add.w r0, r4, #88 ; 0x58 + 8042e02: 6665 str r5, [r4, #100] ; 0x64 + 8042e04: f000 f847 bl 8042e96 <__retarget_lock_init_recursive> + 8042e08: f7ff ff96 bl 8042d38 <__sfp_lock_release> + 8042e0c: e9c4 5501 strd r5, r5, [r4, #4] + 8042e10: e9c4 5504 strd r5, r5, [r4, #16] + 8042e14: 6025 str r5, [r4, #0] + 8042e16: 61a5 str r5, [r4, #24] + 8042e18: 2208 movs r2, #8 + 8042e1a: 4629 mov r1, r5 + 8042e1c: f104 005c add.w r0, r4, #92 ; 0x5c + 8042e20: f7ff ff24 bl 8042c6c + 8042e24: e9c4 550d strd r5, r5, [r4, #52] ; 0x34 + 8042e28: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48 + 8042e2c: 4620 mov r0, r4 + 8042e2e: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8042e30: 3468 adds r4, #104 ; 0x68 + 8042e32: e7d9 b.n 8042de8 <__sfp+0x1c> + 8042e34: 2104 movs r1, #4 + 8042e36: 4638 mov r0, r7 + 8042e38: f7ff ff62 bl 8042d00 <__sfmoreglue> + 8042e3c: 4604 mov r4, r0 + 8042e3e: 6030 str r0, [r6, #0] + 8042e40: 2800 cmp r0, #0 + 8042e42: d1d5 bne.n 8042df0 <__sfp+0x24> + 8042e44: f7ff ff78 bl 8042d38 <__sfp_lock_release> + 8042e48: 230c movs r3, #12 + 8042e4a: 603b str r3, [r7, #0] + 8042e4c: e7ee b.n 8042e2c <__sfp+0x60> + 8042e4e: bf00 nop + 8042e50: 08043b78 .word 0x08043b78 + 8042e54: ffff0001 .word 0xffff0001 + +08042e58 <_fwalk_reent>: + 8042e58: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 8042e5c: 4606 mov r6, r0 + 8042e5e: 4688 mov r8, r1 + 8042e60: f100 0448 add.w r4, r0, #72 ; 0x48 + 8042e64: 2700 movs r7, #0 + 8042e66: e9d4 9501 ldrd r9, r5, [r4, #4] + 8042e6a: f1b9 0901 subs.w r9, r9, #1 + 8042e6e: d505 bpl.n 8042e7c <_fwalk_reent+0x24> + 8042e70: 6824 ldr r4, [r4, #0] + 8042e72: 2c00 cmp r4, #0 + 8042e74: d1f7 bne.n 8042e66 <_fwalk_reent+0xe> + 8042e76: 4638 mov r0, r7 + 8042e78: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 8042e7c: 89ab ldrh r3, [r5, #12] + 8042e7e: 2b01 cmp r3, #1 + 8042e80: d907 bls.n 8042e92 <_fwalk_reent+0x3a> + 8042e82: f9b5 300e ldrsh.w r3, [r5, #14] + 8042e86: 3301 adds r3, #1 + 8042e88: d003 beq.n 8042e92 <_fwalk_reent+0x3a> + 8042e8a: 4629 mov r1, r5 + 8042e8c: 4630 mov r0, r6 + 8042e8e: 47c0 blx r8 + 8042e90: 4307 orrs r7, r0 + 8042e92: 3568 adds r5, #104 ; 0x68 + 8042e94: e7e9 b.n 8042e6a <_fwalk_reent+0x12> + +08042e96 <__retarget_lock_init_recursive>: + 8042e96: 4770 bx lr + +08042e98 <__retarget_lock_acquire_recursive>: + 8042e98: 4770 bx lr + +08042e9a <__retarget_lock_release_recursive>: 8042e9a: 4770 bx lr -08042e9c <__retarget_lock_acquire_recursive>: - 8042e9c: 4770 bx lr - -08042e9e <__retarget_lock_release_recursive>: - 8042e9e: 4770 bx lr - -08042ea0 <_malloc_r>: - 8042ea0: b5f8 push {r3, r4, r5, r6, r7, lr} - 8042ea2: 1ccd adds r5, r1, #3 - 8042ea4: f025 0503 bic.w r5, r5, #3 - 8042ea8: 3508 adds r5, #8 - 8042eaa: 2d0c cmp r5, #12 - 8042eac: bf38 it cc - 8042eae: 250c movcc r5, #12 - 8042eb0: 2d00 cmp r5, #0 - 8042eb2: 4606 mov r6, r0 - 8042eb4: db01 blt.n 8042eba <_malloc_r+0x1a> - 8042eb6: 42a9 cmp r1, r5 - 8042eb8: d903 bls.n 8042ec2 <_malloc_r+0x22> - 8042eba: 230c movs r3, #12 - 8042ebc: 6033 str r3, [r6, #0] - 8042ebe: 2000 movs r0, #0 - 8042ec0: bdf8 pop {r3, r4, r5, r6, r7, pc} - 8042ec2: f000 fda3 bl 8043a0c <__malloc_lock> - 8042ec6: 4921 ldr r1, [pc, #132] ; (8042f4c <_malloc_r+0xac>) - 8042ec8: 680a ldr r2, [r1, #0] - 8042eca: 4614 mov r4, r2 - 8042ecc: b99c cbnz r4, 8042ef6 <_malloc_r+0x56> - 8042ece: 4f20 ldr r7, [pc, #128] ; (8042f50 <_malloc_r+0xb0>) - 8042ed0: 683b ldr r3, [r7, #0] - 8042ed2: b923 cbnz r3, 8042ede <_malloc_r+0x3e> - 8042ed4: 4621 mov r1, r4 - 8042ed6: 4630 mov r0, r6 - 8042ed8: f000 fb2a bl 8043530 <_sbrk_r> - 8042edc: 6038 str r0, [r7, #0] - 8042ede: 4629 mov r1, r5 - 8042ee0: 4630 mov r0, r6 - 8042ee2: f000 fb25 bl 8043530 <_sbrk_r> - 8042ee6: 1c43 adds r3, r0, #1 - 8042ee8: d123 bne.n 8042f32 <_malloc_r+0x92> - 8042eea: 230c movs r3, #12 - 8042eec: 6033 str r3, [r6, #0] - 8042eee: 4630 mov r0, r6 - 8042ef0: f000 fd92 bl 8043a18 <__malloc_unlock> - 8042ef4: e7e3 b.n 8042ebe <_malloc_r+0x1e> - 8042ef6: 6823 ldr r3, [r4, #0] - 8042ef8: 1b5b subs r3, r3, r5 - 8042efa: d417 bmi.n 8042f2c <_malloc_r+0x8c> - 8042efc: 2b0b cmp r3, #11 - 8042efe: d903 bls.n 8042f08 <_malloc_r+0x68> - 8042f00: 6023 str r3, [r4, #0] - 8042f02: 441c add r4, r3 - 8042f04: 6025 str r5, [r4, #0] - 8042f06: e004 b.n 8042f12 <_malloc_r+0x72> - 8042f08: 6863 ldr r3, [r4, #4] - 8042f0a: 42a2 cmp r2, r4 - 8042f0c: bf0c ite eq - 8042f0e: 600b streq r3, [r1, #0] - 8042f10: 6053 strne r3, [r2, #4] - 8042f12: 4630 mov r0, r6 - 8042f14: f000 fd80 bl 8043a18 <__malloc_unlock> - 8042f18: f104 000b add.w r0, r4, #11 - 8042f1c: 1d23 adds r3, r4, #4 - 8042f1e: f020 0007 bic.w r0, r0, #7 - 8042f22: 1ac2 subs r2, r0, r3 - 8042f24: d0cc beq.n 8042ec0 <_malloc_r+0x20> - 8042f26: 1a1b subs r3, r3, r0 - 8042f28: 50a3 str r3, [r4, r2] - 8042f2a: e7c9 b.n 8042ec0 <_malloc_r+0x20> - 8042f2c: 4622 mov r2, r4 - 8042f2e: 6864 ldr r4, [r4, #4] - 8042f30: e7cc b.n 8042ecc <_malloc_r+0x2c> - 8042f32: 1cc4 adds r4, r0, #3 - 8042f34: f024 0403 bic.w r4, r4, #3 - 8042f38: 42a0 cmp r0, r4 - 8042f3a: d0e3 beq.n 8042f04 <_malloc_r+0x64> - 8042f3c: 1a21 subs r1, r4, r0 - 8042f3e: 4630 mov r0, r6 - 8042f40: f000 faf6 bl 8043530 <_sbrk_r> - 8042f44: 3001 adds r0, #1 - 8042f46: d1dd bne.n 8042f04 <_malloc_r+0x64> - 8042f48: e7cf b.n 8042eea <_malloc_r+0x4a> - 8042f4a: bf00 nop - 8042f4c: 20000090 .word 0x20000090 - 8042f50: 20000094 .word 0x20000094 - -08042f54 <__sfputc_r>: - 8042f54: 6893 ldr r3, [r2, #8] - 8042f56: 3b01 subs r3, #1 - 8042f58: 2b00 cmp r3, #0 - 8042f5a: b410 push {r4} - 8042f5c: 6093 str r3, [r2, #8] - 8042f5e: da08 bge.n 8042f72 <__sfputc_r+0x1e> - 8042f60: 6994 ldr r4, [r2, #24] - 8042f62: 42a3 cmp r3, r4 - 8042f64: db01 blt.n 8042f6a <__sfputc_r+0x16> - 8042f66: 290a cmp r1, #10 - 8042f68: d103 bne.n 8042f72 <__sfputc_r+0x1e> - 8042f6a: f85d 4b04 ldr.w r4, [sp], #4 - 8042f6e: f000 bb33 b.w 80435d8 <__swbuf_r> - 8042f72: 6813 ldr r3, [r2, #0] - 8042f74: 1c58 adds r0, r3, #1 - 8042f76: 6010 str r0, [r2, #0] - 8042f78: 7019 strb r1, [r3, #0] - 8042f7a: 4608 mov r0, r1 - 8042f7c: f85d 4b04 ldr.w r4, [sp], #4 - 8042f80: 4770 bx lr - -08042f82 <__sfputs_r>: - 8042f82: b5f8 push {r3, r4, r5, r6, r7, lr} - 8042f84: 4606 mov r6, r0 - 8042f86: 460f mov r7, r1 - 8042f88: 4614 mov r4, r2 - 8042f8a: 18d5 adds r5, r2, r3 - 8042f8c: 42ac cmp r4, r5 - 8042f8e: d101 bne.n 8042f94 <__sfputs_r+0x12> - 8042f90: 2000 movs r0, #0 - 8042f92: e007 b.n 8042fa4 <__sfputs_r+0x22> - 8042f94: f814 1b01 ldrb.w r1, [r4], #1 - 8042f98: 463a mov r2, r7 - 8042f9a: 4630 mov r0, r6 - 8042f9c: f7ff ffda bl 8042f54 <__sfputc_r> - 8042fa0: 1c43 adds r3, r0, #1 - 8042fa2: d1f3 bne.n 8042f8c <__sfputs_r+0xa> - 8042fa4: bdf8 pop {r3, r4, r5, r6, r7, pc} +08042e9c <_malloc_r>: + 8042e9c: b5f8 push {r3, r4, r5, r6, r7, lr} + 8042e9e: 1ccd adds r5, r1, #3 + 8042ea0: f025 0503 bic.w r5, r5, #3 + 8042ea4: 3508 adds r5, #8 + 8042ea6: 2d0c cmp r5, #12 + 8042ea8: bf38 it cc + 8042eaa: 250c movcc r5, #12 + 8042eac: 2d00 cmp r5, #0 + 8042eae: 4606 mov r6, r0 + 8042eb0: db01 blt.n 8042eb6 <_malloc_r+0x1a> + 8042eb2: 42a9 cmp r1, r5 + 8042eb4: d903 bls.n 8042ebe <_malloc_r+0x22> + 8042eb6: 230c movs r3, #12 + 8042eb8: 6033 str r3, [r6, #0] + 8042eba: 2000 movs r0, #0 + 8042ebc: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8042ebe: f000 fda3 bl 8043a08 <__malloc_lock> + 8042ec2: 4921 ldr r1, [pc, #132] ; (8042f48 <_malloc_r+0xac>) + 8042ec4: 680a ldr r2, [r1, #0] + 8042ec6: 4614 mov r4, r2 + 8042ec8: b99c cbnz r4, 8042ef2 <_malloc_r+0x56> + 8042eca: 4f20 ldr r7, [pc, #128] ; (8042f4c <_malloc_r+0xb0>) + 8042ecc: 683b ldr r3, [r7, #0] + 8042ece: b923 cbnz r3, 8042eda <_malloc_r+0x3e> + 8042ed0: 4621 mov r1, r4 + 8042ed2: 4630 mov r0, r6 + 8042ed4: f000 fb2a bl 804352c <_sbrk_r> + 8042ed8: 6038 str r0, [r7, #0] + 8042eda: 4629 mov r1, r5 + 8042edc: 4630 mov r0, r6 + 8042ede: f000 fb25 bl 804352c <_sbrk_r> + 8042ee2: 1c43 adds r3, r0, #1 + 8042ee4: d123 bne.n 8042f2e <_malloc_r+0x92> + 8042ee6: 230c movs r3, #12 + 8042ee8: 6033 str r3, [r6, #0] + 8042eea: 4630 mov r0, r6 + 8042eec: f000 fd92 bl 8043a14 <__malloc_unlock> + 8042ef0: e7e3 b.n 8042eba <_malloc_r+0x1e> + 8042ef2: 6823 ldr r3, [r4, #0] + 8042ef4: 1b5b subs r3, r3, r5 + 8042ef6: d417 bmi.n 8042f28 <_malloc_r+0x8c> + 8042ef8: 2b0b cmp r3, #11 + 8042efa: d903 bls.n 8042f04 <_malloc_r+0x68> + 8042efc: 6023 str r3, [r4, #0] + 8042efe: 441c add r4, r3 + 8042f00: 6025 str r5, [r4, #0] + 8042f02: e004 b.n 8042f0e <_malloc_r+0x72> + 8042f04: 6863 ldr r3, [r4, #4] + 8042f06: 42a2 cmp r2, r4 + 8042f08: bf0c ite eq + 8042f0a: 600b streq r3, [r1, #0] + 8042f0c: 6053 strne r3, [r2, #4] + 8042f0e: 4630 mov r0, r6 + 8042f10: f000 fd80 bl 8043a14 <__malloc_unlock> + 8042f14: f104 000b add.w r0, r4, #11 + 8042f18: 1d23 adds r3, r4, #4 + 8042f1a: f020 0007 bic.w r0, r0, #7 + 8042f1e: 1ac2 subs r2, r0, r3 + 8042f20: d0cc beq.n 8042ebc <_malloc_r+0x20> + 8042f22: 1a1b subs r3, r3, r0 + 8042f24: 50a3 str r3, [r4, r2] + 8042f26: e7c9 b.n 8042ebc <_malloc_r+0x20> + 8042f28: 4622 mov r2, r4 + 8042f2a: 6864 ldr r4, [r4, #4] + 8042f2c: e7cc b.n 8042ec8 <_malloc_r+0x2c> + 8042f2e: 1cc4 adds r4, r0, #3 + 8042f30: f024 0403 bic.w r4, r4, #3 + 8042f34: 42a0 cmp r0, r4 + 8042f36: d0e3 beq.n 8042f00 <_malloc_r+0x64> + 8042f38: 1a21 subs r1, r4, r0 + 8042f3a: 4630 mov r0, r6 + 8042f3c: f000 faf6 bl 804352c <_sbrk_r> + 8042f40: 3001 adds r0, #1 + 8042f42: d1dd bne.n 8042f00 <_malloc_r+0x64> + 8042f44: e7cf b.n 8042ee6 <_malloc_r+0x4a> + 8042f46: bf00 nop + 8042f48: 20000090 .word 0x20000090 + 8042f4c: 20000094 .word 0x20000094 + +08042f50 <__sfputc_r>: + 8042f50: 6893 ldr r3, [r2, #8] + 8042f52: 3b01 subs r3, #1 + 8042f54: 2b00 cmp r3, #0 + 8042f56: b410 push {r4} + 8042f58: 6093 str r3, [r2, #8] + 8042f5a: da08 bge.n 8042f6e <__sfputc_r+0x1e> + 8042f5c: 6994 ldr r4, [r2, #24] + 8042f5e: 42a3 cmp r3, r4 + 8042f60: db01 blt.n 8042f66 <__sfputc_r+0x16> + 8042f62: 290a cmp r1, #10 + 8042f64: d103 bne.n 8042f6e <__sfputc_r+0x1e> + 8042f66: f85d 4b04 ldr.w r4, [sp], #4 + 8042f6a: f000 bb33 b.w 80435d4 <__swbuf_r> + 8042f6e: 6813 ldr r3, [r2, #0] + 8042f70: 1c58 adds r0, r3, #1 + 8042f72: 6010 str r0, [r2, #0] + 8042f74: 7019 strb r1, [r3, #0] + 8042f76: 4608 mov r0, r1 + 8042f78: f85d 4b04 ldr.w r4, [sp], #4 + 8042f7c: 4770 bx lr + +08042f7e <__sfputs_r>: + 8042f7e: b5f8 push {r3, r4, r5, r6, r7, lr} + 8042f80: 4606 mov r6, r0 + 8042f82: 460f mov r7, r1 + 8042f84: 4614 mov r4, r2 + 8042f86: 18d5 adds r5, r2, r3 + 8042f88: 42ac cmp r4, r5 + 8042f8a: d101 bne.n 8042f90 <__sfputs_r+0x12> + 8042f8c: 2000 movs r0, #0 + 8042f8e: e007 b.n 8042fa0 <__sfputs_r+0x22> + 8042f90: f814 1b01 ldrb.w r1, [r4], #1 + 8042f94: 463a mov r2, r7 + 8042f96: 4630 mov r0, r6 + 8042f98: f7ff ffda bl 8042f50 <__sfputc_r> + 8042f9c: 1c43 adds r3, r0, #1 + 8042f9e: d1f3 bne.n 8042f88 <__sfputs_r+0xa> + 8042fa0: bdf8 pop {r3, r4, r5, r6, r7, pc} ... -08042fa8 <_vfiprintf_r>: - 8042fa8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 8042fac: 460d mov r5, r1 - 8042fae: b09d sub sp, #116 ; 0x74 - 8042fb0: 4614 mov r4, r2 - 8042fb2: 4698 mov r8, r3 - 8042fb4: 4606 mov r6, r0 - 8042fb6: b118 cbz r0, 8042fc0 <_vfiprintf_r+0x18> - 8042fb8: 6983 ldr r3, [r0, #24] - 8042fba: b90b cbnz r3, 8042fc0 <_vfiprintf_r+0x18> - 8042fbc: f7ff fed0 bl 8042d60 <__sinit> - 8042fc0: 4b89 ldr r3, [pc, #548] ; (80431e8 <_vfiprintf_r+0x240>) - 8042fc2: 429d cmp r5, r3 - 8042fc4: d11b bne.n 8042ffe <_vfiprintf_r+0x56> - 8042fc6: 6875 ldr r5, [r6, #4] - 8042fc8: 6e6b ldr r3, [r5, #100] ; 0x64 - 8042fca: 07d9 lsls r1, r3, #31 - 8042fcc: d405 bmi.n 8042fda <_vfiprintf_r+0x32> - 8042fce: 89ab ldrh r3, [r5, #12] - 8042fd0: 059a lsls r2, r3, #22 - 8042fd2: d402 bmi.n 8042fda <_vfiprintf_r+0x32> - 8042fd4: 6da8 ldr r0, [r5, #88] ; 0x58 - 8042fd6: f7ff ff61 bl 8042e9c <__retarget_lock_acquire_recursive> - 8042fda: 89ab ldrh r3, [r5, #12] - 8042fdc: 071b lsls r3, r3, #28 - 8042fde: d501 bpl.n 8042fe4 <_vfiprintf_r+0x3c> - 8042fe0: 692b ldr r3, [r5, #16] - 8042fe2: b9eb cbnz r3, 8043020 <_vfiprintf_r+0x78> - 8042fe4: 4629 mov r1, r5 - 8042fe6: 4630 mov r0, r6 - 8042fe8: f000 fb5a bl 80436a0 <__swsetup_r> - 8042fec: b1c0 cbz r0, 8043020 <_vfiprintf_r+0x78> - 8042fee: 6e6b ldr r3, [r5, #100] ; 0x64 - 8042ff0: 07dc lsls r4, r3, #31 - 8042ff2: d50e bpl.n 8043012 <_vfiprintf_r+0x6a> - 8042ff4: f04f 30ff mov.w r0, #4294967295 - 8042ff8: b01d add sp, #116 ; 0x74 - 8042ffa: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 8042ffe: 4b7b ldr r3, [pc, #492] ; (80431ec <_vfiprintf_r+0x244>) - 8043000: 429d cmp r5, r3 - 8043002: d101 bne.n 8043008 <_vfiprintf_r+0x60> - 8043004: 68b5 ldr r5, [r6, #8] - 8043006: e7df b.n 8042fc8 <_vfiprintf_r+0x20> - 8043008: 4b79 ldr r3, [pc, #484] ; (80431f0 <_vfiprintf_r+0x248>) - 804300a: 429d cmp r5, r3 - 804300c: bf08 it eq - 804300e: 68f5 ldreq r5, [r6, #12] - 8043010: e7da b.n 8042fc8 <_vfiprintf_r+0x20> - 8043012: 89ab ldrh r3, [r5, #12] - 8043014: 0598 lsls r0, r3, #22 - 8043016: d4ed bmi.n 8042ff4 <_vfiprintf_r+0x4c> - 8043018: 6da8 ldr r0, [r5, #88] ; 0x58 - 804301a: f7ff ff40 bl 8042e9e <__retarget_lock_release_recursive> - 804301e: e7e9 b.n 8042ff4 <_vfiprintf_r+0x4c> - 8043020: 2300 movs r3, #0 - 8043022: 9309 str r3, [sp, #36] ; 0x24 - 8043024: 2320 movs r3, #32 - 8043026: f88d 3029 strb.w r3, [sp, #41] ; 0x29 - 804302a: f8cd 800c str.w r8, [sp, #12] - 804302e: 2330 movs r3, #48 ; 0x30 - 8043030: f8df 81c0 ldr.w r8, [pc, #448] ; 80431f4 <_vfiprintf_r+0x24c> - 8043034: f88d 302a strb.w r3, [sp, #42] ; 0x2a - 8043038: f04f 0901 mov.w r9, #1 - 804303c: 4623 mov r3, r4 - 804303e: 469a mov sl, r3 - 8043040: f813 2b01 ldrb.w r2, [r3], #1 - 8043044: b10a cbz r2, 804304a <_vfiprintf_r+0xa2> - 8043046: 2a25 cmp r2, #37 ; 0x25 - 8043048: d1f9 bne.n 804303e <_vfiprintf_r+0x96> - 804304a: ebba 0b04 subs.w fp, sl, r4 - 804304e: d00b beq.n 8043068 <_vfiprintf_r+0xc0> - 8043050: 465b mov r3, fp - 8043052: 4622 mov r2, r4 - 8043054: 4629 mov r1, r5 - 8043056: 4630 mov r0, r6 - 8043058: f7ff ff93 bl 8042f82 <__sfputs_r> - 804305c: 3001 adds r0, #1 - 804305e: f000 80aa beq.w 80431b6 <_vfiprintf_r+0x20e> - 8043062: 9a09 ldr r2, [sp, #36] ; 0x24 - 8043064: 445a add r2, fp - 8043066: 9209 str r2, [sp, #36] ; 0x24 - 8043068: f89a 3000 ldrb.w r3, [sl] - 804306c: 2b00 cmp r3, #0 - 804306e: f000 80a2 beq.w 80431b6 <_vfiprintf_r+0x20e> - 8043072: 2300 movs r3, #0 - 8043074: f04f 32ff mov.w r2, #4294967295 - 8043078: e9cd 2305 strd r2, r3, [sp, #20] - 804307c: f10a 0a01 add.w sl, sl, #1 - 8043080: 9304 str r3, [sp, #16] - 8043082: 9307 str r3, [sp, #28] - 8043084: f88d 3053 strb.w r3, [sp, #83] ; 0x53 - 8043088: 931a str r3, [sp, #104] ; 0x68 - 804308a: 4654 mov r4, sl - 804308c: 2205 movs r2, #5 - 804308e: f814 1b01 ldrb.w r1, [r4], #1 - 8043092: 4858 ldr r0, [pc, #352] ; (80431f4 <_vfiprintf_r+0x24c>) - 8043094: f7fd f8d4 bl 8040240 - 8043098: 9a04 ldr r2, [sp, #16] - 804309a: b9d8 cbnz r0, 80430d4 <_vfiprintf_r+0x12c> - 804309c: 06d1 lsls r1, r2, #27 - 804309e: bf44 itt mi - 80430a0: 2320 movmi r3, #32 - 80430a2: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 - 80430a6: 0713 lsls r3, r2, #28 - 80430a8: bf44 itt mi - 80430aa: 232b movmi r3, #43 ; 0x2b - 80430ac: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 - 80430b0: f89a 3000 ldrb.w r3, [sl] - 80430b4: 2b2a cmp r3, #42 ; 0x2a - 80430b6: d015 beq.n 80430e4 <_vfiprintf_r+0x13c> - 80430b8: 9a07 ldr r2, [sp, #28] - 80430ba: 4654 mov r4, sl - 80430bc: 2000 movs r0, #0 - 80430be: f04f 0c0a mov.w ip, #10 - 80430c2: 4621 mov r1, r4 - 80430c4: f811 3b01 ldrb.w r3, [r1], #1 - 80430c8: 3b30 subs r3, #48 ; 0x30 - 80430ca: 2b09 cmp r3, #9 - 80430cc: d94e bls.n 804316c <_vfiprintf_r+0x1c4> - 80430ce: b1b0 cbz r0, 80430fe <_vfiprintf_r+0x156> - 80430d0: 9207 str r2, [sp, #28] - 80430d2: e014 b.n 80430fe <_vfiprintf_r+0x156> - 80430d4: eba0 0308 sub.w r3, r0, r8 - 80430d8: fa09 f303 lsl.w r3, r9, r3 - 80430dc: 4313 orrs r3, r2 - 80430de: 9304 str r3, [sp, #16] - 80430e0: 46a2 mov sl, r4 - 80430e2: e7d2 b.n 804308a <_vfiprintf_r+0xe2> - 80430e4: 9b03 ldr r3, [sp, #12] - 80430e6: 1d19 adds r1, r3, #4 - 80430e8: 681b ldr r3, [r3, #0] - 80430ea: 9103 str r1, [sp, #12] - 80430ec: 2b00 cmp r3, #0 - 80430ee: bfbb ittet lt - 80430f0: 425b neglt r3, r3 - 80430f2: f042 0202 orrlt.w r2, r2, #2 - 80430f6: 9307 strge r3, [sp, #28] - 80430f8: 9307 strlt r3, [sp, #28] - 80430fa: bfb8 it lt - 80430fc: 9204 strlt r2, [sp, #16] - 80430fe: 7823 ldrb r3, [r4, #0] - 8043100: 2b2e cmp r3, #46 ; 0x2e - 8043102: d10c bne.n 804311e <_vfiprintf_r+0x176> - 8043104: 7863 ldrb r3, [r4, #1] - 8043106: 2b2a cmp r3, #42 ; 0x2a - 8043108: d135 bne.n 8043176 <_vfiprintf_r+0x1ce> - 804310a: 9b03 ldr r3, [sp, #12] - 804310c: 1d1a adds r2, r3, #4 - 804310e: 681b ldr r3, [r3, #0] - 8043110: 9203 str r2, [sp, #12] - 8043112: 2b00 cmp r3, #0 - 8043114: bfb8 it lt - 8043116: f04f 33ff movlt.w r3, #4294967295 - 804311a: 3402 adds r4, #2 - 804311c: 9305 str r3, [sp, #20] - 804311e: f8df a0e4 ldr.w sl, [pc, #228] ; 8043204 <_vfiprintf_r+0x25c> - 8043122: 7821 ldrb r1, [r4, #0] - 8043124: 2203 movs r2, #3 - 8043126: 4650 mov r0, sl - 8043128: f7fd f88a bl 8040240 - 804312c: b140 cbz r0, 8043140 <_vfiprintf_r+0x198> - 804312e: 2340 movs r3, #64 ; 0x40 - 8043130: eba0 000a sub.w r0, r0, sl - 8043134: fa03 f000 lsl.w r0, r3, r0 - 8043138: 9b04 ldr r3, [sp, #16] - 804313a: 4303 orrs r3, r0 - 804313c: 3401 adds r4, #1 - 804313e: 9304 str r3, [sp, #16] - 8043140: f814 1b01 ldrb.w r1, [r4], #1 - 8043144: 482c ldr r0, [pc, #176] ; (80431f8 <_vfiprintf_r+0x250>) - 8043146: f88d 1028 strb.w r1, [sp, #40] ; 0x28 - 804314a: 2206 movs r2, #6 - 804314c: f7fd f878 bl 8040240 - 8043150: 2800 cmp r0, #0 - 8043152: d03f beq.n 80431d4 <_vfiprintf_r+0x22c> - 8043154: 4b29 ldr r3, [pc, #164] ; (80431fc <_vfiprintf_r+0x254>) - 8043156: bb1b cbnz r3, 80431a0 <_vfiprintf_r+0x1f8> - 8043158: 9b03 ldr r3, [sp, #12] - 804315a: 3307 adds r3, #7 - 804315c: f023 0307 bic.w r3, r3, #7 - 8043160: 3308 adds r3, #8 - 8043162: 9303 str r3, [sp, #12] - 8043164: 9b09 ldr r3, [sp, #36] ; 0x24 - 8043166: 443b add r3, r7 - 8043168: 9309 str r3, [sp, #36] ; 0x24 - 804316a: e767 b.n 804303c <_vfiprintf_r+0x94> - 804316c: fb0c 3202 mla r2, ip, r2, r3 - 8043170: 460c mov r4, r1 - 8043172: 2001 movs r0, #1 - 8043174: e7a5 b.n 80430c2 <_vfiprintf_r+0x11a> - 8043176: 2300 movs r3, #0 - 8043178: 3401 adds r4, #1 - 804317a: 9305 str r3, [sp, #20] - 804317c: 4619 mov r1, r3 - 804317e: f04f 0c0a mov.w ip, #10 - 8043182: 4620 mov r0, r4 - 8043184: f810 2b01 ldrb.w r2, [r0], #1 - 8043188: 3a30 subs r2, #48 ; 0x30 - 804318a: 2a09 cmp r2, #9 - 804318c: d903 bls.n 8043196 <_vfiprintf_r+0x1ee> - 804318e: 2b00 cmp r3, #0 - 8043190: d0c5 beq.n 804311e <_vfiprintf_r+0x176> - 8043192: 9105 str r1, [sp, #20] - 8043194: e7c3 b.n 804311e <_vfiprintf_r+0x176> - 8043196: fb0c 2101 mla r1, ip, r1, r2 - 804319a: 4604 mov r4, r0 - 804319c: 2301 movs r3, #1 - 804319e: e7f0 b.n 8043182 <_vfiprintf_r+0x1da> - 80431a0: ab03 add r3, sp, #12 - 80431a2: 9300 str r3, [sp, #0] - 80431a4: 462a mov r2, r5 - 80431a6: 4b16 ldr r3, [pc, #88] ; (8043200 <_vfiprintf_r+0x258>) - 80431a8: a904 add r1, sp, #16 - 80431aa: 4630 mov r0, r6 - 80431ac: f3af 8000 nop.w - 80431b0: 4607 mov r7, r0 - 80431b2: 1c78 adds r0, r7, #1 - 80431b4: d1d6 bne.n 8043164 <_vfiprintf_r+0x1bc> - 80431b6: 6e6b ldr r3, [r5, #100] ; 0x64 - 80431b8: 07d9 lsls r1, r3, #31 - 80431ba: d405 bmi.n 80431c8 <_vfiprintf_r+0x220> - 80431bc: 89ab ldrh r3, [r5, #12] - 80431be: 059a lsls r2, r3, #22 - 80431c0: d402 bmi.n 80431c8 <_vfiprintf_r+0x220> - 80431c2: 6da8 ldr r0, [r5, #88] ; 0x58 - 80431c4: f7ff fe6b bl 8042e9e <__retarget_lock_release_recursive> - 80431c8: 89ab ldrh r3, [r5, #12] - 80431ca: 065b lsls r3, r3, #25 - 80431cc: f53f af12 bmi.w 8042ff4 <_vfiprintf_r+0x4c> - 80431d0: 9809 ldr r0, [sp, #36] ; 0x24 - 80431d2: e711 b.n 8042ff8 <_vfiprintf_r+0x50> - 80431d4: ab03 add r3, sp, #12 - 80431d6: 9300 str r3, [sp, #0] - 80431d8: 462a mov r2, r5 - 80431da: 4b09 ldr r3, [pc, #36] ; (8043200 <_vfiprintf_r+0x258>) - 80431dc: a904 add r1, sp, #16 - 80431de: 4630 mov r0, r6 - 80431e0: f000 f880 bl 80432e4 <_printf_i> - 80431e4: e7e4 b.n 80431b0 <_vfiprintf_r+0x208> - 80431e6: bf00 nop - 80431e8: 08043ba0 .word 0x08043ba0 - 80431ec: 08043bc0 .word 0x08043bc0 - 80431f0: 08043b80 .word 0x08043b80 - 80431f4: 08043be0 .word 0x08043be0 - 80431f8: 08043bea .word 0x08043bea - 80431fc: 00000000 .word 0x00000000 - 8043200: 08042f83 .word 0x08042f83 - 8043204: 08043be6 .word 0x08043be6 - -08043208 <_printf_common>: - 8043208: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} - 804320c: 4616 mov r6, r2 - 804320e: 4699 mov r9, r3 - 8043210: 688a ldr r2, [r1, #8] - 8043212: 690b ldr r3, [r1, #16] - 8043214: f8dd 8020 ldr.w r8, [sp, #32] - 8043218: 4293 cmp r3, r2 - 804321a: bfb8 it lt - 804321c: 4613 movlt r3, r2 - 804321e: 6033 str r3, [r6, #0] - 8043220: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 - 8043224: 4607 mov r7, r0 - 8043226: 460c mov r4, r1 - 8043228: b10a cbz r2, 804322e <_printf_common+0x26> - 804322a: 3301 adds r3, #1 - 804322c: 6033 str r3, [r6, #0] - 804322e: 6823 ldr r3, [r4, #0] - 8043230: 0699 lsls r1, r3, #26 - 8043232: bf42 ittt mi - 8043234: 6833 ldrmi r3, [r6, #0] - 8043236: 3302 addmi r3, #2 - 8043238: 6033 strmi r3, [r6, #0] - 804323a: 6825 ldr r5, [r4, #0] - 804323c: f015 0506 ands.w r5, r5, #6 - 8043240: d106 bne.n 8043250 <_printf_common+0x48> - 8043242: f104 0a19 add.w sl, r4, #25 - 8043246: 68e3 ldr r3, [r4, #12] - 8043248: 6832 ldr r2, [r6, #0] - 804324a: 1a9b subs r3, r3, r2 - 804324c: 42ab cmp r3, r5 - 804324e: dc26 bgt.n 804329e <_printf_common+0x96> - 8043250: f894 2043 ldrb.w r2, [r4, #67] ; 0x43 - 8043254: 1e13 subs r3, r2, #0 - 8043256: 6822 ldr r2, [r4, #0] - 8043258: bf18 it ne - 804325a: 2301 movne r3, #1 - 804325c: 0692 lsls r2, r2, #26 - 804325e: d42b bmi.n 80432b8 <_printf_common+0xb0> - 8043260: f104 0243 add.w r2, r4, #67 ; 0x43 - 8043264: 4649 mov r1, r9 - 8043266: 4638 mov r0, r7 - 8043268: 47c0 blx r8 - 804326a: 3001 adds r0, #1 - 804326c: d01e beq.n 80432ac <_printf_common+0xa4> - 804326e: 6823 ldr r3, [r4, #0] - 8043270: 68e5 ldr r5, [r4, #12] - 8043272: 6832 ldr r2, [r6, #0] - 8043274: f003 0306 and.w r3, r3, #6 - 8043278: 2b04 cmp r3, #4 - 804327a: bf08 it eq - 804327c: 1aad subeq r5, r5, r2 - 804327e: 68a3 ldr r3, [r4, #8] - 8043280: 6922 ldr r2, [r4, #16] - 8043282: bf0c ite eq - 8043284: ea25 75e5 biceq.w r5, r5, r5, asr #31 - 8043288: 2500 movne r5, #0 - 804328a: 4293 cmp r3, r2 - 804328c: bfc4 itt gt - 804328e: 1a9b subgt r3, r3, r2 - 8043290: 18ed addgt r5, r5, r3 - 8043292: 2600 movs r6, #0 - 8043294: 341a adds r4, #26 - 8043296: 42b5 cmp r5, r6 - 8043298: d11a bne.n 80432d0 <_printf_common+0xc8> - 804329a: 2000 movs r0, #0 - 804329c: e008 b.n 80432b0 <_printf_common+0xa8> - 804329e: 2301 movs r3, #1 - 80432a0: 4652 mov r2, sl - 80432a2: 4649 mov r1, r9 - 80432a4: 4638 mov r0, r7 - 80432a6: 47c0 blx r8 - 80432a8: 3001 adds r0, #1 - 80432aa: d103 bne.n 80432b4 <_printf_common+0xac> - 80432ac: f04f 30ff mov.w r0, #4294967295 - 80432b0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 80432b4: 3501 adds r5, #1 - 80432b6: e7c6 b.n 8043246 <_printf_common+0x3e> - 80432b8: 18e1 adds r1, r4, r3 - 80432ba: 1c5a adds r2, r3, #1 - 80432bc: 2030 movs r0, #48 ; 0x30 - 80432be: f881 0043 strb.w r0, [r1, #67] ; 0x43 - 80432c2: 4422 add r2, r4 - 80432c4: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 - 80432c8: f882 1043 strb.w r1, [r2, #67] ; 0x43 - 80432cc: 3302 adds r3, #2 - 80432ce: e7c7 b.n 8043260 <_printf_common+0x58> - 80432d0: 2301 movs r3, #1 - 80432d2: 4622 mov r2, r4 - 80432d4: 4649 mov r1, r9 - 80432d6: 4638 mov r0, r7 - 80432d8: 47c0 blx r8 - 80432da: 3001 adds r0, #1 - 80432dc: d0e6 beq.n 80432ac <_printf_common+0xa4> - 80432de: 3601 adds r6, #1 - 80432e0: e7d9 b.n 8043296 <_printf_common+0x8e> +08042fa4 <_vfiprintf_r>: + 8042fa4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8042fa8: 460d mov r5, r1 + 8042faa: b09d sub sp, #116 ; 0x74 + 8042fac: 4614 mov r4, r2 + 8042fae: 4698 mov r8, r3 + 8042fb0: 4606 mov r6, r0 + 8042fb2: b118 cbz r0, 8042fbc <_vfiprintf_r+0x18> + 8042fb4: 6983 ldr r3, [r0, #24] + 8042fb6: b90b cbnz r3, 8042fbc <_vfiprintf_r+0x18> + 8042fb8: f7ff fed0 bl 8042d5c <__sinit> + 8042fbc: 4b89 ldr r3, [pc, #548] ; (80431e4 <_vfiprintf_r+0x240>) + 8042fbe: 429d cmp r5, r3 + 8042fc0: d11b bne.n 8042ffa <_vfiprintf_r+0x56> + 8042fc2: 6875 ldr r5, [r6, #4] + 8042fc4: 6e6b ldr r3, [r5, #100] ; 0x64 + 8042fc6: 07d9 lsls r1, r3, #31 + 8042fc8: d405 bmi.n 8042fd6 <_vfiprintf_r+0x32> + 8042fca: 89ab ldrh r3, [r5, #12] + 8042fcc: 059a lsls r2, r3, #22 + 8042fce: d402 bmi.n 8042fd6 <_vfiprintf_r+0x32> + 8042fd0: 6da8 ldr r0, [r5, #88] ; 0x58 + 8042fd2: f7ff ff61 bl 8042e98 <__retarget_lock_acquire_recursive> + 8042fd6: 89ab ldrh r3, [r5, #12] + 8042fd8: 071b lsls r3, r3, #28 + 8042fda: d501 bpl.n 8042fe0 <_vfiprintf_r+0x3c> + 8042fdc: 692b ldr r3, [r5, #16] + 8042fde: b9eb cbnz r3, 804301c <_vfiprintf_r+0x78> + 8042fe0: 4629 mov r1, r5 + 8042fe2: 4630 mov r0, r6 + 8042fe4: f000 fb5a bl 804369c <__swsetup_r> + 8042fe8: b1c0 cbz r0, 804301c <_vfiprintf_r+0x78> + 8042fea: 6e6b ldr r3, [r5, #100] ; 0x64 + 8042fec: 07dc lsls r4, r3, #31 + 8042fee: d50e bpl.n 804300e <_vfiprintf_r+0x6a> + 8042ff0: f04f 30ff mov.w r0, #4294967295 + 8042ff4: b01d add sp, #116 ; 0x74 + 8042ff6: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8042ffa: 4b7b ldr r3, [pc, #492] ; (80431e8 <_vfiprintf_r+0x244>) + 8042ffc: 429d cmp r5, r3 + 8042ffe: d101 bne.n 8043004 <_vfiprintf_r+0x60> + 8043000: 68b5 ldr r5, [r6, #8] + 8043002: e7df b.n 8042fc4 <_vfiprintf_r+0x20> + 8043004: 4b79 ldr r3, [pc, #484] ; (80431ec <_vfiprintf_r+0x248>) + 8043006: 429d cmp r5, r3 + 8043008: bf08 it eq + 804300a: 68f5 ldreq r5, [r6, #12] + 804300c: e7da b.n 8042fc4 <_vfiprintf_r+0x20> + 804300e: 89ab ldrh r3, [r5, #12] + 8043010: 0598 lsls r0, r3, #22 + 8043012: d4ed bmi.n 8042ff0 <_vfiprintf_r+0x4c> + 8043014: 6da8 ldr r0, [r5, #88] ; 0x58 + 8043016: f7ff ff40 bl 8042e9a <__retarget_lock_release_recursive> + 804301a: e7e9 b.n 8042ff0 <_vfiprintf_r+0x4c> + 804301c: 2300 movs r3, #0 + 804301e: 9309 str r3, [sp, #36] ; 0x24 + 8043020: 2320 movs r3, #32 + 8043022: f88d 3029 strb.w r3, [sp, #41] ; 0x29 + 8043026: f8cd 800c str.w r8, [sp, #12] + 804302a: 2330 movs r3, #48 ; 0x30 + 804302c: f8df 81c0 ldr.w r8, [pc, #448] ; 80431f0 <_vfiprintf_r+0x24c> + 8043030: f88d 302a strb.w r3, [sp, #42] ; 0x2a + 8043034: f04f 0901 mov.w r9, #1 + 8043038: 4623 mov r3, r4 + 804303a: 469a mov sl, r3 + 804303c: f813 2b01 ldrb.w r2, [r3], #1 + 8043040: b10a cbz r2, 8043046 <_vfiprintf_r+0xa2> + 8043042: 2a25 cmp r2, #37 ; 0x25 + 8043044: d1f9 bne.n 804303a <_vfiprintf_r+0x96> + 8043046: ebba 0b04 subs.w fp, sl, r4 + 804304a: d00b beq.n 8043064 <_vfiprintf_r+0xc0> + 804304c: 465b mov r3, fp + 804304e: 4622 mov r2, r4 + 8043050: 4629 mov r1, r5 + 8043052: 4630 mov r0, r6 + 8043054: f7ff ff93 bl 8042f7e <__sfputs_r> + 8043058: 3001 adds r0, #1 + 804305a: f000 80aa beq.w 80431b2 <_vfiprintf_r+0x20e> + 804305e: 9a09 ldr r2, [sp, #36] ; 0x24 + 8043060: 445a add r2, fp + 8043062: 9209 str r2, [sp, #36] ; 0x24 + 8043064: f89a 3000 ldrb.w r3, [sl] + 8043068: 2b00 cmp r3, #0 + 804306a: f000 80a2 beq.w 80431b2 <_vfiprintf_r+0x20e> + 804306e: 2300 movs r3, #0 + 8043070: f04f 32ff mov.w r2, #4294967295 + 8043074: e9cd 2305 strd r2, r3, [sp, #20] + 8043078: f10a 0a01 add.w sl, sl, #1 + 804307c: 9304 str r3, [sp, #16] + 804307e: 9307 str r3, [sp, #28] + 8043080: f88d 3053 strb.w r3, [sp, #83] ; 0x53 + 8043084: 931a str r3, [sp, #104] ; 0x68 + 8043086: 4654 mov r4, sl + 8043088: 2205 movs r2, #5 + 804308a: f814 1b01 ldrb.w r1, [r4], #1 + 804308e: 4858 ldr r0, [pc, #352] ; (80431f0 <_vfiprintf_r+0x24c>) + 8043090: f7fd f8d6 bl 8040240 + 8043094: 9a04 ldr r2, [sp, #16] + 8043096: b9d8 cbnz r0, 80430d0 <_vfiprintf_r+0x12c> + 8043098: 06d1 lsls r1, r2, #27 + 804309a: bf44 itt mi + 804309c: 2320 movmi r3, #32 + 804309e: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 + 80430a2: 0713 lsls r3, r2, #28 + 80430a4: bf44 itt mi + 80430a6: 232b movmi r3, #43 ; 0x2b + 80430a8: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 + 80430ac: f89a 3000 ldrb.w r3, [sl] + 80430b0: 2b2a cmp r3, #42 ; 0x2a + 80430b2: d015 beq.n 80430e0 <_vfiprintf_r+0x13c> + 80430b4: 9a07 ldr r2, [sp, #28] + 80430b6: 4654 mov r4, sl + 80430b8: 2000 movs r0, #0 + 80430ba: f04f 0c0a mov.w ip, #10 + 80430be: 4621 mov r1, r4 + 80430c0: f811 3b01 ldrb.w r3, [r1], #1 + 80430c4: 3b30 subs r3, #48 ; 0x30 + 80430c6: 2b09 cmp r3, #9 + 80430c8: d94e bls.n 8043168 <_vfiprintf_r+0x1c4> + 80430ca: b1b0 cbz r0, 80430fa <_vfiprintf_r+0x156> + 80430cc: 9207 str r2, [sp, #28] + 80430ce: e014 b.n 80430fa <_vfiprintf_r+0x156> + 80430d0: eba0 0308 sub.w r3, r0, r8 + 80430d4: fa09 f303 lsl.w r3, r9, r3 + 80430d8: 4313 orrs r3, r2 + 80430da: 9304 str r3, [sp, #16] + 80430dc: 46a2 mov sl, r4 + 80430de: e7d2 b.n 8043086 <_vfiprintf_r+0xe2> + 80430e0: 9b03 ldr r3, [sp, #12] + 80430e2: 1d19 adds r1, r3, #4 + 80430e4: 681b ldr r3, [r3, #0] + 80430e6: 9103 str r1, [sp, #12] + 80430e8: 2b00 cmp r3, #0 + 80430ea: bfbb ittet lt + 80430ec: 425b neglt r3, r3 + 80430ee: f042 0202 orrlt.w r2, r2, #2 + 80430f2: 9307 strge r3, [sp, #28] + 80430f4: 9307 strlt r3, [sp, #28] + 80430f6: bfb8 it lt + 80430f8: 9204 strlt r2, [sp, #16] + 80430fa: 7823 ldrb r3, [r4, #0] + 80430fc: 2b2e cmp r3, #46 ; 0x2e + 80430fe: d10c bne.n 804311a <_vfiprintf_r+0x176> + 8043100: 7863 ldrb r3, [r4, #1] + 8043102: 2b2a cmp r3, #42 ; 0x2a + 8043104: d135 bne.n 8043172 <_vfiprintf_r+0x1ce> + 8043106: 9b03 ldr r3, [sp, #12] + 8043108: 1d1a adds r2, r3, #4 + 804310a: 681b ldr r3, [r3, #0] + 804310c: 9203 str r2, [sp, #12] + 804310e: 2b00 cmp r3, #0 + 8043110: bfb8 it lt + 8043112: f04f 33ff movlt.w r3, #4294967295 + 8043116: 3402 adds r4, #2 + 8043118: 9305 str r3, [sp, #20] + 804311a: f8df a0e4 ldr.w sl, [pc, #228] ; 8043200 <_vfiprintf_r+0x25c> + 804311e: 7821 ldrb r1, [r4, #0] + 8043120: 2203 movs r2, #3 + 8043122: 4650 mov r0, sl + 8043124: f7fd f88c bl 8040240 + 8043128: b140 cbz r0, 804313c <_vfiprintf_r+0x198> + 804312a: 2340 movs r3, #64 ; 0x40 + 804312c: eba0 000a sub.w r0, r0, sl + 8043130: fa03 f000 lsl.w r0, r3, r0 + 8043134: 9b04 ldr r3, [sp, #16] + 8043136: 4303 orrs r3, r0 + 8043138: 3401 adds r4, #1 + 804313a: 9304 str r3, [sp, #16] + 804313c: f814 1b01 ldrb.w r1, [r4], #1 + 8043140: 482c ldr r0, [pc, #176] ; (80431f4 <_vfiprintf_r+0x250>) + 8043142: f88d 1028 strb.w r1, [sp, #40] ; 0x28 + 8043146: 2206 movs r2, #6 + 8043148: f7fd f87a bl 8040240 + 804314c: 2800 cmp r0, #0 + 804314e: d03f beq.n 80431d0 <_vfiprintf_r+0x22c> + 8043150: 4b29 ldr r3, [pc, #164] ; (80431f8 <_vfiprintf_r+0x254>) + 8043152: bb1b cbnz r3, 804319c <_vfiprintf_r+0x1f8> + 8043154: 9b03 ldr r3, [sp, #12] + 8043156: 3307 adds r3, #7 + 8043158: f023 0307 bic.w r3, r3, #7 + 804315c: 3308 adds r3, #8 + 804315e: 9303 str r3, [sp, #12] + 8043160: 9b09 ldr r3, [sp, #36] ; 0x24 + 8043162: 443b add r3, r7 + 8043164: 9309 str r3, [sp, #36] ; 0x24 + 8043166: e767 b.n 8043038 <_vfiprintf_r+0x94> + 8043168: fb0c 3202 mla r2, ip, r2, r3 + 804316c: 460c mov r4, r1 + 804316e: 2001 movs r0, #1 + 8043170: e7a5 b.n 80430be <_vfiprintf_r+0x11a> + 8043172: 2300 movs r3, #0 + 8043174: 3401 adds r4, #1 + 8043176: 9305 str r3, [sp, #20] + 8043178: 4619 mov r1, r3 + 804317a: f04f 0c0a mov.w ip, #10 + 804317e: 4620 mov r0, r4 + 8043180: f810 2b01 ldrb.w r2, [r0], #1 + 8043184: 3a30 subs r2, #48 ; 0x30 + 8043186: 2a09 cmp r2, #9 + 8043188: d903 bls.n 8043192 <_vfiprintf_r+0x1ee> + 804318a: 2b00 cmp r3, #0 + 804318c: d0c5 beq.n 804311a <_vfiprintf_r+0x176> + 804318e: 9105 str r1, [sp, #20] + 8043190: e7c3 b.n 804311a <_vfiprintf_r+0x176> + 8043192: fb0c 2101 mla r1, ip, r1, r2 + 8043196: 4604 mov r4, r0 + 8043198: 2301 movs r3, #1 + 804319a: e7f0 b.n 804317e <_vfiprintf_r+0x1da> + 804319c: ab03 add r3, sp, #12 + 804319e: 9300 str r3, [sp, #0] + 80431a0: 462a mov r2, r5 + 80431a2: 4b16 ldr r3, [pc, #88] ; (80431fc <_vfiprintf_r+0x258>) + 80431a4: a904 add r1, sp, #16 + 80431a6: 4630 mov r0, r6 + 80431a8: f3af 8000 nop.w + 80431ac: 4607 mov r7, r0 + 80431ae: 1c78 adds r0, r7, #1 + 80431b0: d1d6 bne.n 8043160 <_vfiprintf_r+0x1bc> + 80431b2: 6e6b ldr r3, [r5, #100] ; 0x64 + 80431b4: 07d9 lsls r1, r3, #31 + 80431b6: d405 bmi.n 80431c4 <_vfiprintf_r+0x220> + 80431b8: 89ab ldrh r3, [r5, #12] + 80431ba: 059a lsls r2, r3, #22 + 80431bc: d402 bmi.n 80431c4 <_vfiprintf_r+0x220> + 80431be: 6da8 ldr r0, [r5, #88] ; 0x58 + 80431c0: f7ff fe6b bl 8042e9a <__retarget_lock_release_recursive> + 80431c4: 89ab ldrh r3, [r5, #12] + 80431c6: 065b lsls r3, r3, #25 + 80431c8: f53f af12 bmi.w 8042ff0 <_vfiprintf_r+0x4c> + 80431cc: 9809 ldr r0, [sp, #36] ; 0x24 + 80431ce: e711 b.n 8042ff4 <_vfiprintf_r+0x50> + 80431d0: ab03 add r3, sp, #12 + 80431d2: 9300 str r3, [sp, #0] + 80431d4: 462a mov r2, r5 + 80431d6: 4b09 ldr r3, [pc, #36] ; (80431fc <_vfiprintf_r+0x258>) + 80431d8: a904 add r1, sp, #16 + 80431da: 4630 mov r0, r6 + 80431dc: f000 f880 bl 80432e0 <_printf_i> + 80431e0: e7e4 b.n 80431ac <_vfiprintf_r+0x208> + 80431e2: bf00 nop + 80431e4: 08043b9c .word 0x08043b9c + 80431e8: 08043bbc .word 0x08043bbc + 80431ec: 08043b7c .word 0x08043b7c + 80431f0: 08043bdc .word 0x08043bdc + 80431f4: 08043be6 .word 0x08043be6 + 80431f8: 00000000 .word 0x00000000 + 80431fc: 08042f7f .word 0x08042f7f + 8043200: 08043be2 .word 0x08043be2 + +08043204 <_printf_common>: + 8043204: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8043208: 4616 mov r6, r2 + 804320a: 4699 mov r9, r3 + 804320c: 688a ldr r2, [r1, #8] + 804320e: 690b ldr r3, [r1, #16] + 8043210: f8dd 8020 ldr.w r8, [sp, #32] + 8043214: 4293 cmp r3, r2 + 8043216: bfb8 it lt + 8043218: 4613 movlt r3, r2 + 804321a: 6033 str r3, [r6, #0] + 804321c: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 + 8043220: 4607 mov r7, r0 + 8043222: 460c mov r4, r1 + 8043224: b10a cbz r2, 804322a <_printf_common+0x26> + 8043226: 3301 adds r3, #1 + 8043228: 6033 str r3, [r6, #0] + 804322a: 6823 ldr r3, [r4, #0] + 804322c: 0699 lsls r1, r3, #26 + 804322e: bf42 ittt mi + 8043230: 6833 ldrmi r3, [r6, #0] + 8043232: 3302 addmi r3, #2 + 8043234: 6033 strmi r3, [r6, #0] + 8043236: 6825 ldr r5, [r4, #0] + 8043238: f015 0506 ands.w r5, r5, #6 + 804323c: d106 bne.n 804324c <_printf_common+0x48> + 804323e: f104 0a19 add.w sl, r4, #25 + 8043242: 68e3 ldr r3, [r4, #12] + 8043244: 6832 ldr r2, [r6, #0] + 8043246: 1a9b subs r3, r3, r2 + 8043248: 42ab cmp r3, r5 + 804324a: dc26 bgt.n 804329a <_printf_common+0x96> + 804324c: f894 2043 ldrb.w r2, [r4, #67] ; 0x43 + 8043250: 1e13 subs r3, r2, #0 + 8043252: 6822 ldr r2, [r4, #0] + 8043254: bf18 it ne + 8043256: 2301 movne r3, #1 + 8043258: 0692 lsls r2, r2, #26 + 804325a: d42b bmi.n 80432b4 <_printf_common+0xb0> + 804325c: f104 0243 add.w r2, r4, #67 ; 0x43 + 8043260: 4649 mov r1, r9 + 8043262: 4638 mov r0, r7 + 8043264: 47c0 blx r8 + 8043266: 3001 adds r0, #1 + 8043268: d01e beq.n 80432a8 <_printf_common+0xa4> + 804326a: 6823 ldr r3, [r4, #0] + 804326c: 68e5 ldr r5, [r4, #12] + 804326e: 6832 ldr r2, [r6, #0] + 8043270: f003 0306 and.w r3, r3, #6 + 8043274: 2b04 cmp r3, #4 + 8043276: bf08 it eq + 8043278: 1aad subeq r5, r5, r2 + 804327a: 68a3 ldr r3, [r4, #8] + 804327c: 6922 ldr r2, [r4, #16] + 804327e: bf0c ite eq + 8043280: ea25 75e5 biceq.w r5, r5, r5, asr #31 + 8043284: 2500 movne r5, #0 + 8043286: 4293 cmp r3, r2 + 8043288: bfc4 itt gt + 804328a: 1a9b subgt r3, r3, r2 + 804328c: 18ed addgt r5, r5, r3 + 804328e: 2600 movs r6, #0 + 8043290: 341a adds r4, #26 + 8043292: 42b5 cmp r5, r6 + 8043294: d11a bne.n 80432cc <_printf_common+0xc8> + 8043296: 2000 movs r0, #0 + 8043298: e008 b.n 80432ac <_printf_common+0xa8> + 804329a: 2301 movs r3, #1 + 804329c: 4652 mov r2, sl + 804329e: 4649 mov r1, r9 + 80432a0: 4638 mov r0, r7 + 80432a2: 47c0 blx r8 + 80432a4: 3001 adds r0, #1 + 80432a6: d103 bne.n 80432b0 <_printf_common+0xac> + 80432a8: f04f 30ff mov.w r0, #4294967295 + 80432ac: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 80432b0: 3501 adds r5, #1 + 80432b2: e7c6 b.n 8043242 <_printf_common+0x3e> + 80432b4: 18e1 adds r1, r4, r3 + 80432b6: 1c5a adds r2, r3, #1 + 80432b8: 2030 movs r0, #48 ; 0x30 + 80432ba: f881 0043 strb.w r0, [r1, #67] ; 0x43 + 80432be: 4422 add r2, r4 + 80432c0: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 + 80432c4: f882 1043 strb.w r1, [r2, #67] ; 0x43 + 80432c8: 3302 adds r3, #2 + 80432ca: e7c7 b.n 804325c <_printf_common+0x58> + 80432cc: 2301 movs r3, #1 + 80432ce: 4622 mov r2, r4 + 80432d0: 4649 mov r1, r9 + 80432d2: 4638 mov r0, r7 + 80432d4: 47c0 blx r8 + 80432d6: 3001 adds r0, #1 + 80432d8: d0e6 beq.n 80432a8 <_printf_common+0xa4> + 80432da: 3601 adds r6, #1 + 80432dc: e7d9 b.n 8043292 <_printf_common+0x8e> ... -080432e4 <_printf_i>: - 80432e4: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} - 80432e8: 460c mov r4, r1 - 80432ea: 4691 mov r9, r2 - 80432ec: 7e27 ldrb r7, [r4, #24] - 80432ee: 990c ldr r1, [sp, #48] ; 0x30 - 80432f0: 2f78 cmp r7, #120 ; 0x78 - 80432f2: 4680 mov r8, r0 - 80432f4: 469a mov sl, r3 - 80432f6: f104 0243 add.w r2, r4, #67 ; 0x43 - 80432fa: d807 bhi.n 804330c <_printf_i+0x28> - 80432fc: 2f62 cmp r7, #98 ; 0x62 - 80432fe: d80a bhi.n 8043316 <_printf_i+0x32> - 8043300: 2f00 cmp r7, #0 - 8043302: f000 80d8 beq.w 80434b6 <_printf_i+0x1d2> - 8043306: 2f58 cmp r7, #88 ; 0x58 - 8043308: f000 80a3 beq.w 8043452 <_printf_i+0x16e> - 804330c: f104 0642 add.w r6, r4, #66 ; 0x42 - 8043310: f884 7042 strb.w r7, [r4, #66] ; 0x42 - 8043314: e03a b.n 804338c <_printf_i+0xa8> - 8043316: f1a7 0363 sub.w r3, r7, #99 ; 0x63 - 804331a: 2b15 cmp r3, #21 - 804331c: d8f6 bhi.n 804330c <_printf_i+0x28> - 804331e: a001 add r0, pc, #4 ; (adr r0, 8043324 <_printf_i+0x40>) - 8043320: f850 f023 ldr.w pc, [r0, r3, lsl #2] - 8043324: 0804337d .word 0x0804337d - 8043328: 08043391 .word 0x08043391 - 804332c: 0804330d .word 0x0804330d - 8043330: 0804330d .word 0x0804330d - 8043334: 0804330d .word 0x0804330d - 8043338: 0804330d .word 0x0804330d - 804333c: 08043391 .word 0x08043391 - 8043340: 0804330d .word 0x0804330d - 8043344: 0804330d .word 0x0804330d - 8043348: 0804330d .word 0x0804330d - 804334c: 0804330d .word 0x0804330d - 8043350: 0804349d .word 0x0804349d - 8043354: 080433c1 .word 0x080433c1 - 8043358: 0804347f .word 0x0804347f - 804335c: 0804330d .word 0x0804330d - 8043360: 0804330d .word 0x0804330d - 8043364: 080434bf .word 0x080434bf - 8043368: 0804330d .word 0x0804330d - 804336c: 080433c1 .word 0x080433c1 - 8043370: 0804330d .word 0x0804330d - 8043374: 0804330d .word 0x0804330d - 8043378: 08043487 .word 0x08043487 - 804337c: 680b ldr r3, [r1, #0] - 804337e: 1d1a adds r2, r3, #4 - 8043380: 681b ldr r3, [r3, #0] - 8043382: 600a str r2, [r1, #0] - 8043384: f104 0642 add.w r6, r4, #66 ; 0x42 - 8043388: f884 3042 strb.w r3, [r4, #66] ; 0x42 - 804338c: 2301 movs r3, #1 - 804338e: e0a3 b.n 80434d8 <_printf_i+0x1f4> - 8043390: 6825 ldr r5, [r4, #0] - 8043392: 6808 ldr r0, [r1, #0] - 8043394: 062e lsls r6, r5, #24 - 8043396: f100 0304 add.w r3, r0, #4 - 804339a: d50a bpl.n 80433b2 <_printf_i+0xce> - 804339c: 6805 ldr r5, [r0, #0] - 804339e: 600b str r3, [r1, #0] - 80433a0: 2d00 cmp r5, #0 - 80433a2: da03 bge.n 80433ac <_printf_i+0xc8> - 80433a4: 232d movs r3, #45 ; 0x2d - 80433a6: 426d negs r5, r5 - 80433a8: f884 3043 strb.w r3, [r4, #67] ; 0x43 - 80433ac: 485e ldr r0, [pc, #376] ; (8043528 <_printf_i+0x244>) - 80433ae: 230a movs r3, #10 - 80433b0: e019 b.n 80433e6 <_printf_i+0x102> - 80433b2: f015 0f40 tst.w r5, #64 ; 0x40 - 80433b6: 6805 ldr r5, [r0, #0] - 80433b8: 600b str r3, [r1, #0] - 80433ba: bf18 it ne - 80433bc: b22d sxthne r5, r5 - 80433be: e7ef b.n 80433a0 <_printf_i+0xbc> - 80433c0: 680b ldr r3, [r1, #0] - 80433c2: 6825 ldr r5, [r4, #0] - 80433c4: 1d18 adds r0, r3, #4 - 80433c6: 6008 str r0, [r1, #0] - 80433c8: 0628 lsls r0, r5, #24 - 80433ca: d501 bpl.n 80433d0 <_printf_i+0xec> - 80433cc: 681d ldr r5, [r3, #0] - 80433ce: e002 b.n 80433d6 <_printf_i+0xf2> - 80433d0: 0669 lsls r1, r5, #25 - 80433d2: d5fb bpl.n 80433cc <_printf_i+0xe8> - 80433d4: 881d ldrh r5, [r3, #0] - 80433d6: 4854 ldr r0, [pc, #336] ; (8043528 <_printf_i+0x244>) - 80433d8: 2f6f cmp r7, #111 ; 0x6f - 80433da: bf0c ite eq - 80433dc: 2308 moveq r3, #8 - 80433de: 230a movne r3, #10 - 80433e0: 2100 movs r1, #0 - 80433e2: f884 1043 strb.w r1, [r4, #67] ; 0x43 - 80433e6: 6866 ldr r6, [r4, #4] - 80433e8: 60a6 str r6, [r4, #8] - 80433ea: 2e00 cmp r6, #0 - 80433ec: bfa2 ittt ge - 80433ee: 6821 ldrge r1, [r4, #0] - 80433f0: f021 0104 bicge.w r1, r1, #4 - 80433f4: 6021 strge r1, [r4, #0] - 80433f6: b90d cbnz r5, 80433fc <_printf_i+0x118> - 80433f8: 2e00 cmp r6, #0 - 80433fa: d04d beq.n 8043498 <_printf_i+0x1b4> - 80433fc: 4616 mov r6, r2 - 80433fe: fbb5 f1f3 udiv r1, r5, r3 - 8043402: fb03 5711 mls r7, r3, r1, r5 - 8043406: 5dc7 ldrb r7, [r0, r7] - 8043408: f806 7d01 strb.w r7, [r6, #-1]! - 804340c: 462f mov r7, r5 - 804340e: 42bb cmp r3, r7 - 8043410: 460d mov r5, r1 - 8043412: d9f4 bls.n 80433fe <_printf_i+0x11a> - 8043414: 2b08 cmp r3, #8 - 8043416: d10b bne.n 8043430 <_printf_i+0x14c> - 8043418: 6823 ldr r3, [r4, #0] - 804341a: 07df lsls r7, r3, #31 - 804341c: d508 bpl.n 8043430 <_printf_i+0x14c> - 804341e: 6923 ldr r3, [r4, #16] - 8043420: 6861 ldr r1, [r4, #4] - 8043422: 4299 cmp r1, r3 - 8043424: bfde ittt le - 8043426: 2330 movle r3, #48 ; 0x30 - 8043428: f806 3c01 strble.w r3, [r6, #-1] - 804342c: f106 36ff addle.w r6, r6, #4294967295 - 8043430: 1b92 subs r2, r2, r6 - 8043432: 6122 str r2, [r4, #16] - 8043434: f8cd a000 str.w sl, [sp] - 8043438: 464b mov r3, r9 - 804343a: aa03 add r2, sp, #12 - 804343c: 4621 mov r1, r4 - 804343e: 4640 mov r0, r8 - 8043440: f7ff fee2 bl 8043208 <_printf_common> - 8043444: 3001 adds r0, #1 - 8043446: d14c bne.n 80434e2 <_printf_i+0x1fe> - 8043448: f04f 30ff mov.w r0, #4294967295 - 804344c: b004 add sp, #16 - 804344e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 8043452: 4835 ldr r0, [pc, #212] ; (8043528 <_printf_i+0x244>) - 8043454: f884 7045 strb.w r7, [r4, #69] ; 0x45 - 8043458: 6823 ldr r3, [r4, #0] - 804345a: 680e ldr r6, [r1, #0] - 804345c: 061f lsls r7, r3, #24 - 804345e: f856 5b04 ldr.w r5, [r6], #4 - 8043462: 600e str r6, [r1, #0] - 8043464: d514 bpl.n 8043490 <_printf_i+0x1ac> - 8043466: 07d9 lsls r1, r3, #31 - 8043468: bf44 itt mi - 804346a: f043 0320 orrmi.w r3, r3, #32 - 804346e: 6023 strmi r3, [r4, #0] - 8043470: b91d cbnz r5, 804347a <_printf_i+0x196> - 8043472: 6823 ldr r3, [r4, #0] - 8043474: f023 0320 bic.w r3, r3, #32 - 8043478: 6023 str r3, [r4, #0] - 804347a: 2310 movs r3, #16 - 804347c: e7b0 b.n 80433e0 <_printf_i+0xfc> - 804347e: 6823 ldr r3, [r4, #0] - 8043480: f043 0320 orr.w r3, r3, #32 - 8043484: 6023 str r3, [r4, #0] - 8043486: 2378 movs r3, #120 ; 0x78 - 8043488: 4828 ldr r0, [pc, #160] ; (804352c <_printf_i+0x248>) - 804348a: f884 3045 strb.w r3, [r4, #69] ; 0x45 - 804348e: e7e3 b.n 8043458 <_printf_i+0x174> - 8043490: 065e lsls r6, r3, #25 - 8043492: bf48 it mi - 8043494: b2ad uxthmi r5, r5 - 8043496: e7e6 b.n 8043466 <_printf_i+0x182> - 8043498: 4616 mov r6, r2 - 804349a: e7bb b.n 8043414 <_printf_i+0x130> - 804349c: 680b ldr r3, [r1, #0] - 804349e: 6826 ldr r6, [r4, #0] - 80434a0: 6960 ldr r0, [r4, #20] - 80434a2: 1d1d adds r5, r3, #4 - 80434a4: 600d str r5, [r1, #0] - 80434a6: 0635 lsls r5, r6, #24 - 80434a8: 681b ldr r3, [r3, #0] - 80434aa: d501 bpl.n 80434b0 <_printf_i+0x1cc> - 80434ac: 6018 str r0, [r3, #0] - 80434ae: e002 b.n 80434b6 <_printf_i+0x1d2> - 80434b0: 0671 lsls r1, r6, #25 - 80434b2: d5fb bpl.n 80434ac <_printf_i+0x1c8> - 80434b4: 8018 strh r0, [r3, #0] - 80434b6: 2300 movs r3, #0 - 80434b8: 6123 str r3, [r4, #16] - 80434ba: 4616 mov r6, r2 - 80434bc: e7ba b.n 8043434 <_printf_i+0x150> - 80434be: 680b ldr r3, [r1, #0] - 80434c0: 1d1a adds r2, r3, #4 - 80434c2: 600a str r2, [r1, #0] - 80434c4: 681e ldr r6, [r3, #0] - 80434c6: 6862 ldr r2, [r4, #4] - 80434c8: 2100 movs r1, #0 - 80434ca: 4630 mov r0, r6 - 80434cc: f7fc feb8 bl 8040240 - 80434d0: b108 cbz r0, 80434d6 <_printf_i+0x1f2> - 80434d2: 1b80 subs r0, r0, r6 - 80434d4: 6060 str r0, [r4, #4] - 80434d6: 6863 ldr r3, [r4, #4] - 80434d8: 6123 str r3, [r4, #16] - 80434da: 2300 movs r3, #0 - 80434dc: f884 3043 strb.w r3, [r4, #67] ; 0x43 - 80434e0: e7a8 b.n 8043434 <_printf_i+0x150> - 80434e2: 6923 ldr r3, [r4, #16] - 80434e4: 4632 mov r2, r6 - 80434e6: 4649 mov r1, r9 - 80434e8: 4640 mov r0, r8 - 80434ea: 47d0 blx sl - 80434ec: 3001 adds r0, #1 - 80434ee: d0ab beq.n 8043448 <_printf_i+0x164> - 80434f0: 6823 ldr r3, [r4, #0] - 80434f2: 079b lsls r3, r3, #30 - 80434f4: d413 bmi.n 804351e <_printf_i+0x23a> - 80434f6: 68e0 ldr r0, [r4, #12] - 80434f8: 9b03 ldr r3, [sp, #12] - 80434fa: 4298 cmp r0, r3 - 80434fc: bfb8 it lt - 80434fe: 4618 movlt r0, r3 - 8043500: e7a4 b.n 804344c <_printf_i+0x168> - 8043502: 2301 movs r3, #1 - 8043504: 4632 mov r2, r6 - 8043506: 4649 mov r1, r9 - 8043508: 4640 mov r0, r8 - 804350a: 47d0 blx sl - 804350c: 3001 adds r0, #1 - 804350e: d09b beq.n 8043448 <_printf_i+0x164> - 8043510: 3501 adds r5, #1 - 8043512: 68e3 ldr r3, [r4, #12] - 8043514: 9903 ldr r1, [sp, #12] - 8043516: 1a5b subs r3, r3, r1 - 8043518: 42ab cmp r3, r5 - 804351a: dcf2 bgt.n 8043502 <_printf_i+0x21e> - 804351c: e7eb b.n 80434f6 <_printf_i+0x212> - 804351e: 2500 movs r5, #0 - 8043520: f104 0619 add.w r6, r4, #25 - 8043524: e7f5 b.n 8043512 <_printf_i+0x22e> - 8043526: bf00 nop - 8043528: 08043bf1 .word 0x08043bf1 - 804352c: 08043c02 .word 0x08043c02 - -08043530 <_sbrk_r>: - 8043530: b538 push {r3, r4, r5, lr} - 8043532: 4d06 ldr r5, [pc, #24] ; (804354c <_sbrk_r+0x1c>) - 8043534: 2300 movs r3, #0 - 8043536: 4604 mov r4, r0 - 8043538: 4608 mov r0, r1 - 804353a: 602b str r3, [r5, #0] - 804353c: f7fd fa74 bl 8040a28 <_sbrk> - 8043540: 1c43 adds r3, r0, #1 - 8043542: d102 bne.n 804354a <_sbrk_r+0x1a> - 8043544: 682b ldr r3, [r5, #0] - 8043546: b103 cbz r3, 804354a <_sbrk_r+0x1a> - 8043548: 6023 str r3, [r4, #0] - 804354a: bd38 pop {r3, r4, r5, pc} - 804354c: 2000012c .word 0x2000012c - -08043550 <__sread>: - 8043550: b510 push {r4, lr} - 8043552: 460c mov r4, r1 - 8043554: f9b1 100e ldrsh.w r1, [r1, #14] - 8043558: f000 fab4 bl 8043ac4 <_read_r> - 804355c: 2800 cmp r0, #0 - 804355e: bfab itete ge - 8043560: 6d63 ldrge r3, [r4, #84] ; 0x54 - 8043562: 89a3 ldrhlt r3, [r4, #12] - 8043564: 181b addge r3, r3, r0 - 8043566: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 - 804356a: bfac ite ge - 804356c: 6563 strge r3, [r4, #84] ; 0x54 - 804356e: 81a3 strhlt r3, [r4, #12] - 8043570: bd10 pop {r4, pc} - -08043572 <__swrite>: - 8043572: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} - 8043576: 461f mov r7, r3 - 8043578: 898b ldrh r3, [r1, #12] - 804357a: 05db lsls r3, r3, #23 - 804357c: 4605 mov r5, r0 - 804357e: 460c mov r4, r1 - 8043580: 4616 mov r6, r2 - 8043582: d505 bpl.n 8043590 <__swrite+0x1e> - 8043584: f9b1 100e ldrsh.w r1, [r1, #14] - 8043588: 2302 movs r3, #2 - 804358a: 2200 movs r2, #0 - 804358c: f000 f9c8 bl 8043920 <_lseek_r> - 8043590: 89a3 ldrh r3, [r4, #12] - 8043592: f9b4 100e ldrsh.w r1, [r4, #14] - 8043596: f423 5380 bic.w r3, r3, #4096 ; 0x1000 - 804359a: 81a3 strh r3, [r4, #12] - 804359c: 4632 mov r2, r6 - 804359e: 463b mov r3, r7 - 80435a0: 4628 mov r0, r5 - 80435a2: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} - 80435a6: f000 b869 b.w 804367c <_write_r> - -080435aa <__sseek>: - 80435aa: b510 push {r4, lr} - 80435ac: 460c mov r4, r1 - 80435ae: f9b1 100e ldrsh.w r1, [r1, #14] - 80435b2: f000 f9b5 bl 8043920 <_lseek_r> - 80435b6: 1c43 adds r3, r0, #1 - 80435b8: 89a3 ldrh r3, [r4, #12] - 80435ba: bf15 itete ne - 80435bc: 6560 strne r0, [r4, #84] ; 0x54 - 80435be: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 - 80435c2: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 - 80435c6: 81a3 strheq r3, [r4, #12] - 80435c8: bf18 it ne - 80435ca: 81a3 strhne r3, [r4, #12] - 80435cc: bd10 pop {r4, pc} - -080435ce <__sclose>: - 80435ce: f9b1 100e ldrsh.w r1, [r1, #14] - 80435d2: f000 b8d3 b.w 804377c <_close_r> +080432e0 <_printf_i>: + 80432e0: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} + 80432e4: 460c mov r4, r1 + 80432e6: 4691 mov r9, r2 + 80432e8: 7e27 ldrb r7, [r4, #24] + 80432ea: 990c ldr r1, [sp, #48] ; 0x30 + 80432ec: 2f78 cmp r7, #120 ; 0x78 + 80432ee: 4680 mov r8, r0 + 80432f0: 469a mov sl, r3 + 80432f2: f104 0243 add.w r2, r4, #67 ; 0x43 + 80432f6: d807 bhi.n 8043308 <_printf_i+0x28> + 80432f8: 2f62 cmp r7, #98 ; 0x62 + 80432fa: d80a bhi.n 8043312 <_printf_i+0x32> + 80432fc: 2f00 cmp r7, #0 + 80432fe: f000 80d8 beq.w 80434b2 <_printf_i+0x1d2> + 8043302: 2f58 cmp r7, #88 ; 0x58 + 8043304: f000 80a3 beq.w 804344e <_printf_i+0x16e> + 8043308: f104 0642 add.w r6, r4, #66 ; 0x42 + 804330c: f884 7042 strb.w r7, [r4, #66] ; 0x42 + 8043310: e03a b.n 8043388 <_printf_i+0xa8> + 8043312: f1a7 0363 sub.w r3, r7, #99 ; 0x63 + 8043316: 2b15 cmp r3, #21 + 8043318: d8f6 bhi.n 8043308 <_printf_i+0x28> + 804331a: a001 add r0, pc, #4 ; (adr r0, 8043320 <_printf_i+0x40>) + 804331c: f850 f023 ldr.w pc, [r0, r3, lsl #2] + 8043320: 08043379 .word 0x08043379 + 8043324: 0804338d .word 0x0804338d + 8043328: 08043309 .word 0x08043309 + 804332c: 08043309 .word 0x08043309 + 8043330: 08043309 .word 0x08043309 + 8043334: 08043309 .word 0x08043309 + 8043338: 0804338d .word 0x0804338d + 804333c: 08043309 .word 0x08043309 + 8043340: 08043309 .word 0x08043309 + 8043344: 08043309 .word 0x08043309 + 8043348: 08043309 .word 0x08043309 + 804334c: 08043499 .word 0x08043499 + 8043350: 080433bd .word 0x080433bd + 8043354: 0804347b .word 0x0804347b + 8043358: 08043309 .word 0x08043309 + 804335c: 08043309 .word 0x08043309 + 8043360: 080434bb .word 0x080434bb + 8043364: 08043309 .word 0x08043309 + 8043368: 080433bd .word 0x080433bd + 804336c: 08043309 .word 0x08043309 + 8043370: 08043309 .word 0x08043309 + 8043374: 08043483 .word 0x08043483 + 8043378: 680b ldr r3, [r1, #0] + 804337a: 1d1a adds r2, r3, #4 + 804337c: 681b ldr r3, [r3, #0] + 804337e: 600a str r2, [r1, #0] + 8043380: f104 0642 add.w r6, r4, #66 ; 0x42 + 8043384: f884 3042 strb.w r3, [r4, #66] ; 0x42 + 8043388: 2301 movs r3, #1 + 804338a: e0a3 b.n 80434d4 <_printf_i+0x1f4> + 804338c: 6825 ldr r5, [r4, #0] + 804338e: 6808 ldr r0, [r1, #0] + 8043390: 062e lsls r6, r5, #24 + 8043392: f100 0304 add.w r3, r0, #4 + 8043396: d50a bpl.n 80433ae <_printf_i+0xce> + 8043398: 6805 ldr r5, [r0, #0] + 804339a: 600b str r3, [r1, #0] + 804339c: 2d00 cmp r5, #0 + 804339e: da03 bge.n 80433a8 <_printf_i+0xc8> + 80433a0: 232d movs r3, #45 ; 0x2d + 80433a2: 426d negs r5, r5 + 80433a4: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 80433a8: 485e ldr r0, [pc, #376] ; (8043524 <_printf_i+0x244>) + 80433aa: 230a movs r3, #10 + 80433ac: e019 b.n 80433e2 <_printf_i+0x102> + 80433ae: f015 0f40 tst.w r5, #64 ; 0x40 + 80433b2: 6805 ldr r5, [r0, #0] + 80433b4: 600b str r3, [r1, #0] + 80433b6: bf18 it ne + 80433b8: b22d sxthne r5, r5 + 80433ba: e7ef b.n 804339c <_printf_i+0xbc> + 80433bc: 680b ldr r3, [r1, #0] + 80433be: 6825 ldr r5, [r4, #0] + 80433c0: 1d18 adds r0, r3, #4 + 80433c2: 6008 str r0, [r1, #0] + 80433c4: 0628 lsls r0, r5, #24 + 80433c6: d501 bpl.n 80433cc <_printf_i+0xec> + 80433c8: 681d ldr r5, [r3, #0] + 80433ca: e002 b.n 80433d2 <_printf_i+0xf2> + 80433cc: 0669 lsls r1, r5, #25 + 80433ce: d5fb bpl.n 80433c8 <_printf_i+0xe8> + 80433d0: 881d ldrh r5, [r3, #0] + 80433d2: 4854 ldr r0, [pc, #336] ; (8043524 <_printf_i+0x244>) + 80433d4: 2f6f cmp r7, #111 ; 0x6f + 80433d6: bf0c ite eq + 80433d8: 2308 moveq r3, #8 + 80433da: 230a movne r3, #10 + 80433dc: 2100 movs r1, #0 + 80433de: f884 1043 strb.w r1, [r4, #67] ; 0x43 + 80433e2: 6866 ldr r6, [r4, #4] + 80433e4: 60a6 str r6, [r4, #8] + 80433e6: 2e00 cmp r6, #0 + 80433e8: bfa2 ittt ge + 80433ea: 6821 ldrge r1, [r4, #0] + 80433ec: f021 0104 bicge.w r1, r1, #4 + 80433f0: 6021 strge r1, [r4, #0] + 80433f2: b90d cbnz r5, 80433f8 <_printf_i+0x118> + 80433f4: 2e00 cmp r6, #0 + 80433f6: d04d beq.n 8043494 <_printf_i+0x1b4> + 80433f8: 4616 mov r6, r2 + 80433fa: fbb5 f1f3 udiv r1, r5, r3 + 80433fe: fb03 5711 mls r7, r3, r1, r5 + 8043402: 5dc7 ldrb r7, [r0, r7] + 8043404: f806 7d01 strb.w r7, [r6, #-1]! + 8043408: 462f mov r7, r5 + 804340a: 42bb cmp r3, r7 + 804340c: 460d mov r5, r1 + 804340e: d9f4 bls.n 80433fa <_printf_i+0x11a> + 8043410: 2b08 cmp r3, #8 + 8043412: d10b bne.n 804342c <_printf_i+0x14c> + 8043414: 6823 ldr r3, [r4, #0] + 8043416: 07df lsls r7, r3, #31 + 8043418: d508 bpl.n 804342c <_printf_i+0x14c> + 804341a: 6923 ldr r3, [r4, #16] + 804341c: 6861 ldr r1, [r4, #4] + 804341e: 4299 cmp r1, r3 + 8043420: bfde ittt le + 8043422: 2330 movle r3, #48 ; 0x30 + 8043424: f806 3c01 strble.w r3, [r6, #-1] + 8043428: f106 36ff addle.w r6, r6, #4294967295 + 804342c: 1b92 subs r2, r2, r6 + 804342e: 6122 str r2, [r4, #16] + 8043430: f8cd a000 str.w sl, [sp] + 8043434: 464b mov r3, r9 + 8043436: aa03 add r2, sp, #12 + 8043438: 4621 mov r1, r4 + 804343a: 4640 mov r0, r8 + 804343c: f7ff fee2 bl 8043204 <_printf_common> + 8043440: 3001 adds r0, #1 + 8043442: d14c bne.n 80434de <_printf_i+0x1fe> + 8043444: f04f 30ff mov.w r0, #4294967295 + 8043448: b004 add sp, #16 + 804344a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 804344e: 4835 ldr r0, [pc, #212] ; (8043524 <_printf_i+0x244>) + 8043450: f884 7045 strb.w r7, [r4, #69] ; 0x45 + 8043454: 6823 ldr r3, [r4, #0] + 8043456: 680e ldr r6, [r1, #0] + 8043458: 061f lsls r7, r3, #24 + 804345a: f856 5b04 ldr.w r5, [r6], #4 + 804345e: 600e str r6, [r1, #0] + 8043460: d514 bpl.n 804348c <_printf_i+0x1ac> + 8043462: 07d9 lsls r1, r3, #31 + 8043464: bf44 itt mi + 8043466: f043 0320 orrmi.w r3, r3, #32 + 804346a: 6023 strmi r3, [r4, #0] + 804346c: b91d cbnz r5, 8043476 <_printf_i+0x196> + 804346e: 6823 ldr r3, [r4, #0] + 8043470: f023 0320 bic.w r3, r3, #32 + 8043474: 6023 str r3, [r4, #0] + 8043476: 2310 movs r3, #16 + 8043478: e7b0 b.n 80433dc <_printf_i+0xfc> + 804347a: 6823 ldr r3, [r4, #0] + 804347c: f043 0320 orr.w r3, r3, #32 + 8043480: 6023 str r3, [r4, #0] + 8043482: 2378 movs r3, #120 ; 0x78 + 8043484: 4828 ldr r0, [pc, #160] ; (8043528 <_printf_i+0x248>) + 8043486: f884 3045 strb.w r3, [r4, #69] ; 0x45 + 804348a: e7e3 b.n 8043454 <_printf_i+0x174> + 804348c: 065e lsls r6, r3, #25 + 804348e: bf48 it mi + 8043490: b2ad uxthmi r5, r5 + 8043492: e7e6 b.n 8043462 <_printf_i+0x182> + 8043494: 4616 mov r6, r2 + 8043496: e7bb b.n 8043410 <_printf_i+0x130> + 8043498: 680b ldr r3, [r1, #0] + 804349a: 6826 ldr r6, [r4, #0] + 804349c: 6960 ldr r0, [r4, #20] + 804349e: 1d1d adds r5, r3, #4 + 80434a0: 600d str r5, [r1, #0] + 80434a2: 0635 lsls r5, r6, #24 + 80434a4: 681b ldr r3, [r3, #0] + 80434a6: d501 bpl.n 80434ac <_printf_i+0x1cc> + 80434a8: 6018 str r0, [r3, #0] + 80434aa: e002 b.n 80434b2 <_printf_i+0x1d2> + 80434ac: 0671 lsls r1, r6, #25 + 80434ae: d5fb bpl.n 80434a8 <_printf_i+0x1c8> + 80434b0: 8018 strh r0, [r3, #0] + 80434b2: 2300 movs r3, #0 + 80434b4: 6123 str r3, [r4, #16] + 80434b6: 4616 mov r6, r2 + 80434b8: e7ba b.n 8043430 <_printf_i+0x150> + 80434ba: 680b ldr r3, [r1, #0] + 80434bc: 1d1a adds r2, r3, #4 + 80434be: 600a str r2, [r1, #0] + 80434c0: 681e ldr r6, [r3, #0] + 80434c2: 6862 ldr r2, [r4, #4] + 80434c4: 2100 movs r1, #0 + 80434c6: 4630 mov r0, r6 + 80434c8: f7fc feba bl 8040240 + 80434cc: b108 cbz r0, 80434d2 <_printf_i+0x1f2> + 80434ce: 1b80 subs r0, r0, r6 + 80434d0: 6060 str r0, [r4, #4] + 80434d2: 6863 ldr r3, [r4, #4] + 80434d4: 6123 str r3, [r4, #16] + 80434d6: 2300 movs r3, #0 + 80434d8: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 80434dc: e7a8 b.n 8043430 <_printf_i+0x150> + 80434de: 6923 ldr r3, [r4, #16] + 80434e0: 4632 mov r2, r6 + 80434e2: 4649 mov r1, r9 + 80434e4: 4640 mov r0, r8 + 80434e6: 47d0 blx sl + 80434e8: 3001 adds r0, #1 + 80434ea: d0ab beq.n 8043444 <_printf_i+0x164> + 80434ec: 6823 ldr r3, [r4, #0] + 80434ee: 079b lsls r3, r3, #30 + 80434f0: d413 bmi.n 804351a <_printf_i+0x23a> + 80434f2: 68e0 ldr r0, [r4, #12] + 80434f4: 9b03 ldr r3, [sp, #12] + 80434f6: 4298 cmp r0, r3 + 80434f8: bfb8 it lt + 80434fa: 4618 movlt r0, r3 + 80434fc: e7a4 b.n 8043448 <_printf_i+0x168> + 80434fe: 2301 movs r3, #1 + 8043500: 4632 mov r2, r6 + 8043502: 4649 mov r1, r9 + 8043504: 4640 mov r0, r8 + 8043506: 47d0 blx sl + 8043508: 3001 adds r0, #1 + 804350a: d09b beq.n 8043444 <_printf_i+0x164> + 804350c: 3501 adds r5, #1 + 804350e: 68e3 ldr r3, [r4, #12] + 8043510: 9903 ldr r1, [sp, #12] + 8043512: 1a5b subs r3, r3, r1 + 8043514: 42ab cmp r3, r5 + 8043516: dcf2 bgt.n 80434fe <_printf_i+0x21e> + 8043518: e7eb b.n 80434f2 <_printf_i+0x212> + 804351a: 2500 movs r5, #0 + 804351c: f104 0619 add.w r6, r4, #25 + 8043520: e7f5 b.n 804350e <_printf_i+0x22e> + 8043522: bf00 nop + 8043524: 08043bed .word 0x08043bed + 8043528: 08043bfe .word 0x08043bfe + +0804352c <_sbrk_r>: + 804352c: b538 push {r3, r4, r5, lr} + 804352e: 4d06 ldr r5, [pc, #24] ; (8043548 <_sbrk_r+0x1c>) + 8043530: 2300 movs r3, #0 + 8043532: 4604 mov r4, r0 + 8043534: 4608 mov r0, r1 + 8043536: 602b str r3, [r5, #0] + 8043538: f7fd fa74 bl 8040a24 <_sbrk> + 804353c: 1c43 adds r3, r0, #1 + 804353e: d102 bne.n 8043546 <_sbrk_r+0x1a> + 8043540: 682b ldr r3, [r5, #0] + 8043542: b103 cbz r3, 8043546 <_sbrk_r+0x1a> + 8043544: 6023 str r3, [r4, #0] + 8043546: bd38 pop {r3, r4, r5, pc} + 8043548: 2000012c .word 0x2000012c + +0804354c <__sread>: + 804354c: b510 push {r4, lr} + 804354e: 460c mov r4, r1 + 8043550: f9b1 100e ldrsh.w r1, [r1, #14] + 8043554: f000 fab4 bl 8043ac0 <_read_r> + 8043558: 2800 cmp r0, #0 + 804355a: bfab itete ge + 804355c: 6d63 ldrge r3, [r4, #84] ; 0x54 + 804355e: 89a3 ldrhlt r3, [r4, #12] + 8043560: 181b addge r3, r3, r0 + 8043562: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 + 8043566: bfac ite ge + 8043568: 6563 strge r3, [r4, #84] ; 0x54 + 804356a: 81a3 strhlt r3, [r4, #12] + 804356c: bd10 pop {r4, pc} + +0804356e <__swrite>: + 804356e: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8043572: 461f mov r7, r3 + 8043574: 898b ldrh r3, [r1, #12] + 8043576: 05db lsls r3, r3, #23 + 8043578: 4605 mov r5, r0 + 804357a: 460c mov r4, r1 + 804357c: 4616 mov r6, r2 + 804357e: d505 bpl.n 804358c <__swrite+0x1e> + 8043580: f9b1 100e ldrsh.w r1, [r1, #14] + 8043584: 2302 movs r3, #2 + 8043586: 2200 movs r2, #0 + 8043588: f000 f9c8 bl 804391c <_lseek_r> + 804358c: 89a3 ldrh r3, [r4, #12] + 804358e: f9b4 100e ldrsh.w r1, [r4, #14] + 8043592: f423 5380 bic.w r3, r3, #4096 ; 0x1000 + 8043596: 81a3 strh r3, [r4, #12] + 8043598: 4632 mov r2, r6 + 804359a: 463b mov r3, r7 + 804359c: 4628 mov r0, r5 + 804359e: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 80435a2: f000 b869 b.w 8043678 <_write_r> + +080435a6 <__sseek>: + 80435a6: b510 push {r4, lr} + 80435a8: 460c mov r4, r1 + 80435aa: f9b1 100e ldrsh.w r1, [r1, #14] + 80435ae: f000 f9b5 bl 804391c <_lseek_r> + 80435b2: 1c43 adds r3, r0, #1 + 80435b4: 89a3 ldrh r3, [r4, #12] + 80435b6: bf15 itete ne + 80435b8: 6560 strne r0, [r4, #84] ; 0x54 + 80435ba: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 + 80435be: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 + 80435c2: 81a3 strheq r3, [r4, #12] + 80435c4: bf18 it ne + 80435c6: 81a3 strhne r3, [r4, #12] + 80435c8: bd10 pop {r4, pc} + +080435ca <__sclose>: + 80435ca: f9b1 100e ldrsh.w r1, [r1, #14] + 80435ce: f000 b8d3 b.w 8043778 <_close_r> ... -080435d8 <__swbuf_r>: - 80435d8: b5f8 push {r3, r4, r5, r6, r7, lr} - 80435da: 460e mov r6, r1 - 80435dc: 4614 mov r4, r2 - 80435de: 4605 mov r5, r0 - 80435e0: b118 cbz r0, 80435ea <__swbuf_r+0x12> - 80435e2: 6983 ldr r3, [r0, #24] - 80435e4: b90b cbnz r3, 80435ea <__swbuf_r+0x12> - 80435e6: f7ff fbbb bl 8042d60 <__sinit> - 80435ea: 4b21 ldr r3, [pc, #132] ; (8043670 <__swbuf_r+0x98>) - 80435ec: 429c cmp r4, r3 - 80435ee: d12b bne.n 8043648 <__swbuf_r+0x70> - 80435f0: 686c ldr r4, [r5, #4] - 80435f2: 69a3 ldr r3, [r4, #24] - 80435f4: 60a3 str r3, [r4, #8] - 80435f6: 89a3 ldrh r3, [r4, #12] - 80435f8: 071a lsls r2, r3, #28 - 80435fa: d52f bpl.n 804365c <__swbuf_r+0x84> +080435d4 <__swbuf_r>: + 80435d4: b5f8 push {r3, r4, r5, r6, r7, lr} + 80435d6: 460e mov r6, r1 + 80435d8: 4614 mov r4, r2 + 80435da: 4605 mov r5, r0 + 80435dc: b118 cbz r0, 80435e6 <__swbuf_r+0x12> + 80435de: 6983 ldr r3, [r0, #24] + 80435e0: b90b cbnz r3, 80435e6 <__swbuf_r+0x12> + 80435e2: f7ff fbbb bl 8042d5c <__sinit> + 80435e6: 4b21 ldr r3, [pc, #132] ; (804366c <__swbuf_r+0x98>) + 80435e8: 429c cmp r4, r3 + 80435ea: d12b bne.n 8043644 <__swbuf_r+0x70> + 80435ec: 686c ldr r4, [r5, #4] + 80435ee: 69a3 ldr r3, [r4, #24] + 80435f0: 60a3 str r3, [r4, #8] + 80435f2: 89a3 ldrh r3, [r4, #12] + 80435f4: 071a lsls r2, r3, #28 + 80435f6: d52f bpl.n 8043658 <__swbuf_r+0x84> + 80435f8: 6923 ldr r3, [r4, #16] + 80435fa: b36b cbz r3, 8043658 <__swbuf_r+0x84> 80435fc: 6923 ldr r3, [r4, #16] - 80435fe: b36b cbz r3, 804365c <__swbuf_r+0x84> - 8043600: 6923 ldr r3, [r4, #16] - 8043602: 6820 ldr r0, [r4, #0] - 8043604: 1ac0 subs r0, r0, r3 - 8043606: 6963 ldr r3, [r4, #20] - 8043608: b2f6 uxtb r6, r6 - 804360a: 4283 cmp r3, r0 - 804360c: 4637 mov r7, r6 - 804360e: dc04 bgt.n 804361a <__swbuf_r+0x42> - 8043610: 4621 mov r1, r4 - 8043612: 4628 mov r0, r5 - 8043614: f000 f948 bl 80438a8 <_fflush_r> - 8043618: bb30 cbnz r0, 8043668 <__swbuf_r+0x90> - 804361a: 68a3 ldr r3, [r4, #8] - 804361c: 3b01 subs r3, #1 - 804361e: 60a3 str r3, [r4, #8] - 8043620: 6823 ldr r3, [r4, #0] - 8043622: 1c5a adds r2, r3, #1 - 8043624: 6022 str r2, [r4, #0] - 8043626: 701e strb r6, [r3, #0] - 8043628: 6963 ldr r3, [r4, #20] - 804362a: 3001 adds r0, #1 - 804362c: 4283 cmp r3, r0 - 804362e: d004 beq.n 804363a <__swbuf_r+0x62> - 8043630: 89a3 ldrh r3, [r4, #12] - 8043632: 07db lsls r3, r3, #31 - 8043634: d506 bpl.n 8043644 <__swbuf_r+0x6c> - 8043636: 2e0a cmp r6, #10 - 8043638: d104 bne.n 8043644 <__swbuf_r+0x6c> - 804363a: 4621 mov r1, r4 - 804363c: 4628 mov r0, r5 - 804363e: f000 f933 bl 80438a8 <_fflush_r> - 8043642: b988 cbnz r0, 8043668 <__swbuf_r+0x90> - 8043644: 4638 mov r0, r7 - 8043646: bdf8 pop {r3, r4, r5, r6, r7, pc} - 8043648: 4b0a ldr r3, [pc, #40] ; (8043674 <__swbuf_r+0x9c>) - 804364a: 429c cmp r4, r3 - 804364c: d101 bne.n 8043652 <__swbuf_r+0x7a> - 804364e: 68ac ldr r4, [r5, #8] - 8043650: e7cf b.n 80435f2 <__swbuf_r+0x1a> - 8043652: 4b09 ldr r3, [pc, #36] ; (8043678 <__swbuf_r+0xa0>) - 8043654: 429c cmp r4, r3 - 8043656: bf08 it eq - 8043658: 68ec ldreq r4, [r5, #12] - 804365a: e7ca b.n 80435f2 <__swbuf_r+0x1a> - 804365c: 4621 mov r1, r4 - 804365e: 4628 mov r0, r5 - 8043660: f000 f81e bl 80436a0 <__swsetup_r> - 8043664: 2800 cmp r0, #0 - 8043666: d0cb beq.n 8043600 <__swbuf_r+0x28> - 8043668: f04f 37ff mov.w r7, #4294967295 - 804366c: e7ea b.n 8043644 <__swbuf_r+0x6c> - 804366e: bf00 nop - 8043670: 08043ba0 .word 0x08043ba0 - 8043674: 08043bc0 .word 0x08043bc0 - 8043678: 08043b80 .word 0x08043b80 - -0804367c <_write_r>: - 804367c: b538 push {r3, r4, r5, lr} - 804367e: 4d07 ldr r5, [pc, #28] ; (804369c <_write_r+0x20>) - 8043680: 4604 mov r4, r0 - 8043682: 4608 mov r0, r1 - 8043684: 4611 mov r1, r2 - 8043686: 2200 movs r2, #0 - 8043688: 602a str r2, [r5, #0] - 804368a: 461a mov r2, r3 - 804368c: f7fd f97b bl 8040986 <_write> - 8043690: 1c43 adds r3, r0, #1 - 8043692: d102 bne.n 804369a <_write_r+0x1e> - 8043694: 682b ldr r3, [r5, #0] - 8043696: b103 cbz r3, 804369a <_write_r+0x1e> - 8043698: 6023 str r3, [r4, #0] - 804369a: bd38 pop {r3, r4, r5, pc} - 804369c: 2000012c .word 0x2000012c - -080436a0 <__swsetup_r>: - 80436a0: 4b32 ldr r3, [pc, #200] ; (804376c <__swsetup_r+0xcc>) - 80436a2: b570 push {r4, r5, r6, lr} - 80436a4: 681d ldr r5, [r3, #0] - 80436a6: 4606 mov r6, r0 - 80436a8: 460c mov r4, r1 - 80436aa: b125 cbz r5, 80436b6 <__swsetup_r+0x16> - 80436ac: 69ab ldr r3, [r5, #24] - 80436ae: b913 cbnz r3, 80436b6 <__swsetup_r+0x16> - 80436b0: 4628 mov r0, r5 - 80436b2: f7ff fb55 bl 8042d60 <__sinit> - 80436b6: 4b2e ldr r3, [pc, #184] ; (8043770 <__swsetup_r+0xd0>) - 80436b8: 429c cmp r4, r3 - 80436ba: d10f bne.n 80436dc <__swsetup_r+0x3c> - 80436bc: 686c ldr r4, [r5, #4] - 80436be: 89a3 ldrh r3, [r4, #12] - 80436c0: f9b4 200c ldrsh.w r2, [r4, #12] - 80436c4: 0719 lsls r1, r3, #28 - 80436c6: d42c bmi.n 8043722 <__swsetup_r+0x82> - 80436c8: 06dd lsls r5, r3, #27 - 80436ca: d411 bmi.n 80436f0 <__swsetup_r+0x50> - 80436cc: 2309 movs r3, #9 - 80436ce: 6033 str r3, [r6, #0] - 80436d0: f042 0340 orr.w r3, r2, #64 ; 0x40 - 80436d4: 81a3 strh r3, [r4, #12] - 80436d6: f04f 30ff mov.w r0, #4294967295 - 80436da: e03e b.n 804375a <__swsetup_r+0xba> - 80436dc: 4b25 ldr r3, [pc, #148] ; (8043774 <__swsetup_r+0xd4>) - 80436de: 429c cmp r4, r3 - 80436e0: d101 bne.n 80436e6 <__swsetup_r+0x46> - 80436e2: 68ac ldr r4, [r5, #8] - 80436e4: e7eb b.n 80436be <__swsetup_r+0x1e> - 80436e6: 4b24 ldr r3, [pc, #144] ; (8043778 <__swsetup_r+0xd8>) - 80436e8: 429c cmp r4, r3 - 80436ea: bf08 it eq - 80436ec: 68ec ldreq r4, [r5, #12] - 80436ee: e7e6 b.n 80436be <__swsetup_r+0x1e> - 80436f0: 0758 lsls r0, r3, #29 - 80436f2: d512 bpl.n 804371a <__swsetup_r+0x7a> - 80436f4: 6b61 ldr r1, [r4, #52] ; 0x34 - 80436f6: b141 cbz r1, 804370a <__swsetup_r+0x6a> - 80436f8: f104 0344 add.w r3, r4, #68 ; 0x44 - 80436fc: 4299 cmp r1, r3 - 80436fe: d002 beq.n 8043706 <__swsetup_r+0x66> - 8043700: 4630 mov r0, r6 - 8043702: f000 f98f bl 8043a24 <_free_r> - 8043706: 2300 movs r3, #0 - 8043708: 6363 str r3, [r4, #52] ; 0x34 - 804370a: 89a3 ldrh r3, [r4, #12] - 804370c: f023 0324 bic.w r3, r3, #36 ; 0x24 - 8043710: 81a3 strh r3, [r4, #12] - 8043712: 2300 movs r3, #0 - 8043714: 6063 str r3, [r4, #4] - 8043716: 6923 ldr r3, [r4, #16] - 8043718: 6023 str r3, [r4, #0] - 804371a: 89a3 ldrh r3, [r4, #12] - 804371c: f043 0308 orr.w r3, r3, #8 - 8043720: 81a3 strh r3, [r4, #12] - 8043722: 6923 ldr r3, [r4, #16] - 8043724: b94b cbnz r3, 804373a <__swsetup_r+0x9a> - 8043726: 89a3 ldrh r3, [r4, #12] - 8043728: f403 7320 and.w r3, r3, #640 ; 0x280 - 804372c: f5b3 7f00 cmp.w r3, #512 ; 0x200 - 8043730: d003 beq.n 804373a <__swsetup_r+0x9a> - 8043732: 4621 mov r1, r4 - 8043734: 4630 mov r0, r6 - 8043736: f000 f929 bl 804398c <__smakebuf_r> - 804373a: 89a0 ldrh r0, [r4, #12] - 804373c: f9b4 200c ldrsh.w r2, [r4, #12] - 8043740: f010 0301 ands.w r3, r0, #1 - 8043744: d00a beq.n 804375c <__swsetup_r+0xbc> - 8043746: 2300 movs r3, #0 - 8043748: 60a3 str r3, [r4, #8] - 804374a: 6963 ldr r3, [r4, #20] - 804374c: 425b negs r3, r3 - 804374e: 61a3 str r3, [r4, #24] - 8043750: 6923 ldr r3, [r4, #16] - 8043752: b943 cbnz r3, 8043766 <__swsetup_r+0xc6> - 8043754: f010 0080 ands.w r0, r0, #128 ; 0x80 - 8043758: d1ba bne.n 80436d0 <__swsetup_r+0x30> - 804375a: bd70 pop {r4, r5, r6, pc} - 804375c: 0781 lsls r1, r0, #30 - 804375e: bf58 it pl - 8043760: 6963 ldrpl r3, [r4, #20] - 8043762: 60a3 str r3, [r4, #8] - 8043764: e7f4 b.n 8043750 <__swsetup_r+0xb0> - 8043766: 2000 movs r0, #0 - 8043768: e7f7 b.n 804375a <__swsetup_r+0xba> - 804376a: bf00 nop - 804376c: 2000000c .word 0x2000000c - 8043770: 08043ba0 .word 0x08043ba0 - 8043774: 08043bc0 .word 0x08043bc0 - 8043778: 08043b80 .word 0x08043b80 - -0804377c <_close_r>: - 804377c: b538 push {r3, r4, r5, lr} - 804377e: 4d06 ldr r5, [pc, #24] ; (8043798 <_close_r+0x1c>) - 8043780: 2300 movs r3, #0 - 8043782: 4604 mov r4, r0 - 8043784: 4608 mov r0, r1 - 8043786: 602b str r3, [r5, #0] - 8043788: f7fd f919 bl 80409be <_close> - 804378c: 1c43 adds r3, r0, #1 - 804378e: d102 bne.n 8043796 <_close_r+0x1a> - 8043790: 682b ldr r3, [r5, #0] - 8043792: b103 cbz r3, 8043796 <_close_r+0x1a> - 8043794: 6023 str r3, [r4, #0] - 8043796: bd38 pop {r3, r4, r5, pc} - 8043798: 2000012c .word 0x2000012c - -0804379c <__sflush_r>: - 804379c: 898a ldrh r2, [r1, #12] - 804379e: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} - 80437a2: 4605 mov r5, r0 - 80437a4: 0710 lsls r0, r2, #28 - 80437a6: 460c mov r4, r1 - 80437a8: d458 bmi.n 804385c <__sflush_r+0xc0> - 80437aa: 684b ldr r3, [r1, #4] - 80437ac: 2b00 cmp r3, #0 - 80437ae: dc05 bgt.n 80437bc <__sflush_r+0x20> - 80437b0: 6c0b ldr r3, [r1, #64] ; 0x40 - 80437b2: 2b00 cmp r3, #0 - 80437b4: dc02 bgt.n 80437bc <__sflush_r+0x20> - 80437b6: 2000 movs r0, #0 - 80437b8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} - 80437bc: 6ae6 ldr r6, [r4, #44] ; 0x2c - 80437be: 2e00 cmp r6, #0 - 80437c0: d0f9 beq.n 80437b6 <__sflush_r+0x1a> - 80437c2: 2300 movs r3, #0 - 80437c4: f412 5280 ands.w r2, r2, #4096 ; 0x1000 - 80437c8: 682f ldr r7, [r5, #0] - 80437ca: 602b str r3, [r5, #0] - 80437cc: d032 beq.n 8043834 <__sflush_r+0x98> - 80437ce: 6d60 ldr r0, [r4, #84] ; 0x54 - 80437d0: 89a3 ldrh r3, [r4, #12] - 80437d2: 075a lsls r2, r3, #29 - 80437d4: d505 bpl.n 80437e2 <__sflush_r+0x46> - 80437d6: 6863 ldr r3, [r4, #4] - 80437d8: 1ac0 subs r0, r0, r3 - 80437da: 6b63 ldr r3, [r4, #52] ; 0x34 - 80437dc: b10b cbz r3, 80437e2 <__sflush_r+0x46> - 80437de: 6c23 ldr r3, [r4, #64] ; 0x40 - 80437e0: 1ac0 subs r0, r0, r3 - 80437e2: 2300 movs r3, #0 - 80437e4: 4602 mov r2, r0 - 80437e6: 6ae6 ldr r6, [r4, #44] ; 0x2c - 80437e8: 6a21 ldr r1, [r4, #32] - 80437ea: 4628 mov r0, r5 - 80437ec: 47b0 blx r6 - 80437ee: 1c43 adds r3, r0, #1 - 80437f0: 89a3 ldrh r3, [r4, #12] - 80437f2: d106 bne.n 8043802 <__sflush_r+0x66> - 80437f4: 6829 ldr r1, [r5, #0] - 80437f6: 291d cmp r1, #29 - 80437f8: d82c bhi.n 8043854 <__sflush_r+0xb8> - 80437fa: 4a2a ldr r2, [pc, #168] ; (80438a4 <__sflush_r+0x108>) - 80437fc: 40ca lsrs r2, r1 - 80437fe: 07d6 lsls r6, r2, #31 - 8043800: d528 bpl.n 8043854 <__sflush_r+0xb8> - 8043802: 2200 movs r2, #0 - 8043804: 6062 str r2, [r4, #4] - 8043806: 04d9 lsls r1, r3, #19 - 8043808: 6922 ldr r2, [r4, #16] - 804380a: 6022 str r2, [r4, #0] - 804380c: d504 bpl.n 8043818 <__sflush_r+0x7c> - 804380e: 1c42 adds r2, r0, #1 - 8043810: d101 bne.n 8043816 <__sflush_r+0x7a> - 8043812: 682b ldr r3, [r5, #0] - 8043814: b903 cbnz r3, 8043818 <__sflush_r+0x7c> - 8043816: 6560 str r0, [r4, #84] ; 0x54 - 8043818: 6b61 ldr r1, [r4, #52] ; 0x34 - 804381a: 602f str r7, [r5, #0] - 804381c: 2900 cmp r1, #0 - 804381e: d0ca beq.n 80437b6 <__sflush_r+0x1a> - 8043820: f104 0344 add.w r3, r4, #68 ; 0x44 - 8043824: 4299 cmp r1, r3 - 8043826: d002 beq.n 804382e <__sflush_r+0x92> - 8043828: 4628 mov r0, r5 - 804382a: f000 f8fb bl 8043a24 <_free_r> - 804382e: 2000 movs r0, #0 - 8043830: 6360 str r0, [r4, #52] ; 0x34 - 8043832: e7c1 b.n 80437b8 <__sflush_r+0x1c> - 8043834: 6a21 ldr r1, [r4, #32] - 8043836: 2301 movs r3, #1 - 8043838: 4628 mov r0, r5 - 804383a: 47b0 blx r6 - 804383c: 1c41 adds r1, r0, #1 - 804383e: d1c7 bne.n 80437d0 <__sflush_r+0x34> - 8043840: 682b ldr r3, [r5, #0] - 8043842: 2b00 cmp r3, #0 - 8043844: d0c4 beq.n 80437d0 <__sflush_r+0x34> - 8043846: 2b1d cmp r3, #29 - 8043848: d001 beq.n 804384e <__sflush_r+0xb2> - 804384a: 2b16 cmp r3, #22 - 804384c: d101 bne.n 8043852 <__sflush_r+0xb6> - 804384e: 602f str r7, [r5, #0] - 8043850: e7b1 b.n 80437b6 <__sflush_r+0x1a> - 8043852: 89a3 ldrh r3, [r4, #12] - 8043854: f043 0340 orr.w r3, r3, #64 ; 0x40 - 8043858: 81a3 strh r3, [r4, #12] - 804385a: e7ad b.n 80437b8 <__sflush_r+0x1c> - 804385c: 690f ldr r7, [r1, #16] - 804385e: 2f00 cmp r7, #0 - 8043860: d0a9 beq.n 80437b6 <__sflush_r+0x1a> - 8043862: 0793 lsls r3, r2, #30 - 8043864: 680e ldr r6, [r1, #0] - 8043866: bf08 it eq - 8043868: 694b ldreq r3, [r1, #20] - 804386a: 600f str r7, [r1, #0] - 804386c: bf18 it ne - 804386e: 2300 movne r3, #0 - 8043870: eba6 0807 sub.w r8, r6, r7 - 8043874: 608b str r3, [r1, #8] - 8043876: f1b8 0f00 cmp.w r8, #0 - 804387a: dd9c ble.n 80437b6 <__sflush_r+0x1a> - 804387c: 6a21 ldr r1, [r4, #32] - 804387e: 6aa6 ldr r6, [r4, #40] ; 0x28 - 8043880: 4643 mov r3, r8 - 8043882: 463a mov r2, r7 - 8043884: 4628 mov r0, r5 - 8043886: 47b0 blx r6 - 8043888: 2800 cmp r0, #0 - 804388a: dc06 bgt.n 804389a <__sflush_r+0xfe> - 804388c: 89a3 ldrh r3, [r4, #12] - 804388e: f043 0340 orr.w r3, r3, #64 ; 0x40 - 8043892: 81a3 strh r3, [r4, #12] - 8043894: f04f 30ff mov.w r0, #4294967295 - 8043898: e78e b.n 80437b8 <__sflush_r+0x1c> - 804389a: 4407 add r7, r0 - 804389c: eba8 0800 sub.w r8, r8, r0 - 80438a0: e7e9 b.n 8043876 <__sflush_r+0xda> - 80438a2: bf00 nop - 80438a4: 20400001 .word 0x20400001 - -080438a8 <_fflush_r>: - 80438a8: b538 push {r3, r4, r5, lr} - 80438aa: 690b ldr r3, [r1, #16] - 80438ac: 4605 mov r5, r0 - 80438ae: 460c mov r4, r1 - 80438b0: b913 cbnz r3, 80438b8 <_fflush_r+0x10> - 80438b2: 2500 movs r5, #0 - 80438b4: 4628 mov r0, r5 - 80438b6: bd38 pop {r3, r4, r5, pc} - 80438b8: b118 cbz r0, 80438c2 <_fflush_r+0x1a> - 80438ba: 6983 ldr r3, [r0, #24] - 80438bc: b90b cbnz r3, 80438c2 <_fflush_r+0x1a> - 80438be: f7ff fa4f bl 8042d60 <__sinit> - 80438c2: 4b14 ldr r3, [pc, #80] ; (8043914 <_fflush_r+0x6c>) - 80438c4: 429c cmp r4, r3 - 80438c6: d11b bne.n 8043900 <_fflush_r+0x58> - 80438c8: 686c ldr r4, [r5, #4] - 80438ca: f9b4 300c ldrsh.w r3, [r4, #12] - 80438ce: 2b00 cmp r3, #0 - 80438d0: d0ef beq.n 80438b2 <_fflush_r+0xa> - 80438d2: 6e62 ldr r2, [r4, #100] ; 0x64 - 80438d4: 07d0 lsls r0, r2, #31 - 80438d6: d404 bmi.n 80438e2 <_fflush_r+0x3a> - 80438d8: 0599 lsls r1, r3, #22 - 80438da: d402 bmi.n 80438e2 <_fflush_r+0x3a> - 80438dc: 6da0 ldr r0, [r4, #88] ; 0x58 - 80438de: f7ff fadd bl 8042e9c <__retarget_lock_acquire_recursive> - 80438e2: 4628 mov r0, r5 - 80438e4: 4621 mov r1, r4 - 80438e6: f7ff ff59 bl 804379c <__sflush_r> - 80438ea: 6e63 ldr r3, [r4, #100] ; 0x64 - 80438ec: 07da lsls r2, r3, #31 - 80438ee: 4605 mov r5, r0 - 80438f0: d4e0 bmi.n 80438b4 <_fflush_r+0xc> - 80438f2: 89a3 ldrh r3, [r4, #12] - 80438f4: 059b lsls r3, r3, #22 - 80438f6: d4dd bmi.n 80438b4 <_fflush_r+0xc> - 80438f8: 6da0 ldr r0, [r4, #88] ; 0x58 - 80438fa: f7ff fad0 bl 8042e9e <__retarget_lock_release_recursive> - 80438fe: e7d9 b.n 80438b4 <_fflush_r+0xc> - 8043900: 4b05 ldr r3, [pc, #20] ; (8043918 <_fflush_r+0x70>) - 8043902: 429c cmp r4, r3 - 8043904: d101 bne.n 804390a <_fflush_r+0x62> - 8043906: 68ac ldr r4, [r5, #8] - 8043908: e7df b.n 80438ca <_fflush_r+0x22> - 804390a: 4b04 ldr r3, [pc, #16] ; (804391c <_fflush_r+0x74>) - 804390c: 429c cmp r4, r3 - 804390e: bf08 it eq - 8043910: 68ec ldreq r4, [r5, #12] - 8043912: e7da b.n 80438ca <_fflush_r+0x22> - 8043914: 08043ba0 .word 0x08043ba0 - 8043918: 08043bc0 .word 0x08043bc0 - 804391c: 08043b80 .word 0x08043b80 - -08043920 <_lseek_r>: - 8043920: b538 push {r3, r4, r5, lr} - 8043922: 4d07 ldr r5, [pc, #28] ; (8043940 <_lseek_r+0x20>) - 8043924: 4604 mov r4, r0 - 8043926: 4608 mov r0, r1 - 8043928: 4611 mov r1, r2 - 804392a: 2200 movs r2, #0 - 804392c: 602a str r2, [r5, #0] - 804392e: 461a mov r2, r3 - 8043930: f7fd f86c bl 8040a0c <_lseek> - 8043934: 1c43 adds r3, r0, #1 - 8043936: d102 bne.n 804393e <_lseek_r+0x1e> - 8043938: 682b ldr r3, [r5, #0] - 804393a: b103 cbz r3, 804393e <_lseek_r+0x1e> - 804393c: 6023 str r3, [r4, #0] - 804393e: bd38 pop {r3, r4, r5, pc} - 8043940: 2000012c .word 0x2000012c - -08043944 <__swhatbuf_r>: - 8043944: b570 push {r4, r5, r6, lr} - 8043946: 460e mov r6, r1 - 8043948: f9b1 100e ldrsh.w r1, [r1, #14] - 804394c: 2900 cmp r1, #0 - 804394e: b096 sub sp, #88 ; 0x58 - 8043950: 4614 mov r4, r2 - 8043952: 461d mov r5, r3 - 8043954: da07 bge.n 8043966 <__swhatbuf_r+0x22> - 8043956: 2300 movs r3, #0 - 8043958: 602b str r3, [r5, #0] - 804395a: 89b3 ldrh r3, [r6, #12] - 804395c: 061a lsls r2, r3, #24 - 804395e: d410 bmi.n 8043982 <__swhatbuf_r+0x3e> - 8043960: f44f 6380 mov.w r3, #1024 ; 0x400 - 8043964: e00e b.n 8043984 <__swhatbuf_r+0x40> - 8043966: 466a mov r2, sp - 8043968: f000 f8be bl 8043ae8 <_fstat_r> - 804396c: 2800 cmp r0, #0 - 804396e: dbf2 blt.n 8043956 <__swhatbuf_r+0x12> - 8043970: 9a01 ldr r2, [sp, #4] - 8043972: f402 4270 and.w r2, r2, #61440 ; 0xf000 - 8043976: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000 - 804397a: 425a negs r2, r3 - 804397c: 415a adcs r2, r3 - 804397e: 602a str r2, [r5, #0] - 8043980: e7ee b.n 8043960 <__swhatbuf_r+0x1c> - 8043982: 2340 movs r3, #64 ; 0x40 - 8043984: 2000 movs r0, #0 - 8043986: 6023 str r3, [r4, #0] - 8043988: b016 add sp, #88 ; 0x58 - 804398a: bd70 pop {r4, r5, r6, pc} - -0804398c <__smakebuf_r>: - 804398c: 898b ldrh r3, [r1, #12] - 804398e: b573 push {r0, r1, r4, r5, r6, lr} - 8043990: 079d lsls r5, r3, #30 - 8043992: 4606 mov r6, r0 - 8043994: 460c mov r4, r1 - 8043996: d507 bpl.n 80439a8 <__smakebuf_r+0x1c> - 8043998: f104 0347 add.w r3, r4, #71 ; 0x47 - 804399c: 6023 str r3, [r4, #0] - 804399e: 6123 str r3, [r4, #16] - 80439a0: 2301 movs r3, #1 - 80439a2: 6163 str r3, [r4, #20] - 80439a4: b002 add sp, #8 - 80439a6: bd70 pop {r4, r5, r6, pc} - 80439a8: ab01 add r3, sp, #4 - 80439aa: 466a mov r2, sp - 80439ac: f7ff ffca bl 8043944 <__swhatbuf_r> - 80439b0: 9900 ldr r1, [sp, #0] - 80439b2: 4605 mov r5, r0 - 80439b4: 4630 mov r0, r6 - 80439b6: f7ff fa73 bl 8042ea0 <_malloc_r> - 80439ba: b948 cbnz r0, 80439d0 <__smakebuf_r+0x44> - 80439bc: f9b4 300c ldrsh.w r3, [r4, #12] - 80439c0: 059a lsls r2, r3, #22 - 80439c2: d4ef bmi.n 80439a4 <__smakebuf_r+0x18> - 80439c4: f023 0303 bic.w r3, r3, #3 - 80439c8: f043 0302 orr.w r3, r3, #2 - 80439cc: 81a3 strh r3, [r4, #12] - 80439ce: e7e3 b.n 8043998 <__smakebuf_r+0xc> - 80439d0: 4b0d ldr r3, [pc, #52] ; (8043a08 <__smakebuf_r+0x7c>) - 80439d2: 62b3 str r3, [r6, #40] ; 0x28 - 80439d4: 89a3 ldrh r3, [r4, #12] - 80439d6: 6020 str r0, [r4, #0] - 80439d8: f043 0380 orr.w r3, r3, #128 ; 0x80 - 80439dc: 81a3 strh r3, [r4, #12] - 80439de: 9b00 ldr r3, [sp, #0] - 80439e0: 6163 str r3, [r4, #20] - 80439e2: 9b01 ldr r3, [sp, #4] - 80439e4: 6120 str r0, [r4, #16] - 80439e6: b15b cbz r3, 8043a00 <__smakebuf_r+0x74> - 80439e8: f9b4 100e ldrsh.w r1, [r4, #14] - 80439ec: 4630 mov r0, r6 - 80439ee: f000 f88d bl 8043b0c <_isatty_r> - 80439f2: b128 cbz r0, 8043a00 <__smakebuf_r+0x74> - 80439f4: 89a3 ldrh r3, [r4, #12] - 80439f6: f023 0303 bic.w r3, r3, #3 - 80439fa: f043 0301 orr.w r3, r3, #1 - 80439fe: 81a3 strh r3, [r4, #12] - 8043a00: 89a0 ldrh r0, [r4, #12] - 8043a02: 4305 orrs r5, r0 - 8043a04: 81a5 strh r5, [r4, #12] - 8043a06: e7cd b.n 80439a4 <__smakebuf_r+0x18> - 8043a08: 08042cf9 .word 0x08042cf9 - -08043a0c <__malloc_lock>: - 8043a0c: 4801 ldr r0, [pc, #4] ; (8043a14 <__malloc_lock+0x8>) - 8043a0e: f7ff ba45 b.w 8042e9c <__retarget_lock_acquire_recursive> - 8043a12: bf00 nop - 8043a14: 20000124 .word 0x20000124 - -08043a18 <__malloc_unlock>: - 8043a18: 4801 ldr r0, [pc, #4] ; (8043a20 <__malloc_unlock+0x8>) - 8043a1a: f7ff ba40 b.w 8042e9e <__retarget_lock_release_recursive> - 8043a1e: bf00 nop - 8043a20: 20000124 .word 0x20000124 - -08043a24 <_free_r>: - 8043a24: b537 push {r0, r1, r2, r4, r5, lr} - 8043a26: 2900 cmp r1, #0 - 8043a28: d048 beq.n 8043abc <_free_r+0x98> - 8043a2a: f851 3c04 ldr.w r3, [r1, #-4] - 8043a2e: 9001 str r0, [sp, #4] - 8043a30: 2b00 cmp r3, #0 - 8043a32: f1a1 0404 sub.w r4, r1, #4 - 8043a36: bfb8 it lt - 8043a38: 18e4 addlt r4, r4, r3 - 8043a3a: f7ff ffe7 bl 8043a0c <__malloc_lock> - 8043a3e: 4a20 ldr r2, [pc, #128] ; (8043ac0 <_free_r+0x9c>) - 8043a40: 9801 ldr r0, [sp, #4] - 8043a42: 6813 ldr r3, [r2, #0] - 8043a44: 4615 mov r5, r2 - 8043a46: b933 cbnz r3, 8043a56 <_free_r+0x32> - 8043a48: 6063 str r3, [r4, #4] - 8043a4a: 6014 str r4, [r2, #0] - 8043a4c: b003 add sp, #12 - 8043a4e: e8bd 4030 ldmia.w sp!, {r4, r5, lr} - 8043a52: f7ff bfe1 b.w 8043a18 <__malloc_unlock> - 8043a56: 42a3 cmp r3, r4 - 8043a58: d90b bls.n 8043a72 <_free_r+0x4e> - 8043a5a: 6821 ldr r1, [r4, #0] - 8043a5c: 1862 adds r2, r4, r1 - 8043a5e: 4293 cmp r3, r2 - 8043a60: bf04 itt eq - 8043a62: 681a ldreq r2, [r3, #0] - 8043a64: 685b ldreq r3, [r3, #4] - 8043a66: 6063 str r3, [r4, #4] - 8043a68: bf04 itt eq - 8043a6a: 1852 addeq r2, r2, r1 - 8043a6c: 6022 streq r2, [r4, #0] - 8043a6e: 602c str r4, [r5, #0] - 8043a70: e7ec b.n 8043a4c <_free_r+0x28> - 8043a72: 461a mov r2, r3 - 8043a74: 685b ldr r3, [r3, #4] - 8043a76: b10b cbz r3, 8043a7c <_free_r+0x58> - 8043a78: 42a3 cmp r3, r4 - 8043a7a: d9fa bls.n 8043a72 <_free_r+0x4e> - 8043a7c: 6811 ldr r1, [r2, #0] - 8043a7e: 1855 adds r5, r2, r1 - 8043a80: 42a5 cmp r5, r4 - 8043a82: d10b bne.n 8043a9c <_free_r+0x78> - 8043a84: 6824 ldr r4, [r4, #0] - 8043a86: 4421 add r1, r4 - 8043a88: 1854 adds r4, r2, r1 - 8043a8a: 42a3 cmp r3, r4 - 8043a8c: 6011 str r1, [r2, #0] - 8043a8e: d1dd bne.n 8043a4c <_free_r+0x28> - 8043a90: 681c ldr r4, [r3, #0] - 8043a92: 685b ldr r3, [r3, #4] - 8043a94: 6053 str r3, [r2, #4] - 8043a96: 4421 add r1, r4 - 8043a98: 6011 str r1, [r2, #0] - 8043a9a: e7d7 b.n 8043a4c <_free_r+0x28> - 8043a9c: d902 bls.n 8043aa4 <_free_r+0x80> - 8043a9e: 230c movs r3, #12 - 8043aa0: 6003 str r3, [r0, #0] - 8043aa2: e7d3 b.n 8043a4c <_free_r+0x28> - 8043aa4: 6825 ldr r5, [r4, #0] - 8043aa6: 1961 adds r1, r4, r5 - 8043aa8: 428b cmp r3, r1 - 8043aaa: bf04 itt eq - 8043aac: 6819 ldreq r1, [r3, #0] - 8043aae: 685b ldreq r3, [r3, #4] - 8043ab0: 6063 str r3, [r4, #4] - 8043ab2: bf04 itt eq - 8043ab4: 1949 addeq r1, r1, r5 - 8043ab6: 6021 streq r1, [r4, #0] - 8043ab8: 6054 str r4, [r2, #4] - 8043aba: e7c7 b.n 8043a4c <_free_r+0x28> - 8043abc: b003 add sp, #12 - 8043abe: bd30 pop {r4, r5, pc} - 8043ac0: 20000090 .word 0x20000090 - -08043ac4 <_read_r>: - 8043ac4: b538 push {r3, r4, r5, lr} - 8043ac6: 4d07 ldr r5, [pc, #28] ; (8043ae4 <_read_r+0x20>) - 8043ac8: 4604 mov r4, r0 - 8043aca: 4608 mov r0, r1 - 8043acc: 4611 mov r1, r2 - 8043ace: 2200 movs r2, #0 - 8043ad0: 602a str r2, [r5, #0] - 8043ad2: 461a mov r2, r3 - 8043ad4: f7fc ff3a bl 804094c <_read> - 8043ad8: 1c43 adds r3, r0, #1 - 8043ada: d102 bne.n 8043ae2 <_read_r+0x1e> - 8043adc: 682b ldr r3, [r5, #0] - 8043ade: b103 cbz r3, 8043ae2 <_read_r+0x1e> - 8043ae0: 6023 str r3, [r4, #0] - 8043ae2: bd38 pop {r3, r4, r5, pc} - 8043ae4: 2000012c .word 0x2000012c - -08043ae8 <_fstat_r>: - 8043ae8: b538 push {r3, r4, r5, lr} - 8043aea: 4d07 ldr r5, [pc, #28] ; (8043b08 <_fstat_r+0x20>) - 8043aec: 2300 movs r3, #0 - 8043aee: 4604 mov r4, r0 - 8043af0: 4608 mov r0, r1 - 8043af2: 4611 mov r1, r2 - 8043af4: 602b str r3, [r5, #0] - 8043af6: f7fc ff6e bl 80409d6 <_fstat> - 8043afa: 1c43 adds r3, r0, #1 - 8043afc: d102 bne.n 8043b04 <_fstat_r+0x1c> - 8043afe: 682b ldr r3, [r5, #0] - 8043b00: b103 cbz r3, 8043b04 <_fstat_r+0x1c> - 8043b02: 6023 str r3, [r4, #0] - 8043b04: bd38 pop {r3, r4, r5, pc} - 8043b06: bf00 nop - 8043b08: 2000012c .word 0x2000012c - -08043b0c <_isatty_r>: - 8043b0c: b538 push {r3, r4, r5, lr} - 8043b0e: 4d06 ldr r5, [pc, #24] ; (8043b28 <_isatty_r+0x1c>) - 8043b10: 2300 movs r3, #0 - 8043b12: 4604 mov r4, r0 - 8043b14: 4608 mov r0, r1 - 8043b16: 602b str r3, [r5, #0] - 8043b18: f7fc ff6d bl 80409f6 <_isatty> - 8043b1c: 1c43 adds r3, r0, #1 - 8043b1e: d102 bne.n 8043b26 <_isatty_r+0x1a> - 8043b20: 682b ldr r3, [r5, #0] - 8043b22: b103 cbz r3, 8043b26 <_isatty_r+0x1a> - 8043b24: 6023 str r3, [r4, #0] - 8043b26: bd38 pop {r3, r4, r5, pc} - 8043b28: 2000012c .word 0x2000012c - -08043b2c <_init>: - 8043b2c: b5f8 push {r3, r4, r5, r6, r7, lr} - 8043b2e: bf00 nop - 8043b30: bcf8 pop {r3, r4, r5, r6, r7} - 8043b32: bc08 pop {r3} - 8043b34: 469e mov lr, r3 - 8043b36: 4770 bx lr - -08043b38 <_fini>: - 8043b38: b5f8 push {r3, r4, r5, r6, r7, lr} - 8043b3a: bf00 nop - 8043b3c: bcf8 pop {r3, r4, r5, r6, r7} - 8043b3e: bc08 pop {r3} - 8043b40: 469e mov lr, r3 - 8043b42: 4770 bx lr + 80435fe: 6820 ldr r0, [r4, #0] + 8043600: 1ac0 subs r0, r0, r3 + 8043602: 6963 ldr r3, [r4, #20] + 8043604: b2f6 uxtb r6, r6 + 8043606: 4283 cmp r3, r0 + 8043608: 4637 mov r7, r6 + 804360a: dc04 bgt.n 8043616 <__swbuf_r+0x42> + 804360c: 4621 mov r1, r4 + 804360e: 4628 mov r0, r5 + 8043610: f000 f948 bl 80438a4 <_fflush_r> + 8043614: bb30 cbnz r0, 8043664 <__swbuf_r+0x90> + 8043616: 68a3 ldr r3, [r4, #8] + 8043618: 3b01 subs r3, #1 + 804361a: 60a3 str r3, [r4, #8] + 804361c: 6823 ldr r3, [r4, #0] + 804361e: 1c5a adds r2, r3, #1 + 8043620: 6022 str r2, [r4, #0] + 8043622: 701e strb r6, [r3, #0] + 8043624: 6963 ldr r3, [r4, #20] + 8043626: 3001 adds r0, #1 + 8043628: 4283 cmp r3, r0 + 804362a: d004 beq.n 8043636 <__swbuf_r+0x62> + 804362c: 89a3 ldrh r3, [r4, #12] + 804362e: 07db lsls r3, r3, #31 + 8043630: d506 bpl.n 8043640 <__swbuf_r+0x6c> + 8043632: 2e0a cmp r6, #10 + 8043634: d104 bne.n 8043640 <__swbuf_r+0x6c> + 8043636: 4621 mov r1, r4 + 8043638: 4628 mov r0, r5 + 804363a: f000 f933 bl 80438a4 <_fflush_r> + 804363e: b988 cbnz r0, 8043664 <__swbuf_r+0x90> + 8043640: 4638 mov r0, r7 + 8043642: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8043644: 4b0a ldr r3, [pc, #40] ; (8043670 <__swbuf_r+0x9c>) + 8043646: 429c cmp r4, r3 + 8043648: d101 bne.n 804364e <__swbuf_r+0x7a> + 804364a: 68ac ldr r4, [r5, #8] + 804364c: e7cf b.n 80435ee <__swbuf_r+0x1a> + 804364e: 4b09 ldr r3, [pc, #36] ; (8043674 <__swbuf_r+0xa0>) + 8043650: 429c cmp r4, r3 + 8043652: bf08 it eq + 8043654: 68ec ldreq r4, [r5, #12] + 8043656: e7ca b.n 80435ee <__swbuf_r+0x1a> + 8043658: 4621 mov r1, r4 + 804365a: 4628 mov r0, r5 + 804365c: f000 f81e bl 804369c <__swsetup_r> + 8043660: 2800 cmp r0, #0 + 8043662: d0cb beq.n 80435fc <__swbuf_r+0x28> + 8043664: f04f 37ff mov.w r7, #4294967295 + 8043668: e7ea b.n 8043640 <__swbuf_r+0x6c> + 804366a: bf00 nop + 804366c: 08043b9c .word 0x08043b9c + 8043670: 08043bbc .word 0x08043bbc + 8043674: 08043b7c .word 0x08043b7c + +08043678 <_write_r>: + 8043678: b538 push {r3, r4, r5, lr} + 804367a: 4d07 ldr r5, [pc, #28] ; (8043698 <_write_r+0x20>) + 804367c: 4604 mov r4, r0 + 804367e: 4608 mov r0, r1 + 8043680: 4611 mov r1, r2 + 8043682: 2200 movs r2, #0 + 8043684: 602a str r2, [r5, #0] + 8043686: 461a mov r2, r3 + 8043688: f7fd f97b bl 8040982 <_write> + 804368c: 1c43 adds r3, r0, #1 + 804368e: d102 bne.n 8043696 <_write_r+0x1e> + 8043690: 682b ldr r3, [r5, #0] + 8043692: b103 cbz r3, 8043696 <_write_r+0x1e> + 8043694: 6023 str r3, [r4, #0] + 8043696: bd38 pop {r3, r4, r5, pc} + 8043698: 2000012c .word 0x2000012c + +0804369c <__swsetup_r>: + 804369c: 4b32 ldr r3, [pc, #200] ; (8043768 <__swsetup_r+0xcc>) + 804369e: b570 push {r4, r5, r6, lr} + 80436a0: 681d ldr r5, [r3, #0] + 80436a2: 4606 mov r6, r0 + 80436a4: 460c mov r4, r1 + 80436a6: b125 cbz r5, 80436b2 <__swsetup_r+0x16> + 80436a8: 69ab ldr r3, [r5, #24] + 80436aa: b913 cbnz r3, 80436b2 <__swsetup_r+0x16> + 80436ac: 4628 mov r0, r5 + 80436ae: f7ff fb55 bl 8042d5c <__sinit> + 80436b2: 4b2e ldr r3, [pc, #184] ; (804376c <__swsetup_r+0xd0>) + 80436b4: 429c cmp r4, r3 + 80436b6: d10f bne.n 80436d8 <__swsetup_r+0x3c> + 80436b8: 686c ldr r4, [r5, #4] + 80436ba: 89a3 ldrh r3, [r4, #12] + 80436bc: f9b4 200c ldrsh.w r2, [r4, #12] + 80436c0: 0719 lsls r1, r3, #28 + 80436c2: d42c bmi.n 804371e <__swsetup_r+0x82> + 80436c4: 06dd lsls r5, r3, #27 + 80436c6: d411 bmi.n 80436ec <__swsetup_r+0x50> + 80436c8: 2309 movs r3, #9 + 80436ca: 6033 str r3, [r6, #0] + 80436cc: f042 0340 orr.w r3, r2, #64 ; 0x40 + 80436d0: 81a3 strh r3, [r4, #12] + 80436d2: f04f 30ff mov.w r0, #4294967295 + 80436d6: e03e b.n 8043756 <__swsetup_r+0xba> + 80436d8: 4b25 ldr r3, [pc, #148] ; (8043770 <__swsetup_r+0xd4>) + 80436da: 429c cmp r4, r3 + 80436dc: d101 bne.n 80436e2 <__swsetup_r+0x46> + 80436de: 68ac ldr r4, [r5, #8] + 80436e0: e7eb b.n 80436ba <__swsetup_r+0x1e> + 80436e2: 4b24 ldr r3, [pc, #144] ; (8043774 <__swsetup_r+0xd8>) + 80436e4: 429c cmp r4, r3 + 80436e6: bf08 it eq + 80436e8: 68ec ldreq r4, [r5, #12] + 80436ea: e7e6 b.n 80436ba <__swsetup_r+0x1e> + 80436ec: 0758 lsls r0, r3, #29 + 80436ee: d512 bpl.n 8043716 <__swsetup_r+0x7a> + 80436f0: 6b61 ldr r1, [r4, #52] ; 0x34 + 80436f2: b141 cbz r1, 8043706 <__swsetup_r+0x6a> + 80436f4: f104 0344 add.w r3, r4, #68 ; 0x44 + 80436f8: 4299 cmp r1, r3 + 80436fa: d002 beq.n 8043702 <__swsetup_r+0x66> + 80436fc: 4630 mov r0, r6 + 80436fe: f000 f98f bl 8043a20 <_free_r> + 8043702: 2300 movs r3, #0 + 8043704: 6363 str r3, [r4, #52] ; 0x34 + 8043706: 89a3 ldrh r3, [r4, #12] + 8043708: f023 0324 bic.w r3, r3, #36 ; 0x24 + 804370c: 81a3 strh r3, [r4, #12] + 804370e: 2300 movs r3, #0 + 8043710: 6063 str r3, [r4, #4] + 8043712: 6923 ldr r3, [r4, #16] + 8043714: 6023 str r3, [r4, #0] + 8043716: 89a3 ldrh r3, [r4, #12] + 8043718: f043 0308 orr.w r3, r3, #8 + 804371c: 81a3 strh r3, [r4, #12] + 804371e: 6923 ldr r3, [r4, #16] + 8043720: b94b cbnz r3, 8043736 <__swsetup_r+0x9a> + 8043722: 89a3 ldrh r3, [r4, #12] + 8043724: f403 7320 and.w r3, r3, #640 ; 0x280 + 8043728: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 804372c: d003 beq.n 8043736 <__swsetup_r+0x9a> + 804372e: 4621 mov r1, r4 + 8043730: 4630 mov r0, r6 + 8043732: f000 f929 bl 8043988 <__smakebuf_r> + 8043736: 89a0 ldrh r0, [r4, #12] + 8043738: f9b4 200c ldrsh.w r2, [r4, #12] + 804373c: f010 0301 ands.w r3, r0, #1 + 8043740: d00a beq.n 8043758 <__swsetup_r+0xbc> + 8043742: 2300 movs r3, #0 + 8043744: 60a3 str r3, [r4, #8] + 8043746: 6963 ldr r3, [r4, #20] + 8043748: 425b negs r3, r3 + 804374a: 61a3 str r3, [r4, #24] + 804374c: 6923 ldr r3, [r4, #16] + 804374e: b943 cbnz r3, 8043762 <__swsetup_r+0xc6> + 8043750: f010 0080 ands.w r0, r0, #128 ; 0x80 + 8043754: d1ba bne.n 80436cc <__swsetup_r+0x30> + 8043756: bd70 pop {r4, r5, r6, pc} + 8043758: 0781 lsls r1, r0, #30 + 804375a: bf58 it pl + 804375c: 6963 ldrpl r3, [r4, #20] + 804375e: 60a3 str r3, [r4, #8] + 8043760: e7f4 b.n 804374c <__swsetup_r+0xb0> + 8043762: 2000 movs r0, #0 + 8043764: e7f7 b.n 8043756 <__swsetup_r+0xba> + 8043766: bf00 nop + 8043768: 2000000c .word 0x2000000c + 804376c: 08043b9c .word 0x08043b9c + 8043770: 08043bbc .word 0x08043bbc + 8043774: 08043b7c .word 0x08043b7c + +08043778 <_close_r>: + 8043778: b538 push {r3, r4, r5, lr} + 804377a: 4d06 ldr r5, [pc, #24] ; (8043794 <_close_r+0x1c>) + 804377c: 2300 movs r3, #0 + 804377e: 4604 mov r4, r0 + 8043780: 4608 mov r0, r1 + 8043782: 602b str r3, [r5, #0] + 8043784: f7fd f919 bl 80409ba <_close> + 8043788: 1c43 adds r3, r0, #1 + 804378a: d102 bne.n 8043792 <_close_r+0x1a> + 804378c: 682b ldr r3, [r5, #0] + 804378e: b103 cbz r3, 8043792 <_close_r+0x1a> + 8043790: 6023 str r3, [r4, #0] + 8043792: bd38 pop {r3, r4, r5, pc} + 8043794: 2000012c .word 0x2000012c + +08043798 <__sflush_r>: + 8043798: 898a ldrh r2, [r1, #12] + 804379a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 804379e: 4605 mov r5, r0 + 80437a0: 0710 lsls r0, r2, #28 + 80437a2: 460c mov r4, r1 + 80437a4: d458 bmi.n 8043858 <__sflush_r+0xc0> + 80437a6: 684b ldr r3, [r1, #4] + 80437a8: 2b00 cmp r3, #0 + 80437aa: dc05 bgt.n 80437b8 <__sflush_r+0x20> + 80437ac: 6c0b ldr r3, [r1, #64] ; 0x40 + 80437ae: 2b00 cmp r3, #0 + 80437b0: dc02 bgt.n 80437b8 <__sflush_r+0x20> + 80437b2: 2000 movs r0, #0 + 80437b4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 80437b8: 6ae6 ldr r6, [r4, #44] ; 0x2c + 80437ba: 2e00 cmp r6, #0 + 80437bc: d0f9 beq.n 80437b2 <__sflush_r+0x1a> + 80437be: 2300 movs r3, #0 + 80437c0: f412 5280 ands.w r2, r2, #4096 ; 0x1000 + 80437c4: 682f ldr r7, [r5, #0] + 80437c6: 602b str r3, [r5, #0] + 80437c8: d032 beq.n 8043830 <__sflush_r+0x98> + 80437ca: 6d60 ldr r0, [r4, #84] ; 0x54 + 80437cc: 89a3 ldrh r3, [r4, #12] + 80437ce: 075a lsls r2, r3, #29 + 80437d0: d505 bpl.n 80437de <__sflush_r+0x46> + 80437d2: 6863 ldr r3, [r4, #4] + 80437d4: 1ac0 subs r0, r0, r3 + 80437d6: 6b63 ldr r3, [r4, #52] ; 0x34 + 80437d8: b10b cbz r3, 80437de <__sflush_r+0x46> + 80437da: 6c23 ldr r3, [r4, #64] ; 0x40 + 80437dc: 1ac0 subs r0, r0, r3 + 80437de: 2300 movs r3, #0 + 80437e0: 4602 mov r2, r0 + 80437e2: 6ae6 ldr r6, [r4, #44] ; 0x2c + 80437e4: 6a21 ldr r1, [r4, #32] + 80437e6: 4628 mov r0, r5 + 80437e8: 47b0 blx r6 + 80437ea: 1c43 adds r3, r0, #1 + 80437ec: 89a3 ldrh r3, [r4, #12] + 80437ee: d106 bne.n 80437fe <__sflush_r+0x66> + 80437f0: 6829 ldr r1, [r5, #0] + 80437f2: 291d cmp r1, #29 + 80437f4: d82c bhi.n 8043850 <__sflush_r+0xb8> + 80437f6: 4a2a ldr r2, [pc, #168] ; (80438a0 <__sflush_r+0x108>) + 80437f8: 40ca lsrs r2, r1 + 80437fa: 07d6 lsls r6, r2, #31 + 80437fc: d528 bpl.n 8043850 <__sflush_r+0xb8> + 80437fe: 2200 movs r2, #0 + 8043800: 6062 str r2, [r4, #4] + 8043802: 04d9 lsls r1, r3, #19 + 8043804: 6922 ldr r2, [r4, #16] + 8043806: 6022 str r2, [r4, #0] + 8043808: d504 bpl.n 8043814 <__sflush_r+0x7c> + 804380a: 1c42 adds r2, r0, #1 + 804380c: d101 bne.n 8043812 <__sflush_r+0x7a> + 804380e: 682b ldr r3, [r5, #0] + 8043810: b903 cbnz r3, 8043814 <__sflush_r+0x7c> + 8043812: 6560 str r0, [r4, #84] ; 0x54 + 8043814: 6b61 ldr r1, [r4, #52] ; 0x34 + 8043816: 602f str r7, [r5, #0] + 8043818: 2900 cmp r1, #0 + 804381a: d0ca beq.n 80437b2 <__sflush_r+0x1a> + 804381c: f104 0344 add.w r3, r4, #68 ; 0x44 + 8043820: 4299 cmp r1, r3 + 8043822: d002 beq.n 804382a <__sflush_r+0x92> + 8043824: 4628 mov r0, r5 + 8043826: f000 f8fb bl 8043a20 <_free_r> + 804382a: 2000 movs r0, #0 + 804382c: 6360 str r0, [r4, #52] ; 0x34 + 804382e: e7c1 b.n 80437b4 <__sflush_r+0x1c> + 8043830: 6a21 ldr r1, [r4, #32] + 8043832: 2301 movs r3, #1 + 8043834: 4628 mov r0, r5 + 8043836: 47b0 blx r6 + 8043838: 1c41 adds r1, r0, #1 + 804383a: d1c7 bne.n 80437cc <__sflush_r+0x34> + 804383c: 682b ldr r3, [r5, #0] + 804383e: 2b00 cmp r3, #0 + 8043840: d0c4 beq.n 80437cc <__sflush_r+0x34> + 8043842: 2b1d cmp r3, #29 + 8043844: d001 beq.n 804384a <__sflush_r+0xb2> + 8043846: 2b16 cmp r3, #22 + 8043848: d101 bne.n 804384e <__sflush_r+0xb6> + 804384a: 602f str r7, [r5, #0] + 804384c: e7b1 b.n 80437b2 <__sflush_r+0x1a> + 804384e: 89a3 ldrh r3, [r4, #12] + 8043850: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8043854: 81a3 strh r3, [r4, #12] + 8043856: e7ad b.n 80437b4 <__sflush_r+0x1c> + 8043858: 690f ldr r7, [r1, #16] + 804385a: 2f00 cmp r7, #0 + 804385c: d0a9 beq.n 80437b2 <__sflush_r+0x1a> + 804385e: 0793 lsls r3, r2, #30 + 8043860: 680e ldr r6, [r1, #0] + 8043862: bf08 it eq + 8043864: 694b ldreq r3, [r1, #20] + 8043866: 600f str r7, [r1, #0] + 8043868: bf18 it ne + 804386a: 2300 movne r3, #0 + 804386c: eba6 0807 sub.w r8, r6, r7 + 8043870: 608b str r3, [r1, #8] + 8043872: f1b8 0f00 cmp.w r8, #0 + 8043876: dd9c ble.n 80437b2 <__sflush_r+0x1a> + 8043878: 6a21 ldr r1, [r4, #32] + 804387a: 6aa6 ldr r6, [r4, #40] ; 0x28 + 804387c: 4643 mov r3, r8 + 804387e: 463a mov r2, r7 + 8043880: 4628 mov r0, r5 + 8043882: 47b0 blx r6 + 8043884: 2800 cmp r0, #0 + 8043886: dc06 bgt.n 8043896 <__sflush_r+0xfe> + 8043888: 89a3 ldrh r3, [r4, #12] + 804388a: f043 0340 orr.w r3, r3, #64 ; 0x40 + 804388e: 81a3 strh r3, [r4, #12] + 8043890: f04f 30ff mov.w r0, #4294967295 + 8043894: e78e b.n 80437b4 <__sflush_r+0x1c> + 8043896: 4407 add r7, r0 + 8043898: eba8 0800 sub.w r8, r8, r0 + 804389c: e7e9 b.n 8043872 <__sflush_r+0xda> + 804389e: bf00 nop + 80438a0: 20400001 .word 0x20400001 + +080438a4 <_fflush_r>: + 80438a4: b538 push {r3, r4, r5, lr} + 80438a6: 690b ldr r3, [r1, #16] + 80438a8: 4605 mov r5, r0 + 80438aa: 460c mov r4, r1 + 80438ac: b913 cbnz r3, 80438b4 <_fflush_r+0x10> + 80438ae: 2500 movs r5, #0 + 80438b0: 4628 mov r0, r5 + 80438b2: bd38 pop {r3, r4, r5, pc} + 80438b4: b118 cbz r0, 80438be <_fflush_r+0x1a> + 80438b6: 6983 ldr r3, [r0, #24] + 80438b8: b90b cbnz r3, 80438be <_fflush_r+0x1a> + 80438ba: f7ff fa4f bl 8042d5c <__sinit> + 80438be: 4b14 ldr r3, [pc, #80] ; (8043910 <_fflush_r+0x6c>) + 80438c0: 429c cmp r4, r3 + 80438c2: d11b bne.n 80438fc <_fflush_r+0x58> + 80438c4: 686c ldr r4, [r5, #4] + 80438c6: f9b4 300c ldrsh.w r3, [r4, #12] + 80438ca: 2b00 cmp r3, #0 + 80438cc: d0ef beq.n 80438ae <_fflush_r+0xa> + 80438ce: 6e62 ldr r2, [r4, #100] ; 0x64 + 80438d0: 07d0 lsls r0, r2, #31 + 80438d2: d404 bmi.n 80438de <_fflush_r+0x3a> + 80438d4: 0599 lsls r1, r3, #22 + 80438d6: d402 bmi.n 80438de <_fflush_r+0x3a> + 80438d8: 6da0 ldr r0, [r4, #88] ; 0x58 + 80438da: f7ff fadd bl 8042e98 <__retarget_lock_acquire_recursive> + 80438de: 4628 mov r0, r5 + 80438e0: 4621 mov r1, r4 + 80438e2: f7ff ff59 bl 8043798 <__sflush_r> + 80438e6: 6e63 ldr r3, [r4, #100] ; 0x64 + 80438e8: 07da lsls r2, r3, #31 + 80438ea: 4605 mov r5, r0 + 80438ec: d4e0 bmi.n 80438b0 <_fflush_r+0xc> + 80438ee: 89a3 ldrh r3, [r4, #12] + 80438f0: 059b lsls r3, r3, #22 + 80438f2: d4dd bmi.n 80438b0 <_fflush_r+0xc> + 80438f4: 6da0 ldr r0, [r4, #88] ; 0x58 + 80438f6: f7ff fad0 bl 8042e9a <__retarget_lock_release_recursive> + 80438fa: e7d9 b.n 80438b0 <_fflush_r+0xc> + 80438fc: 4b05 ldr r3, [pc, #20] ; (8043914 <_fflush_r+0x70>) + 80438fe: 429c cmp r4, r3 + 8043900: d101 bne.n 8043906 <_fflush_r+0x62> + 8043902: 68ac ldr r4, [r5, #8] + 8043904: e7df b.n 80438c6 <_fflush_r+0x22> + 8043906: 4b04 ldr r3, [pc, #16] ; (8043918 <_fflush_r+0x74>) + 8043908: 429c cmp r4, r3 + 804390a: bf08 it eq + 804390c: 68ec ldreq r4, [r5, #12] + 804390e: e7da b.n 80438c6 <_fflush_r+0x22> + 8043910: 08043b9c .word 0x08043b9c + 8043914: 08043bbc .word 0x08043bbc + 8043918: 08043b7c .word 0x08043b7c + +0804391c <_lseek_r>: + 804391c: b538 push {r3, r4, r5, lr} + 804391e: 4d07 ldr r5, [pc, #28] ; (804393c <_lseek_r+0x20>) + 8043920: 4604 mov r4, r0 + 8043922: 4608 mov r0, r1 + 8043924: 4611 mov r1, r2 + 8043926: 2200 movs r2, #0 + 8043928: 602a str r2, [r5, #0] + 804392a: 461a mov r2, r3 + 804392c: f7fd f86c bl 8040a08 <_lseek> + 8043930: 1c43 adds r3, r0, #1 + 8043932: d102 bne.n 804393a <_lseek_r+0x1e> + 8043934: 682b ldr r3, [r5, #0] + 8043936: b103 cbz r3, 804393a <_lseek_r+0x1e> + 8043938: 6023 str r3, [r4, #0] + 804393a: bd38 pop {r3, r4, r5, pc} + 804393c: 2000012c .word 0x2000012c + +08043940 <__swhatbuf_r>: + 8043940: b570 push {r4, r5, r6, lr} + 8043942: 460e mov r6, r1 + 8043944: f9b1 100e ldrsh.w r1, [r1, #14] + 8043948: 2900 cmp r1, #0 + 804394a: b096 sub sp, #88 ; 0x58 + 804394c: 4614 mov r4, r2 + 804394e: 461d mov r5, r3 + 8043950: da07 bge.n 8043962 <__swhatbuf_r+0x22> + 8043952: 2300 movs r3, #0 + 8043954: 602b str r3, [r5, #0] + 8043956: 89b3 ldrh r3, [r6, #12] + 8043958: 061a lsls r2, r3, #24 + 804395a: d410 bmi.n 804397e <__swhatbuf_r+0x3e> + 804395c: f44f 6380 mov.w r3, #1024 ; 0x400 + 8043960: e00e b.n 8043980 <__swhatbuf_r+0x40> + 8043962: 466a mov r2, sp + 8043964: f000 f8be bl 8043ae4 <_fstat_r> + 8043968: 2800 cmp r0, #0 + 804396a: dbf2 blt.n 8043952 <__swhatbuf_r+0x12> + 804396c: 9a01 ldr r2, [sp, #4] + 804396e: f402 4270 and.w r2, r2, #61440 ; 0xf000 + 8043972: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000 + 8043976: 425a negs r2, r3 + 8043978: 415a adcs r2, r3 + 804397a: 602a str r2, [r5, #0] + 804397c: e7ee b.n 804395c <__swhatbuf_r+0x1c> + 804397e: 2340 movs r3, #64 ; 0x40 + 8043980: 2000 movs r0, #0 + 8043982: 6023 str r3, [r4, #0] + 8043984: b016 add sp, #88 ; 0x58 + 8043986: bd70 pop {r4, r5, r6, pc} + +08043988 <__smakebuf_r>: + 8043988: 898b ldrh r3, [r1, #12] + 804398a: b573 push {r0, r1, r4, r5, r6, lr} + 804398c: 079d lsls r5, r3, #30 + 804398e: 4606 mov r6, r0 + 8043990: 460c mov r4, r1 + 8043992: d507 bpl.n 80439a4 <__smakebuf_r+0x1c> + 8043994: f104 0347 add.w r3, r4, #71 ; 0x47 + 8043998: 6023 str r3, [r4, #0] + 804399a: 6123 str r3, [r4, #16] + 804399c: 2301 movs r3, #1 + 804399e: 6163 str r3, [r4, #20] + 80439a0: b002 add sp, #8 + 80439a2: bd70 pop {r4, r5, r6, pc} + 80439a4: ab01 add r3, sp, #4 + 80439a6: 466a mov r2, sp + 80439a8: f7ff ffca bl 8043940 <__swhatbuf_r> + 80439ac: 9900 ldr r1, [sp, #0] + 80439ae: 4605 mov r5, r0 + 80439b0: 4630 mov r0, r6 + 80439b2: f7ff fa73 bl 8042e9c <_malloc_r> + 80439b6: b948 cbnz r0, 80439cc <__smakebuf_r+0x44> + 80439b8: f9b4 300c ldrsh.w r3, [r4, #12] + 80439bc: 059a lsls r2, r3, #22 + 80439be: d4ef bmi.n 80439a0 <__smakebuf_r+0x18> + 80439c0: f023 0303 bic.w r3, r3, #3 + 80439c4: f043 0302 orr.w r3, r3, #2 + 80439c8: 81a3 strh r3, [r4, #12] + 80439ca: e7e3 b.n 8043994 <__smakebuf_r+0xc> + 80439cc: 4b0d ldr r3, [pc, #52] ; (8043a04 <__smakebuf_r+0x7c>) + 80439ce: 62b3 str r3, [r6, #40] ; 0x28 + 80439d0: 89a3 ldrh r3, [r4, #12] + 80439d2: 6020 str r0, [r4, #0] + 80439d4: f043 0380 orr.w r3, r3, #128 ; 0x80 + 80439d8: 81a3 strh r3, [r4, #12] + 80439da: 9b00 ldr r3, [sp, #0] + 80439dc: 6163 str r3, [r4, #20] + 80439de: 9b01 ldr r3, [sp, #4] + 80439e0: 6120 str r0, [r4, #16] + 80439e2: b15b cbz r3, 80439fc <__smakebuf_r+0x74> + 80439e4: f9b4 100e ldrsh.w r1, [r4, #14] + 80439e8: 4630 mov r0, r6 + 80439ea: f000 f88d bl 8043b08 <_isatty_r> + 80439ee: b128 cbz r0, 80439fc <__smakebuf_r+0x74> + 80439f0: 89a3 ldrh r3, [r4, #12] + 80439f2: f023 0303 bic.w r3, r3, #3 + 80439f6: f043 0301 orr.w r3, r3, #1 + 80439fa: 81a3 strh r3, [r4, #12] + 80439fc: 89a0 ldrh r0, [r4, #12] + 80439fe: 4305 orrs r5, r0 + 8043a00: 81a5 strh r5, [r4, #12] + 8043a02: e7cd b.n 80439a0 <__smakebuf_r+0x18> + 8043a04: 08042cf5 .word 0x08042cf5 + +08043a08 <__malloc_lock>: + 8043a08: 4801 ldr r0, [pc, #4] ; (8043a10 <__malloc_lock+0x8>) + 8043a0a: f7ff ba45 b.w 8042e98 <__retarget_lock_acquire_recursive> + 8043a0e: bf00 nop + 8043a10: 20000124 .word 0x20000124 + +08043a14 <__malloc_unlock>: + 8043a14: 4801 ldr r0, [pc, #4] ; (8043a1c <__malloc_unlock+0x8>) + 8043a16: f7ff ba40 b.w 8042e9a <__retarget_lock_release_recursive> + 8043a1a: bf00 nop + 8043a1c: 20000124 .word 0x20000124 + +08043a20 <_free_r>: + 8043a20: b537 push {r0, r1, r2, r4, r5, lr} + 8043a22: 2900 cmp r1, #0 + 8043a24: d048 beq.n 8043ab8 <_free_r+0x98> + 8043a26: f851 3c04 ldr.w r3, [r1, #-4] + 8043a2a: 9001 str r0, [sp, #4] + 8043a2c: 2b00 cmp r3, #0 + 8043a2e: f1a1 0404 sub.w r4, r1, #4 + 8043a32: bfb8 it lt + 8043a34: 18e4 addlt r4, r4, r3 + 8043a36: f7ff ffe7 bl 8043a08 <__malloc_lock> + 8043a3a: 4a20 ldr r2, [pc, #128] ; (8043abc <_free_r+0x9c>) + 8043a3c: 9801 ldr r0, [sp, #4] + 8043a3e: 6813 ldr r3, [r2, #0] + 8043a40: 4615 mov r5, r2 + 8043a42: b933 cbnz r3, 8043a52 <_free_r+0x32> + 8043a44: 6063 str r3, [r4, #4] + 8043a46: 6014 str r4, [r2, #0] + 8043a48: b003 add sp, #12 + 8043a4a: e8bd 4030 ldmia.w sp!, {r4, r5, lr} + 8043a4e: f7ff bfe1 b.w 8043a14 <__malloc_unlock> + 8043a52: 42a3 cmp r3, r4 + 8043a54: d90b bls.n 8043a6e <_free_r+0x4e> + 8043a56: 6821 ldr r1, [r4, #0] + 8043a58: 1862 adds r2, r4, r1 + 8043a5a: 4293 cmp r3, r2 + 8043a5c: bf04 itt eq + 8043a5e: 681a ldreq r2, [r3, #0] + 8043a60: 685b ldreq r3, [r3, #4] + 8043a62: 6063 str r3, [r4, #4] + 8043a64: bf04 itt eq + 8043a66: 1852 addeq r2, r2, r1 + 8043a68: 6022 streq r2, [r4, #0] + 8043a6a: 602c str r4, [r5, #0] + 8043a6c: e7ec b.n 8043a48 <_free_r+0x28> + 8043a6e: 461a mov r2, r3 + 8043a70: 685b ldr r3, [r3, #4] + 8043a72: b10b cbz r3, 8043a78 <_free_r+0x58> + 8043a74: 42a3 cmp r3, r4 + 8043a76: d9fa bls.n 8043a6e <_free_r+0x4e> + 8043a78: 6811 ldr r1, [r2, #0] + 8043a7a: 1855 adds r5, r2, r1 + 8043a7c: 42a5 cmp r5, r4 + 8043a7e: d10b bne.n 8043a98 <_free_r+0x78> + 8043a80: 6824 ldr r4, [r4, #0] + 8043a82: 4421 add r1, r4 + 8043a84: 1854 adds r4, r2, r1 + 8043a86: 42a3 cmp r3, r4 + 8043a88: 6011 str r1, [r2, #0] + 8043a8a: d1dd bne.n 8043a48 <_free_r+0x28> + 8043a8c: 681c ldr r4, [r3, #0] + 8043a8e: 685b ldr r3, [r3, #4] + 8043a90: 6053 str r3, [r2, #4] + 8043a92: 4421 add r1, r4 + 8043a94: 6011 str r1, [r2, #0] + 8043a96: e7d7 b.n 8043a48 <_free_r+0x28> + 8043a98: d902 bls.n 8043aa0 <_free_r+0x80> + 8043a9a: 230c movs r3, #12 + 8043a9c: 6003 str r3, [r0, #0] + 8043a9e: e7d3 b.n 8043a48 <_free_r+0x28> + 8043aa0: 6825 ldr r5, [r4, #0] + 8043aa2: 1961 adds r1, r4, r5 + 8043aa4: 428b cmp r3, r1 + 8043aa6: bf04 itt eq + 8043aa8: 6819 ldreq r1, [r3, #0] + 8043aaa: 685b ldreq r3, [r3, #4] + 8043aac: 6063 str r3, [r4, #4] + 8043aae: bf04 itt eq + 8043ab0: 1949 addeq r1, r1, r5 + 8043ab2: 6021 streq r1, [r4, #0] + 8043ab4: 6054 str r4, [r2, #4] + 8043ab6: e7c7 b.n 8043a48 <_free_r+0x28> + 8043ab8: b003 add sp, #12 + 8043aba: bd30 pop {r4, r5, pc} + 8043abc: 20000090 .word 0x20000090 + +08043ac0 <_read_r>: + 8043ac0: b538 push {r3, r4, r5, lr} + 8043ac2: 4d07 ldr r5, [pc, #28] ; (8043ae0 <_read_r+0x20>) + 8043ac4: 4604 mov r4, r0 + 8043ac6: 4608 mov r0, r1 + 8043ac8: 4611 mov r1, r2 + 8043aca: 2200 movs r2, #0 + 8043acc: 602a str r2, [r5, #0] + 8043ace: 461a mov r2, r3 + 8043ad0: f7fc ff3a bl 8040948 <_read> + 8043ad4: 1c43 adds r3, r0, #1 + 8043ad6: d102 bne.n 8043ade <_read_r+0x1e> + 8043ad8: 682b ldr r3, [r5, #0] + 8043ada: b103 cbz r3, 8043ade <_read_r+0x1e> + 8043adc: 6023 str r3, [r4, #0] + 8043ade: bd38 pop {r3, r4, r5, pc} + 8043ae0: 2000012c .word 0x2000012c + +08043ae4 <_fstat_r>: + 8043ae4: b538 push {r3, r4, r5, lr} + 8043ae6: 4d07 ldr r5, [pc, #28] ; (8043b04 <_fstat_r+0x20>) + 8043ae8: 2300 movs r3, #0 + 8043aea: 4604 mov r4, r0 + 8043aec: 4608 mov r0, r1 + 8043aee: 4611 mov r1, r2 + 8043af0: 602b str r3, [r5, #0] + 8043af2: f7fc ff6e bl 80409d2 <_fstat> + 8043af6: 1c43 adds r3, r0, #1 + 8043af8: d102 bne.n 8043b00 <_fstat_r+0x1c> + 8043afa: 682b ldr r3, [r5, #0] + 8043afc: b103 cbz r3, 8043b00 <_fstat_r+0x1c> + 8043afe: 6023 str r3, [r4, #0] + 8043b00: bd38 pop {r3, r4, r5, pc} + 8043b02: bf00 nop + 8043b04: 2000012c .word 0x2000012c + +08043b08 <_isatty_r>: + 8043b08: b538 push {r3, r4, r5, lr} + 8043b0a: 4d06 ldr r5, [pc, #24] ; (8043b24 <_isatty_r+0x1c>) + 8043b0c: 2300 movs r3, #0 + 8043b0e: 4604 mov r4, r0 + 8043b10: 4608 mov r0, r1 + 8043b12: 602b str r3, [r5, #0] + 8043b14: f7fc ff6d bl 80409f2 <_isatty> + 8043b18: 1c43 adds r3, r0, #1 + 8043b1a: d102 bne.n 8043b22 <_isatty_r+0x1a> + 8043b1c: 682b ldr r3, [r5, #0] + 8043b1e: b103 cbz r3, 8043b22 <_isatty_r+0x1a> + 8043b20: 6023 str r3, [r4, #0] + 8043b22: bd38 pop {r3, r4, r5, pc} + 8043b24: 2000012c .word 0x2000012c + +08043b28 <_init>: + 8043b28: b5f8 push {r3, r4, r5, r6, r7, lr} + 8043b2a: bf00 nop + 8043b2c: bcf8 pop {r3, r4, r5, r6, r7} + 8043b2e: bc08 pop {r3} + 8043b30: 469e mov lr, r3 + 8043b32: 4770 bx lr + +08043b34 <_fini>: + 8043b34: b5f8 push {r3, r4, r5, r6, r7, lr} + 8043b36: bf00 nop + 8043b38: bcf8 pop {r3, r4, r5, r6, r7} + 8043b3a: bc08 pop {r3} + 8043b3c: 469e mov lr, r3 + 8043b3e: 4770 bx lr diff --git a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/.mxproject b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/.mxproject index 4bacc8a..621997a 100644 --- a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/.mxproject +++ b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/.mxproject @@ -1,8 +1,8 @@ [PreviousLibFiles] -LibFiles=Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h;Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h;Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; +LibFiles=Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h;Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h;Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h;Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h;Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; [PreviousUsedCubeIDEFiles] -SourceFiles=Core\Src\main.c;Core\Src\stm32f7xx_it.c;Core\Src\stm32f7xx_hal_msp.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;Core\Src/system_stm32f7xx.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;Core\Src/system_stm32f7xx.c;;; +SourceFiles=Core\Src\main.c;Core\Src\stm32f7xx_it.c;Core\Src\stm32f7xx_hal_msp.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c;Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;Core\Src/system_stm32f7xx.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c;Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c;Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c;Core\Src/system_stm32f7xx.c;;; HeaderPath=Drivers\STM32F7xx_HAL_Driver\Inc;Drivers\STM32F7xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32F7xx\Include;Drivers\CMSIS\Include;Core\Inc; CDefines=USE_HAL_DRIVER;STM32F767xx;USE_HAL_DRIVER;USE_HAL_DRIVER; diff --git a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Bootloader Debug.launch b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Bootloader Debug.launch index 91cb32a..3f3672a 100644 --- a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Bootloader Debug.launch +++ b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Bootloader Debug.launch @@ -68,6 +68,6 @@ - + diff --git a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Bootloader.ioc b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Bootloader.ioc index 2b412c2..af68891 100644 --- a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Bootloader.ioc +++ b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Bootloader.ioc @@ -3,12 +3,13 @@ File.Version=6 KeepUserPlacement=false Mcu.Family=STM32F7 Mcu.IP0=CORTEX_M7 -Mcu.IP1=NVIC -Mcu.IP2=RCC -Mcu.IP3=SYS -Mcu.IP4=USART2 -Mcu.IP5=USART3 -Mcu.IPNb=6 +Mcu.IP1=CRC +Mcu.IP2=NVIC +Mcu.IP3=RCC +Mcu.IP4=SYS +Mcu.IP5=USART2 +Mcu.IP6=USART3 +Mcu.IPNb=7 Mcu.Name=STM32F767ZITx Mcu.Package=LQFP144 Mcu.Pin0=PC13 @@ -17,8 +18,9 @@ Mcu.Pin2=PD8 Mcu.Pin3=PD9 Mcu.Pin4=PD5 Mcu.Pin5=PD6 -Mcu.Pin6=VP_SYS_VS_Systick -Mcu.PinsNb=7 +Mcu.Pin6=VP_CRC_VS_CRC +Mcu.Pin7=VP_SYS_VS_Systick +Mcu.PinsNb=8 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F767ZITx @@ -79,7 +81,7 @@ ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=STM32CubeIDE ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART3_UART_Init-USART3-false-HAL-true,4-MX_UART4_Init-UART4-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART3_UART_Init-USART3-false-HAL-true,4-MX_USART2_UART_Init-USART2-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true RCC.CECFreq_Value=32786.88524590164 RCC.DFSDMFreq_Value=16000000 RCC.FamilyName=M @@ -114,6 +116,8 @@ USART2.IPParameters=VirtualMode-Asynchronous USART2.VirtualMode-Asynchronous=VM_ASYNC USART3.IPParameters=VirtualMode-Asynchronous USART3.VirtualMode-Asynchronous=VM_ASYNC +VP_CRC_VS_CRC.Mode=CRC_Activate +VP_CRC_VS_CRC.Signal=CRC_VS_CRC VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick board=custom diff --git a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Core/Inc/etx_ota_update.h b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Core/Inc/etx_ota_update.h index 8ce413e..3235071 100644 --- a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Core/Inc/etx_ota_update.h +++ b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Core/Inc/etx_ota_update.h @@ -8,17 +8,34 @@ #ifndef INC_ETX_OTA_UPDATE_H_ #define INC_ETX_OTA_UPDATE_H_ +#include +#include "main.h" + #define ETX_OTA_SOF 0xAA // Start of Frame #define ETX_OTA_EOF 0xBB // End of Frame #define ETX_OTA_ACK 0x00 // ACK #define ETX_OTA_NACK 0x01 // NACK -#define ETX_APP_FLASH_ADDR 0x08040000 //Application's Flash Address +#define ETX_APP_FLASH_ADDR 0x08040000 //Application's Flash Address +#define ETX_APP_SLOT0_FLASH_ADDR 0x080C0000 //App slot 0 address +#define ETX_APP_SLOT1_FLASH_ADDR 0x08140000 //App slot 1 address +#define ETX_CONFIG_FLASH_ADDR 0x08020000 //Configuration's address + +#define ETX_NO_OF_SLOTS 2 //Number of slots +#define ETX_SLOT_MAX_SIZE (512 * 1024) //Each slot size (512KB) #define ETX_OTA_DATA_MAX_SIZE ( 1024 ) //Maximum data Size #define ETX_OTA_DATA_OVERHEAD ( 9 ) //data overhead #define ETX_OTA_PACKET_MAX_SIZE ( ETX_OTA_DATA_MAX_SIZE + ETX_OTA_DATA_OVERHEAD ) +/* + * Reboot reason + */ +#define ETX_FIRST_TIME_BOOT ( 0xFFFFFFFF ) //First time boot +#define ETX_NORMAL_BOOT ( 0xBEEFFEED ) //Normal Boot +#define ETX_OTA_REQUEST ( 0xDEADBEEF ) //OTA request by application +#define ETX_LOAD_PREV_APP ( 0xFACEFADE ) //App requests to load the previous version + /* * Exception codes */ @@ -61,6 +78,30 @@ typedef enum ETX_OTA_CMD_ABORT = 2, // OTA Abort command }ETX_OTA_CMD_; +/* + * Slot table + */ +typedef struct +{ + uint8_t is_this_slot_not_valid; //Is this slot has a valid firmware/application? + uint8_t is_this_slot_active; //Is this slot's firmware is currently running? + uint8_t should_we_run_this_fw; //Do we have to run this slot's firmware? + uint32_t fw_size; //Slot's firmware/application size + uint32_t fw_crc; //Slot's firmware/application CRC + uint32_t reserved1; + uint32_t reserved2; + uint32_t reserved3; +}__attribute__((packed)) ETX_SLOT_; + +/* + * General configuration + */ +typedef struct +{ + uint32_t reboot_cause; + ETX_SLOT_ slot_table[ETX_NO_OF_SLOTS]; +}__attribute__((packed)) ETX_GNRL_CFG_; + /* * OTA meta info */ @@ -147,4 +188,5 @@ typedef struct }__attribute__((packed)) ETX_OTA_RESP_; ETX_OTA_EX_ etx_ota_download_and_flash( void ); +void load_new_app( void ); #endif /* INC_ETX_OTA_UPDATE_H_ */ diff --git a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Core/Inc/stm32f7xx_hal_conf.h b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Core/Inc/stm32f7xx_hal_conf.h index cef4f33..b8e24c2 100644 --- a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Core/Inc/stm32f7xx_hal_conf.h +++ b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Core/Inc/stm32f7xx_hal_conf.h @@ -40,7 +40,7 @@ /* #define HAL_CRYP_MODULE_ENABLED */ /* #define HAL_CAN_MODULE_ENABLED */ /* #define HAL_CEC_MODULE_ENABLED */ -/* #define HAL_CRC_MODULE_ENABLED */ +#define HAL_CRC_MODULE_ENABLED /* #define HAL_CRYP_MODULE_ENABLED */ /* #define HAL_DAC_MODULE_ENABLED */ /* #define HAL_DCMI_MODULE_ENABLED */ diff --git a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Core/Src/etx_ota_update.c b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Core/Src/etx_ota_update.c index 00f3b76..3a754ac 100644 --- a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Core/Src/etx_ota_update.c +++ b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Core/Src/etx_ota_update.c @@ -23,12 +23,24 @@ static uint32_t ota_fw_total_size; static uint32_t ota_fw_crc; /* Firmware Size that we have received */ static uint32_t ota_fw_received_size; +/* Slot number to write the received firmware */ +static uint8_t slot_num_to_write; +/* Configuration */ +ETX_GNRL_CFG_ *cfg_flash = (ETX_GNRL_CFG_*) (ETX_CONFIG_FLASH_ADDR); + +/* Hardware CRC handle */ +extern CRC_HandleTypeDef hcrc; static uint16_t etx_receive_chunk( uint8_t *buf, uint16_t max_len ); static ETX_OTA_EX_ etx_process_data( uint8_t *buf, uint16_t len ); static void etx_ota_send_resp( uint8_t type ); -static HAL_StatusTypeDef write_data_to_flash_app( uint8_t *data, - uint16_t data_len, bool is_full_image ); +static HAL_StatusTypeDef write_data_to_slot( uint8_t slot_num, + uint8_t *data, + uint16_t data_len, + bool is_first_block ); +static HAL_StatusTypeDef write_data_to_flash_app( uint8_t *data, uint32_t data_len ); +static uint8_t get_available_slot_number( void ); +static HAL_StatusTypeDef write_cfg_to_flash( ETX_GNRL_CFG_ *cfg ); /** * @brief Download the application from UART and flash it. @@ -47,6 +59,7 @@ ETX_OTA_EX_ etx_ota_download_and_flash( void ) ota_fw_received_size = 0u; ota_fw_crc = 0u; ota_state = ETX_OTA_STATE_START; + slot_num_to_write = 0xFFu; do { @@ -144,8 +157,14 @@ static ETX_OTA_EX_ etx_process_data( uint8_t *buf, uint16_t len ) ota_fw_total_size = header->meta_data.package_size; ota_fw_crc = header->meta_data.package_crc; printf("Received OTA Header. FW Size = %ld\r\n", ota_fw_total_size); - ota_state = ETX_OTA_STATE_DATA; - ret = ETX_OTA_EX_OK; + + //get the slot number + slot_num_to_write = get_available_slot_number(); + if( slot_num_to_write != 0xFF ) + { + ota_state = ETX_OTA_STATE_DATA; + ret = ETX_OTA_EX_OK; + } } } break; @@ -158,8 +177,29 @@ static ETX_OTA_EX_ etx_process_data( uint8_t *buf, uint16_t len ) if( data->packet_type == ETX_OTA_PACKET_TYPE_DATA ) { + bool is_first_block = false; + if( ota_fw_received_size == 0 ) + { + //This is the first block + is_first_block = true; + + /* Read the configuration */ + ETX_GNRL_CFG_ cfg; + memcpy( &cfg, cfg_flash, sizeof(ETX_GNRL_CFG_) ); + + /* Before writing the data, reset the available slot */ + cfg.slot_table[slot_num_to_write].is_this_slot_not_valid = 1u; + + /* write back the updated config */ + ret = write_cfg_to_flash( &cfg ); + if( ret != ETX_OTA_EX_OK ) + { + break; + } + } + /* write the chunk to the Flash (App location) */ - ex = write_data_to_flash_app( buf, data_len, ( ota_fw_received_size == 0) ); + ex = write_data_to_slot( slot_num_to_write, buf+4, data_len, is_first_block ); if( ex == HAL_OK ) { @@ -186,10 +226,57 @@ static ETX_OTA_EX_ etx_process_data( uint8_t *buf, uint16_t len ) { printf("Received OTA END Command\r\n"); - //TODO: Very full package CRC + printf("Validating the received Binary...\r\n"); - ota_state = ETX_OTA_STATE_IDLE; - ret = ETX_OTA_EX_OK; + uint32_t slot_addr; + if( slot_num_to_write == 0u ) + { + slot_addr = ETX_APP_SLOT0_FLASH_ADDR; + } + else + { + slot_addr = ETX_APP_SLOT1_FLASH_ADDR; + } + + //Calculate and verify the CRC + uint32_t cal_crc = HAL_CRC_Calculate( &hcrc, (uint32_t*)slot_addr, ota_fw_total_size); + if( cal_crc != ota_fw_crc ) + { + printf("ERROR: FW CRC Mismatch\r\n"); + break; + } + printf("Done!!!\r\n"); + + /* Read the configuration */ + ETX_GNRL_CFG_ cfg; + memcpy( &cfg, cfg_flash, sizeof(ETX_GNRL_CFG_) ); + + //update the slot + cfg.slot_table[slot_num_to_write].fw_crc = cal_crc; + cfg.slot_table[slot_num_to_write].fw_size = ota_fw_total_size; + cfg.slot_table[slot_num_to_write].is_this_slot_not_valid = 0u; + cfg.slot_table[slot_num_to_write].should_we_run_this_fw = 1u; + + //reset other slots + for( uint8_t i = 0; i < ETX_NO_OF_SLOTS; i++ ) + { + if( slot_num_to_write != i ) + { + //update the slot as inactive + cfg.slot_table[i].should_we_run_this_fw = 0u; + } + } + + //update the reboot reason + cfg.reboot_cause = ETX_NORMAL_BOOT; + + /* write back the updated config */ + ret = write_cfg_to_flash( &cfg ); + if( ret == ETX_OTA_EX_OK ) + { + ota_state = ETX_OTA_STATE_IDLE; + ret = ETX_OTA_EX_OK; + } } } } @@ -216,8 +303,10 @@ static ETX_OTA_EX_ etx_process_data( uint8_t *buf, uint16_t len ) static uint16_t etx_receive_chunk( uint8_t *buf, uint16_t max_len ) { int16_t ret; - uint16_t index = 0u; + uint16_t index = 0u; uint16_t data_len; + uint32_t cal_data_crc = 0u; + uint32_t rec_data_crc = 0u; do { @@ -260,16 +349,20 @@ static uint16_t etx_receive_chunk( uint8_t *buf, uint16_t max_len ) } } + if( ret != HAL_OK ) + { + break; + } + //Get the CRC. ret = HAL_UART_Receive( &huart2, &buf[index], 4, HAL_MAX_DELAY ); if( ret != HAL_OK ) { break; } + rec_data_crc = *(uint32_t *)&buf[index]; index += 4u; - //TODO: Add CRC verification - //receive EOF byte (1byte) ret = HAL_UART_Receive( &huart2, &buf[index], 1, HAL_MAX_DELAY ); if( ret != HAL_OK ) @@ -284,6 +377,18 @@ static uint16_t etx_receive_chunk( uint8_t *buf, uint16_t max_len ) break; } + //Calculate the received data's CRC + cal_data_crc = HAL_CRC_Calculate( &hcrc, (uint32_t*)&buf[4], data_len); + + //Verify the CRC + if( cal_data_crc != rec_data_crc ) + { + printf("Chunk's CRC mismatch [Cal CRC = 0x%08lX] [Rec CRC = 0x%08lX]\r\n", + cal_data_crc, rec_data_crc ); + ret = ETX_OTA_EX_ERR; + break; + } + }while( false ); if( ret != HAL_OK ) @@ -315,28 +420,39 @@ static void etx_ota_send_resp( uint8_t type ) .packet_type = ETX_OTA_PACKET_TYPE_RESPONSE, .data_len = 1u, .status = type, - .crc = 0u, //TODO: Add CRC .eof = ETX_OTA_EOF }; + rsp.crc = HAL_CRC_Calculate( &hcrc, (uint32_t*)&rsp.status, 1); + //send response HAL_UART_Transmit(&huart2, (uint8_t *)&rsp, sizeof(ETX_OTA_RESP_), HAL_MAX_DELAY); } /** - * @brief Write data to the Application's actual flash location. + * @brief Write data to the Slot + * @param slot_num slot to be written * @param data data to be written * @param data_len data length * @is_first_block true - if this is first block, false - not first block * @retval HAL_StatusTypeDef */ -static HAL_StatusTypeDef write_data_to_flash_app( uint8_t *data, - uint16_t data_len, bool is_first_block ) +static HAL_StatusTypeDef write_data_to_slot( uint8_t slot_num, + uint8_t *data, + uint16_t data_len, + bool is_first_block ) { HAL_StatusTypeDef ret; do { + + if( slot_num >= ETX_NO_OF_SLOTS ) + { + ret = HAL_ERROR; + break; + } + ret = HAL_FLASH_Unlock(); if( ret != HAL_OK ) { @@ -346,29 +462,46 @@ static HAL_StatusTypeDef write_data_to_flash_app( uint8_t *data, //No need to erase every time. Erase only the first time. if( is_first_block ) { - - printf("Erasing the Flash memory...\r\n"); + printf("Erasing the Slot %d Flash memory...\r\n", slot_num); //Erase the Flash FLASH_EraseInitTypeDef EraseInitStruct; uint32_t SectorError; EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS; - EraseInitStruct.Sector = FLASH_SECTOR_5; - EraseInitStruct.NbSectors = 2; //erase 2 sectors(5,6) + if( slot_num == 0 ) + { + EraseInitStruct.Sector = FLASH_SECTOR_7; + } + else + { + EraseInitStruct.Sector = FLASH_SECTOR_9; + } + EraseInitStruct.NbSectors = 2; //erase 2 sectors EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3; ret = HAL_FLASHEx_Erase( &EraseInitStruct, &SectorError ); if( ret != HAL_OK ) { + printf("Flash Erase Error\r\n"); break; } } + uint32_t flash_addr; + if( slot_num == 0 ) + { + flash_addr = ETX_APP_SLOT0_FLASH_ADDR; + } + else + { + flash_addr = ETX_APP_SLOT1_FLASH_ADDR; + } + for(int i = 0; i < data_len; i++ ) { ret = HAL_FLASH_Program( FLASH_TYPEPROGRAM_BYTE, - (ETX_APP_FLASH_ADDR + ota_fw_received_size), - data[4+i] + (flash_addr + ota_fw_received_size), + data[i] ); if( ret == HAL_OK ) { @@ -396,3 +529,294 @@ static HAL_StatusTypeDef write_data_to_flash_app( uint8_t *data, return ret; } + +/** + * @brief Return the available slot number + * @param none + * @retval slot number + */ +static uint8_t get_available_slot_number( void ) +{ + uint8_t slot_number = 0xFF; + + /* Read the configuration */ + ETX_GNRL_CFG_ cfg; + memcpy( &cfg, cfg_flash, sizeof(ETX_GNRL_CFG_) ); + /* + * Check the slot is valid or not. If it is valid, + * then check the slot is active or not. + * + * If it is valid and not active, then use that slot. + * If it is not valid, then use that slot. + * + */ + + for( uint8_t i = 0; i < ETX_NO_OF_SLOTS; i++ ) + { + if( ( cfg.slot_table[i].is_this_slot_not_valid != 0u ) || ( cfg.slot_table[i].is_this_slot_active == 0u ) ) + { + slot_number = i; + printf("Slot %d is available for OTA update\r\n", slot_number); + break; + } + } + + return slot_number; +} + + +/** + * @brief Write data to the Application's actual flash location. + * @param data data to be written + * @param data_len data length + * @retval HAL_StatusTypeDef + */ +static HAL_StatusTypeDef write_data_to_flash_app( uint8_t *data, uint32_t data_len ) +{ + HAL_StatusTypeDef ret; + + do + { + ret = HAL_FLASH_Unlock(); + if( ret != HAL_OK ) + { + break; + } + + //Check if the FLASH_FLAG_BSY. + FLASH_WaitForLastOperation( HAL_MAX_DELAY ); + + // clear all flags before you write it to flash + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | + FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR); + + printf("Erasing the App Flash memory...\r\n"); + //Erase the Flash + FLASH_EraseInitTypeDef EraseInitStruct; + uint32_t SectorError; + + EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS; + EraseInitStruct.Sector = FLASH_SECTOR_5; + EraseInitStruct.NbSectors = 2; //erase 2 sectors(5,6) + EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3; + + ret = HAL_FLASHEx_Erase( &EraseInitStruct, &SectorError ); + if( ret != HAL_OK ) + { + printf("Flash erase Error\r\n"); + break; + } + + for( uint32_t i = 0; i < data_len; i++ ) + { + ret = HAL_FLASH_Program( FLASH_TYPEPROGRAM_BYTE, + (ETX_APP_FLASH_ADDR + i), + data[i] + ); + if( ret != HAL_OK ) + { + printf("App Flash Write Error\r\n"); + break; + } + } + + if( ret != HAL_OK ) + { + break; + } + + ret = HAL_FLASH_Lock(); + if( ret != HAL_OK ) + { + break; + } + + //Check if the FLASH_FLAG_BSY. + FLASH_WaitForLastOperation( HAL_MAX_DELAY ); + + }while( false ); + + return ret; +} + +/** + * @brief Load the new app to the app's actual flash memory. + * @param none + * @retval none + */ +void load_new_app( void ) +{ + bool is_update_available = false; + uint8_t slot_num; + HAL_StatusTypeDef ret; + + /* Read the configuration */ + ETX_GNRL_CFG_ cfg; + memcpy( &cfg, cfg_flash, sizeof(ETX_GNRL_CFG_) ); + + /* + * Check the slot whether it has a new application. + */ + + for( uint8_t i = 0; i < ETX_NO_OF_SLOTS; i++ ) + { + if( cfg.slot_table[i].should_we_run_this_fw == 1u ) + { + printf("New Application is available in the slot %d!!!\r\n", i); + is_update_available = true; + slot_num = i; + + //update the slot + cfg.slot_table[i].is_this_slot_active = 1u; + cfg.slot_table[i].should_we_run_this_fw = 0u; + + break; + } + } + + if( is_update_available ) + { + //make other slots inactive + for( uint8_t i = 0; i < ETX_NO_OF_SLOTS; i++ ) + { + if( slot_num != i ) + { + //update the slot as inactive + cfg.slot_table[i].is_this_slot_active = 0u; + } + } + + uint32_t slot_addr; + if( slot_num == 0u ) + { + slot_addr = ETX_APP_SLOT0_FLASH_ADDR; + } + else + { + slot_addr = ETX_APP_SLOT1_FLASH_ADDR; + } + + //Load the new app or firmware to app's flash address + ret = write_data_to_flash_app( (uint8_t*)slot_addr, cfg.slot_table[slot_num].fw_size ); + if( ret != HAL_OK ) + { + printf("App Flash write Error\r\n"); + } + else + { + /* write back the updated config */ + ret = write_cfg_to_flash( &cfg ); + if( ret != HAL_OK ) + { + printf("Config Flash write Error\r\n"); + } + } + } + else + { + //Find the active slot in case the update is not available + for( uint8_t i = 0; i < ETX_NO_OF_SLOTS; i++ ) + { + if( cfg.slot_table[i].is_this_slot_active == 1u ) + { + slot_num = i; + break; + } + } + } + + //Verify the application is corrupted or not + printf("Verifying the Application..."); + + FLASH_WaitForLastOperation( HAL_MAX_DELAY ); + //Verify the application + uint32_t cal_data_crc = HAL_CRC_Calculate( &hcrc, (uint32_t*)ETX_APP_FLASH_ADDR, cfg.slot_table[slot_num].fw_size ); + FLASH_WaitForLastOperation( HAL_MAX_DELAY ); + + //Verify the CRC + if( cal_data_crc != cfg.slot_table[slot_num].fw_crc ) + { + printf("ERROR!!!\r\n"); + printf("Invalid Application. HALT!!!\r\n"); + while(1); + } + printf("Done!!!\r\n"); +} + +/** + * @brief Write the configuration to flash + * @param cfg config structure + * @retval none + */ +static HAL_StatusTypeDef write_cfg_to_flash( ETX_GNRL_CFG_ *cfg ) +{ + HAL_StatusTypeDef ret; + + do + { + if( cfg == NULL ) + { + ret = HAL_ERROR; + break; + } + + ret = HAL_FLASH_Unlock(); + if( ret != HAL_OK ) + { + break; + } + + //Check if the FLASH_FLAG_BSY. + FLASH_WaitForLastOperation( HAL_MAX_DELAY ); + + //Erase the Flash + FLASH_EraseInitTypeDef EraseInitStruct; + uint32_t SectorError; + + EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS; + EraseInitStruct.Sector = FLASH_SECTOR_4; + EraseInitStruct.NbSectors = 1; //erase only sector 4 + EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3; + + // clear all flags before you write it to flash + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | + FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR); + + ret = HAL_FLASHEx_Erase( &EraseInitStruct, &SectorError ); + if( ret != HAL_OK ) + { + break; + } + + //write the configuration + uint8_t *data = (uint8_t *) cfg; + for( uint32_t i = 0u; i < sizeof(ETX_GNRL_CFG_); i++ ) + { + ret = HAL_FLASH_Program( FLASH_TYPEPROGRAM_BYTE, + ETX_CONFIG_FLASH_ADDR + i, + data[i] + ); + if( ret != HAL_OK ) + { + printf("Slot table Flash Write Error\r\n"); + break; + } + } + + //Check if the FLASH_FLAG_BSY. + FLASH_WaitForLastOperation( HAL_MAX_DELAY ); + + if( ret != HAL_OK ) + { + break; + } + + ret = HAL_FLASH_Lock(); + if( ret != HAL_OK ) + { + break; + } + }while( false ); + + return ret; +} diff --git a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Core/Src/main.c b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Core/Src/main.c index 87a21d3..8c05809 100644 --- a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Core/Src/main.c +++ b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Core/Src/main.c @@ -37,11 +37,13 @@ /* Private macro -------------------------------------------------------------*/ /* USER CODE BEGIN PM */ #define MAJOR 0 // BL Major version Number -#define MINOR 2 // BL Minor version Number +#define MINOR 3 // BL Minor version Number /* USER CODE END PM */ /* Private variables ---------------------------------------------------------*/ +CRC_HandleTypeDef hcrc; + UART_HandleTypeDef huart2; UART_HandleTypeDef huart3; @@ -54,6 +56,7 @@ void SystemClock_Config(void); static void MX_GPIO_Init(void); static void MX_USART3_UART_Init(void); static void MX_USART2_UART_Init(void); +static void MX_CRC_Init(void); /* USER CODE BEGIN PFP */ static void goto_application( void ); /* USER CODE END PFP */ @@ -93,12 +96,53 @@ int main(void) MX_GPIO_Init(); MX_USART3_UART_Init(); MX_USART2_UART_Init(); + MX_CRC_Init(); /* USER CODE BEGIN 2 */ // Turn ON the Green Led to tell the user that Bootloader is running HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_SET ); //Green LED ON printf("Starting Bootloader(%d.%d)\r\n", BL_Version[0], BL_Version[1] ); //HAL_Delay(2000); //2sec delay for nothing + + //Read the reboot cause and act accordingly + printf("Reading the reboot reason...\r\n"); + + ETX_GNRL_CFG_ *cfg = (ETX_GNRL_CFG_*) (ETX_CONFIG_FLASH_ADDR); + bool goto_ota_mode = false; + + switch( cfg->reboot_cause ) + { + case ETX_NORMAL_BOOT: + { + /* + * It is a normal boot. So, do nothing here. + */ + printf("Normal Boot\r\n"); + break; + } + case ETX_OTA_REQUEST: + case ETX_FIRST_TIME_BOOT: + { + /* + * Application has requested for the OTA update or this is the first + * time boot. So, don't wait for the user to press the button. + * Directly go to OTA mode. + */ + printf("First time boot / OTA Request...\r\n"); + printf("Going to OTA mode...\r\n"); + goto_ota_mode = true; + break; + } + case ETX_LOAD_PREV_APP: + { + //TODO: Implement + break; + } + default: + /* should not get here */ + break; + }; + /* Check the GPIO for 3 seconds */ GPIO_PinState OTA_Pin_state; uint32_t end_tick = HAL_GetTick() + 3000; // from now to 3 Seconds @@ -115,10 +159,10 @@ int main(void) /* Either timeout or Button is pressed */ break; } - }while( 1 ); + }while( !goto_ota_mode ); /*Start the Firmware or Application update */ - if( OTA_Pin_state == GPIO_PIN_SET ) + if( ( OTA_Pin_state == GPIO_PIN_SET ) || ( goto_ota_mode ) ) { printf("Starting Firmware Download!!!\r\n"); /* OTA Request. Receive the data from the UART4 and flash */ @@ -136,6 +180,9 @@ int main(void) } } + //Load the updated app, if it is available + load_new_app(); + // Jump to application goto_application(); /* USER CODE END 2 */ @@ -198,6 +245,37 @@ void SystemClock_Config(void) } } +/** + * @brief CRC Initialization Function + * @param None + * @retval None + */ +static void MX_CRC_Init(void) +{ + + /* USER CODE BEGIN CRC_Init 0 */ + + /* USER CODE END CRC_Init 0 */ + + /* USER CODE BEGIN CRC_Init 1 */ + + /* USER CODE END CRC_Init 1 */ + hcrc.Instance = CRC; + hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE; + hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE; + hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE; + hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE; + hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES; + if (HAL_CRC_Init(&hcrc) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN CRC_Init 2 */ + + /* USER CODE END CRC_Init 2 */ + +} + /** * @brief USART2 Initialization Function * @param None @@ -328,9 +406,9 @@ static void goto_application(void) { printf("Gonna Jump to Application\r\n"); - void (*app_reset_handler)(void) = (void*)(*((volatile uint32_t*) (0x08040000 + 4U))); + void (*app_reset_handler)(void) = (void*)(*((volatile uint32_t*) (ETX_APP_FLASH_ADDR + 4U))); - //__set_MSP(*(volatile uint32_t*) 0x08040000); + //__set_MSP(*(volatile uint32_t*) ETX_APP_FLASH_ADDR); // Turn OFF the Green Led to tell the user that Bootloader is not running HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_RESET ); //Green LED OFF diff --git a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Core/Src/stm32f7xx_hal_msp.c b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Core/Src/stm32f7xx_hal_msp.c index cbd2cb5..fbeefb7 100644 --- a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Core/Src/stm32f7xx_hal_msp.c +++ b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Core/Src/stm32f7xx_hal_msp.c @@ -77,6 +77,50 @@ void HAL_MspInit(void) /* USER CODE END MspInit 1 */ } +/** +* @brief CRC MSP Initialization +* This function configures the hardware resources used in this example +* @param hcrc: CRC handle pointer +* @retval None +*/ +void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc) +{ + if(hcrc->Instance==CRC) + { + /* USER CODE BEGIN CRC_MspInit 0 */ + + /* USER CODE END CRC_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_CRC_CLK_ENABLE(); + /* USER CODE BEGIN CRC_MspInit 1 */ + + /* USER CODE END CRC_MspInit 1 */ + } + +} + +/** +* @brief CRC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hcrc: CRC handle pointer +* @retval None +*/ +void HAL_CRC_MspDeInit(CRC_HandleTypeDef* hcrc) +{ + if(hcrc->Instance==CRC) + { + /* USER CODE BEGIN CRC_MspDeInit 0 */ + + /* USER CODE END CRC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_CRC_CLK_DISABLE(); + /* USER CODE BEGIN CRC_MspDeInit 1 */ + + /* USER CODE END CRC_MspDeInit 1 */ + } + +} + /** * @brief UART MSP Initialization * This function configures the hardware resources used in this example diff --git a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Debug/Bootloader.bin b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Debug/Bootloader.bin index a0bea1a..952c482 100644 Binary files a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Debug/Bootloader.bin and b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Debug/Bootloader.bin differ diff --git a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Debug/Bootloader.list b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Debug/Bootloader.list index d144db9..1cd5ca4 100644 --- a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Debug/Bootloader.list +++ b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Debug/Bootloader.list @@ -5,45 +5,45 @@ Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001f8 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA - 1 .text 000047f0 08000200 08000200 00010200 2**4 + 1 .text 0000549c 08000200 08000200 00010200 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE - 2 .rodata 000002bc 080049f0 080049f0 000149f0 2**2 + 2 .rodata 00000518 0800569c 0800569c 0001569c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 3 .ARM.extab 00000000 08004cac 08004cac 00020070 2**0 + 3 .ARM.extab 00000000 08005bb4 08005bb4 00020074 2**0 CONTENTS - 4 .ARM 00000008 08004cac 08004cac 00014cac 2**2 + 4 .ARM 00000008 08005bb4 08005bb4 00015bb4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 5 .preinit_array 00000000 08004cb4 08004cb4 00020070 2**0 + 5 .preinit_array 00000000 08005bbc 08005bbc 00020074 2**0 CONTENTS, ALLOC, LOAD, DATA - 6 .init_array 00000004 08004cb4 08004cb4 00014cb4 2**2 + 6 .init_array 00000004 08005bbc 08005bbc 00015bbc 2**2 CONTENTS, ALLOC, LOAD, DATA - 7 .fini_array 00000004 08004cb8 08004cb8 00014cb8 2**2 + 7 .fini_array 00000004 08005bc0 08005bc0 00015bc0 2**2 CONTENTS, ALLOC, LOAD, DATA - 8 .data 00000070 20000000 08004cbc 00020000 2**2 + 8 .data 00000074 20000000 08005bc4 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA - 9 .bss 00000578 20000070 08004d2c 00020070 2**2 + 9 .bss 000005a0 20000074 08005c38 00020074 2**2 ALLOC - 10 ._user_heap_stack 00000600 200005e8 08004d2c 000205e8 2**0 + 10 ._user_heap_stack 00000604 20000614 08005c38 00020614 2**0 ALLOC - 11 .ARM.attributes 0000002e 00000000 00000000 00020070 2**0 + 11 .ARM.attributes 0000002e 00000000 00000000 00020074 2**0 CONTENTS, READONLY - 12 .debug_info 0000c391 00000000 00000000 0002009e 2**0 + 12 .debug_info 0000d8e1 00000000 00000000 000200a2 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 13 .debug_abbrev 000020ee 00000000 00000000 0002c42f 2**0 + 13 .debug_abbrev 000024e7 00000000 00000000 0002d983 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 14 .debug_aranges 00000908 00000000 00000000 0002e520 2**3 + 14 .debug_aranges 000009d0 00000000 00000000 0002fe70 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS - 15 .debug_ranges 00000858 00000000 00000000 0002ee28 2**3 + 15 .debug_ranges 00000930 00000000 00000000 00030840 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS - 16 .debug_macro 00028243 00000000 00000000 0002f680 2**0 + 16 .debug_macro 00028881 00000000 00000000 00031170 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 17 .debug_line 0000a97c 00000000 00000000 000578c3 2**0 + 17 .debug_line 0000c137 00000000 00000000 000599f1 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 18 .debug_str 000f27c2 00000000 00000000 0006223f 2**0 + 18 .debug_str 000f376f 00000000 00000000 00065b28 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 19 .comment 00000053 00000000 00000000 00154a01 2**0 + 19 .comment 00000053 00000000 00000000 00159297 2**0 CONTENTS, READONLY - 20 .debug_frame 00002b1c 00000000 00000000 00154a54 2**2 + 20 .debug_frame 00002e20 00000000 00000000 001592ec 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: @@ -60,9 +60,9 @@ Disassembly of section .text: 8000212: 2301 movs r3, #1 8000214: 7023 strb r3, [r4, #0] 8000216: bd10 pop {r4, pc} - 8000218: 20000070 .word 0x20000070 + 8000218: 20000074 .word 0x20000074 800021c: 00000000 .word 0x00000000 - 8000220: 080049d8 .word 0x080049d8 + 8000220: 08005684 .word 0x08005684 08000224 : 8000224: b508 push {r3, lr} @@ -73,8 +73,8 @@ Disassembly of section .text: 800022e: f3af 8000 nop.w 8000232: bd08 pop {r3, pc} 8000234: 00000000 .word 0x00000000 - 8000238: 20000074 .word 0x20000074 - 800023c: 080049d8 .word 0x080049d8 + 8000238: 20000078 .word 0x20000078 + 800023c: 08005684 .word 0x08005684 08000240 : 8000240: f001 01ff and.w r1, r1, #255 ; 0xff @@ -427,10942 +427,13027 @@ ETX_OTA_EX_ etx_ota_download_and_flash( void ) uint16_t len; printf("Waiting for the OTA data...\r\n"); - 80005e2: 481f ldr r0, [pc, #124] ; (8000660 ) - 80005e4: f003 fab2 bl 8003b4c + 80005e2: 4821 ldr r0, [pc, #132] ; (8000668 ) + 80005e4: f004 f908 bl 80047f8 /* Reset the variables */ ota_fw_total_size = 0u; - 80005e8: 4b1e ldr r3, [pc, #120] ; (8000664 ) + 80005e8: 4b20 ldr r3, [pc, #128] ; (800066c ) 80005ea: 2200 movs r2, #0 80005ec: 601a str r2, [r3, #0] ota_fw_received_size = 0u; - 80005ee: 4b1e ldr r3, [pc, #120] ; (8000668 ) + 80005ee: 4b20 ldr r3, [pc, #128] ; (8000670 ) 80005f0: 2200 movs r2, #0 80005f2: 601a str r2, [r3, #0] ota_fw_crc = 0u; - 80005f4: 4b1d ldr r3, [pc, #116] ; (800066c ) + 80005f4: 4b1f ldr r3, [pc, #124] ; (8000674 ) 80005f6: 2200 movs r2, #0 80005f8: 601a str r2, [r3, #0] ota_state = ETX_OTA_STATE_START; - 80005fa: 4b1d ldr r3, [pc, #116] ; (8000670 ) + 80005fa: 4b1f ldr r3, [pc, #124] ; (8000678 ) 80005fc: 2201 movs r2, #1 80005fe: 701a strb r2, [r3, #0] + slot_num_to_write = 0xFFu; + 8000600: 4b1e ldr r3, [pc, #120] ; (800067c ) + 8000602: 22ff movs r2, #255 ; 0xff + 8000604: 701a strb r2, [r3, #0] do { //clear the buffer memset( Rx_Buffer, 0, ETX_OTA_PACKET_MAX_SIZE ); - 8000600: f240 4209 movw r2, #1033 ; 0x409 - 8000604: 2100 movs r1, #0 - 8000606: 481b ldr r0, [pc, #108] ; (8000674 ) - 8000608: f003 fa12 bl 8003a30 + 8000606: f240 4209 movw r2, #1033 ; 0x409 + 800060a: 2100 movs r1, #0 + 800060c: 481c ldr r0, [pc, #112] ; (8000680 ) + 800060e: f004 f865 bl 80046dc len = etx_receive_chunk( Rx_Buffer, ETX_OTA_PACKET_MAX_SIZE ); - 800060c: f240 4109 movw r1, #1033 ; 0x409 - 8000610: 4818 ldr r0, [pc, #96] ; (8000674 ) - 8000612: f000 f907 bl 8000824 - 8000616: 4603 mov r3, r0 - 8000618: 80bb strh r3, [r7, #4] + 8000612: f240 4109 movw r1, #1033 ; 0x409 + 8000616: 481a ldr r0, [pc, #104] ; (8000680 ) + 8000618: f000 fa0c bl 8000a34 + 800061c: 4603 mov r3, r0 + 800061e: 80bb strh r3, [r7, #4] if( len != 0u ) - 800061a: 88bb ldrh r3, [r7, #4] - 800061c: 2b00 cmp r3, #0 - 800061e: d007 beq.n 8000630 + 8000620: 88bb ldrh r3, [r7, #4] + 8000622: 2b00 cmp r3, #0 + 8000624: d007 beq.n 8000636 { ret = etx_process_data( Rx_Buffer, len ); - 8000620: 88bb ldrh r3, [r7, #4] - 8000622: 4619 mov r1, r3 - 8000624: 4813 ldr r0, [pc, #76] ; (8000674 ) - 8000626: f000 f829 bl 800067c - 800062a: 4603 mov r3, r0 - 800062c: 71fb strb r3, [r7, #7] - 800062e: e001 b.n 8000634 + 8000626: 88bb ldrh r3, [r7, #4] + 8000628: 4619 mov r1, r3 + 800062a: 4815 ldr r0, [pc, #84] ; (8000680 ) + 800062c: f000 f82c bl 8000688 + 8000630: 4603 mov r3, r0 + 8000632: 71fb strb r3, [r7, #7] + 8000634: e001 b.n 800063a } else { //didn't received data. break. ret = ETX_OTA_EX_ERR; - 8000630: 2301 movs r3, #1 - 8000632: 71fb strb r3, [r7, #7] + 8000636: 2301 movs r3, #1 + 8000638: 71fb strb r3, [r7, #7] } //Send ACK or NACK if( ret != ETX_OTA_EX_OK ) - 8000634: 79fb ldrb r3, [r7, #7] - 8000636: 2b00 cmp r3, #0 - 8000638: d006 beq.n 8000648 + 800063a: 79fb ldrb r3, [r7, #7] + 800063c: 2b00 cmp r3, #0 + 800063e: d006 beq.n 800064e { printf("Sending NACK\r\n"); - 800063a: 480f ldr r0, [pc, #60] ; (8000678 ) - 800063c: f003 fa86 bl 8003b4c + 8000640: 4810 ldr r0, [pc, #64] ; (8000684 ) + 8000642: f004 f8d9 bl 80047f8 etx_ota_send_resp( ETX_OTA_NACK ); - 8000640: 2001 movs r0, #1 - 8000642: f000 f9ab bl 800099c + 8000646: 2001 movs r0, #1 + 8000648: f000 fad8 bl 8000bfc break; - 8000646: e006 b.n 8000656 + 800064c: e006 b.n 800065c } else { //printf("Sending ACK\r\n"); etx_ota_send_resp( ETX_OTA_ACK ); - 8000648: 2000 movs r0, #0 - 800064a: f000 f9a7 bl 800099c + 800064e: 2000 movs r0, #0 + 8000650: f000 fad4 bl 8000bfc } }while( ota_state != ETX_OTA_STATE_IDLE ); - 800064e: 4b08 ldr r3, [pc, #32] ; (8000670 ) - 8000650: 781b ldrb r3, [r3, #0] - 8000652: 2b00 cmp r3, #0 - 8000654: d1d4 bne.n 8000600 + 8000654: 4b08 ldr r3, [pc, #32] ; (8000678 ) + 8000656: 781b ldrb r3, [r3, #0] + 8000658: 2b00 cmp r3, #0 + 800065a: d1d4 bne.n 8000606 return ret; - 8000656: 79fb ldrb r3, [r7, #7] + 800065c: 79fb ldrb r3, [r7, #7] } - 8000658: 4618 mov r0, r3 - 800065a: 3708 adds r7, #8 - 800065c: 46bd mov sp, r7 - 800065e: bd80 pop {r7, pc} - 8000660: 080049f0 .word 0x080049f0 - 8000664: 20000498 .word 0x20000498 - 8000668: 200004a0 .word 0x200004a0 + 800065e: 4618 mov r0, r3 + 8000660: 3708 adds r7, #8 + 8000662: 46bd mov sp, r7 + 8000664: bd80 pop {r7, pc} + 8000666: bf00 nop + 8000668: 0800569c .word 0x0800569c 800066c: 2000049c .word 0x2000049c - 8000670: 20000495 .word 0x20000495 - 8000674: 2000008c .word 0x2000008c - 8000678: 08004a10 .word 0x08004a10 - -0800067c : + 8000670: 200004a4 .word 0x200004a4 + 8000674: 200004a0 .word 0x200004a0 + 8000678: 20000499 .word 0x20000499 + 800067c: 200004a8 .word 0x200004a8 + 8000680: 20000090 .word 0x20000090 + 8000684: 080056bc .word 0x080056bc + +08000688 : * @param buf buffer to store the received data * @param max_len maximum length to receive * @retval ETX_OTA_EX_ */ static ETX_OTA_EX_ etx_process_data( uint8_t *buf, uint16_t len ) { - 800067c: b580 push {r7, lr} - 800067e: b08a sub sp, #40 ; 0x28 - 8000680: af00 add r7, sp, #0 - 8000682: 6078 str r0, [r7, #4] - 8000684: 460b mov r3, r1 - 8000686: 807b strh r3, [r7, #2] + 8000688: b5f0 push {r4, r5, r6, r7, lr} + 800068a: b09b sub sp, #108 ; 0x6c + 800068c: af00 add r7, sp, #0 + 800068e: 6078 str r0, [r7, #4] + 8000690: 460b mov r3, r1 + 8000692: 807b strh r3, [r7, #2] ETX_OTA_EX_ ret = ETX_OTA_EX_ERR; - 8000688: 2301 movs r3, #1 - 800068a: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8000694: 2301 movs r3, #1 + 8000696: f887 3067 strb.w r3, [r7, #103] ; 0x67 do { if( ( buf == NULL ) || ( len == 0u) ) - 800068e: 687b ldr r3, [r7, #4] - 8000690: 2b00 cmp r3, #0 - 8000692: f000 80a3 beq.w 80007dc - 8000696: 887b ldrh r3, [r7, #2] - 8000698: 2b00 cmp r3, #0 - 800069a: f000 809f beq.w 80007dc + 800069a: 687b ldr r3, [r7, #4] + 800069c: 2b00 cmp r3, #0 + 800069e: f000 8190 beq.w 80009c2 + 80006a2: 887b ldrh r3, [r7, #2] + 80006a4: 2b00 cmp r3, #0 + 80006a6: f000 818c beq.w 80009c2 { break; } //Check we received OTA Abort command ETX_OTA_COMMAND_ *cmd = (ETX_OTA_COMMAND_*)buf; - 800069e: 687b ldr r3, [r7, #4] - 80006a0: 623b str r3, [r7, #32] + 80006aa: 687b ldr r3, [r7, #4] + 80006ac: 65bb str r3, [r7, #88] ; 0x58 if( cmd->packet_type == ETX_OTA_PACKET_TYPE_CMD ) - 80006a2: 6a3b ldr r3, [r7, #32] - 80006a4: 785b ldrb r3, [r3, #1] - 80006a6: 2b00 cmp r3, #0 - 80006a8: d104 bne.n 80006b4 + 80006ae: 6dbb ldr r3, [r7, #88] ; 0x58 + 80006b0: 785b ldrb r3, [r3, #1] + 80006b2: 2b00 cmp r3, #0 + 80006b4: d104 bne.n 80006c0 { if( cmd->cmd == ETX_OTA_CMD_ABORT ) - 80006aa: 6a3b ldr r3, [r7, #32] - 80006ac: 791b ldrb r3, [r3, #4] - 80006ae: 2b02 cmp r3, #2 - 80006b0: f000 8096 beq.w 80007e0 + 80006b6: 6dbb ldr r3, [r7, #88] ; 0x58 + 80006b8: 791b ldrb r3, [r3, #4] + 80006ba: 2b02 cmp r3, #2 + 80006bc: f000 81a8 beq.w 8000a10 //received OTA Abort command. Stop the process break; } } switch( ota_state ) - 80006b4: 4b52 ldr r3, [pc, #328] ; (8000800 ) - 80006b6: 781b ldrb r3, [r3, #0] - 80006b8: 2b04 cmp r3, #4 - 80006ba: f200 808b bhi.w 80007d4 - 80006be: a201 add r2, pc, #4 ; (adr r2, 80006c4 ) - 80006c0: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 80006c4: 080006d9 .word 0x080006d9 - 80006c8: 080006e7 .word 0x080006e7 - 80006cc: 0800070f .word 0x0800070f - 80006d0: 08000745 .word 0x08000745 - 80006d4: 080007ad .word 0x080007ad + 80006c0: 4bc1 ldr r3, [pc, #772] ; (80009c8 ) + 80006c2: 781b ldrb r3, [r3, #0] + 80006c4: 2b04 cmp r3, #4 + 80006c6: f200 8178 bhi.w 80009ba + 80006ca: a201 add r2, pc, #4 ; (adr r2, 80006d0 ) + 80006cc: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80006d0: 080006e5 .word 0x080006e5 + 80006d4: 080006f3 .word 0x080006f3 + 80006d8: 0800071f .word 0x0800071f + 80006dc: 0800076d .word 0x0800076d + 80006e0: 08000851 .word 0x08000851 { case ETX_OTA_STATE_IDLE: { printf("ETX_OTA_STATE_IDLE...\r\n"); - 80006d8: 484a ldr r0, [pc, #296] ; (8000804 ) - 80006da: f003 fa37 bl 8003b4c + 80006e4: 48b9 ldr r0, [pc, #740] ; (80009cc ) + 80006e6: f004 f887 bl 80047f8 ret = ETX_OTA_EX_OK; - 80006de: 2300 movs r3, #0 - 80006e0: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 80006ea: 2300 movs r3, #0 + 80006ec: f887 3067 strb.w r3, [r7, #103] ; 0x67 } break; - 80006e4: e085 b.n 80007f2 + 80006f0: e199 b.n 8000a26 case ETX_OTA_STATE_START: { ETX_OTA_COMMAND_ *cmd = (ETX_OTA_COMMAND_*)buf; - 80006e6: 687b ldr r3, [r7, #4] - 80006e8: 60fb str r3, [r7, #12] + 80006f2: 687b ldr r3, [r7, #4] + 80006f4: 643b str r3, [r7, #64] ; 0x40 if( cmd->packet_type == ETX_OTA_PACKET_TYPE_CMD ) - 80006ea: 68fb ldr r3, [r7, #12] - 80006ec: 785b ldrb r3, [r3, #1] - 80006ee: 2b00 cmp r3, #0 - 80006f0: d178 bne.n 80007e4 + 80006f6: 6c3b ldr r3, [r7, #64] ; 0x40 + 80006f8: 785b ldrb r3, [r3, #1] + 80006fa: 2b00 cmp r3, #0 + 80006fc: f040 818a bne.w 8000a14 { if( cmd->cmd == ETX_OTA_CMD_START ) - 80006f2: 68fb ldr r3, [r7, #12] - 80006f4: 791b ldrb r3, [r3, #4] - 80006f6: 2b00 cmp r3, #0 - 80006f8: d174 bne.n 80007e4 + 8000700: 6c3b ldr r3, [r7, #64] ; 0x40 + 8000702: 791b ldrb r3, [r3, #4] + 8000704: 2b00 cmp r3, #0 + 8000706: f040 8185 bne.w 8000a14 { printf("Received OTA START Command\r\n"); - 80006fa: 4843 ldr r0, [pc, #268] ; (8000808 ) - 80006fc: f003 fa26 bl 8003b4c + 800070a: 48b1 ldr r0, [pc, #708] ; (80009d0 ) + 800070c: f004 f874 bl 80047f8 ota_state = ETX_OTA_STATE_HEADER; - 8000700: 4b3f ldr r3, [pc, #252] ; (8000800 ) - 8000702: 2202 movs r2, #2 - 8000704: 701a strb r2, [r3, #0] + 8000710: 4bad ldr r3, [pc, #692] ; (80009c8 ) + 8000712: 2202 movs r2, #2 + 8000714: 701a strb r2, [r3, #0] ret = ETX_OTA_EX_OK; - 8000706: 2300 movs r3, #0 - 8000708: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8000716: 2300 movs r3, #0 + 8000718: f887 3067 strb.w r3, [r7, #103] ; 0x67 } } } break; - 800070c: e06a b.n 80007e4 + 800071c: e17a b.n 8000a14 case ETX_OTA_STATE_HEADER: { ETX_OTA_HEADER_ *header = (ETX_OTA_HEADER_*)buf; - 800070e: 687b ldr r3, [r7, #4] - 8000710: 613b str r3, [r7, #16] + 800071e: 687b ldr r3, [r7, #4] + 8000720: 647b str r3, [r7, #68] ; 0x44 if( header->packet_type == ETX_OTA_PACKET_TYPE_HEADER ) - 8000712: 693b ldr r3, [r7, #16] - 8000714: 785b ldrb r3, [r3, #1] - 8000716: 2b02 cmp r3, #2 - 8000718: d166 bne.n 80007e8 + 8000722: 6c7b ldr r3, [r7, #68] ; 0x44 + 8000724: 785b ldrb r3, [r3, #1] + 8000726: 2b02 cmp r3, #2 + 8000728: f040 8176 bne.w 8000a18 { ota_fw_total_size = header->meta_data.package_size; - 800071a: 693b ldr r3, [r7, #16] - 800071c: 685b ldr r3, [r3, #4] - 800071e: 4a3b ldr r2, [pc, #236] ; (800080c ) - 8000720: 6013 str r3, [r2, #0] + 800072c: 6c7b ldr r3, [r7, #68] ; 0x44 + 800072e: 685b ldr r3, [r3, #4] + 8000730: 4aa8 ldr r2, [pc, #672] ; (80009d4 ) + 8000732: 6013 str r3, [r2, #0] ota_fw_crc = header->meta_data.package_crc; - 8000722: 693b ldr r3, [r7, #16] - 8000724: 689b ldr r3, [r3, #8] - 8000726: 4a3a ldr r2, [pc, #232] ; (8000810 ) - 8000728: 6013 str r3, [r2, #0] + 8000734: 6c7b ldr r3, [r7, #68] ; 0x44 + 8000736: 689b ldr r3, [r3, #8] + 8000738: 4aa7 ldr r2, [pc, #668] ; (80009d8 ) + 800073a: 6013 str r3, [r2, #0] printf("Received OTA Header. FW Size = %ld\r\n", ota_fw_total_size); - 800072a: 4b38 ldr r3, [pc, #224] ; (800080c ) - 800072c: 681b ldr r3, [r3, #0] - 800072e: 4619 mov r1, r3 - 8000730: 4838 ldr r0, [pc, #224] ; (8000814 ) - 8000732: f003 f985 bl 8003a40 - ota_state = ETX_OTA_STATE_DATA; - 8000736: 4b32 ldr r3, [pc, #200] ; (8000800 ) - 8000738: 2203 movs r2, #3 - 800073a: 701a strb r2, [r3, #0] - ret = ETX_OTA_EX_OK; - 800073c: 2300 movs r3, #0 - 800073e: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 800073c: 4ba5 ldr r3, [pc, #660] ; (80009d4 ) + 800073e: 681b ldr r3, [r3, #0] + 8000740: 4619 mov r1, r3 + 8000742: 48a6 ldr r0, [pc, #664] ; (80009dc ) + 8000744: f003 ffd2 bl 80046ec + + //get the slot number + slot_num_to_write = get_available_slot_number(); + 8000748: f000 fb20 bl 8000d8c + 800074c: 4603 mov r3, r0 + 800074e: 461a mov r2, r3 + 8000750: 4ba3 ldr r3, [pc, #652] ; (80009e0 ) + 8000752: 701a strb r2, [r3, #0] + if( slot_num_to_write != 0xFF ) + 8000754: 4ba2 ldr r3, [pc, #648] ; (80009e0 ) + 8000756: 781b ldrb r3, [r3, #0] + 8000758: 2bff cmp r3, #255 ; 0xff + 800075a: f000 815d beq.w 8000a18 + { + ota_state = ETX_OTA_STATE_DATA; + 800075e: 4b9a ldr r3, [pc, #616] ; (80009c8 ) + 8000760: 2203 movs r2, #3 + 8000762: 701a strb r2, [r3, #0] + ret = ETX_OTA_EX_OK; + 8000764: 2300 movs r3, #0 + 8000766: f887 3067 strb.w r3, [r7, #103] ; 0x67 + } } } break; - 8000742: e051 b.n 80007e8 + 800076a: e155 b.n 8000a18 case ETX_OTA_STATE_DATA: { ETX_OTA_DATA_ *data = (ETX_OTA_DATA_*)buf; - 8000744: 687b ldr r3, [r7, #4] - 8000746: 61bb str r3, [r7, #24] + 800076c: 687b ldr r3, [r7, #4] + 800076e: 64fb str r3, [r7, #76] ; 0x4c uint16_t data_len = data->data_len; - 8000748: 69bb ldr r3, [r7, #24] - 800074a: 789a ldrb r2, [r3, #2] - 800074c: 78db ldrb r3, [r3, #3] - 800074e: 021b lsls r3, r3, #8 - 8000750: 4313 orrs r3, r2 - 8000752: 82fb strh r3, [r7, #22] + 8000770: 6cfb ldr r3, [r7, #76] ; 0x4c + 8000772: 789a ldrb r2, [r3, #2] + 8000774: 78db ldrb r3, [r3, #3] + 8000776: 021b lsls r3, r3, #8 + 8000778: 4313 orrs r3, r2 + 800077a: f8a7 304a strh.w r3, [r7, #74] ; 0x4a HAL_StatusTypeDef ex; if( data->packet_type == ETX_OTA_PACKET_TYPE_DATA ) - 8000754: 69bb ldr r3, [r7, #24] - 8000756: 785b ldrb r3, [r3, #1] - 8000758: 2b01 cmp r3, #1 - 800075a: d147 bne.n 80007ec + 800077e: 6cfb ldr r3, [r7, #76] ; 0x4c + 8000780: 785b ldrb r3, [r3, #1] + 8000782: 2b01 cmp r3, #1 + 8000784: f040 814a bne.w 8000a1c { + bool is_first_block = false; + 8000788: 2300 movs r3, #0 + 800078a: f887 3066 strb.w r3, [r7, #102] ; 0x66 + if( ota_fw_received_size == 0 ) + 800078e: 4b95 ldr r3, [pc, #596] ; (80009e4 ) + 8000790: 681b ldr r3, [r3, #0] + 8000792: 2b00 cmp r3, #0 + 8000794: d133 bne.n 80007fe + { + //This is the first block + is_first_block = true; + 8000796: 2301 movs r3, #1 + 8000798: f887 3066 strb.w r3, [r7, #102] ; 0x66 + + /* Read the configuration */ + ETX_GNRL_CFG_ cfg; + memcpy( &cfg, cfg_flash, sizeof(ETX_GNRL_CFG_) ); + 800079c: 4b92 ldr r3, [pc, #584] ; (80009e8 ) + 800079e: 681b ldr r3, [r3, #0] + 80007a0: 461c mov r4, r3 + 80007a2: f107 060c add.w r6, r7, #12 + 80007a6: f104 0c30 add.w ip, r4, #48 ; 0x30 + 80007aa: 4635 mov r5, r6 + 80007ac: 4623 mov r3, r4 + 80007ae: 6818 ldr r0, [r3, #0] + 80007b0: 6859 ldr r1, [r3, #4] + 80007b2: 689a ldr r2, [r3, #8] + 80007b4: 68db ldr r3, [r3, #12] + 80007b6: c50f stmia r5!, {r0, r1, r2, r3} + 80007b8: 3410 adds r4, #16 + 80007ba: 3610 adds r6, #16 + 80007bc: 4564 cmp r4, ip + 80007be: d1f4 bne.n 80007aa + 80007c0: 4632 mov r2, r6 + 80007c2: 4623 mov r3, r4 + 80007c4: 881b ldrh r3, [r3, #0] + 80007c6: 8013 strh r3, [r2, #0] + + /* Before writing the data, reset the available slot */ + cfg.slot_table[slot_num_to_write].is_this_slot_not_valid = 1u; + 80007c8: 4b85 ldr r3, [pc, #532] ; (80009e0 ) + 80007ca: 781b ldrb r3, [r3, #0] + 80007cc: 461a mov r2, r3 + 80007ce: 4613 mov r3, r2 + 80007d0: 005b lsls r3, r3, #1 + 80007d2: 4413 add r3, r2 + 80007d4: 00db lsls r3, r3, #3 + 80007d6: 1a9b subs r3, r3, r2 + 80007d8: f107 0268 add.w r2, r7, #104 ; 0x68 + 80007dc: 4413 add r3, r2 + 80007de: 3b58 subs r3, #88 ; 0x58 + 80007e0: 2201 movs r2, #1 + 80007e2: 701a strb r2, [r3, #0] + + /* write back the updated config */ + ret = write_cfg_to_flash( &cfg ); + 80007e4: f107 030c add.w r3, r7, #12 + 80007e8: 4618 mov r0, r3 + 80007ea: f000 fccf bl 800118c + 80007ee: 4603 mov r3, r0 + 80007f0: f887 3067 strb.w r3, [r7, #103] ; 0x67 + if( ret != ETX_OTA_EX_OK ) + 80007f4: f897 3067 ldrb.w r3, [r7, #103] ; 0x67 + 80007f8: 2b00 cmp r3, #0 + 80007fa: f040 8111 bne.w 8000a20 + break; + } + } + /* write the chunk to the Flash (App location) */ - ex = write_data_to_flash_app( buf, data_len, ( ota_fw_received_size == 0) ); - 800075c: 4b2e ldr r3, [pc, #184] ; (8000818 ) - 800075e: 681b ldr r3, [r3, #0] - 8000760: 2b00 cmp r3, #0 - 8000762: bf0c ite eq - 8000764: 2301 moveq r3, #1 - 8000766: 2300 movne r3, #0 - 8000768: b2da uxtb r2, r3 - 800076a: 8afb ldrh r3, [r7, #22] - 800076c: 4619 mov r1, r3 - 800076e: 6878 ldr r0, [r7, #4] - 8000770: f000 f93a bl 80009e8 - 8000774: 4603 mov r3, r0 - 8000776: 757b strb r3, [r7, #21] + ex = write_data_to_slot( slot_num_to_write, buf+4, data_len, is_first_block ); + 80007fe: 4b78 ldr r3, [pc, #480] ; (80009e0 ) + 8000800: 7818 ldrb r0, [r3, #0] + 8000802: 687b ldr r3, [r7, #4] + 8000804: 1d19 adds r1, r3, #4 + 8000806: f897 3066 ldrb.w r3, [r7, #102] ; 0x66 + 800080a: f8b7 204a ldrh.w r2, [r7, #74] ; 0x4a + 800080e: f000 fa25 bl 8000c5c + 8000812: 4603 mov r3, r0 + 8000814: f887 3049 strb.w r3, [r7, #73] ; 0x49 if( ex == HAL_OK ) - 8000778: 7d7b ldrb r3, [r7, #21] - 800077a: 2b00 cmp r3, #0 - 800077c: d136 bne.n 80007ec + 8000818: f897 3049 ldrb.w r3, [r7, #73] ; 0x49 + 800081c: 2b00 cmp r3, #0 + 800081e: f040 80fd bne.w 8000a1c { printf("[%ld/%ld]\r\n", ota_fw_received_size/ETX_OTA_DATA_MAX_SIZE, ota_fw_total_size/ETX_OTA_DATA_MAX_SIZE); - 800077e: 4b26 ldr r3, [pc, #152] ; (8000818 ) - 8000780: 681b ldr r3, [r3, #0] - 8000782: 0a99 lsrs r1, r3, #10 - 8000784: 4b21 ldr r3, [pc, #132] ; (800080c ) - 8000786: 681b ldr r3, [r3, #0] - 8000788: 0a9b lsrs r3, r3, #10 - 800078a: 461a mov r2, r3 - 800078c: 4823 ldr r0, [pc, #140] ; (800081c ) - 800078e: f003 f957 bl 8003a40 + 8000822: 4b70 ldr r3, [pc, #448] ; (80009e4 ) + 8000824: 681b ldr r3, [r3, #0] + 8000826: 0a99 lsrs r1, r3, #10 + 8000828: 4b6a ldr r3, [pc, #424] ; (80009d4 ) + 800082a: 681b ldr r3, [r3, #0] + 800082c: 0a9b lsrs r3, r3, #10 + 800082e: 461a mov r2, r3 + 8000830: 486e ldr r0, [pc, #440] ; (80009ec ) + 8000832: f003 ff5b bl 80046ec if( ota_fw_received_size >= ota_fw_total_size ) - 8000792: 4b21 ldr r3, [pc, #132] ; (8000818 ) - 8000794: 681a ldr r2, [r3, #0] - 8000796: 4b1d ldr r3, [pc, #116] ; (800080c ) - 8000798: 681b ldr r3, [r3, #0] - 800079a: 429a cmp r2, r3 - 800079c: d302 bcc.n 80007a4 + 8000836: 4b6b ldr r3, [pc, #428] ; (80009e4 ) + 8000838: 681a ldr r2, [r3, #0] + 800083a: 4b66 ldr r3, [pc, #408] ; (80009d4 ) + 800083c: 681b ldr r3, [r3, #0] + 800083e: 429a cmp r2, r3 + 8000840: d302 bcc.n 8000848 { //received the full data. So, move to end ota_state = ETX_OTA_STATE_END; - 800079e: 4b18 ldr r3, [pc, #96] ; (8000800 ) - 80007a0: 2204 movs r2, #4 - 80007a2: 701a strb r2, [r3, #0] + 8000842: 4b61 ldr r3, [pc, #388] ; (80009c8 ) + 8000844: 2204 movs r2, #4 + 8000846: 701a strb r2, [r3, #0] } ret = ETX_OTA_EX_OK; - 80007a4: 2300 movs r3, #0 - 80007a6: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8000848: 2300 movs r3, #0 + 800084a: f887 3067 strb.w r3, [r7, #103] ; 0x67 } } } break; - 80007aa: e01f b.n 80007ec + 800084e: e0e5 b.n 8000a1c case ETX_OTA_STATE_END: { ETX_OTA_COMMAND_ *cmd = (ETX_OTA_COMMAND_*)buf; - 80007ac: 687b ldr r3, [r7, #4] - 80007ae: 61fb str r3, [r7, #28] + 8000850: 687b ldr r3, [r7, #4] + 8000852: 657b str r3, [r7, #84] ; 0x54 if( cmd->packet_type == ETX_OTA_PACKET_TYPE_CMD ) - 80007b0: 69fb ldr r3, [r7, #28] - 80007b2: 785b ldrb r3, [r3, #1] - 80007b4: 2b00 cmp r3, #0 - 80007b6: d11b bne.n 80007f0 + 8000854: 6d7b ldr r3, [r7, #84] ; 0x54 + 8000856: 785b ldrb r3, [r3, #1] + 8000858: 2b00 cmp r3, #0 + 800085a: f040 80e3 bne.w 8000a24 { if( cmd->cmd == ETX_OTA_CMD_END ) - 80007b8: 69fb ldr r3, [r7, #28] - 80007ba: 791b ldrb r3, [r3, #4] - 80007bc: 2b01 cmp r3, #1 - 80007be: d117 bne.n 80007f0 + 800085e: 6d7b ldr r3, [r7, #84] ; 0x54 + 8000860: 791b ldrb r3, [r3, #4] + 8000862: 2b01 cmp r3, #1 + 8000864: f040 80de bne.w 8000a24 { printf("Received OTA END Command\r\n"); - 80007c0: 4817 ldr r0, [pc, #92] ; (8000820 ) - 80007c2: f003 f9c3 bl 8003b4c + 8000868: 4861 ldr r0, [pc, #388] ; (80009f0 ) + 800086a: f003 ffc5 bl 80047f8 + + printf("Validating the received Binary...\r\n"); + 800086e: 4861 ldr r0, [pc, #388] ; (80009f4 ) + 8000870: f003 ffc2 bl 80047f8 + + uint32_t slot_addr; + if( slot_num_to_write == 0u ) + 8000874: 4b5a ldr r3, [pc, #360] ; (80009e0 ) + 8000876: 781b ldrb r3, [r3, #0] + 8000878: 2b00 cmp r3, #0 + 800087a: d102 bne.n 8000882 + { + slot_addr = ETX_APP_SLOT0_FLASH_ADDR; + 800087c: 4b5e ldr r3, [pc, #376] ; (80009f8 ) + 800087e: 663b str r3, [r7, #96] ; 0x60 + 8000880: e001 b.n 8000886 + } + else + { + slot_addr = ETX_APP_SLOT1_FLASH_ADDR; + 8000882: 4b5e ldr r3, [pc, #376] ; (80009fc ) + 8000884: 663b str r3, [r7, #96] ; 0x60 + } - //TODO: Very full package CRC + //Calculate and verify the CRC + uint32_t cal_crc = HAL_CRC_Calculate( &hcrc, (uint32_t*)slot_addr, ota_fw_total_size); + 8000886: 6e3b ldr r3, [r7, #96] ; 0x60 + 8000888: 4a52 ldr r2, [pc, #328] ; (80009d4 ) + 800088a: 6812 ldr r2, [r2, #0] + 800088c: 4619 mov r1, r3 + 800088e: 485c ldr r0, [pc, #368] ; (8000a00 ) + 8000890: f001 fa9e bl 8001dd0 + 8000894: 6538 str r0, [r7, #80] ; 0x50 + if( cal_crc != ota_fw_crc ) + 8000896: 4b50 ldr r3, [pc, #320] ; (80009d8 ) + 8000898: 681b ldr r3, [r3, #0] + 800089a: 6d3a ldr r2, [r7, #80] ; 0x50 + 800089c: 429a cmp r2, r3 + 800089e: d003 beq.n 80008a8 + { + printf("ERROR: FW CRC Mismatch\r\n"); + 80008a0: 4858 ldr r0, [pc, #352] ; (8000a04 ) + 80008a2: f003 ffa9 bl 80047f8 + 80008a6: e0be b.n 8000a26 + break; + } + printf("Done!!!\r\n"); + 80008a8: 4857 ldr r0, [pc, #348] ; (8000a08 ) + 80008aa: f003 ffa5 bl 80047f8 + + /* Read the configuration */ + ETX_GNRL_CFG_ cfg; + memcpy( &cfg, cfg_flash, sizeof(ETX_GNRL_CFG_) ); + 80008ae: 4b4e ldr r3, [pc, #312] ; (80009e8 ) + 80008b0: 681b ldr r3, [r3, #0] + 80008b2: 461c mov r4, r3 + 80008b4: f107 060c add.w r6, r7, #12 + 80008b8: f104 0c30 add.w ip, r4, #48 ; 0x30 + 80008bc: 4635 mov r5, r6 + 80008be: 4623 mov r3, r4 + 80008c0: 6818 ldr r0, [r3, #0] + 80008c2: 6859 ldr r1, [r3, #4] + 80008c4: 689a ldr r2, [r3, #8] + 80008c6: 68db ldr r3, [r3, #12] + 80008c8: c50f stmia r5!, {r0, r1, r2, r3} + 80008ca: 3410 adds r4, #16 + 80008cc: 3610 adds r6, #16 + 80008ce: 4564 cmp r4, ip + 80008d0: d1f4 bne.n 80008bc + 80008d2: 4632 mov r2, r6 + 80008d4: 4623 mov r3, r4 + 80008d6: 881b ldrh r3, [r3, #0] + 80008d8: 8013 strh r3, [r2, #0] + + //update the slot + cfg.slot_table[slot_num_to_write].fw_crc = cal_crc; + 80008da: 4b41 ldr r3, [pc, #260] ; (80009e0 ) + 80008dc: 781b ldrb r3, [r3, #0] + 80008de: 461a mov r2, r3 + 80008e0: 4613 mov r3, r2 + 80008e2: 005b lsls r3, r3, #1 + 80008e4: 4413 add r3, r2 + 80008e6: 00db lsls r3, r3, #3 + 80008e8: 1a9b subs r3, r3, r2 + 80008ea: f107 0268 add.w r2, r7, #104 ; 0x68 + 80008ee: 4413 add r3, r2 + 80008f0: 3b5c subs r3, #92 ; 0x5c + 80008f2: 6d3a ldr r2, [r7, #80] ; 0x50 + 80008f4: f8c3 200b str.w r2, [r3, #11] + cfg.slot_table[slot_num_to_write].fw_size = ota_fw_total_size; + 80008f8: 4b39 ldr r3, [pc, #228] ; (80009e0 ) + 80008fa: 781b ldrb r3, [r3, #0] + 80008fc: 461a mov r2, r3 + 80008fe: 4b35 ldr r3, [pc, #212] ; (80009d4 ) + 8000900: 6819 ldr r1, [r3, #0] + 8000902: 4613 mov r3, r2 + 8000904: 005b lsls r3, r3, #1 + 8000906: 4413 add r3, r2 + 8000908: 00db lsls r3, r3, #3 + 800090a: 1a9b subs r3, r3, r2 + 800090c: f107 0268 add.w r2, r7, #104 ; 0x68 + 8000910: 4413 add r3, r2 + 8000912: 3b5c subs r3, #92 ; 0x5c + 8000914: f8c3 1007 str.w r1, [r3, #7] + cfg.slot_table[slot_num_to_write].is_this_slot_not_valid = 0u; + 8000918: 4b31 ldr r3, [pc, #196] ; (80009e0 ) + 800091a: 781b ldrb r3, [r3, #0] + 800091c: 461a mov r2, r3 + 800091e: 4613 mov r3, r2 + 8000920: 005b lsls r3, r3, #1 + 8000922: 4413 add r3, r2 + 8000924: 00db lsls r3, r3, #3 + 8000926: 1a9b subs r3, r3, r2 + 8000928: f107 0268 add.w r2, r7, #104 ; 0x68 + 800092c: 4413 add r3, r2 + 800092e: 3b58 subs r3, #88 ; 0x58 + 8000930: 2200 movs r2, #0 + 8000932: 701a strb r2, [r3, #0] + cfg.slot_table[slot_num_to_write].should_we_run_this_fw = 1u; + 8000934: 4b2a ldr r3, [pc, #168] ; (80009e0 ) + 8000936: 781b ldrb r3, [r3, #0] + 8000938: 461a mov r2, r3 + 800093a: 4613 mov r3, r2 + 800093c: 005b lsls r3, r3, #1 + 800093e: 4413 add r3, r2 + 8000940: 00db lsls r3, r3, #3 + 8000942: 1a9b subs r3, r3, r2 + 8000944: f107 0268 add.w r2, r7, #104 ; 0x68 + 8000948: 4413 add r3, r2 + 800094a: 3b56 subs r3, #86 ; 0x56 + 800094c: 2201 movs r2, #1 + 800094e: 701a strb r2, [r3, #0] + + //reset other slots + for( uint8_t i = 0; i < ETX_NO_OF_SLOTS; i++ ) + 8000950: 2300 movs r3, #0 + 8000952: f887 305f strb.w r3, [r7, #95] ; 0x5f + 8000956: e017 b.n 8000988 + { + if( slot_num_to_write != i ) + 8000958: 4b21 ldr r3, [pc, #132] ; (80009e0 ) + 800095a: 781b ldrb r3, [r3, #0] + 800095c: f897 205f ldrb.w r2, [r7, #95] ; 0x5f + 8000960: 429a cmp r2, r3 + 8000962: d00c beq.n 800097e + { + //update the slot as inactive + cfg.slot_table[i].should_we_run_this_fw = 0u; + 8000964: f897 205f ldrb.w r2, [r7, #95] ; 0x5f + 8000968: 4613 mov r3, r2 + 800096a: 005b lsls r3, r3, #1 + 800096c: 4413 add r3, r2 + 800096e: 00db lsls r3, r3, #3 + 8000970: 1a9b subs r3, r3, r2 + 8000972: f107 0268 add.w r2, r7, #104 ; 0x68 + 8000976: 4413 add r3, r2 + 8000978: 3b56 subs r3, #86 ; 0x56 + 800097a: 2200 movs r2, #0 + 800097c: 701a strb r2, [r3, #0] + for( uint8_t i = 0; i < ETX_NO_OF_SLOTS; i++ ) + 800097e: f897 305f ldrb.w r3, [r7, #95] ; 0x5f + 8000982: 3301 adds r3, #1 + 8000984: f887 305f strb.w r3, [r7, #95] ; 0x5f + 8000988: f897 305f ldrb.w r3, [r7, #95] ; 0x5f + 800098c: 2b01 cmp r3, #1 + 800098e: d9e3 bls.n 8000958 + } + } - ota_state = ETX_OTA_STATE_IDLE; - 80007c6: 4b0e ldr r3, [pc, #56] ; (8000800 ) - 80007c8: 2200 movs r2, #0 - 80007ca: 701a strb r2, [r3, #0] - ret = ETX_OTA_EX_OK; - 80007cc: 2300 movs r3, #0 - 80007ce: f887 3027 strb.w r3, [r7, #39] ; 0x27 + //update the reboot reason + cfg.reboot_cause = ETX_NORMAL_BOOT; + 8000990: 4b1e ldr r3, [pc, #120] ; (8000a0c ) + 8000992: 60fb str r3, [r7, #12] + + /* write back the updated config */ + ret = write_cfg_to_flash( &cfg ); + 8000994: f107 030c add.w r3, r7, #12 + 8000998: 4618 mov r0, r3 + 800099a: f000 fbf7 bl 800118c + 800099e: 4603 mov r3, r0 + 80009a0: f887 3067 strb.w r3, [r7, #103] ; 0x67 + if( ret == ETX_OTA_EX_OK ) + 80009a4: f897 3067 ldrb.w r3, [r7, #103] ; 0x67 + 80009a8: 2b00 cmp r3, #0 + 80009aa: d13b bne.n 8000a24 + { + ota_state = ETX_OTA_STATE_IDLE; + 80009ac: 4b06 ldr r3, [pc, #24] ; (80009c8 ) + 80009ae: 2200 movs r2, #0 + 80009b0: 701a strb r2, [r3, #0] + ret = ETX_OTA_EX_OK; + 80009b2: 2300 movs r3, #0 + 80009b4: f887 3067 strb.w r3, [r7, #103] ; 0x67 + } } } } break; - 80007d2: e00d b.n 80007f0 + 80009b8: e034 b.n 8000a24 default: { /* Should not come here */ ret = ETX_OTA_EX_ERR; - 80007d4: 2301 movs r3, #1 - 80007d6: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 80009ba: 2301 movs r3, #1 + 80009bc: f887 3067 strb.w r3, [r7, #103] ; 0x67 } break; - 80007da: e00a b.n 80007f2 + 80009c0: e031 b.n 8000a26 }; - 80007dc: bf00 nop - 80007de: e008 b.n 80007f2 + 80009c2: bf00 nop + 80009c4: e02f b.n 8000a26 + 80009c6: bf00 nop + 80009c8: 20000499 .word 0x20000499 + 80009cc: 080056cc .word 0x080056cc + 80009d0: 080056e4 .word 0x080056e4 + 80009d4: 2000049c .word 0x2000049c + 80009d8: 200004a0 .word 0x200004a0 + 80009dc: 08005700 .word 0x08005700 + 80009e0: 200004a8 .word 0x200004a8 + 80009e4: 200004a4 .word 0x200004a4 + 80009e8: 20000000 .word 0x20000000 + 80009ec: 08005728 .word 0x08005728 + 80009f0: 08005734 .word 0x08005734 + 80009f4: 08005750 .word 0x08005750 + 80009f8: 080c0000 .word 0x080c0000 + 80009fc: 08140000 .word 0x08140000 + 8000a00: 2000053c .word 0x2000053c + 8000a04: 08005774 .word 0x08005774 + 8000a08: 0800578c .word 0x0800578c + 8000a0c: beeffeed .word 0xbeeffeed break; - 80007e0: bf00 nop - 80007e2: e006 b.n 80007f2 + 8000a10: bf00 nop + 8000a12: e008 b.n 8000a26 break; - 80007e4: bf00 nop - 80007e6: e004 b.n 80007f2 + 8000a14: bf00 nop + 8000a16: e006 b.n 8000a26 break; - 80007e8: bf00 nop - 80007ea: e002 b.n 80007f2 + 8000a18: bf00 nop + 8000a1a: e004 b.n 8000a26 break; - 80007ec: bf00 nop - 80007ee: e000 b.n 80007f2 + 8000a1c: bf00 nop + 8000a1e: e002 b.n 8000a26 + break; + 8000a20: bf00 nop + 8000a22: e000 b.n 8000a26 break; - 80007f0: bf00 nop + 8000a24: bf00 nop }while( false ); return ret; - 80007f2: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8000a26: f897 3067 ldrb.w r3, [r7, #103] ; 0x67 } - 80007f6: 4618 mov r0, r3 - 80007f8: 3728 adds r7, #40 ; 0x28 - 80007fa: 46bd mov sp, r7 - 80007fc: bd80 pop {r7, pc} - 80007fe: bf00 nop - 8000800: 20000495 .word 0x20000495 - 8000804: 08004a20 .word 0x08004a20 - 8000808: 08004a38 .word 0x08004a38 - 800080c: 20000498 .word 0x20000498 - 8000810: 2000049c .word 0x2000049c - 8000814: 08004a54 .word 0x08004a54 - 8000818: 200004a0 .word 0x200004a0 - 800081c: 08004a7c .word 0x08004a7c - 8000820: 08004a88 .word 0x08004a88 - -08000824 : + 8000a2a: 4618 mov r0, r3 + 8000a2c: 376c adds r7, #108 ; 0x6c + 8000a2e: 46bd mov sp, r7 + 8000a30: bdf0 pop {r4, r5, r6, r7, pc} + 8000a32: bf00 nop + +08000a34 : * @param buf buffer to store the received data * @param max_len maximum length to receive * @retval ETX_OTA_EX_ */ static uint16_t etx_receive_chunk( uint8_t *buf, uint16_t max_len ) { - 8000824: b580 push {r7, lr} - 8000826: b084 sub sp, #16 - 8000828: af00 add r7, sp, #0 - 800082a: 6078 str r0, [r7, #4] - 800082c: 460b mov r3, r1 - 800082e: 807b strh r3, [r7, #2] + 8000a34: b580 push {r7, lr} + 8000a36: b088 sub sp, #32 + 8000a38: af00 add r7, sp, #0 + 8000a3a: 6078 str r0, [r7, #4] + 8000a3c: 460b mov r3, r1 + 8000a3e: 807b strh r3, [r7, #2] int16_t ret; - uint16_t index = 0u; - 8000830: 2300 movs r3, #0 - 8000832: 81bb strh r3, [r7, #12] + uint16_t index = 0u; + 8000a40: 2300 movs r3, #0 + 8000a42: 83bb strh r3, [r7, #28] uint16_t data_len; + uint32_t cal_data_crc = 0u; + 8000a44: 2300 movs r3, #0 + 8000a46: 617b str r3, [r7, #20] + uint32_t rec_data_crc = 0u; + 8000a48: 2300 movs r3, #0 + 8000a4a: 613b str r3, [r7, #16] do { //receive SOF byte (1byte) ret = HAL_UART_Receive( &huart2, &buf[index], 1, HAL_MAX_DELAY ); - 8000834: 89bb ldrh r3, [r7, #12] - 8000836: 687a ldr r2, [r7, #4] - 8000838: 18d1 adds r1, r2, r3 - 800083a: f04f 33ff mov.w r3, #4294967295 - 800083e: 2201 movs r2, #1 - 8000840: 4854 ldr r0, [pc, #336] ; (8000994 ) - 8000842: f002 fc30 bl 80030a6 - 8000846: 4603 mov r3, r0 - 8000848: 81fb strh r3, [r7, #14] + 8000a4c: 8bbb ldrh r3, [r7, #28] + 8000a4e: 687a ldr r2, [r7, #4] + 8000a50: 18d1 adds r1, r2, r3 + 8000a52: f04f 33ff mov.w r3, #4294967295 + 8000a56: 2201 movs r2, #1 + 8000a58: 4864 ldr r0, [pc, #400] ; (8000bec ) + 8000a5a: f003 f97a bl 8003d52 + 8000a5e: 4603 mov r3, r0 + 8000a60: 83fb strh r3, [r7, #30] if( ret != HAL_OK ) - 800084a: f9b7 300e ldrsh.w r3, [r7, #14] - 800084e: 2b00 cmp r3, #0 - 8000850: d17f bne.n 8000952 + 8000a62: f9b7 301e ldrsh.w r3, [r7, #30] + 8000a66: 2b00 cmp r3, #0 + 8000a68: f040 809e bne.w 8000ba8 { break; } if( buf[index++] != ETX_OTA_SOF ) - 8000852: 89bb ldrh r3, [r7, #12] - 8000854: 1c5a adds r2, r3, #1 - 8000856: 81ba strh r2, [r7, #12] - 8000858: 461a mov r2, r3 - 800085a: 687b ldr r3, [r7, #4] - 800085c: 4413 add r3, r2 - 800085e: 781b ldrb r3, [r3, #0] - 8000860: 2baa cmp r3, #170 ; 0xaa - 8000862: d002 beq.n 800086a + 8000a6c: 8bbb ldrh r3, [r7, #28] + 8000a6e: 1c5a adds r2, r3, #1 + 8000a70: 83ba strh r2, [r7, #28] + 8000a72: 461a mov r2, r3 + 8000a74: 687b ldr r3, [r7, #4] + 8000a76: 4413 add r3, r2 + 8000a78: 781b ldrb r3, [r3, #0] + 8000a7a: 2baa cmp r3, #170 ; 0xaa + 8000a7c: d002 beq.n 8000a84 { //Not received start of frame ret = ETX_OTA_EX_ERR; - 8000864: 2301 movs r3, #1 - 8000866: 81fb strh r3, [r7, #14] + 8000a7e: 2301 movs r3, #1 + 8000a80: 83fb strh r3, [r7, #30] break; - 8000868: e07c b.n 8000964 + 8000a82: e09c b.n 8000bbe } //Receive the packet type (1byte). ret = HAL_UART_Receive( &huart2, &buf[index++], 1, HAL_MAX_DELAY ); - 800086a: 89bb ldrh r3, [r7, #12] - 800086c: 1c5a adds r2, r3, #1 - 800086e: 81ba strh r2, [r7, #12] - 8000870: 461a mov r2, r3 - 8000872: 687b ldr r3, [r7, #4] - 8000874: 1899 adds r1, r3, r2 - 8000876: f04f 33ff mov.w r3, #4294967295 - 800087a: 2201 movs r2, #1 - 800087c: 4845 ldr r0, [pc, #276] ; (8000994 ) - 800087e: f002 fc12 bl 80030a6 - 8000882: 4603 mov r3, r0 - 8000884: 81fb strh r3, [r7, #14] + 8000a84: 8bbb ldrh r3, [r7, #28] + 8000a86: 1c5a adds r2, r3, #1 + 8000a88: 83ba strh r2, [r7, #28] + 8000a8a: 461a mov r2, r3 + 8000a8c: 687b ldr r3, [r7, #4] + 8000a8e: 1899 adds r1, r3, r2 + 8000a90: f04f 33ff mov.w r3, #4294967295 + 8000a94: 2201 movs r2, #1 + 8000a96: 4855 ldr r0, [pc, #340] ; (8000bec ) + 8000a98: f003 f95b bl 8003d52 + 8000a9c: 4603 mov r3, r0 + 8000a9e: 83fb strh r3, [r7, #30] if( ret != HAL_OK ) - 8000886: f9b7 300e ldrsh.w r3, [r7, #14] - 800088a: 2b00 cmp r3, #0 - 800088c: d163 bne.n 8000956 + 8000aa0: f9b7 301e ldrsh.w r3, [r7, #30] + 8000aa4: 2b00 cmp r3, #0 + 8000aa6: f040 8081 bne.w 8000bac { break; } //Get the data length (2bytes). ret = HAL_UART_Receive( &huart2, &buf[index], 2, HAL_MAX_DELAY ); - 800088e: 89bb ldrh r3, [r7, #12] - 8000890: 687a ldr r2, [r7, #4] - 8000892: 18d1 adds r1, r2, r3 - 8000894: f04f 33ff mov.w r3, #4294967295 - 8000898: 2202 movs r2, #2 - 800089a: 483e ldr r0, [pc, #248] ; (8000994 ) - 800089c: f002 fc03 bl 80030a6 - 80008a0: 4603 mov r3, r0 - 80008a2: 81fb strh r3, [r7, #14] + 8000aaa: 8bbb ldrh r3, [r7, #28] + 8000aac: 687a ldr r2, [r7, #4] + 8000aae: 18d1 adds r1, r2, r3 + 8000ab0: f04f 33ff mov.w r3, #4294967295 + 8000ab4: 2202 movs r2, #2 + 8000ab6: 484d ldr r0, [pc, #308] ; (8000bec ) + 8000ab8: f003 f94b bl 8003d52 + 8000abc: 4603 mov r3, r0 + 8000abe: 83fb strh r3, [r7, #30] if( ret != HAL_OK ) - 80008a4: f9b7 300e ldrsh.w r3, [r7, #14] - 80008a8: 2b00 cmp r3, #0 - 80008aa: d156 bne.n 800095a + 8000ac0: f9b7 301e ldrsh.w r3, [r7, #30] + 8000ac4: 2b00 cmp r3, #0 + 8000ac6: d173 bne.n 8000bb0 { break; } data_len = *(uint16_t *)&buf[index]; - 80008ac: 89bb ldrh r3, [r7, #12] - 80008ae: 687a ldr r2, [r7, #4] - 80008b0: 4413 add r3, r2 - 80008b2: 881b ldrh r3, [r3, #0] - 80008b4: 813b strh r3, [r7, #8] + 8000ac8: 8bbb ldrh r3, [r7, #28] + 8000aca: 687a ldr r2, [r7, #4] + 8000acc: 4413 add r3, r2 + 8000ace: 881b ldrh r3, [r3, #0] + 8000ad0: 81fb strh r3, [r7, #14] index += 2u; - 80008b6: 89bb ldrh r3, [r7, #12] - 80008b8: 3302 adds r3, #2 - 80008ba: 81bb strh r3, [r7, #12] + 8000ad2: 8bbb ldrh r3, [r7, #28] + 8000ad4: 3302 adds r3, #2 + 8000ad6: 83bb strh r3, [r7, #28] for( uint16_t i = 0u; i < data_len; i++ ) - 80008bc: 2300 movs r3, #0 - 80008be: 817b strh r3, [r7, #10] - 80008c0: e014 b.n 80008ec + 8000ad8: 2300 movs r3, #0 + 8000ada: 837b strh r3, [r7, #26] + 8000adc: e014 b.n 8000b08 { ret = HAL_UART_Receive( &huart2, &buf[index++], 1, HAL_MAX_DELAY ); - 80008c2: 89bb ldrh r3, [r7, #12] - 80008c4: 1c5a adds r2, r3, #1 - 80008c6: 81ba strh r2, [r7, #12] - 80008c8: 461a mov r2, r3 - 80008ca: 687b ldr r3, [r7, #4] - 80008cc: 1899 adds r1, r3, r2 - 80008ce: f04f 33ff mov.w r3, #4294967295 - 80008d2: 2201 movs r2, #1 - 80008d4: 482f ldr r0, [pc, #188] ; (8000994 ) - 80008d6: f002 fbe6 bl 80030a6 - 80008da: 4603 mov r3, r0 - 80008dc: 81fb strh r3, [r7, #14] + 8000ade: 8bbb ldrh r3, [r7, #28] + 8000ae0: 1c5a adds r2, r3, #1 + 8000ae2: 83ba strh r2, [r7, #28] + 8000ae4: 461a mov r2, r3 + 8000ae6: 687b ldr r3, [r7, #4] + 8000ae8: 1899 adds r1, r3, r2 + 8000aea: f04f 33ff mov.w r3, #4294967295 + 8000aee: 2201 movs r2, #1 + 8000af0: 483e ldr r0, [pc, #248] ; (8000bec ) + 8000af2: f003 f92e bl 8003d52 + 8000af6: 4603 mov r3, r0 + 8000af8: 83fb strh r3, [r7, #30] if( ret != HAL_OK ) - 80008de: f9b7 300e ldrsh.w r3, [r7, #14] - 80008e2: 2b00 cmp r3, #0 - 80008e4: d107 bne.n 80008f6 + 8000afa: f9b7 301e ldrsh.w r3, [r7, #30] + 8000afe: 2b00 cmp r3, #0 + 8000b00: d107 bne.n 8000b12 for( uint16_t i = 0u; i < data_len; i++ ) - 80008e6: 897b ldrh r3, [r7, #10] - 80008e8: 3301 adds r3, #1 - 80008ea: 817b strh r3, [r7, #10] - 80008ec: 897a ldrh r2, [r7, #10] - 80008ee: 893b ldrh r3, [r7, #8] - 80008f0: 429a cmp r2, r3 - 80008f2: d3e6 bcc.n 80008c2 - 80008f4: e000 b.n 80008f8 + 8000b02: 8b7b ldrh r3, [r7, #26] + 8000b04: 3301 adds r3, #1 + 8000b06: 837b strh r3, [r7, #26] + 8000b08: 8b7a ldrh r2, [r7, #26] + 8000b0a: 89fb ldrh r3, [r7, #14] + 8000b0c: 429a cmp r2, r3 + 8000b0e: d3e6 bcc.n 8000ade + 8000b10: e000 b.n 8000b14 { break; - 80008f6: bf00 nop + 8000b12: bf00 nop } } + if( ret != HAL_OK ) + 8000b14: f9b7 301e ldrsh.w r3, [r7, #30] + 8000b18: 2b00 cmp r3, #0 + 8000b1a: d14b bne.n 8000bb4 + { + break; + } + //Get the CRC. ret = HAL_UART_Receive( &huart2, &buf[index], 4, HAL_MAX_DELAY ); - 80008f8: 89bb ldrh r3, [r7, #12] - 80008fa: 687a ldr r2, [r7, #4] - 80008fc: 18d1 adds r1, r2, r3 - 80008fe: f04f 33ff mov.w r3, #4294967295 - 8000902: 2204 movs r2, #4 - 8000904: 4823 ldr r0, [pc, #140] ; (8000994 ) - 8000906: f002 fbce bl 80030a6 - 800090a: 4603 mov r3, r0 - 800090c: 81fb strh r3, [r7, #14] + 8000b1c: 8bbb ldrh r3, [r7, #28] + 8000b1e: 687a ldr r2, [r7, #4] + 8000b20: 18d1 adds r1, r2, r3 + 8000b22: f04f 33ff mov.w r3, #4294967295 + 8000b26: 2204 movs r2, #4 + 8000b28: 4830 ldr r0, [pc, #192] ; (8000bec ) + 8000b2a: f003 f912 bl 8003d52 + 8000b2e: 4603 mov r3, r0 + 8000b30: 83fb strh r3, [r7, #30] if( ret != HAL_OK ) - 800090e: f9b7 300e ldrsh.w r3, [r7, #14] - 8000912: 2b00 cmp r3, #0 - 8000914: d123 bne.n 800095e + 8000b32: f9b7 301e ldrsh.w r3, [r7, #30] + 8000b36: 2b00 cmp r3, #0 + 8000b38: d13e bne.n 8000bb8 { break; } + rec_data_crc = *(uint32_t *)&buf[index]; + 8000b3a: 8bbb ldrh r3, [r7, #28] + 8000b3c: 687a ldr r2, [r7, #4] + 8000b3e: 4413 add r3, r2 + 8000b40: 681b ldr r3, [r3, #0] + 8000b42: 613b str r3, [r7, #16] index += 4u; - 8000916: 89bb ldrh r3, [r7, #12] - 8000918: 3304 adds r3, #4 - 800091a: 81bb strh r3, [r7, #12] - - //TODO: Add CRC verification + 8000b44: 8bbb ldrh r3, [r7, #28] + 8000b46: 3304 adds r3, #4 + 8000b48: 83bb strh r3, [r7, #28] //receive EOF byte (1byte) ret = HAL_UART_Receive( &huart2, &buf[index], 1, HAL_MAX_DELAY ); - 800091c: 89bb ldrh r3, [r7, #12] - 800091e: 687a ldr r2, [r7, #4] - 8000920: 18d1 adds r1, r2, r3 - 8000922: f04f 33ff mov.w r3, #4294967295 - 8000926: 2201 movs r2, #1 - 8000928: 481a ldr r0, [pc, #104] ; (8000994 ) - 800092a: f002 fbbc bl 80030a6 - 800092e: 4603 mov r3, r0 - 8000930: 81fb strh r3, [r7, #14] + 8000b4a: 8bbb ldrh r3, [r7, #28] + 8000b4c: 687a ldr r2, [r7, #4] + 8000b4e: 18d1 adds r1, r2, r3 + 8000b50: f04f 33ff mov.w r3, #4294967295 + 8000b54: 2201 movs r2, #1 + 8000b56: 4825 ldr r0, [pc, #148] ; (8000bec ) + 8000b58: f003 f8fb bl 8003d52 + 8000b5c: 4603 mov r3, r0 + 8000b5e: 83fb strh r3, [r7, #30] if( ret != HAL_OK ) - 8000932: f9b7 300e ldrsh.w r3, [r7, #14] - 8000936: 2b00 cmp r3, #0 - 8000938: d113 bne.n 8000962 + 8000b60: f9b7 301e ldrsh.w r3, [r7, #30] + 8000b64: 2b00 cmp r3, #0 + 8000b66: d129 bne.n 8000bbc { break; } if( buf[index++] != ETX_OTA_EOF ) - 800093a: 89bb ldrh r3, [r7, #12] - 800093c: 1c5a adds r2, r3, #1 - 800093e: 81ba strh r2, [r7, #12] - 8000940: 461a mov r2, r3 - 8000942: 687b ldr r3, [r7, #4] - 8000944: 4413 add r3, r2 - 8000946: 781b ldrb r3, [r3, #0] - 8000948: 2bbb cmp r3, #187 ; 0xbb - 800094a: d00b beq.n 8000964 + 8000b68: 8bbb ldrh r3, [r7, #28] + 8000b6a: 1c5a adds r2, r3, #1 + 8000b6c: 83ba strh r2, [r7, #28] + 8000b6e: 461a mov r2, r3 + 8000b70: 687b ldr r3, [r7, #4] + 8000b72: 4413 add r3, r2 + 8000b74: 781b ldrb r3, [r3, #0] + 8000b76: 2bbb cmp r3, #187 ; 0xbb + 8000b78: d002 beq.n 8000b80 { //Not received end of frame ret = ETX_OTA_EX_ERR; - 800094c: 2301 movs r3, #1 - 800094e: 81fb strh r3, [r7, #14] + 8000b7a: 2301 movs r3, #1 + 8000b7c: 83fb strh r3, [r7, #30] + break; + 8000b7e: e01e b.n 8000bbe + } + + //Calculate the received data's CRC + cal_data_crc = HAL_CRC_Calculate( &hcrc, (uint32_t*)&buf[4], data_len); + 8000b80: 687b ldr r3, [r7, #4] + 8000b82: 3304 adds r3, #4 + 8000b84: 89fa ldrh r2, [r7, #14] + 8000b86: 4619 mov r1, r3 + 8000b88: 4819 ldr r0, [pc, #100] ; (8000bf0 ) + 8000b8a: f001 f921 bl 8001dd0 + 8000b8e: 6178 str r0, [r7, #20] + + //Verify the CRC + if( cal_data_crc != rec_data_crc ) + 8000b90: 697a ldr r2, [r7, #20] + 8000b92: 693b ldr r3, [r7, #16] + 8000b94: 429a cmp r2, r3 + 8000b96: d012 beq.n 8000bbe + { + printf("Chunk's CRC mismatch [Cal CRC = 0x%08lX] [Rec CRC = 0x%08lX]\r\n", + 8000b98: 693a ldr r2, [r7, #16] + 8000b9a: 6979 ldr r1, [r7, #20] + 8000b9c: 4815 ldr r0, [pc, #84] ; (8000bf4 ) + 8000b9e: f003 fda5 bl 80046ec + cal_data_crc, rec_data_crc ); + ret = ETX_OTA_EX_ERR; + 8000ba2: 2301 movs r3, #1 + 8000ba4: 83fb strh r3, [r7, #30] break; - 8000950: e008 b.n 8000964 + 8000ba6: e00a b.n 8000bbe break; - 8000952: bf00 nop - 8000954: e006 b.n 8000964 + 8000ba8: bf00 nop + 8000baa: e008 b.n 8000bbe break; - 8000956: bf00 nop - 8000958: e004 b.n 8000964 + 8000bac: bf00 nop + 8000bae: e006 b.n 8000bbe break; - 800095a: bf00 nop - 800095c: e002 b.n 8000964 + 8000bb0: bf00 nop + 8000bb2: e004 b.n 8000bbe break; - 800095e: bf00 nop - 8000960: e000 b.n 8000964 + 8000bb4: bf00 nop + 8000bb6: e002 b.n 8000bbe break; - 8000962: bf00 nop + 8000bb8: bf00 nop + 8000bba: e000 b.n 8000bbe + break; + 8000bbc: bf00 nop } }while( false ); if( ret != HAL_OK ) - 8000964: f9b7 300e ldrsh.w r3, [r7, #14] - 8000968: 2b00 cmp r3, #0 - 800096a: d001 beq.n 8000970 + 8000bbe: f9b7 301e ldrsh.w r3, [r7, #30] + 8000bc2: 2b00 cmp r3, #0 + 8000bc4: d001 beq.n 8000bca { //clear the index if error index = 0u; - 800096c: 2300 movs r3, #0 - 800096e: 81bb strh r3, [r7, #12] + 8000bc6: 2300 movs r3, #0 + 8000bc8: 83bb strh r3, [r7, #28] } if( max_len < index ) - 8000970: 887a ldrh r2, [r7, #2] - 8000972: 89bb ldrh r3, [r7, #12] - 8000974: 429a cmp r2, r3 - 8000976: d207 bcs.n 8000988 + 8000bca: 887a ldrh r2, [r7, #2] + 8000bcc: 8bbb ldrh r3, [r7, #28] + 8000bce: 429a cmp r2, r3 + 8000bd0: d207 bcs.n 8000be2 { printf("Received more data than expected. Expected = %d, Received = %d\r\n", - 8000978: 887b ldrh r3, [r7, #2] - 800097a: 89ba ldrh r2, [r7, #12] - 800097c: 4619 mov r1, r3 - 800097e: 4806 ldr r0, [pc, #24] ; (8000998 ) - 8000980: f003 f85e bl 8003a40 + 8000bd2: 887b ldrh r3, [r7, #2] + 8000bd4: 8bba ldrh r2, [r7, #28] + 8000bd6: 4619 mov r1, r3 + 8000bd8: 4807 ldr r0, [pc, #28] ; (8000bf8 ) + 8000bda: f003 fd87 bl 80046ec max_len, index ); index = 0u; - 8000984: 2300 movs r3, #0 - 8000986: 81bb strh r3, [r7, #12] + 8000bde: 2300 movs r3, #0 + 8000be0: 83bb strh r3, [r7, #28] } return index; - 8000988: 89bb ldrh r3, [r7, #12] + 8000be2: 8bbb ldrh r3, [r7, #28] } - 800098a: 4618 mov r0, r3 - 800098c: 3710 adds r7, #16 - 800098e: 46bd mov sp, r7 - 8000990: bd80 pop {r7, pc} - 8000992: bf00 nop - 8000994: 20000534 .word 0x20000534 - 8000998: 08004aa4 .word 0x08004aa4 - -0800099c : + 8000be4: 4618 mov r0, r3 + 8000be6: 3720 adds r7, #32 + 8000be8: 46bd mov sp, r7 + 8000bea: bd80 pop {r7, pc} + 8000bec: 20000560 .word 0x20000560 + 8000bf0: 2000053c .word 0x2000053c + 8000bf4: 08005798 .word 0x08005798 + 8000bf8: 080057d8 .word 0x080057d8 + +08000bfc : * @brief Send the response. * @param type ACK or NACK * @retval none */ static void etx_ota_send_resp( uint8_t type ) { - 800099c: b580 push {r7, lr} - 800099e: b086 sub sp, #24 - 80009a0: af00 add r7, sp, #0 - 80009a2: 4603 mov r3, r0 - 80009a4: 71fb strb r3, [r7, #7] + 8000bfc: b580 push {r7, lr} + 8000bfe: b086 sub sp, #24 + 8000c00: af00 add r7, sp, #0 + 8000c02: 4603 mov r3, r0 + 8000c04: 71fb strb r3, [r7, #7] ETX_OTA_RESP_ rsp = - 80009a6: 23aa movs r3, #170 ; 0xaa - 80009a8: 733b strb r3, [r7, #12] - 80009aa: 2303 movs r3, #3 - 80009ac: 737b strb r3, [r7, #13] - 80009ae: 2301 movs r3, #1 - 80009b0: 81fb strh r3, [r7, #14] - 80009b2: 79fb ldrb r3, [r7, #7] - 80009b4: 743b strb r3, [r7, #16] - 80009b6: 2300 movs r3, #0 - 80009b8: 747b strb r3, [r7, #17] - 80009ba: 2300 movs r3, #0 - 80009bc: 74bb strb r3, [r7, #18] - 80009be: 2300 movs r3, #0 - 80009c0: 74fb strb r3, [r7, #19] - 80009c2: 2300 movs r3, #0 - 80009c4: 753b strb r3, [r7, #20] - 80009c6: 23bb movs r3, #187 ; 0xbb - 80009c8: 757b strb r3, [r7, #21] - .crc = 0u, //TODO: Add CRC + 8000c06: f107 030c add.w r3, r7, #12 + 8000c0a: 2200 movs r2, #0 + 8000c0c: 601a str r2, [r3, #0] + 8000c0e: 605a str r2, [r3, #4] + 8000c10: 811a strh r2, [r3, #8] + 8000c12: 23aa movs r3, #170 ; 0xaa + 8000c14: 733b strb r3, [r7, #12] + 8000c16: 2303 movs r3, #3 + 8000c18: 737b strb r3, [r7, #13] + 8000c1a: 2301 movs r3, #1 + 8000c1c: 81fb strh r3, [r7, #14] + 8000c1e: 79fb ldrb r3, [r7, #7] + 8000c20: 743b strb r3, [r7, #16] + 8000c22: 23bb movs r3, #187 ; 0xbb + 8000c24: 757b strb r3, [r7, #21] + .data_len = 1u, + .status = type, .eof = ETX_OTA_EOF }; + rsp.crc = HAL_CRC_Calculate( &hcrc, (uint32_t*)&rsp.status, 1); + 8000c26: f107 030c add.w r3, r7, #12 + 8000c2a: 3304 adds r3, #4 + 8000c2c: 2201 movs r2, #1 + 8000c2e: 4619 mov r1, r3 + 8000c30: 4808 ldr r0, [pc, #32] ; (8000c54 ) + 8000c32: f001 f8cd bl 8001dd0 + 8000c36: 4603 mov r3, r0 + 8000c38: f8c7 3011 str.w r3, [r7, #17] + //send response HAL_UART_Transmit(&huart2, (uint8_t *)&rsp, sizeof(ETX_OTA_RESP_), HAL_MAX_DELAY); - 80009ca: f107 010c add.w r1, r7, #12 - 80009ce: f04f 33ff mov.w r3, #4294967295 - 80009d2: 220a movs r2, #10 - 80009d4: 4803 ldr r0, [pc, #12] ; (80009e4 ) - 80009d6: f002 fad3 bl 8002f80 + 8000c3c: f107 010c add.w r1, r7, #12 + 8000c40: f04f 33ff mov.w r3, #4294967295 + 8000c44: 220a movs r2, #10 + 8000c46: 4804 ldr r0, [pc, #16] ; (8000c58 ) + 8000c48: f002 fff0 bl 8003c2c } - 80009da: bf00 nop - 80009dc: 3718 adds r7, #24 - 80009de: 46bd mov sp, r7 - 80009e0: bd80 pop {r7, pc} - 80009e2: bf00 nop - 80009e4: 20000534 .word 0x20000534 - -080009e8 : - * @is_first_block true - if this is first block, false - not first block - * @retval HAL_StatusTypeDef + 8000c4c: bf00 nop + 8000c4e: 3718 adds r7, #24 + 8000c50: 46bd mov sp, r7 + 8000c52: bd80 pop {r7, pc} + 8000c54: 2000053c .word 0x2000053c + 8000c58: 20000560 .word 0x20000560 + +08000c5c : */ -static HAL_StatusTypeDef write_data_to_flash_app( uint8_t *data, - uint16_t data_len, bool is_first_block ) +static HAL_StatusTypeDef write_data_to_slot( uint8_t slot_num, + uint8_t *data, + uint16_t data_len, + bool is_first_block ) { - 80009e8: b580 push {r7, lr} - 80009ea: b08a sub sp, #40 ; 0x28 - 80009ec: af00 add r7, sp, #0 - 80009ee: 6078 str r0, [r7, #4] - 80009f0: 460b mov r3, r1 - 80009f2: 807b strh r3, [r7, #2] - 80009f4: 4613 mov r3, r2 - 80009f6: 707b strb r3, [r7, #1] + 8000c5c: b580 push {r7, lr} + 8000c5e: b08c sub sp, #48 ; 0x30 + 8000c60: af00 add r7, sp, #0 + 8000c62: 6039 str r1, [r7, #0] + 8000c64: 4611 mov r1, r2 + 8000c66: 461a mov r2, r3 + 8000c68: 4603 mov r3, r0 + 8000c6a: 71fb strb r3, [r7, #7] + 8000c6c: 460b mov r3, r1 + 8000c6e: 80bb strh r3, [r7, #4] + 8000c70: 4613 mov r3, r2 + 8000c72: 71bb strb r3, [r7, #6] HAL_StatusTypeDef ret; do { + + if( slot_num >= ETX_NO_OF_SLOTS ) + 8000c74: 79fb ldrb r3, [r7, #7] + 8000c76: 2b01 cmp r3, #1 + 8000c78: d903 bls.n 8000c82 + { + ret = HAL_ERROR; + 8000c7a: 2301 movs r3, #1 + 8000c7c: f887 302f strb.w r3, [r7, #47] ; 0x2f + break; + 8000c80: e072 b.n 8000d68 + } + ret = HAL_FLASH_Unlock(); - 80009f8: f000 fd8a bl 8001510 - 80009fc: 4603 mov r3, r0 - 80009fe: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8000c82: f001 fa9b bl 80021bc + 8000c86: 4603 mov r3, r0 + 8000c88: f887 302f strb.w r3, [r7, #47] ; 0x2f if( ret != HAL_OK ) - 8000a02: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 - 8000a06: 2b00 cmp r3, #0 - 8000a08: d154 bne.n 8000ab4 + 8000c8c: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 8000c90: 2b00 cmp r3, #0 + 8000c92: d166 bne.n 8000d62 { break; } //No need to erase every time. Erase only the first time. if( is_first_block ) - 8000a0a: 787b ldrb r3, [r7, #1] - 8000a0c: 2b00 cmp r3, #0 - 8000a0e: d019 beq.n 8000a44 + 8000c94: 79bb ldrb r3, [r7, #6] + 8000c96: 2b00 cmp r3, #0 + 8000c98: d025 beq.n 8000ce6 { - - printf("Erasing the Flash memory...\r\n"); - 8000a10: 482e ldr r0, [pc, #184] ; (8000acc ) - 8000a12: f003 f89b bl 8003b4c + printf("Erasing the Slot %d Flash memory...\r\n", slot_num); + 8000c9a: 79fb ldrb r3, [r7, #7] + 8000c9c: 4619 mov r1, r3 + 8000c9e: 4835 ldr r0, [pc, #212] ; (8000d74 ) + 8000ca0: f003 fd24 bl 80046ec //Erase the Flash FLASH_EraseInitTypeDef EraseInitStruct; uint32_t SectorError; EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS; - 8000a16: 2300 movs r3, #0 - 8000a18: 60fb str r3, [r7, #12] - EraseInitStruct.Sector = FLASH_SECTOR_5; - 8000a1a: 2305 movs r3, #5 - 8000a1c: 617b str r3, [r7, #20] - EraseInitStruct.NbSectors = 2; //erase 2 sectors(5,6) - 8000a1e: 2302 movs r3, #2 - 8000a20: 61bb str r3, [r7, #24] + 8000ca4: 2300 movs r3, #0 + 8000ca6: 613b str r3, [r7, #16] + if( slot_num == 0 ) + 8000ca8: 79fb ldrb r3, [r7, #7] + 8000caa: 2b00 cmp r3, #0 + 8000cac: d102 bne.n 8000cb4 + { + EraseInitStruct.Sector = FLASH_SECTOR_7; + 8000cae: 2307 movs r3, #7 + 8000cb0: 61bb str r3, [r7, #24] + 8000cb2: e001 b.n 8000cb8 + } + else + { + EraseInitStruct.Sector = FLASH_SECTOR_9; + 8000cb4: 2309 movs r3, #9 + 8000cb6: 61bb str r3, [r7, #24] + } + EraseInitStruct.NbSectors = 2; //erase 2 sectors + 8000cb8: 2302 movs r3, #2 + 8000cba: 61fb str r3, [r7, #28] EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3; - 8000a22: 2302 movs r3, #2 - 8000a24: 61fb str r3, [r7, #28] + 8000cbc: 2302 movs r3, #2 + 8000cbe: 623b str r3, [r7, #32] ret = HAL_FLASHEx_Erase( &EraseInitStruct, &SectorError ); - 8000a26: f107 0208 add.w r2, r7, #8 - 8000a2a: f107 030c add.w r3, r7, #12 - 8000a2e: 4611 mov r1, r2 - 8000a30: 4618 mov r0, r3 - 8000a32: f000 fecf bl 80017d4 - 8000a36: 4603 mov r3, r0 - 8000a38: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8000cc0: f107 020c add.w r2, r7, #12 + 8000cc4: f107 0310 add.w r3, r7, #16 + 8000cc8: 4611 mov r1, r2 + 8000cca: 4618 mov r0, r3 + 8000ccc: f001 fbd8 bl 8002480 + 8000cd0: 4603 mov r3, r0 + 8000cd2: f887 302f strb.w r3, [r7, #47] ; 0x2f if( ret != HAL_OK ) - 8000a3c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 - 8000a40: 2b00 cmp r3, #0 - 8000a42: d139 bne.n 8000ab8 + 8000cd6: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 8000cda: 2b00 cmp r3, #0 + 8000cdc: d003 beq.n 8000ce6 { + printf("Flash Erase Error\r\n"); + 8000cde: 4826 ldr r0, [pc, #152] ; (8000d78 ) + 8000ce0: f003 fd8a bl 80047f8 + 8000ce4: e040 b.n 8000d68 break; } } + uint32_t flash_addr; + if( slot_num == 0 ) + 8000ce6: 79fb ldrb r3, [r7, #7] + 8000ce8: 2b00 cmp r3, #0 + 8000cea: d102 bne.n 8000cf2 + { + flash_addr = ETX_APP_SLOT0_FLASH_ADDR; + 8000cec: 4b23 ldr r3, [pc, #140] ; (8000d7c ) + 8000cee: 62bb str r3, [r7, #40] ; 0x28 + 8000cf0: e001 b.n 8000cf6 + } + else + { + flash_addr = ETX_APP_SLOT1_FLASH_ADDR; + 8000cf2: 4b23 ldr r3, [pc, #140] ; (8000d80 ) + 8000cf4: 62bb str r3, [r7, #40] ; 0x28 + } + for(int i = 0; i < data_len; i++ ) - 8000a44: 2300 movs r3, #0 - 8000a46: 623b str r3, [r7, #32] - 8000a48: e023 b.n 8000a92 + 8000cf6: 2300 movs r3, #0 + 8000cf8: 627b str r3, [r7, #36] ; 0x24 + 8000cfa: e021 b.n 8000d40 { ret = HAL_FLASH_Program( FLASH_TYPEPROGRAM_BYTE, - 8000a4a: 4b21 ldr r3, [pc, #132] ; (8000ad0 ) - 8000a4c: 681b ldr r3, [r3, #0] - 8000a4e: 4921 ldr r1, [pc, #132] ; (8000ad4 ) - 8000a50: 4419 add r1, r3 - (ETX_APP_FLASH_ADDR + ota_fw_received_size), - data[4+i] - 8000a52: 6a3b ldr r3, [r7, #32] - 8000a54: 3304 adds r3, #4 - 8000a56: 461a mov r2, r3 - 8000a58: 687b ldr r3, [r7, #4] - 8000a5a: 4413 add r3, r2 - 8000a5c: 781b ldrb r3, [r3, #0] + 8000cfc: 4b21 ldr r3, [pc, #132] ; (8000d84 ) + 8000cfe: 681a ldr r2, [r3, #0] + 8000d00: 6abb ldr r3, [r7, #40] ; 0x28 + 8000d02: 18d1 adds r1, r2, r3 + (flash_addr + ota_fw_received_size), + data[i] + 8000d04: 6a7b ldr r3, [r7, #36] ; 0x24 + 8000d06: 683a ldr r2, [r7, #0] + 8000d08: 4413 add r3, r2 + 8000d0a: 781b ldrb r3, [r3, #0] ret = HAL_FLASH_Program( FLASH_TYPEPROGRAM_BYTE, - 8000a5e: b2da uxtb r2, r3 - 8000a60: f04f 0300 mov.w r3, #0 - 8000a64: 2000 movs r0, #0 - 8000a66: f000 fcf7 bl 8001458 - 8000a6a: 4603 mov r3, r0 - 8000a6c: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8000d0c: b2da uxtb r2, r3 + 8000d0e: f04f 0300 mov.w r3, #0 + 8000d12: 2000 movs r0, #0 + 8000d14: f001 f9f6 bl 8002104 + 8000d18: 4603 mov r3, r0 + 8000d1a: f887 302f strb.w r3, [r7, #47] ; 0x2f ); if( ret == HAL_OK ) - 8000a70: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 - 8000a74: 2b00 cmp r3, #0 - 8000a76: d105 bne.n 8000a84 + 8000d1e: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 8000d22: 2b00 cmp r3, #0 + 8000d24: d105 bne.n 8000d32 { //update the data count ota_fw_received_size += 1; - 8000a78: 4b15 ldr r3, [pc, #84] ; (8000ad0 ) - 8000a7a: 681b ldr r3, [r3, #0] - 8000a7c: 3301 adds r3, #1 - 8000a7e: 4a14 ldr r2, [pc, #80] ; (8000ad0 ) - 8000a80: 6013 str r3, [r2, #0] - 8000a82: e003 b.n 8000a8c + 8000d26: 4b17 ldr r3, [pc, #92] ; (8000d84 ) + 8000d28: 681b ldr r3, [r3, #0] + 8000d2a: 3301 adds r3, #1 + 8000d2c: 4a15 ldr r2, [pc, #84] ; (8000d84 ) + 8000d2e: 6013 str r3, [r2, #0] + 8000d30: e003 b.n 8000d3a } else { printf("Flash Write Error\r\n"); - 8000a84: 4814 ldr r0, [pc, #80] ; (8000ad8 ) - 8000a86: f003 f861 bl 8003b4c + 8000d32: 4815 ldr r0, [pc, #84] ; (8000d88 ) + 8000d34: f003 fd60 bl 80047f8 break; - 8000a8a: e006 b.n 8000a9a + 8000d38: e006 b.n 8000d48 for(int i = 0; i < data_len; i++ ) - 8000a8c: 6a3b ldr r3, [r7, #32] - 8000a8e: 3301 adds r3, #1 - 8000a90: 623b str r3, [r7, #32] - 8000a92: 887b ldrh r3, [r7, #2] - 8000a94: 6a3a ldr r2, [r7, #32] - 8000a96: 429a cmp r2, r3 - 8000a98: dbd7 blt.n 8000a4a + 8000d3a: 6a7b ldr r3, [r7, #36] ; 0x24 + 8000d3c: 3301 adds r3, #1 + 8000d3e: 627b str r3, [r7, #36] ; 0x24 + 8000d40: 88bb ldrh r3, [r7, #4] + 8000d42: 6a7a ldr r2, [r7, #36] ; 0x24 + 8000d44: 429a cmp r2, r3 + 8000d46: dbd9 blt.n 8000cfc } } if( ret != HAL_OK ) - 8000a9a: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 - 8000a9e: 2b00 cmp r3, #0 - 8000aa0: d10c bne.n 8000abc + 8000d48: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 8000d4c: 2b00 cmp r3, #0 + 8000d4e: d10a bne.n 8000d66 { break; } ret = HAL_FLASH_Lock(); - 8000aa2: f000 fd57 bl 8001554 - 8000aa6: 4603 mov r3, r0 - 8000aa8: f887 3027 strb.w r3, [r7, #39] ; 0x27 + 8000d50: f001 fa56 bl 8002200 + 8000d54: 4603 mov r3, r0 + 8000d56: f887 302f strb.w r3, [r7, #47] ; 0x2f if( ret != HAL_OK ) - 8000aac: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 - 8000ab0: 2b00 cmp r3, #0 - 8000ab2: e004 b.n 8000abe + 8000d5a: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 8000d5e: 2b00 cmp r3, #0 + 8000d60: e002 b.n 8000d68 + break; + 8000d62: bf00 nop + 8000d64: e000 b.n 8000d68 + break; + 8000d66: bf00 nop + { break; - 8000ab4: bf00 nop - 8000ab6: e002 b.n 8000abe + } + }while( false ); + + return ret; + 8000d68: f897 302f ldrb.w r3, [r7, #47] ; 0x2f +} + 8000d6c: 4618 mov r0, r3 + 8000d6e: 3730 adds r7, #48 ; 0x30 + 8000d70: 46bd mov sp, r7 + 8000d72: bd80 pop {r7, pc} + 8000d74: 0800581c .word 0x0800581c + 8000d78: 08005844 .word 0x08005844 + 8000d7c: 080c0000 .word 0x080c0000 + 8000d80: 08140000 .word 0x08140000 + 8000d84: 200004a4 .word 0x200004a4 + 8000d88: 08005858 .word 0x08005858 + +08000d8c : + * @brief Return the available slot number + * @param none + * @retval slot number + */ +static uint8_t get_available_slot_number( void ) +{ + 8000d8c: b5f0 push {r4, r5, r6, r7, lr} + 8000d8e: b08f sub sp, #60 ; 0x3c + 8000d90: af00 add r7, sp, #0 + uint8_t slot_number = 0xFF; + 8000d92: 23ff movs r3, #255 ; 0xff + 8000d94: f887 3037 strb.w r3, [r7, #55] ; 0x37 + + /* Read the configuration */ + ETX_GNRL_CFG_ cfg; + memcpy( &cfg, cfg_flash, sizeof(ETX_GNRL_CFG_) ); + 8000d98: 4b27 ldr r3, [pc, #156] ; (8000e38 ) + 8000d9a: 681b ldr r3, [r3, #0] + 8000d9c: 461c mov r4, r3 + 8000d9e: 1d3e adds r6, r7, #4 + 8000da0: f104 0c30 add.w ip, r4, #48 ; 0x30 + 8000da4: 4635 mov r5, r6 + 8000da6: 4623 mov r3, r4 + 8000da8: 6818 ldr r0, [r3, #0] + 8000daa: 6859 ldr r1, [r3, #4] + 8000dac: 689a ldr r2, [r3, #8] + 8000dae: 68db ldr r3, [r3, #12] + 8000db0: c50f stmia r5!, {r0, r1, r2, r3} + 8000db2: 3410 adds r4, #16 + 8000db4: 3610 adds r6, #16 + 8000db6: 4564 cmp r4, ip + 8000db8: d1f4 bne.n 8000da4 + 8000dba: 4632 mov r2, r6 + 8000dbc: 4623 mov r3, r4 + 8000dbe: 881b ldrh r3, [r3, #0] + 8000dc0: 8013 strh r3, [r2, #0] + * If it is valid and not active, then use that slot. + * If it is not valid, then use that slot. + * + */ + + for( uint8_t i = 0; i < ETX_NO_OF_SLOTS; i++ ) + 8000dc2: 2300 movs r3, #0 + 8000dc4: f887 3036 strb.w r3, [r7, #54] ; 0x36 + 8000dc8: e02b b.n 8000e22 + { + if( ( cfg.slot_table[i].is_this_slot_not_valid != 0u ) || ( cfg.slot_table[i].is_this_slot_active == 0u ) ) + 8000dca: f897 2036 ldrb.w r2, [r7, #54] ; 0x36 + 8000dce: 4613 mov r3, r2 + 8000dd0: 005b lsls r3, r3, #1 + 8000dd2: 4413 add r3, r2 + 8000dd4: 00db lsls r3, r3, #3 + 8000dd6: 1a9b subs r3, r3, r2 + 8000dd8: f107 0238 add.w r2, r7, #56 ; 0x38 + 8000ddc: 4413 add r3, r2 + 8000dde: 3b30 subs r3, #48 ; 0x30 + 8000de0: 781b ldrb r3, [r3, #0] + 8000de2: 2b00 cmp r3, #0 + 8000de4: d10d bne.n 8000e02 + 8000de6: f897 2036 ldrb.w r2, [r7, #54] ; 0x36 + 8000dea: 4613 mov r3, r2 + 8000dec: 005b lsls r3, r3, #1 + 8000dee: 4413 add r3, r2 + 8000df0: 00db lsls r3, r3, #3 + 8000df2: 1a9b subs r3, r3, r2 + 8000df4: f107 0238 add.w r2, r7, #56 ; 0x38 + 8000df8: 4413 add r3, r2 + 8000dfa: 3b2f subs r3, #47 ; 0x2f + 8000dfc: 781b ldrb r3, [r3, #0] + 8000dfe: 2b00 cmp r3, #0 + 8000e00: d10a bne.n 8000e18 + { + slot_number = i; + 8000e02: f897 3036 ldrb.w r3, [r7, #54] ; 0x36 + 8000e06: f887 3037 strb.w r3, [r7, #55] ; 0x37 + printf("Slot %d is available for OTA update\r\n", slot_number); + 8000e0a: f897 3037 ldrb.w r3, [r7, #55] ; 0x37 + 8000e0e: 4619 mov r1, r3 + 8000e10: 480a ldr r0, [pc, #40] ; (8000e3c ) + 8000e12: f003 fc6b bl 80046ec + break; + 8000e16: e008 b.n 8000e2a + for( uint8_t i = 0; i < ETX_NO_OF_SLOTS; i++ ) + 8000e18: f897 3036 ldrb.w r3, [r7, #54] ; 0x36 + 8000e1c: 3301 adds r3, #1 + 8000e1e: f887 3036 strb.w r3, [r7, #54] ; 0x36 + 8000e22: f897 3036 ldrb.w r3, [r7, #54] ; 0x36 + 8000e26: 2b01 cmp r3, #1 + 8000e28: d9cf bls.n 8000dca + } + } + + return slot_number; + 8000e2a: f897 3037 ldrb.w r3, [r7, #55] ; 0x37 +} + 8000e2e: 4618 mov r0, r3 + 8000e30: 373c adds r7, #60 ; 0x3c + 8000e32: 46bd mov sp, r7 + 8000e34: bdf0 pop {r4, r5, r6, r7, pc} + 8000e36: bf00 nop + 8000e38: 20000000 .word 0x20000000 + 8000e3c: 0800586c .word 0x0800586c + +08000e40 : + * @param data data to be written + * @param data_len data length + * @retval HAL_StatusTypeDef + */ +static HAL_StatusTypeDef write_data_to_flash_app( uint8_t *data, uint32_t data_len ) +{ + 8000e40: b580 push {r7, lr} + 8000e42: b08a sub sp, #40 ; 0x28 + 8000e44: af00 add r7, sp, #0 + 8000e46: 6078 str r0, [r7, #4] + 8000e48: 6039 str r1, [r7, #0] + HAL_StatusTypeDef ret; + + do + { + ret = HAL_FLASH_Unlock(); + 8000e4a: f001 f9b7 bl 80021bc + 8000e4e: 4603 mov r3, r0 + 8000e50: f887 3027 strb.w r3, [r7, #39] ; 0x27 + if( ret != HAL_OK ) + 8000e54: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8000e58: 2b00 cmp r3, #0 + 8000e5a: d158 bne.n 8000f0e + { + break; + } + + //Check if the FLASH_FLAG_BSY. + FLASH_WaitForLastOperation( HAL_MAX_DELAY ); + 8000e5c: f04f 30ff mov.w r0, #4294967295 + 8000e60: f001 f9de bl 8002220 + + // clear all flags before you write it to flash + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | + 8000e64: 4b2f ldr r3, [pc, #188] ; (8000f24 ) + 8000e66: 2273 movs r2, #115 ; 0x73 + 8000e68: 60da str r2, [r3, #12] + FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR); + + printf("Erasing the App Flash memory...\r\n"); + 8000e6a: 482f ldr r0, [pc, #188] ; (8000f28 ) + 8000e6c: f003 fcc4 bl 80047f8 + //Erase the Flash + FLASH_EraseInitTypeDef EraseInitStruct; + uint32_t SectorError; + + EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS; + 8000e70: 2300 movs r3, #0 + 8000e72: 60fb str r3, [r7, #12] + EraseInitStruct.Sector = FLASH_SECTOR_5; + 8000e74: 2305 movs r3, #5 + 8000e76: 617b str r3, [r7, #20] + EraseInitStruct.NbSectors = 2; //erase 2 sectors(5,6) + 8000e78: 2302 movs r3, #2 + 8000e7a: 61bb str r3, [r7, #24] + EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3; + 8000e7c: 2302 movs r3, #2 + 8000e7e: 61fb str r3, [r7, #28] + + ret = HAL_FLASHEx_Erase( &EraseInitStruct, &SectorError ); + 8000e80: f107 0208 add.w r2, r7, #8 + 8000e84: f107 030c add.w r3, r7, #12 + 8000e88: 4611 mov r1, r2 + 8000e8a: 4618 mov r0, r3 + 8000e8c: f001 faf8 bl 8002480 + 8000e90: 4603 mov r3, r0 + 8000e92: f887 3027 strb.w r3, [r7, #39] ; 0x27 + if( ret != HAL_OK ) + 8000e96: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8000e9a: 2b00 cmp r3, #0 + 8000e9c: d003 beq.n 8000ea6 + { + printf("Flash erase Error\r\n"); + 8000e9e: 4823 ldr r0, [pc, #140] ; (8000f2c ) + 8000ea0: f003 fcaa bl 80047f8 + break; + 8000ea4: e038 b.n 8000f18 + } + + for( uint32_t i = 0; i < data_len; i++ ) + 8000ea6: 2300 movs r3, #0 + 8000ea8: 623b str r3, [r7, #32] + 8000eaa: e01a b.n 8000ee2 + { + ret = HAL_FLASH_Program( FLASH_TYPEPROGRAM_BYTE, + 8000eac: 6a3b ldr r3, [r7, #32] + 8000eae: 4920 ldr r1, [pc, #128] ; (8000f30 ) + 8000eb0: 4419 add r1, r3 + (ETX_APP_FLASH_ADDR + i), + data[i] + 8000eb2: 687a ldr r2, [r7, #4] + 8000eb4: 6a3b ldr r3, [r7, #32] + 8000eb6: 4413 add r3, r2 + 8000eb8: 781b ldrb r3, [r3, #0] + ret = HAL_FLASH_Program( FLASH_TYPEPROGRAM_BYTE, + 8000eba: b2da uxtb r2, r3 + 8000ebc: f04f 0300 mov.w r3, #0 + 8000ec0: 2000 movs r0, #0 + 8000ec2: f001 f91f bl 8002104 + 8000ec6: 4603 mov r3, r0 + 8000ec8: f887 3027 strb.w r3, [r7, #39] ; 0x27 + ); + if( ret != HAL_OK ) + 8000ecc: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8000ed0: 2b00 cmp r3, #0 + 8000ed2: d003 beq.n 8000edc + { + printf("App Flash Write Error\r\n"); + 8000ed4: 4817 ldr r0, [pc, #92] ; (8000f34 ) + 8000ed6: f003 fc8f bl 80047f8 break; - 8000ab8: bf00 nop - 8000aba: e000 b.n 8000abe + 8000eda: e006 b.n 8000eea + for( uint32_t i = 0; i < data_len; i++ ) + 8000edc: 6a3b ldr r3, [r7, #32] + 8000ede: 3301 adds r3, #1 + 8000ee0: 623b str r3, [r7, #32] + 8000ee2: 6a3a ldr r2, [r7, #32] + 8000ee4: 683b ldr r3, [r7, #0] + 8000ee6: 429a cmp r2, r3 + 8000ee8: d3e0 bcc.n 8000eac + } + } + + if( ret != HAL_OK ) + 8000eea: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8000eee: 2b00 cmp r3, #0 + 8000ef0: d10f bne.n 8000f12 + { + break; + } + + ret = HAL_FLASH_Lock(); + 8000ef2: f001 f985 bl 8002200 + 8000ef6: 4603 mov r3, r0 + 8000ef8: f887 3027 strb.w r3, [r7, #39] ; 0x27 + if( ret != HAL_OK ) + 8000efc: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8000f00: 2b00 cmp r3, #0 + 8000f02: d108 bne.n 8000f16 + { + break; + } + + //Check if the FLASH_FLAG_BSY. + FLASH_WaitForLastOperation( HAL_MAX_DELAY ); + 8000f04: f04f 30ff mov.w r0, #4294967295 + 8000f08: f001 f98a bl 8002220 + 8000f0c: e004 b.n 8000f18 + break; + 8000f0e: bf00 nop + 8000f10: e002 b.n 8000f18 + break; + 8000f12: bf00 nop + 8000f14: e000 b.n 8000f18 + break; + 8000f16: bf00 nop + + }while( false ); + + return ret; + 8000f18: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 +} + 8000f1c: 4618 mov r0, r3 + 8000f1e: 3728 adds r7, #40 ; 0x28 + 8000f20: 46bd mov sp, r7 + 8000f22: bd80 pop {r7, pc} + 8000f24: 40023c00 .word 0x40023c00 + 8000f28: 08005894 .word 0x08005894 + 8000f2c: 080058b8 .word 0x080058b8 + 8000f30: 08040000 .word 0x08040000 + 8000f34: 080058cc .word 0x080058cc + +08000f38 : + * @brief Load the new app to the app's actual flash memory. + * @param none + * @retval none + */ +void load_new_app( void ) +{ + 8000f38: b5f0 push {r4, r5, r6, r7, lr} + 8000f3a: b093 sub sp, #76 ; 0x4c + 8000f3c: af00 add r7, sp, #0 + bool is_update_available = false; + 8000f3e: 2300 movs r3, #0 + 8000f40: f887 3047 strb.w r3, [r7, #71] ; 0x47 + uint8_t slot_num; + HAL_StatusTypeDef ret; + + /* Read the configuration */ + ETX_GNRL_CFG_ cfg; + memcpy( &cfg, cfg_flash, sizeof(ETX_GNRL_CFG_) ); + 8000f44: 4b85 ldr r3, [pc, #532] ; (800115c ) + 8000f46: 681b ldr r3, [r3, #0] + 8000f48: 461c mov r4, r3 + 8000f4a: 1d3e adds r6, r7, #4 + 8000f4c: f104 0c30 add.w ip, r4, #48 ; 0x30 + 8000f50: 4635 mov r5, r6 + 8000f52: 4623 mov r3, r4 + 8000f54: 6818 ldr r0, [r3, #0] + 8000f56: 6859 ldr r1, [r3, #4] + 8000f58: 689a ldr r2, [r3, #8] + 8000f5a: 68db ldr r3, [r3, #12] + 8000f5c: c50f stmia r5!, {r0, r1, r2, r3} + 8000f5e: 3410 adds r4, #16 + 8000f60: 3610 adds r6, #16 + 8000f62: 4564 cmp r4, ip + 8000f64: d1f4 bne.n 8000f50 + 8000f66: 4632 mov r2, r6 + 8000f68: 4623 mov r3, r4 + 8000f6a: 881b ldrh r3, [r3, #0] + 8000f6c: 8013 strh r3, [r2, #0] + + /* + * Check the slot whether it has a new application. + */ + + for( uint8_t i = 0; i < ETX_NO_OF_SLOTS; i++ ) + 8000f6e: 2300 movs r3, #0 + 8000f70: f887 3045 strb.w r3, [r7, #69] ; 0x45 + 8000f74: e03a b.n 8000fec + { + if( cfg.slot_table[i].should_we_run_this_fw == 1u ) + 8000f76: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 + 8000f7a: 4613 mov r3, r2 + 8000f7c: 005b lsls r3, r3, #1 + 8000f7e: 4413 add r3, r2 + 8000f80: 00db lsls r3, r3, #3 + 8000f82: 1a9b subs r3, r3, r2 + 8000f84: f107 0248 add.w r2, r7, #72 ; 0x48 + 8000f88: 4413 add r3, r2 + 8000f8a: 3b3e subs r3, #62 ; 0x3e + 8000f8c: 781b ldrb r3, [r3, #0] + 8000f8e: 2b01 cmp r3, #1 + 8000f90: d127 bne.n 8000fe2 + { + printf("New Application is available in the slot %d!!!\r\n", i); + 8000f92: f897 3045 ldrb.w r3, [r7, #69] ; 0x45 + 8000f96: 4619 mov r1, r3 + 8000f98: 4871 ldr r0, [pc, #452] ; (8001160 ) + 8000f9a: f003 fba7 bl 80046ec + is_update_available = true; + 8000f9e: 2301 movs r3, #1 + 8000fa0: f887 3047 strb.w r3, [r7, #71] ; 0x47 + slot_num = i; + 8000fa4: f897 3045 ldrb.w r3, [r7, #69] ; 0x45 + 8000fa8: f887 3046 strb.w r3, [r7, #70] ; 0x46 + + //update the slot + cfg.slot_table[i].is_this_slot_active = 1u; + 8000fac: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 + 8000fb0: 4613 mov r3, r2 + 8000fb2: 005b lsls r3, r3, #1 + 8000fb4: 4413 add r3, r2 + 8000fb6: 00db lsls r3, r3, #3 + 8000fb8: 1a9b subs r3, r3, r2 + 8000fba: f107 0248 add.w r2, r7, #72 ; 0x48 + 8000fbe: 4413 add r3, r2 + 8000fc0: 3b3f subs r3, #63 ; 0x3f + 8000fc2: 2201 movs r2, #1 + 8000fc4: 701a strb r2, [r3, #0] + cfg.slot_table[i].should_we_run_this_fw = 0u; + 8000fc6: f897 2045 ldrb.w r2, [r7, #69] ; 0x45 + 8000fca: 4613 mov r3, r2 + 8000fcc: 005b lsls r3, r3, #1 + 8000fce: 4413 add r3, r2 + 8000fd0: 00db lsls r3, r3, #3 + 8000fd2: 1a9b subs r3, r3, r2 + 8000fd4: f107 0248 add.w r2, r7, #72 ; 0x48 + 8000fd8: 4413 add r3, r2 + 8000fda: 3b3e subs r3, #62 ; 0x3e + 8000fdc: 2200 movs r2, #0 + 8000fde: 701a strb r2, [r3, #0] + + break; + 8000fe0: e008 b.n 8000ff4 + for( uint8_t i = 0; i < ETX_NO_OF_SLOTS; i++ ) + 8000fe2: f897 3045 ldrb.w r3, [r7, #69] ; 0x45 + 8000fe6: 3301 adds r3, #1 + 8000fe8: f887 3045 strb.w r3, [r7, #69] ; 0x45 + 8000fec: f897 3045 ldrb.w r3, [r7, #69] ; 0x45 + 8000ff0: 2b01 cmp r3, #1 + 8000ff2: d9c0 bls.n 8000f76 + } + } + + if( is_update_available ) + 8000ff4: f897 3047 ldrb.w r3, [r7, #71] ; 0x47 + 8000ff8: 2b00 cmp r3, #0 + 8000ffa: d053 beq.n 80010a4 + { + //make other slots inactive + for( uint8_t i = 0; i < ETX_NO_OF_SLOTS; i++ ) + 8000ffc: 2300 movs r3, #0 + 8000ffe: f887 3044 strb.w r3, [r7, #68] ; 0x44 + 8001002: e017 b.n 8001034 + { + if( slot_num != i ) + 8001004: f897 2046 ldrb.w r2, [r7, #70] ; 0x46 + 8001008: f897 3044 ldrb.w r3, [r7, #68] ; 0x44 + 800100c: 429a cmp r2, r3 + 800100e: d00c beq.n 800102a + { + //update the slot as inactive + cfg.slot_table[i].is_this_slot_active = 0u; + 8001010: f897 2044 ldrb.w r2, [r7, #68] ; 0x44 + 8001014: 4613 mov r3, r2 + 8001016: 005b lsls r3, r3, #1 + 8001018: 4413 add r3, r2 + 800101a: 00db lsls r3, r3, #3 + 800101c: 1a9b subs r3, r3, r2 + 800101e: f107 0248 add.w r2, r7, #72 ; 0x48 + 8001022: 4413 add r3, r2 + 8001024: 3b3f subs r3, #63 ; 0x3f + 8001026: 2200 movs r2, #0 + 8001028: 701a strb r2, [r3, #0] + for( uint8_t i = 0; i < ETX_NO_OF_SLOTS; i++ ) + 800102a: f897 3044 ldrb.w r3, [r7, #68] ; 0x44 + 800102e: 3301 adds r3, #1 + 8001030: f887 3044 strb.w r3, [r7, #68] ; 0x44 + 8001034: f897 3044 ldrb.w r3, [r7, #68] ; 0x44 + 8001038: 2b01 cmp r3, #1 + 800103a: d9e3 bls.n 8001004 + } + } + + uint32_t slot_addr; + if( slot_num == 0u ) + 800103c: f897 3046 ldrb.w r3, [r7, #70] ; 0x46 + 8001040: 2b00 cmp r3, #0 + 8001042: d102 bne.n 800104a + { + slot_addr = ETX_APP_SLOT0_FLASH_ADDR; + 8001044: 4b47 ldr r3, [pc, #284] ; (8001164 ) + 8001046: 643b str r3, [r7, #64] ; 0x40 + 8001048: e001 b.n 800104e + } + else + { + slot_addr = ETX_APP_SLOT1_FLASH_ADDR; + 800104a: 4b47 ldr r3, [pc, #284] ; (8001168 ) + 800104c: 643b str r3, [r7, #64] ; 0x40 + } + + //Load the new app or firmware to app's flash address + ret = write_data_to_flash_app( (uint8_t*)slot_addr, cfg.slot_table[slot_num].fw_size); + 800104e: 6c38 ldr r0, [r7, #64] ; 0x40 + 8001050: f897 2046 ldrb.w r2, [r7, #70] ; 0x46 + 8001054: 4613 mov r3, r2 + 8001056: 005b lsls r3, r3, #1 + 8001058: 4413 add r3, r2 + 800105a: 00db lsls r3, r3, #3 + 800105c: 1a9b subs r3, r3, r2 + 800105e: f107 0248 add.w r2, r7, #72 ; 0x48 + 8001062: 4413 add r3, r2 + 8001064: 3b44 subs r3, #68 ; 0x44 + 8001066: f8d3 3007 ldr.w r3, [r3, #7] + 800106a: 4619 mov r1, r3 + 800106c: f7ff fee8 bl 8000e40 + 8001070: 4603 mov r3, r0 + 8001072: f887 303e strb.w r3, [r7, #62] ; 0x3e + if( ret != HAL_OK ) + 8001076: f897 303e ldrb.w r3, [r7, #62] ; 0x3e + 800107a: 2b00 cmp r3, #0 + 800107c: d003 beq.n 8001086 + { + printf("App Flash write Error\r\n"); + 800107e: 483b ldr r0, [pc, #236] ; (800116c ) + 8001080: f003 fbba bl 80047f8 + 8001084: e02e b.n 80010e4 + } + else + { + /* write back the updated config */ + ret = write_cfg_to_flash( &cfg ); + 8001086: 1d3b adds r3, r7, #4 + 8001088: 4618 mov r0, r3 + 800108a: f000 f87f bl 800118c + 800108e: 4603 mov r3, r0 + 8001090: f887 303e strb.w r3, [r7, #62] ; 0x3e + if( ret != HAL_OK ) + 8001094: f897 303e ldrb.w r3, [r7, #62] ; 0x3e + 8001098: 2b00 cmp r3, #0 + 800109a: d023 beq.n 80010e4 + { + printf("Config Flash write Error\r\n"); + 800109c: 4834 ldr r0, [pc, #208] ; (8001170 ) + 800109e: f003 fbab bl 80047f8 + 80010a2: e01f b.n 80010e4 + } + } + else + { + //Find the active slot in case the update is not available + for( uint8_t i = 0; i < ETX_NO_OF_SLOTS; i++ ) + 80010a4: 2300 movs r3, #0 + 80010a6: f887 303f strb.w r3, [r7, #63] ; 0x3f + 80010aa: e017 b.n 80010dc + { + if( cfg.slot_table[i].is_this_slot_active == 1u ) + 80010ac: f897 203f ldrb.w r2, [r7, #63] ; 0x3f + 80010b0: 4613 mov r3, r2 + 80010b2: 005b lsls r3, r3, #1 + 80010b4: 4413 add r3, r2 + 80010b6: 00db lsls r3, r3, #3 + 80010b8: 1a9b subs r3, r3, r2 + 80010ba: f107 0248 add.w r2, r7, #72 ; 0x48 + 80010be: 4413 add r3, r2 + 80010c0: 3b3f subs r3, #63 ; 0x3f + 80010c2: 781b ldrb r3, [r3, #0] + 80010c4: 2b01 cmp r3, #1 + 80010c6: d104 bne.n 80010d2 + { + slot_num = i; + 80010c8: f897 303f ldrb.w r3, [r7, #63] ; 0x3f + 80010cc: f887 3046 strb.w r3, [r7, #70] ; 0x46 + break; + 80010d0: e008 b.n 80010e4 + for( uint8_t i = 0; i < ETX_NO_OF_SLOTS; i++ ) + 80010d2: f897 303f ldrb.w r3, [r7, #63] ; 0x3f + 80010d6: 3301 adds r3, #1 + 80010d8: f887 303f strb.w r3, [r7, #63] ; 0x3f + 80010dc: f897 303f ldrb.w r3, [r7, #63] ; 0x3f + 80010e0: 2b01 cmp r3, #1 + 80010e2: d9e3 bls.n 80010ac + } + } + } + + //Verify the application is corrupted or not + printf("Verifying the Application..."); + 80010e4: 4823 ldr r0, [pc, #140] ; (8001174 ) + 80010e6: f003 fb01 bl 80046ec + + FLASH_WaitForLastOperation( HAL_MAX_DELAY ); + 80010ea: f04f 30ff mov.w r0, #4294967295 + 80010ee: f001 f897 bl 8002220 + //Verify the application + uint32_t cal_data_crc = HAL_CRC_Calculate( &hcrc, (uint32_t*)ETX_APP_FLASH_ADDR, cfg.slot_table[slot_num].fw_size); + 80010f2: f897 2046 ldrb.w r2, [r7, #70] ; 0x46 + 80010f6: 4613 mov r3, r2 + 80010f8: 005b lsls r3, r3, #1 + 80010fa: 4413 add r3, r2 + 80010fc: 00db lsls r3, r3, #3 + 80010fe: 1a9b subs r3, r3, r2 + 8001100: f107 0248 add.w r2, r7, #72 ; 0x48 + 8001104: 4413 add r3, r2 + 8001106: 3b44 subs r3, #68 ; 0x44 + 8001108: f8d3 3007 ldr.w r3, [r3, #7] + 800110c: 461a mov r2, r3 + 800110e: 491a ldr r1, [pc, #104] ; (8001178 ) + 8001110: 481a ldr r0, [pc, #104] ; (800117c ) + 8001112: f000 fe5d bl 8001dd0 + 8001116: 63b8 str r0, [r7, #56] ; 0x38 + FLASH_WaitForLastOperation( HAL_MAX_DELAY ); + 8001118: f04f 30ff mov.w r0, #4294967295 + 800111c: f001 f880 bl 8002220 + + //Verify the CRC + if( cal_data_crc != cfg.slot_table[slot_num].fw_crc ) + 8001120: f897 2046 ldrb.w r2, [r7, #70] ; 0x46 + 8001124: 4613 mov r3, r2 + 8001126: 005b lsls r3, r3, #1 + 8001128: 4413 add r3, r2 + 800112a: 00db lsls r3, r3, #3 + 800112c: 1a9b subs r3, r3, r2 + 800112e: f107 0248 add.w r2, r7, #72 ; 0x48 + 8001132: 4413 add r3, r2 + 8001134: 3b44 subs r3, #68 ; 0x44 + 8001136: f8d3 300b ldr.w r3, [r3, #11] + 800113a: 6bba ldr r2, [r7, #56] ; 0x38 + 800113c: 429a cmp r2, r3 + 800113e: d006 beq.n 800114e + { + printf("ERROR!!!\r\n"); + 8001140: 480f ldr r0, [pc, #60] ; (8001180 ) + 8001142: f003 fb59 bl 80047f8 + printf("Invalid Application. HALT!!!\r\n"); + 8001146: 480f ldr r0, [pc, #60] ; (8001184 ) + 8001148: f003 fb56 bl 80047f8 + while(1); + 800114c: e7fe b.n 800114c + } + printf("Done!!!\r\n"); + 800114e: 480e ldr r0, [pc, #56] ; (8001188 ) + 8001150: f003 fb52 bl 80047f8 +} + 8001154: bf00 nop + 8001156: 374c adds r7, #76 ; 0x4c + 8001158: 46bd mov sp, r7 + 800115a: bdf0 pop {r4, r5, r6, r7, pc} + 800115c: 20000000 .word 0x20000000 + 8001160: 080058e4 .word 0x080058e4 + 8001164: 080c0000 .word 0x080c0000 + 8001168: 08140000 .word 0x08140000 + 800116c: 08005918 .word 0x08005918 + 8001170: 08005930 .word 0x08005930 + 8001174: 0800594c .word 0x0800594c + 8001178: 08040000 .word 0x08040000 + 800117c: 2000053c .word 0x2000053c + 8001180: 0800596c .word 0x0800596c + 8001184: 08005978 .word 0x08005978 + 8001188: 0800578c .word 0x0800578c + +0800118c : + * @brief Write the configuration to flash + * @param cfg config structure + * @retval none + */ +static HAL_StatusTypeDef write_cfg_to_flash( ETX_GNRL_CFG_ *cfg ) +{ + 800118c: b580 push {r7, lr} + 800118e: b08c sub sp, #48 ; 0x30 + 8001190: af00 add r7, sp, #0 + 8001192: 6078 str r0, [r7, #4] + HAL_StatusTypeDef ret; + + do + { + if( cfg == NULL ) + 8001194: 687b ldr r3, [r7, #4] + 8001196: 2b00 cmp r3, #0 + 8001198: d103 bne.n 80011a2 + { + ret = HAL_ERROR; + 800119a: 2301 movs r3, #1 + 800119c: f887 302f strb.w r3, [r7, #47] ; 0x2f + break; + 80011a0: e05f b.n 8001262 + } + + ret = HAL_FLASH_Unlock(); + 80011a2: f001 f80b bl 80021bc + 80011a6: 4603 mov r3, r0 + 80011a8: f887 302f strb.w r3, [r7, #47] ; 0x2f + if( ret != HAL_OK ) + 80011ac: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 80011b0: 2b00 cmp r3, #0 + 80011b2: d151 bne.n 8001258 + { + break; + } + + //Check if the FLASH_FLAG_BSY. + FLASH_WaitForLastOperation( HAL_MAX_DELAY ); + 80011b4: f04f 30ff mov.w r0, #4294967295 + 80011b8: f001 f832 bl 8002220 + + //Erase the Flash + FLASH_EraseInitTypeDef EraseInitStruct; + uint32_t SectorError; + + EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS; + 80011bc: 2300 movs r3, #0 + 80011be: 613b str r3, [r7, #16] + EraseInitStruct.Sector = FLASH_SECTOR_4; + 80011c0: 2304 movs r3, #4 + 80011c2: 61bb str r3, [r7, #24] + EraseInitStruct.NbSectors = 1; //erase only sector 4 + 80011c4: 2301 movs r3, #1 + 80011c6: 61fb str r3, [r7, #28] + EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3; + 80011c8: 2302 movs r3, #2 + 80011ca: 623b str r3, [r7, #32] + + // clear all flags before you write it to flash + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | + 80011cc: 4b28 ldr r3, [pc, #160] ; (8001270 ) + 80011ce: 2273 movs r2, #115 ; 0x73 + 80011d0: 60da str r2, [r3, #12] + FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR); + + ret = HAL_FLASHEx_Erase( &EraseInitStruct, &SectorError ); + 80011d2: f107 020c add.w r2, r7, #12 + 80011d6: f107 0310 add.w r3, r7, #16 + 80011da: 4611 mov r1, r2 + 80011dc: 4618 mov r0, r3 + 80011de: f001 f94f bl 8002480 + 80011e2: 4603 mov r3, r0 + 80011e4: f887 302f strb.w r3, [r7, #47] ; 0x2f + if( ret != HAL_OK ) + 80011e8: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 80011ec: 2b00 cmp r3, #0 + 80011ee: d135 bne.n 800125c + { break; - 8000abc: bf00 nop + } + + //write the configuration + uint8_t *data = (uint8_t *) cfg; + 80011f0: 687b ldr r3, [r7, #4] + 80011f2: 627b str r3, [r7, #36] ; 0x24 + for( uint32_t i = 0u; i < sizeof(ETX_GNRL_CFG_); i++ ) + 80011f4: 2300 movs r3, #0 + 80011f6: 62bb str r3, [r7, #40] ; 0x28 + 80011f8: e01a b.n 8001230 + { + ret = HAL_FLASH_Program( FLASH_TYPEPROGRAM_BYTE, + 80011fa: 6abb ldr r3, [r7, #40] ; 0x28 + 80011fc: 491d ldr r1, [pc, #116] ; (8001274 ) + 80011fe: 4419 add r1, r3 + ETX_CONFIG_FLASH_ADDR + i, + data[i] + 8001200: 6a7a ldr r2, [r7, #36] ; 0x24 + 8001202: 6abb ldr r3, [r7, #40] ; 0x28 + 8001204: 4413 add r3, r2 + 8001206: 781b ldrb r3, [r3, #0] + ret = HAL_FLASH_Program( FLASH_TYPEPROGRAM_BYTE, + 8001208: b2da uxtb r2, r3 + 800120a: f04f 0300 mov.w r3, #0 + 800120e: 2000 movs r0, #0 + 8001210: f000 ff78 bl 8002104 + 8001214: 4603 mov r3, r0 + 8001216: f887 302f strb.w r3, [r7, #47] ; 0x2f + ); + if( ret != HAL_OK ) + 800121a: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 800121e: 2b00 cmp r3, #0 + 8001220: d003 beq.n 800122a + { + printf("Slot table Flash Write Error\r\n"); + 8001222: 4815 ldr r0, [pc, #84] ; (8001278 ) + 8001224: f003 fae8 bl 80047f8 + break; + 8001228: e005 b.n 8001236 + for( uint32_t i = 0u; i < sizeof(ETX_GNRL_CFG_); i++ ) + 800122a: 6abb ldr r3, [r7, #40] ; 0x28 + 800122c: 3301 adds r3, #1 + 800122e: 62bb str r3, [r7, #40] ; 0x28 + 8001230: 6abb ldr r3, [r7, #40] ; 0x28 + 8001232: 2b31 cmp r3, #49 ; 0x31 + 8001234: d9e1 bls.n 80011fa + } + } + + //Check if the FLASH_FLAG_BSY. + FLASH_WaitForLastOperation( HAL_MAX_DELAY ); + 8001236: f04f 30ff mov.w r0, #4294967295 + 800123a: f000 fff1 bl 8002220 + + if( ret != HAL_OK ) + 800123e: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 8001242: 2b00 cmp r3, #0 + 8001244: d10c bne.n 8001260 + { + break; + } + + ret = HAL_FLASH_Lock(); + 8001246: f000 ffdb bl 8002200 + 800124a: 4603 mov r3, r0 + 800124c: f887 302f strb.w r3, [r7, #47] ; 0x2f + if( ret != HAL_OK ) + 8001250: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 8001254: 2b00 cmp r3, #0 + 8001256: e004 b.n 8001262 + break; + 8001258: bf00 nop + 800125a: e002 b.n 8001262 + break; + 800125c: bf00 nop + 800125e: e000 b.n 8001262 + break; + 8001260: bf00 nop { break; } }while( false ); return ret; - 8000abe: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8001262: f897 302f ldrb.w r3, [r7, #47] ; 0x2f } - 8000ac2: 4618 mov r0, r3 - 8000ac4: 3728 adds r7, #40 ; 0x28 - 8000ac6: 46bd mov sp, r7 - 8000ac8: bd80 pop {r7, pc} - 8000aca: bf00 nop - 8000acc: 08004ae8 .word 0x08004ae8 - 8000ad0: 200004a0 .word 0x200004a0 - 8000ad4: 08040000 .word 0x08040000 - 8000ad8: 08004b08 .word 0x08004b08 - -08000adc
: + 8001266: 4618 mov r0, r3 + 8001268: 3730 adds r7, #48 ; 0x30 + 800126a: 46bd mov sp, r7 + 800126c: bd80 pop {r7, pc} + 800126e: bf00 nop + 8001270: 40023c00 .word 0x40023c00 + 8001274: 08020000 .word 0x08020000 + 8001278: 08005998 .word 0x08005998 + +0800127c
: /** * @brief The application entry point. * @retval int */ int main(void) { - 8000adc: b580 push {r7, lr} - 8000ade: b084 sub sp, #16 - 8000ae0: af00 add r7, sp, #0 + 800127c: b580 push {r7, lr} + 800127e: b086 sub sp, #24 + 8001280: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); - 8000ae2: f000 fb5c bl 800119e + 8001282: f000 fbe4 bl 8001a4e /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); - 8000ae6: f000 f851 bl 8000b8c + 8001286: f000 f897 bl 80013b8 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); - 8000aea: f000 f92b bl 8000d44 + 800128a: f000 f993 bl 80015b4 MX_USART3_UART_Init(); - 8000aee: f000 f8f9 bl 8000ce4 + 800128e: f000 f961 bl 8001554 MX_USART2_UART_Init(); - 8000af2: f000 f8c7 bl 8000c84 + 8001292: f000 f92f bl 80014f4 + MX_CRC_Init(); + 8001296: f000 f90b bl 80014b0 /* USER CODE BEGIN 2 */ // Turn ON the Green Led to tell the user that Bootloader is running HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_SET ); //Green LED ON - 8000af6: 2201 movs r2, #1 - 8000af8: 2101 movs r1, #1 - 8000afa: 481d ldr r0, [pc, #116] ; (8000b70 ) - 8000afc: f001 f92c bl 8001d58 + 800129a: 2201 movs r2, #1 + 800129c: 2101 movs r1, #1 + 800129e: 4837 ldr r0, [pc, #220] ; (800137c ) + 80012a0: f001 fbb0 bl 8002a04 printf("Starting Bootloader(%d.%d)\r\n", BL_Version[0], BL_Version[1] ); - 8000b00: 2300 movs r3, #0 - 8000b02: 2202 movs r2, #2 - 8000b04: 4619 mov r1, r3 - 8000b06: 481b ldr r0, [pc, #108] ; (8000b74 ) - 8000b08: f002 ff9a bl 8003a40 + 80012a4: 2300 movs r3, #0 + 80012a6: 2203 movs r2, #3 + 80012a8: 4619 mov r1, r3 + 80012aa: 4835 ldr r0, [pc, #212] ; (8001380 ) + 80012ac: f003 fa1e bl 80046ec //HAL_Delay(2000); //2sec delay for nothing + + //Read the reboot cause and act accordingly + printf("Reading the reboot reason...\r\n"); + 80012b0: 4834 ldr r0, [pc, #208] ; (8001384 ) + 80012b2: f003 faa1 bl 80047f8 + + ETX_GNRL_CFG_ *cfg = (ETX_GNRL_CFG_*) (ETX_CONFIG_FLASH_ADDR); + 80012b6: 4b34 ldr r3, [pc, #208] ; (8001388 ) + 80012b8: 613b str r3, [r7, #16] + bool goto_ota_mode = false; + 80012ba: 2300 movs r3, #0 + 80012bc: 75fb strb r3, [r7, #23] + + switch( cfg->reboot_cause ) + 80012be: 693b ldr r3, [r7, #16] + 80012c0: 681b ldr r3, [r3, #0] + 80012c2: f1b3 3fff cmp.w r3, #4294967295 + 80012c6: d010 beq.n 80012ea + 80012c8: 4a30 ldr r2, [pc, #192] ; (800138c ) + 80012ca: 4293 cmp r3, r2 + 80012cc: d016 beq.n 80012fc + 80012ce: 4a2f ldr r2, [pc, #188] ; (800138c ) + 80012d0: 4293 cmp r3, r2 + 80012d2: d815 bhi.n 8001300 + 80012d4: 4a2e ldr r2, [pc, #184] ; (8001390 ) + 80012d6: 4293 cmp r3, r2 + 80012d8: d003 beq.n 80012e2 + 80012da: 4a2e ldr r2, [pc, #184] ; (8001394 ) + 80012dc: 4293 cmp r3, r2 + 80012de: d004 beq.n 80012ea + //TODO: Implement + break; + } + default: + /* should not get here */ + break; + 80012e0: e00e b.n 8001300 + printf("Normal Boot\r\n"); + 80012e2: 482d ldr r0, [pc, #180] ; (8001398 ) + 80012e4: f003 fa88 bl 80047f8 + break; + 80012e8: e00b b.n 8001302 + printf("First time boot / OTA Request...\r\n"); + 80012ea: 482c ldr r0, [pc, #176] ; (800139c ) + 80012ec: f003 fa84 bl 80047f8 + printf("Going to OTA mode...\r\n"); + 80012f0: 482b ldr r0, [pc, #172] ; (80013a0 ) + 80012f2: f003 fa81 bl 80047f8 + goto_ota_mode = true; + 80012f6: 2301 movs r3, #1 + 80012f8: 75fb strb r3, [r7, #23] + break; + 80012fa: e002 b.n 8001302 + break; + 80012fc: bf00 nop + 80012fe: e000 b.n 8001302 + break; + 8001300: bf00 nop + }; + /* Check the GPIO for 3 seconds */ GPIO_PinState OTA_Pin_state; uint32_t end_tick = HAL_GetTick() + 3000; // from now to 3 Seconds - 8000b0c: f000 fb98 bl 8001240 - 8000b10: 4603 mov r3, r0 - 8000b12: f603 33b8 addw r3, r3, #3000 ; 0xbb8 - 8000b16: 60fb str r3, [r7, #12] + 8001302: f000 fbf5 bl 8001af0 + 8001306: 4603 mov r3, r0 + 8001308: f603 33b8 addw r3, r3, #3000 ; 0xbb8 + 800130c: 60fb str r3, [r7, #12] printf("Press the User Button PC13 to trigger OTA update...\r\n"); - 8000b18: 4817 ldr r0, [pc, #92] ; (8000b78 ) - 8000b1a: f003 f817 bl 8003b4c + 800130e: 4825 ldr r0, [pc, #148] ; (80013a4 ) + 8001310: f003 fa72 bl 80047f8 do { OTA_Pin_state = HAL_GPIO_ReadPin( GPIOC, GPIO_PIN_13 ); - 8000b1e: f44f 5100 mov.w r1, #8192 ; 0x2000 - 8000b22: 4816 ldr r0, [pc, #88] ; (8000b7c ) - 8000b24: f001 f900 bl 8001d28 - 8000b28: 4603 mov r3, r0 - 8000b2a: 72fb strb r3, [r7, #11] + 8001314: f44f 5100 mov.w r1, #8192 ; 0x2000 + 8001318: 4823 ldr r0, [pc, #140] ; (80013a8 ) + 800131a: f001 fb5b bl 80029d4 + 800131e: 4603 mov r3, r0 + 8001320: 72fb strb r3, [r7, #11] uint32_t current_tick = HAL_GetTick(); - 8000b2c: f000 fb88 bl 8001240 - 8000b30: 6078 str r0, [r7, #4] + 8001322: f000 fbe5 bl 8001af0 + 8001326: 6078 str r0, [r7, #4] /* Check the button is pressed or not for 3seconds */ if( ( OTA_Pin_state != GPIO_PIN_RESET ) || ( current_tick > end_tick ) ) - 8000b32: 7afb ldrb r3, [r7, #11] - 8000b34: 2b00 cmp r3, #0 - 8000b36: d104 bne.n 8000b42 - 8000b38: 687a ldr r2, [r7, #4] - 8000b3a: 68fb ldr r3, [r7, #12] - 8000b3c: 429a cmp r2, r3 - 8000b3e: d800 bhi.n 8000b42 - { - 8000b40: e7ed b.n 8000b1e + 8001328: 7afb ldrb r3, [r7, #11] + 800132a: 2b00 cmp r3, #0 + 800132c: d109 bne.n 8001342 + 800132e: 687a ldr r2, [r7, #4] + 8001330: 68fb ldr r3, [r7, #12] + 8001332: 429a cmp r2, r3 + 8001334: d805 bhi.n 8001342 + { + /* Either timeout or Button is pressed */ break; } - }while( 1 ); + }while( !goto_ota_mode ); + 8001336: 7dfb ldrb r3, [r7, #23] + 8001338: f083 0301 eor.w r3, r3, #1 + 800133c: b2db uxtb r3, r3 + 800133e: 2b00 cmp r3, #0 + 8001340: d1e8 bne.n 8001314 /*Start the Firmware or Application update */ - if( OTA_Pin_state == GPIO_PIN_SET ) - 8000b42: 7afb ldrb r3, [r7, #11] - 8000b44: 2b01 cmp r3, #1 - 8000b46: d110 bne.n 8000b6a + if( ( OTA_Pin_state == GPIO_PIN_SET ) || ( goto_ota_mode ) ) + 8001342: 7afb ldrb r3, [r7, #11] + 8001344: 2b01 cmp r3, #1 + 8001346: d002 beq.n 800134e + 8001348: 7dfb ldrb r3, [r7, #23] + 800134a: 2b00 cmp r3, #0 + 800134c: d010 beq.n 8001370 { printf("Starting Firmware Download!!!\r\n"); - 8000b48: 480d ldr r0, [pc, #52] ; (8000b80 ) - 8000b4a: f002 ffff bl 8003b4c + 800134e: 4817 ldr r0, [pc, #92] ; (80013ac ) + 8001350: f003 fa52 bl 80047f8 /* OTA Request. Receive the data from the UART4 and flash */ if( etx_ota_download_and_flash() != ETX_OTA_EX_OK ) - 8000b4e: f7ff fd43 bl 80005d8 - 8000b52: 4603 mov r3, r0 - 8000b54: 2b00 cmp r3, #0 - 8000b56: d003 beq.n 8000b60 + 8001354: f7ff f940 bl 80005d8 + 8001358: 4603 mov r3, r0 + 800135a: 2b00 cmp r3, #0 + 800135c: d003 beq.n 8001366 { /* Error. Don't process. */ printf("OTA Update : ERROR!!! HALT!!!\r\n"); - 8000b58: 480a ldr r0, [pc, #40] ; (8000b84 ) - 8000b5a: f002 fff7 bl 8003b4c + 800135e: 4814 ldr r0, [pc, #80] ; (80013b0 ) + 8001360: f003 fa4a bl 80047f8 while( 1 ); - 8000b5e: e7fe b.n 8000b5e + 8001364: e7fe b.n 8001364 } else { /* Reset to load the new application */ printf("Firmware update is done!!! Rebooting...\r\n"); - 8000b60: 4809 ldr r0, [pc, #36] ; (8000b88 ) - 8000b62: f002 fff3 bl 8003b4c + 8001366: 4813 ldr r0, [pc, #76] ; (80013b4 ) + 8001368: f003 fa46 bl 80047f8 HAL_NVIC_SystemReset(); - 8000b66: f000 fc66 bl 8001436 + 800136c: f000 fcbb bl 8001ce6 } } + //Load the updated app, if it is available + load_new_app(); + 8001370: f7ff fde2 bl 8000f38 + // Jump to application goto_application(); - 8000b6a: f000 f957 bl 8000e1c + 8001374: f000 f98a bl 800168c /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) - 8000b6e: e7fe b.n 8000b6e - 8000b70: 40020400 .word 0x40020400 - 8000b74: 08004b1c .word 0x08004b1c - 8000b78: 08004b3c .word 0x08004b3c - 8000b7c: 40020800 .word 0x40020800 - 8000b80: 08004b74 .word 0x08004b74 - 8000b84: 08004b94 .word 0x08004b94 - 8000b88: 08004bb4 .word 0x08004bb4 - -08000b8c : + 8001378: e7fe b.n 8001378 + 800137a: bf00 nop + 800137c: 40020400 .word 0x40020400 + 8001380: 080059b8 .word 0x080059b8 + 8001384: 080059d8 .word 0x080059d8 + 8001388: 08020000 .word 0x08020000 + 800138c: facefade .word 0xfacefade + 8001390: beeffeed .word 0xbeeffeed + 8001394: deadbeef .word 0xdeadbeef + 8001398: 080059f8 .word 0x080059f8 + 800139c: 08005a08 .word 0x08005a08 + 80013a0: 08005a2c .word 0x08005a2c + 80013a4: 08005a44 .word 0x08005a44 + 80013a8: 40020800 .word 0x40020800 + 80013ac: 08005a7c .word 0x08005a7c + 80013b0: 08005a9c .word 0x08005a9c + 80013b4: 08005abc .word 0x08005abc + +080013b8 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { - 8000b8c: b580 push {r7, lr} - 8000b8e: b0b8 sub sp, #224 ; 0xe0 - 8000b90: af00 add r7, sp, #0 + 80013b8: b580 push {r7, lr} + 80013ba: b0b8 sub sp, #224 ; 0xe0 + 80013bc: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - 8000b92: f107 03ac add.w r3, r7, #172 ; 0xac - 8000b96: 2234 movs r2, #52 ; 0x34 - 8000b98: 2100 movs r1, #0 - 8000b9a: 4618 mov r0, r3 - 8000b9c: f002 ff48 bl 8003a30 + 80013be: f107 03ac add.w r3, r7, #172 ; 0xac + 80013c2: 2234 movs r2, #52 ; 0x34 + 80013c4: 2100 movs r1, #0 + 80013c6: 4618 mov r0, r3 + 80013c8: f003 f988 bl 80046dc RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - 8000ba0: f107 0398 add.w r3, r7, #152 ; 0x98 - 8000ba4: 2200 movs r2, #0 - 8000ba6: 601a str r2, [r3, #0] - 8000ba8: 605a str r2, [r3, #4] - 8000baa: 609a str r2, [r3, #8] - 8000bac: 60da str r2, [r3, #12] - 8000bae: 611a str r2, [r3, #16] + 80013cc: f107 0398 add.w r3, r7, #152 ; 0x98 + 80013d0: 2200 movs r2, #0 + 80013d2: 601a str r2, [r3, #0] + 80013d4: 605a str r2, [r3, #4] + 80013d6: 609a str r2, [r3, #8] + 80013d8: 60da str r2, [r3, #12] + 80013da: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - 8000bb0: f107 0308 add.w r3, r7, #8 - 8000bb4: 2290 movs r2, #144 ; 0x90 - 8000bb6: 2100 movs r1, #0 - 8000bb8: 4618 mov r0, r3 - 8000bba: f002 ff39 bl 8003a30 + 80013dc: f107 0308 add.w r3, r7, #8 + 80013e0: 2290 movs r2, #144 ; 0x90 + 80013e2: 2100 movs r1, #0 + 80013e4: 4618 mov r0, r3 + 80013e6: f003 f979 bl 80046dc /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); - 8000bbe: 4b2f ldr r3, [pc, #188] ; (8000c7c ) - 8000bc0: 6c1b ldr r3, [r3, #64] ; 0x40 - 8000bc2: 4a2e ldr r2, [pc, #184] ; (8000c7c ) - 8000bc4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 8000bc8: 6413 str r3, [r2, #64] ; 0x40 - 8000bca: 4b2c ldr r3, [pc, #176] ; (8000c7c ) - 8000bcc: 6c1b ldr r3, [r3, #64] ; 0x40 - 8000bce: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8000bd2: 607b str r3, [r7, #4] - 8000bd4: 687b ldr r3, [r7, #4] + 80013ea: 4b2f ldr r3, [pc, #188] ; (80014a8 ) + 80013ec: 6c1b ldr r3, [r3, #64] ; 0x40 + 80013ee: 4a2e ldr r2, [pc, #184] ; (80014a8 ) + 80013f0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 80013f4: 6413 str r3, [r2, #64] ; 0x40 + 80013f6: 4b2c ldr r3, [pc, #176] ; (80014a8 ) + 80013f8: 6c1b ldr r3, [r3, #64] ; 0x40 + 80013fa: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 80013fe: 607b str r3, [r7, #4] + 8001400: 687b ldr r3, [r7, #4] __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); - 8000bd6: 4b2a ldr r3, [pc, #168] ; (8000c80 ) - 8000bd8: 681b ldr r3, [r3, #0] - 8000bda: f423 4340 bic.w r3, r3, #49152 ; 0xc000 - 8000bde: 4a28 ldr r2, [pc, #160] ; (8000c80 ) - 8000be0: f443 4380 orr.w r3, r3, #16384 ; 0x4000 - 8000be4: 6013 str r3, [r2, #0] - 8000be6: 4b26 ldr r3, [pc, #152] ; (8000c80 ) - 8000be8: 681b ldr r3, [r3, #0] - 8000bea: f403 4340 and.w r3, r3, #49152 ; 0xc000 - 8000bee: 603b str r3, [r7, #0] - 8000bf0: 683b ldr r3, [r7, #0] + 8001402: 4b2a ldr r3, [pc, #168] ; (80014ac ) + 8001404: 681b ldr r3, [r3, #0] + 8001406: f423 4340 bic.w r3, r3, #49152 ; 0xc000 + 800140a: 4a28 ldr r2, [pc, #160] ; (80014ac ) + 800140c: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 8001410: 6013 str r3, [r2, #0] + 8001412: 4b26 ldr r3, [pc, #152] ; (80014ac ) + 8001414: 681b ldr r3, [r3, #0] + 8001416: f403 4340 and.w r3, r3, #49152 ; 0xc000 + 800141a: 603b str r3, [r7, #0] + 800141c: 683b ldr r3, [r7, #0] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - 8000bf2: 2302 movs r3, #2 - 8000bf4: f8c7 30ac str.w r3, [r7, #172] ; 0xac + 800141e: 2302 movs r3, #2 + 8001420: f8c7 30ac str.w r3, [r7, #172] ; 0xac RCC_OscInitStruct.HSIState = RCC_HSI_ON; - 8000bf8: 2301 movs r3, #1 - 8000bfa: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 + 8001424: 2301 movs r3, #1 + 8001426: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - 8000bfe: 2310 movs r3, #16 - 8000c00: f8c7 30bc str.w r3, [r7, #188] ; 0xbc + 800142a: 2310 movs r3, #16 + 800142c: f8c7 30bc str.w r3, [r7, #188] ; 0xbc RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - 8000c04: 2300 movs r3, #0 - 8000c06: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 + 8001430: 2300 movs r3, #0 + 8001432: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - 8000c0a: f107 03ac add.w r3, r7, #172 ; 0xac - 8000c0e: 4618 mov r0, r3 - 8000c10: f001 f8bc bl 8001d8c - 8000c14: 4603 mov r3, r0 - 8000c16: 2b00 cmp r3, #0 - 8000c18: d001 beq.n 8000c1e + 8001436: f107 03ac add.w r3, r7, #172 ; 0xac + 800143a: 4618 mov r0, r3 + 800143c: f001 fafc bl 8002a38 + 8001440: 4603 mov r3, r0 + 8001442: 2b00 cmp r3, #0 + 8001444: d001 beq.n 800144a { Error_Handler(); - 8000c1a: f000 f919 bl 8000e50 + 8001446: f000 f93b bl 80016c0 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - 8000c1e: 230f movs r3, #15 - 8000c20: f8c7 3098 str.w r3, [r7, #152] ; 0x98 + 800144a: 230f movs r3, #15 + 800144c: f8c7 3098 str.w r3, [r7, #152] ; 0x98 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; - 8000c24: 2300 movs r3, #0 - 8000c26: f8c7 309c str.w r3, [r7, #156] ; 0x9c + 8001450: 2300 movs r3, #0 + 8001452: f8c7 309c str.w r3, [r7, #156] ; 0x9c RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - 8000c2a: 2300 movs r3, #0 - 8000c2c: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 + 8001456: 2300 movs r3, #0 + 8001458: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - 8000c30: 2300 movs r3, #0 - 8000c32: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 + 800145c: 2300 movs r3, #0 + 800145e: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - 8000c36: 2300 movs r3, #0 - 8000c38: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 + 8001462: 2300 movs r3, #0 + 8001464: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) - 8000c3c: f107 0398 add.w r3, r7, #152 ; 0x98 - 8000c40: 2100 movs r1, #0 - 8000c42: 4618 mov r0, r3 - 8000c44: f001 fb50 bl 80022e8 - 8000c48: 4603 mov r3, r0 - 8000c4a: 2b00 cmp r3, #0 - 8000c4c: d001 beq.n 8000c52 + 8001468: f107 0398 add.w r3, r7, #152 ; 0x98 + 800146c: 2100 movs r1, #0 + 800146e: 4618 mov r0, r3 + 8001470: f001 fd90 bl 8002f94 + 8001474: 4603 mov r3, r0 + 8001476: 2b00 cmp r3, #0 + 8001478: d001 beq.n 800147e { Error_Handler(); - 8000c4e: f000 f8ff bl 8000e50 + 800147a: f000 f921 bl 80016c0 } PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART2|RCC_PERIPHCLK_USART3; - 8000c52: f44f 73c0 mov.w r3, #384 ; 0x180 - 8000c56: 60bb str r3, [r7, #8] + 800147e: f44f 73c0 mov.w r3, #384 ; 0x180 + 8001482: 60bb str r3, [r7, #8] PeriphClkInitStruct.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; - 8000c58: 2300 movs r3, #0 - 8000c5a: 653b str r3, [r7, #80] ; 0x50 + 8001484: 2300 movs r3, #0 + 8001486: 653b str r3, [r7, #80] ; 0x50 PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; - 8000c5c: 2300 movs r3, #0 - 8000c5e: 657b str r3, [r7, #84] ; 0x54 + 8001488: 2300 movs r3, #0 + 800148a: 657b str r3, [r7, #84] ; 0x54 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - 8000c60: f107 0308 add.w r3, r7, #8 - 8000c64: 4618 mov r0, r3 - 8000c66: f001 fd15 bl 8002694 - 8000c6a: 4603 mov r3, r0 - 8000c6c: 2b00 cmp r3, #0 - 8000c6e: d001 beq.n 8000c74 + 800148c: f107 0308 add.w r3, r7, #8 + 8001490: 4618 mov r0, r3 + 8001492: f001 ff55 bl 8003340 + 8001496: 4603 mov r3, r0 + 8001498: 2b00 cmp r3, #0 + 800149a: d001 beq.n 80014a0 { Error_Handler(); - 8000c70: f000 f8ee bl 8000e50 + 800149c: f000 f910 bl 80016c0 } } - 8000c74: bf00 nop - 8000c76: 37e0 adds r7, #224 ; 0xe0 - 8000c78: 46bd mov sp, r7 - 8000c7a: bd80 pop {r7, pc} - 8000c7c: 40023800 .word 0x40023800 - 8000c80: 40007000 .word 0x40007000 - -08000c84 : + 80014a0: bf00 nop + 80014a2: 37e0 adds r7, #224 ; 0xe0 + 80014a4: 46bd mov sp, r7 + 80014a6: bd80 pop {r7, pc} + 80014a8: 40023800 .word 0x40023800 + 80014ac: 40007000 .word 0x40007000 + +080014b0 : + * @brief CRC Initialization Function + * @param None + * @retval None + */ +static void MX_CRC_Init(void) +{ + 80014b0: b580 push {r7, lr} + 80014b2: af00 add r7, sp, #0 + /* USER CODE END CRC_Init 0 */ + + /* USER CODE BEGIN CRC_Init 1 */ + + /* USER CODE END CRC_Init 1 */ + hcrc.Instance = CRC; + 80014b4: 4b0d ldr r3, [pc, #52] ; (80014ec ) + 80014b6: 4a0e ldr r2, [pc, #56] ; (80014f0 ) + 80014b8: 601a str r2, [r3, #0] + hcrc.Init.DefaultPolynomialUse = DEFAULT_POLYNOMIAL_ENABLE; + 80014ba: 4b0c ldr r3, [pc, #48] ; (80014ec ) + 80014bc: 2200 movs r2, #0 + 80014be: 711a strb r2, [r3, #4] + hcrc.Init.DefaultInitValueUse = DEFAULT_INIT_VALUE_ENABLE; + 80014c0: 4b0a ldr r3, [pc, #40] ; (80014ec ) + 80014c2: 2200 movs r2, #0 + 80014c4: 715a strb r2, [r3, #5] + hcrc.Init.InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE; + 80014c6: 4b09 ldr r3, [pc, #36] ; (80014ec ) + 80014c8: 2200 movs r2, #0 + 80014ca: 615a str r2, [r3, #20] + hcrc.Init.OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE; + 80014cc: 4b07 ldr r3, [pc, #28] ; (80014ec ) + 80014ce: 2200 movs r2, #0 + 80014d0: 619a str r2, [r3, #24] + hcrc.InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES; + 80014d2: 4b06 ldr r3, [pc, #24] ; (80014ec ) + 80014d4: 2201 movs r2, #1 + 80014d6: 621a str r2, [r3, #32] + if (HAL_CRC_Init(&hcrc) != HAL_OK) + 80014d8: 4804 ldr r0, [pc, #16] ; (80014ec ) + 80014da: f000 fc15 bl 8001d08 + 80014de: 4603 mov r3, r0 + 80014e0: 2b00 cmp r3, #0 + 80014e2: d001 beq.n 80014e8 + { + Error_Handler(); + 80014e4: f000 f8ec bl 80016c0 + } + /* USER CODE BEGIN CRC_Init 2 */ + + /* USER CODE END CRC_Init 2 */ + +} + 80014e8: bf00 nop + 80014ea: bd80 pop {r7, pc} + 80014ec: 2000053c .word 0x2000053c + 80014f0: 40023000 .word 0x40023000 + +080014f4 : * @brief USART2 Initialization Function * @param None * @retval None */ static void MX_USART2_UART_Init(void) { - 8000c84: b580 push {r7, lr} - 8000c86: af00 add r7, sp, #0 + 80014f4: b580 push {r7, lr} + 80014f6: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; - 8000c88: 4b14 ldr r3, [pc, #80] ; (8000cdc ) - 8000c8a: 4a15 ldr r2, [pc, #84] ; (8000ce0 ) - 8000c8c: 601a str r2, [r3, #0] + 80014f8: 4b14 ldr r3, [pc, #80] ; (800154c ) + 80014fa: 4a15 ldr r2, [pc, #84] ; (8001550 ) + 80014fc: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; - 8000c8e: 4b13 ldr r3, [pc, #76] ; (8000cdc ) - 8000c90: f44f 32e1 mov.w r2, #115200 ; 0x1c200 - 8000c94: 605a str r2, [r3, #4] + 80014fe: 4b13 ldr r3, [pc, #76] ; (800154c ) + 8001500: f44f 32e1 mov.w r2, #115200 ; 0x1c200 + 8001504: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; - 8000c96: 4b11 ldr r3, [pc, #68] ; (8000cdc ) - 8000c98: 2200 movs r2, #0 - 8000c9a: 609a str r2, [r3, #8] + 8001506: 4b11 ldr r3, [pc, #68] ; (800154c ) + 8001508: 2200 movs r2, #0 + 800150a: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; - 8000c9c: 4b0f ldr r3, [pc, #60] ; (8000cdc ) - 8000c9e: 2200 movs r2, #0 - 8000ca0: 60da str r2, [r3, #12] + 800150c: 4b0f ldr r3, [pc, #60] ; (800154c ) + 800150e: 2200 movs r2, #0 + 8001510: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; - 8000ca2: 4b0e ldr r3, [pc, #56] ; (8000cdc ) - 8000ca4: 2200 movs r2, #0 - 8000ca6: 611a str r2, [r3, #16] + 8001512: 4b0e ldr r3, [pc, #56] ; (800154c ) + 8001514: 2200 movs r2, #0 + 8001516: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; - 8000ca8: 4b0c ldr r3, [pc, #48] ; (8000cdc ) - 8000caa: 220c movs r2, #12 - 8000cac: 615a str r2, [r3, #20] + 8001518: 4b0c ldr r3, [pc, #48] ; (800154c ) + 800151a: 220c movs r2, #12 + 800151c: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; - 8000cae: 4b0b ldr r3, [pc, #44] ; (8000cdc ) - 8000cb0: 2200 movs r2, #0 - 8000cb2: 619a str r2, [r3, #24] + 800151e: 4b0b ldr r3, [pc, #44] ; (800154c ) + 8001520: 2200 movs r2, #0 + 8001522: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; - 8000cb4: 4b09 ldr r3, [pc, #36] ; (8000cdc ) - 8000cb6: 2200 movs r2, #0 - 8000cb8: 61da str r2, [r3, #28] + 8001524: 4b09 ldr r3, [pc, #36] ; (800154c ) + 8001526: 2200 movs r2, #0 + 8001528: 61da str r2, [r3, #28] huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - 8000cba: 4b08 ldr r3, [pc, #32] ; (8000cdc ) - 8000cbc: 2200 movs r2, #0 - 8000cbe: 621a str r2, [r3, #32] + 800152a: 4b08 ldr r3, [pc, #32] ; (800154c ) + 800152c: 2200 movs r2, #0 + 800152e: 621a str r2, [r3, #32] huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - 8000cc0: 4b06 ldr r3, [pc, #24] ; (8000cdc ) - 8000cc2: 2200 movs r2, #0 - 8000cc4: 625a str r2, [r3, #36] ; 0x24 + 8001530: 4b06 ldr r3, [pc, #24] ; (800154c ) + 8001532: 2200 movs r2, #0 + 8001534: 625a str r2, [r3, #36] ; 0x24 if (HAL_UART_Init(&huart2) != HAL_OK) - 8000cc6: 4805 ldr r0, [pc, #20] ; (8000cdc ) - 8000cc8: f002 f90c bl 8002ee4 - 8000ccc: 4603 mov r3, r0 - 8000cce: 2b00 cmp r3, #0 - 8000cd0: d001 beq.n 8000cd6 + 8001536: 4805 ldr r0, [pc, #20] ; (800154c ) + 8001538: f002 fb2a bl 8003b90 + 800153c: 4603 mov r3, r0 + 800153e: 2b00 cmp r3, #0 + 8001540: d001 beq.n 8001546 { Error_Handler(); - 8000cd2: f000 f8bd bl 8000e50 + 8001542: f000 f8bd bl 80016c0 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } - 8000cd6: bf00 nop - 8000cd8: bd80 pop {r7, pc} - 8000cda: bf00 nop - 8000cdc: 20000534 .word 0x20000534 - 8000ce0: 40004400 .word 0x40004400 + 8001546: bf00 nop + 8001548: bd80 pop {r7, pc} + 800154a: bf00 nop + 800154c: 20000560 .word 0x20000560 + 8001550: 40004400 .word 0x40004400 -08000ce4 : +08001554 : * @brief USART3 Initialization Function * @param None * @retval None */ static void MX_USART3_UART_Init(void) { - 8000ce4: b580 push {r7, lr} - 8000ce6: af00 add r7, sp, #0 + 8001554: b580 push {r7, lr} + 8001556: af00 add r7, sp, #0 /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; - 8000ce8: 4b14 ldr r3, [pc, #80] ; (8000d3c ) - 8000cea: 4a15 ldr r2, [pc, #84] ; (8000d40 ) - 8000cec: 601a str r2, [r3, #0] + 8001558: 4b14 ldr r3, [pc, #80] ; (80015ac ) + 800155a: 4a15 ldr r2, [pc, #84] ; (80015b0 ) + 800155c: 601a str r2, [r3, #0] huart3.Init.BaudRate = 115200; - 8000cee: 4b13 ldr r3, [pc, #76] ; (8000d3c ) - 8000cf0: f44f 32e1 mov.w r2, #115200 ; 0x1c200 - 8000cf4: 605a str r2, [r3, #4] + 800155e: 4b13 ldr r3, [pc, #76] ; (80015ac ) + 8001560: f44f 32e1 mov.w r2, #115200 ; 0x1c200 + 8001564: 605a str r2, [r3, #4] huart3.Init.WordLength = UART_WORDLENGTH_8B; - 8000cf6: 4b11 ldr r3, [pc, #68] ; (8000d3c ) - 8000cf8: 2200 movs r2, #0 - 8000cfa: 609a str r2, [r3, #8] + 8001566: 4b11 ldr r3, [pc, #68] ; (80015ac ) + 8001568: 2200 movs r2, #0 + 800156a: 609a str r2, [r3, #8] huart3.Init.StopBits = UART_STOPBITS_1; - 8000cfc: 4b0f ldr r3, [pc, #60] ; (8000d3c ) - 8000cfe: 2200 movs r2, #0 - 8000d00: 60da str r2, [r3, #12] + 800156c: 4b0f ldr r3, [pc, #60] ; (80015ac ) + 800156e: 2200 movs r2, #0 + 8001570: 60da str r2, [r3, #12] huart3.Init.Parity = UART_PARITY_NONE; - 8000d02: 4b0e ldr r3, [pc, #56] ; (8000d3c ) - 8000d04: 2200 movs r2, #0 - 8000d06: 611a str r2, [r3, #16] + 8001572: 4b0e ldr r3, [pc, #56] ; (80015ac ) + 8001574: 2200 movs r2, #0 + 8001576: 611a str r2, [r3, #16] huart3.Init.Mode = UART_MODE_TX_RX; - 8000d08: 4b0c ldr r3, [pc, #48] ; (8000d3c ) - 8000d0a: 220c movs r2, #12 - 8000d0c: 615a str r2, [r3, #20] + 8001578: 4b0c ldr r3, [pc, #48] ; (80015ac ) + 800157a: 220c movs r2, #12 + 800157c: 615a str r2, [r3, #20] huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; - 8000d0e: 4b0b ldr r3, [pc, #44] ; (8000d3c ) - 8000d10: 2200 movs r2, #0 - 8000d12: 619a str r2, [r3, #24] + 800157e: 4b0b ldr r3, [pc, #44] ; (80015ac ) + 8001580: 2200 movs r2, #0 + 8001582: 619a str r2, [r3, #24] huart3.Init.OverSampling = UART_OVERSAMPLING_16; - 8000d14: 4b09 ldr r3, [pc, #36] ; (8000d3c ) - 8000d16: 2200 movs r2, #0 - 8000d18: 61da str r2, [r3, #28] + 8001584: 4b09 ldr r3, [pc, #36] ; (80015ac ) + 8001586: 2200 movs r2, #0 + 8001588: 61da str r2, [r3, #28] huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - 8000d1a: 4b08 ldr r3, [pc, #32] ; (8000d3c ) - 8000d1c: 2200 movs r2, #0 - 8000d1e: 621a str r2, [r3, #32] + 800158a: 4b08 ldr r3, [pc, #32] ; (80015ac ) + 800158c: 2200 movs r2, #0 + 800158e: 621a str r2, [r3, #32] huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - 8000d20: 4b06 ldr r3, [pc, #24] ; (8000d3c ) - 8000d22: 2200 movs r2, #0 - 8000d24: 625a str r2, [r3, #36] ; 0x24 + 8001590: 4b06 ldr r3, [pc, #24] ; (80015ac ) + 8001592: 2200 movs r2, #0 + 8001594: 625a str r2, [r3, #36] ; 0x24 if (HAL_UART_Init(&huart3) != HAL_OK) - 8000d26: 4805 ldr r0, [pc, #20] ; (8000d3c ) - 8000d28: f002 f8dc bl 8002ee4 - 8000d2c: 4603 mov r3, r0 - 8000d2e: 2b00 cmp r3, #0 - 8000d30: d001 beq.n 8000d36 + 8001596: 4805 ldr r0, [pc, #20] ; (80015ac ) + 8001598: f002 fafa bl 8003b90 + 800159c: 4603 mov r3, r0 + 800159e: 2b00 cmp r3, #0 + 80015a0: d001 beq.n 80015a6 { Error_Handler(); - 8000d32: f000 f88d bl 8000e50 + 80015a2: f000 f88d bl 80016c0 } /* USER CODE BEGIN USART3_Init 2 */ /* USER CODE END USART3_Init 2 */ } - 8000d36: bf00 nop - 8000d38: bd80 pop {r7, pc} - 8000d3a: bf00 nop - 8000d3c: 200004b0 .word 0x200004b0 - 8000d40: 40004800 .word 0x40004800 + 80015a6: bf00 nop + 80015a8: bd80 pop {r7, pc} + 80015aa: bf00 nop + 80015ac: 200004b8 .word 0x200004b8 + 80015b0: 40004800 .word 0x40004800 -08000d44 : +080015b4 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { - 8000d44: b580 push {r7, lr} - 8000d46: b088 sub sp, #32 - 8000d48: af00 add r7, sp, #0 + 80015b4: b580 push {r7, lr} + 80015b6: b088 sub sp, #32 + 80015b8: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8000d4a: f107 030c add.w r3, r7, #12 - 8000d4e: 2200 movs r2, #0 - 8000d50: 601a str r2, [r3, #0] - 8000d52: 605a str r2, [r3, #4] - 8000d54: 609a str r2, [r3, #8] - 8000d56: 60da str r2, [r3, #12] - 8000d58: 611a str r2, [r3, #16] + 80015ba: f107 030c add.w r3, r7, #12 + 80015be: 2200 movs r2, #0 + 80015c0: 601a str r2, [r3, #0] + 80015c2: 605a str r2, [r3, #4] + 80015c4: 609a str r2, [r3, #8] + 80015c6: 60da str r2, [r3, #12] + 80015c8: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); - 8000d5a: 4b24 ldr r3, [pc, #144] ; (8000dec ) - 8000d5c: 6b1b ldr r3, [r3, #48] ; 0x30 - 8000d5e: 4a23 ldr r2, [pc, #140] ; (8000dec ) - 8000d60: f043 0304 orr.w r3, r3, #4 - 8000d64: 6313 str r3, [r2, #48] ; 0x30 - 8000d66: 4b21 ldr r3, [pc, #132] ; (8000dec ) - 8000d68: 6b1b ldr r3, [r3, #48] ; 0x30 - 8000d6a: f003 0304 and.w r3, r3, #4 - 8000d6e: 60bb str r3, [r7, #8] - 8000d70: 68bb ldr r3, [r7, #8] + 80015ca: 4b24 ldr r3, [pc, #144] ; (800165c ) + 80015cc: 6b1b ldr r3, [r3, #48] ; 0x30 + 80015ce: 4a23 ldr r2, [pc, #140] ; (800165c ) + 80015d0: f043 0304 orr.w r3, r3, #4 + 80015d4: 6313 str r3, [r2, #48] ; 0x30 + 80015d6: 4b21 ldr r3, [pc, #132] ; (800165c ) + 80015d8: 6b1b ldr r3, [r3, #48] ; 0x30 + 80015da: f003 0304 and.w r3, r3, #4 + 80015de: 60bb str r3, [r7, #8] + 80015e0: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); - 8000d72: 4b1e ldr r3, [pc, #120] ; (8000dec ) - 8000d74: 6b1b ldr r3, [r3, #48] ; 0x30 - 8000d76: 4a1d ldr r2, [pc, #116] ; (8000dec ) - 8000d78: f043 0302 orr.w r3, r3, #2 - 8000d7c: 6313 str r3, [r2, #48] ; 0x30 - 8000d7e: 4b1b ldr r3, [pc, #108] ; (8000dec ) - 8000d80: 6b1b ldr r3, [r3, #48] ; 0x30 - 8000d82: f003 0302 and.w r3, r3, #2 - 8000d86: 607b str r3, [r7, #4] - 8000d88: 687b ldr r3, [r7, #4] + 80015e2: 4b1e ldr r3, [pc, #120] ; (800165c ) + 80015e4: 6b1b ldr r3, [r3, #48] ; 0x30 + 80015e6: 4a1d ldr r2, [pc, #116] ; (800165c ) + 80015e8: f043 0302 orr.w r3, r3, #2 + 80015ec: 6313 str r3, [r2, #48] ; 0x30 + 80015ee: 4b1b ldr r3, [pc, #108] ; (800165c ) + 80015f0: 6b1b ldr r3, [r3, #48] ; 0x30 + 80015f2: f003 0302 and.w r3, r3, #2 + 80015f6: 607b str r3, [r7, #4] + 80015f8: 687b ldr r3, [r7, #4] __HAL_RCC_GPIOD_CLK_ENABLE(); - 8000d8a: 4b18 ldr r3, [pc, #96] ; (8000dec ) - 8000d8c: 6b1b ldr r3, [r3, #48] ; 0x30 - 8000d8e: 4a17 ldr r2, [pc, #92] ; (8000dec ) - 8000d90: f043 0308 orr.w r3, r3, #8 - 8000d94: 6313 str r3, [r2, #48] ; 0x30 - 8000d96: 4b15 ldr r3, [pc, #84] ; (8000dec ) - 8000d98: 6b1b ldr r3, [r3, #48] ; 0x30 - 8000d9a: f003 0308 and.w r3, r3, #8 - 8000d9e: 603b str r3, [r7, #0] - 8000da0: 683b ldr r3, [r7, #0] + 80015fa: 4b18 ldr r3, [pc, #96] ; (800165c ) + 80015fc: 6b1b ldr r3, [r3, #48] ; 0x30 + 80015fe: 4a17 ldr r2, [pc, #92] ; (800165c ) + 8001600: f043 0308 orr.w r3, r3, #8 + 8001604: 6313 str r3, [r2, #48] ; 0x30 + 8001606: 4b15 ldr r3, [pc, #84] ; (800165c ) + 8001608: 6b1b ldr r3, [r3, #48] ; 0x30 + 800160a: f003 0308 and.w r3, r3, #8 + 800160e: 603b str r3, [r7, #0] + 8001610: 683b ldr r3, [r7, #0] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_RESET); - 8000da2: 2200 movs r2, #0 - 8000da4: 2101 movs r1, #1 - 8000da6: 4812 ldr r0, [pc, #72] ; (8000df0 ) - 8000da8: f000 ffd6 bl 8001d58 + 8001612: 2200 movs r2, #0 + 8001614: 2101 movs r1, #1 + 8001616: 4812 ldr r0, [pc, #72] ; (8001660 ) + 8001618: f001 f9f4 bl 8002a04 /*Configure GPIO pin : PC13 */ GPIO_InitStruct.Pin = GPIO_PIN_13; - 8000dac: f44f 5300 mov.w r3, #8192 ; 0x2000 - 8000db0: 60fb str r3, [r7, #12] + 800161c: f44f 5300 mov.w r3, #8192 ; 0x2000 + 8001620: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - 8000db2: 2300 movs r3, #0 - 8000db4: 613b str r3, [r7, #16] + 8001622: 2300 movs r3, #0 + 8001624: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000db6: 2300 movs r3, #0 - 8000db8: 617b str r3, [r7, #20] + 8001626: 2300 movs r3, #0 + 8001628: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - 8000dba: f107 030c add.w r3, r7, #12 - 8000dbe: 4619 mov r1, r3 - 8000dc0: 480c ldr r0, [pc, #48] ; (8000df4 ) - 8000dc2: f000 fe05 bl 80019d0 + 800162a: f107 030c add.w r3, r7, #12 + 800162e: 4619 mov r1, r3 + 8001630: 480c ldr r0, [pc, #48] ; (8001664 ) + 8001632: f001 f823 bl 800267c /*Configure GPIO pin : PB0 */ GPIO_InitStruct.Pin = GPIO_PIN_0; - 8000dc6: 2301 movs r3, #1 - 8000dc8: 60fb str r3, [r7, #12] + 8001636: 2301 movs r3, #1 + 8001638: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 8000dca: 2301 movs r3, #1 - 8000dcc: 613b str r3, [r7, #16] + 800163a: 2301 movs r3, #1 + 800163c: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000dce: 2300 movs r3, #0 - 8000dd0: 617b str r3, [r7, #20] + 800163e: 2300 movs r3, #0 + 8001640: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 8000dd2: 2300 movs r3, #0 - 8000dd4: 61bb str r3, [r7, #24] + 8001642: 2300 movs r3, #0 + 8001644: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - 8000dd6: f107 030c add.w r3, r7, #12 - 8000dda: 4619 mov r1, r3 - 8000ddc: 4804 ldr r0, [pc, #16] ; (8000df0 ) - 8000dde: f000 fdf7 bl 80019d0 + 8001646: f107 030c add.w r3, r7, #12 + 800164a: 4619 mov r1, r3 + 800164c: 4804 ldr r0, [pc, #16] ; (8001660 ) + 800164e: f001 f815 bl 800267c } - 8000de2: bf00 nop - 8000de4: 3720 adds r7, #32 - 8000de6: 46bd mov sp, r7 - 8000de8: bd80 pop {r7, pc} - 8000dea: bf00 nop - 8000dec: 40023800 .word 0x40023800 - 8000df0: 40020400 .word 0x40020400 - 8000df4: 40020800 .word 0x40020800 - -08000df8 <__io_putchar>: + 8001652: bf00 nop + 8001654: 3720 adds r7, #32 + 8001656: 46bd mov sp, r7 + 8001658: bd80 pop {r7, pc} + 800165a: bf00 nop + 800165c: 40023800 .word 0x40023800 + 8001660: 40020400 .word 0x40020400 + 8001664: 40020800 .word 0x40020800 + +08001668 <__io_putchar>: set to 'Yes') calls __io_putchar() */ int __io_putchar(int ch) #else int fputc(int ch, FILE *f) #endif /* __GNUC__ */ { - 8000df8: b580 push {r7, lr} - 8000dfa: b082 sub sp, #8 - 8000dfc: af00 add r7, sp, #0 - 8000dfe: 6078 str r0, [r7, #4] + 8001668: b580 push {r7, lr} + 800166a: b082 sub sp, #8 + 800166c: af00 add r7, sp, #0 + 800166e: 6078 str r0, [r7, #4] /* Place your implementation of fputc here */ /* e.g. write a character to the UART3 and Loop until the end of transmission */ HAL_UART_Transmit(&huart3, (uint8_t *)&ch, 1, HAL_MAX_DELAY); - 8000e00: 1d39 adds r1, r7, #4 - 8000e02: f04f 33ff mov.w r3, #4294967295 - 8000e06: 2201 movs r2, #1 - 8000e08: 4803 ldr r0, [pc, #12] ; (8000e18 <__io_putchar+0x20>) - 8000e0a: f002 f8b9 bl 8002f80 + 8001670: 1d39 adds r1, r7, #4 + 8001672: f04f 33ff mov.w r3, #4294967295 + 8001676: 2201 movs r2, #1 + 8001678: 4803 ldr r0, [pc, #12] ; (8001688 <__io_putchar+0x20>) + 800167a: f002 fad7 bl 8003c2c return ch; - 8000e0e: 687b ldr r3, [r7, #4] + 800167e: 687b ldr r3, [r7, #4] } - 8000e10: 4618 mov r0, r3 - 8000e12: 3708 adds r7, #8 - 8000e14: 46bd mov sp, r7 - 8000e16: bd80 pop {r7, pc} - 8000e18: 200004b0 .word 0x200004b0 + 8001680: 4618 mov r0, r3 + 8001682: 3708 adds r7, #8 + 8001684: 46bd mov sp, r7 + 8001686: bd80 pop {r7, pc} + 8001688: 200004b8 .word 0x200004b8 -08000e1c : +0800168c : /** * @brief Jump to application from the Bootloader * @retval None */ static void goto_application(void) { - 8000e1c: b580 push {r7, lr} - 8000e1e: b082 sub sp, #8 - 8000e20: af00 add r7, sp, #0 + 800168c: b580 push {r7, lr} + 800168e: b082 sub sp, #8 + 8001690: af00 add r7, sp, #0 printf("Gonna Jump to Application\r\n"); - 8000e22: 4808 ldr r0, [pc, #32] ; (8000e44 ) - 8000e24: f002 fe92 bl 8003b4c + 8001692: 4808 ldr r0, [pc, #32] ; (80016b4 ) + 8001694: f003 f8b0 bl 80047f8 - void (*app_reset_handler)(void) = (void*)(*((volatile uint32_t*) (0x08040000 + 4U))); - 8000e28: 4b07 ldr r3, [pc, #28] ; (8000e48 ) - 8000e2a: 681b ldr r3, [r3, #0] - 8000e2c: 607b str r3, [r7, #4] + void (*app_reset_handler)(void) = (void*)(*((volatile uint32_t*) (ETX_APP_FLASH_ADDR + 4U))); + 8001698: 4b07 ldr r3, [pc, #28] ; (80016b8 ) + 800169a: 681b ldr r3, [r3, #0] + 800169c: 607b str r3, [r7, #4] - //__set_MSP(*(volatile uint32_t*) 0x08040000); + //__set_MSP(*(volatile uint32_t*) ETX_APP_FLASH_ADDR); // Turn OFF the Green Led to tell the user that Bootloader is not running HAL_GPIO_WritePin(GPIOB, GPIO_PIN_0, GPIO_PIN_RESET ); //Green LED OFF - 8000e2e: 2200 movs r2, #0 - 8000e30: 2101 movs r1, #1 - 8000e32: 4806 ldr r0, [pc, #24] ; (8000e4c ) - 8000e34: f000 ff90 bl 8001d58 + 800169e: 2200 movs r2, #0 + 80016a0: 2101 movs r1, #1 + 80016a2: 4806 ldr r0, [pc, #24] ; (80016bc ) + 80016a4: f001 f9ae bl 8002a04 app_reset_handler(); //call the app reset handler - 8000e38: 687b ldr r3, [r7, #4] - 8000e3a: 4798 blx r3 + 80016a8: 687b ldr r3, [r7, #4] + 80016aa: 4798 blx r3 } - 8000e3c: bf00 nop - 8000e3e: 3708 adds r7, #8 - 8000e40: 46bd mov sp, r7 - 8000e42: bd80 pop {r7, pc} - 8000e44: 08004be0 .word 0x08004be0 - 8000e48: 08040004 .word 0x08040004 - 8000e4c: 40020400 .word 0x40020400 - -08000e50 : + 80016ac: bf00 nop + 80016ae: 3708 adds r7, #8 + 80016b0: 46bd mov sp, r7 + 80016b2: bd80 pop {r7, pc} + 80016b4: 08005ae8 .word 0x08005ae8 + 80016b8: 08040004 .word 0x08040004 + 80016bc: 40020400 .word 0x40020400 + +080016c0 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { - 8000e50: b480 push {r7} - 8000e52: af00 add r7, sp, #0 + 80016c0: b480 push {r7} + 80016c2: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); - 8000e54: b672 cpsid i + 80016c4: b672 cpsid i } - 8000e56: bf00 nop + 80016c6: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) - 8000e58: e7fe b.n 8000e58 + 80016c8: e7fe b.n 80016c8 ... -08000e5c : +080016cc : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { - 8000e5c: b480 push {r7} - 8000e5e: b083 sub sp, #12 - 8000e60: af00 add r7, sp, #0 + 80016cc: b480 push {r7} + 80016ce: b083 sub sp, #12 + 80016d0: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_PWR_CLK_ENABLE(); - 8000e62: 4b0f ldr r3, [pc, #60] ; (8000ea0 ) - 8000e64: 6c1b ldr r3, [r3, #64] ; 0x40 - 8000e66: 4a0e ldr r2, [pc, #56] ; (8000ea0 ) - 8000e68: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 8000e6c: 6413 str r3, [r2, #64] ; 0x40 - 8000e6e: 4b0c ldr r3, [pc, #48] ; (8000ea0 ) - 8000e70: 6c1b ldr r3, [r3, #64] ; 0x40 - 8000e72: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8000e76: 607b str r3, [r7, #4] - 8000e78: 687b ldr r3, [r7, #4] + 80016d2: 4b0f ldr r3, [pc, #60] ; (8001710 ) + 80016d4: 6c1b ldr r3, [r3, #64] ; 0x40 + 80016d6: 4a0e ldr r2, [pc, #56] ; (8001710 ) + 80016d8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 80016dc: 6413 str r3, [r2, #64] ; 0x40 + 80016de: 4b0c ldr r3, [pc, #48] ; (8001710 ) + 80016e0: 6c1b ldr r3, [r3, #64] ; 0x40 + 80016e2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 80016e6: 607b str r3, [r7, #4] + 80016e8: 687b ldr r3, [r7, #4] __HAL_RCC_SYSCFG_CLK_ENABLE(); - 8000e7a: 4b09 ldr r3, [pc, #36] ; (8000ea0 ) - 8000e7c: 6c5b ldr r3, [r3, #68] ; 0x44 - 8000e7e: 4a08 ldr r2, [pc, #32] ; (8000ea0 ) - 8000e80: f443 4380 orr.w r3, r3, #16384 ; 0x4000 - 8000e84: 6453 str r3, [r2, #68] ; 0x44 - 8000e86: 4b06 ldr r3, [pc, #24] ; (8000ea0 ) - 8000e88: 6c5b ldr r3, [r3, #68] ; 0x44 - 8000e8a: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 8000e8e: 603b str r3, [r7, #0] - 8000e90: 683b ldr r3, [r7, #0] + 80016ea: 4b09 ldr r3, [pc, #36] ; (8001710 ) + 80016ec: 6c5b ldr r3, [r3, #68] ; 0x44 + 80016ee: 4a08 ldr r2, [pc, #32] ; (8001710 ) + 80016f0: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 80016f4: 6453 str r3, [r2, #68] ; 0x44 + 80016f6: 4b06 ldr r3, [pc, #24] ; (8001710 ) + 80016f8: 6c5b ldr r3, [r3, #68] ; 0x44 + 80016fa: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 80016fe: 603b str r3, [r7, #0] + 8001700: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } - 8000e92: bf00 nop - 8000e94: 370c adds r7, #12 - 8000e96: 46bd mov sp, r7 - 8000e98: f85d 7b04 ldr.w r7, [sp], #4 - 8000e9c: 4770 bx lr - 8000e9e: bf00 nop - 8000ea0: 40023800 .word 0x40023800 - -08000ea4 : + 8001702: bf00 nop + 8001704: 370c adds r7, #12 + 8001706: 46bd mov sp, r7 + 8001708: f85d 7b04 ldr.w r7, [sp], #4 + 800170c: 4770 bx lr + 800170e: bf00 nop + 8001710: 40023800 .word 0x40023800 + +08001714 : +* This function configures the hardware resources used in this example +* @param hcrc: CRC handle pointer +* @retval None +*/ +void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc) +{ + 8001714: b480 push {r7} + 8001716: b085 sub sp, #20 + 8001718: af00 add r7, sp, #0 + 800171a: 6078 str r0, [r7, #4] + if(hcrc->Instance==CRC) + 800171c: 687b ldr r3, [r7, #4] + 800171e: 681b ldr r3, [r3, #0] + 8001720: 4a0a ldr r2, [pc, #40] ; (800174c ) + 8001722: 4293 cmp r3, r2 + 8001724: d10b bne.n 800173e + { + /* USER CODE BEGIN CRC_MspInit 0 */ + + /* USER CODE END CRC_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_CRC_CLK_ENABLE(); + 8001726: 4b0a ldr r3, [pc, #40] ; (8001750 ) + 8001728: 6b1b ldr r3, [r3, #48] ; 0x30 + 800172a: 4a09 ldr r2, [pc, #36] ; (8001750 ) + 800172c: f443 5380 orr.w r3, r3, #4096 ; 0x1000 + 8001730: 6313 str r3, [r2, #48] ; 0x30 + 8001732: 4b07 ldr r3, [pc, #28] ; (8001750 ) + 8001734: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001736: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 800173a: 60fb str r3, [r7, #12] + 800173c: 68fb ldr r3, [r7, #12] + /* USER CODE BEGIN CRC_MspInit 1 */ + + /* USER CODE END CRC_MspInit 1 */ + } + +} + 800173e: bf00 nop + 8001740: 3714 adds r7, #20 + 8001742: 46bd mov sp, r7 + 8001744: f85d 7b04 ldr.w r7, [sp], #4 + 8001748: 4770 bx lr + 800174a: bf00 nop + 800174c: 40023000 .word 0x40023000 + 8001750: 40023800 .word 0x40023800 + +08001754 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { - 8000ea4: b580 push {r7, lr} - 8000ea6: b08c sub sp, #48 ; 0x30 - 8000ea8: af00 add r7, sp, #0 - 8000eaa: 6078 str r0, [r7, #4] + 8001754: b580 push {r7, lr} + 8001756: b08c sub sp, #48 ; 0x30 + 8001758: af00 add r7, sp, #0 + 800175a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8000eac: f107 031c add.w r3, r7, #28 - 8000eb0: 2200 movs r2, #0 - 8000eb2: 601a str r2, [r3, #0] - 8000eb4: 605a str r2, [r3, #4] - 8000eb6: 609a str r2, [r3, #8] - 8000eb8: 60da str r2, [r3, #12] - 8000eba: 611a str r2, [r3, #16] + 800175c: f107 031c add.w r3, r7, #28 + 8001760: 2200 movs r2, #0 + 8001762: 601a str r2, [r3, #0] + 8001764: 605a str r2, [r3, #4] + 8001766: 609a str r2, [r3, #8] + 8001768: 60da str r2, [r3, #12] + 800176a: 611a str r2, [r3, #16] if(huart->Instance==USART2) - 8000ebc: 687b ldr r3, [r7, #4] - 8000ebe: 681b ldr r3, [r3, #0] - 8000ec0: 4a2e ldr r2, [pc, #184] ; (8000f7c ) - 8000ec2: 4293 cmp r3, r2 - 8000ec4: d128 bne.n 8000f18 + 800176c: 687b ldr r3, [r7, #4] + 800176e: 681b ldr r3, [r3, #0] + 8001770: 4a2e ldr r2, [pc, #184] ; (800182c ) + 8001772: 4293 cmp r3, r2 + 8001774: d128 bne.n 80017c8 { /* USER CODE BEGIN USART2_MspInit 0 */ /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - 8000ec6: 4b2e ldr r3, [pc, #184] ; (8000f80 ) - 8000ec8: 6c1b ldr r3, [r3, #64] ; 0x40 - 8000eca: 4a2d ldr r2, [pc, #180] ; (8000f80 ) - 8000ecc: f443 3300 orr.w r3, r3, #131072 ; 0x20000 - 8000ed0: 6413 str r3, [r2, #64] ; 0x40 - 8000ed2: 4b2b ldr r3, [pc, #172] ; (8000f80 ) - 8000ed4: 6c1b ldr r3, [r3, #64] ; 0x40 - 8000ed6: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 8000eda: 61bb str r3, [r7, #24] - 8000edc: 69bb ldr r3, [r7, #24] + 8001776: 4b2e ldr r3, [pc, #184] ; (8001830 ) + 8001778: 6c1b ldr r3, [r3, #64] ; 0x40 + 800177a: 4a2d ldr r2, [pc, #180] ; (8001830 ) + 800177c: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 8001780: 6413 str r3, [r2, #64] ; 0x40 + 8001782: 4b2b ldr r3, [pc, #172] ; (8001830 ) + 8001784: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001786: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 800178a: 61bb str r3, [r7, #24] + 800178c: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOD_CLK_ENABLE(); - 8000ede: 4b28 ldr r3, [pc, #160] ; (8000f80 ) - 8000ee0: 6b1b ldr r3, [r3, #48] ; 0x30 - 8000ee2: 4a27 ldr r2, [pc, #156] ; (8000f80 ) - 8000ee4: f043 0308 orr.w r3, r3, #8 - 8000ee8: 6313 str r3, [r2, #48] ; 0x30 - 8000eea: 4b25 ldr r3, [pc, #148] ; (8000f80 ) - 8000eec: 6b1b ldr r3, [r3, #48] ; 0x30 - 8000eee: f003 0308 and.w r3, r3, #8 - 8000ef2: 617b str r3, [r7, #20] - 8000ef4: 697b ldr r3, [r7, #20] + 800178e: 4b28 ldr r3, [pc, #160] ; (8001830 ) + 8001790: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001792: 4a27 ldr r2, [pc, #156] ; (8001830 ) + 8001794: f043 0308 orr.w r3, r3, #8 + 8001798: 6313 str r3, [r2, #48] ; 0x30 + 800179a: 4b25 ldr r3, [pc, #148] ; (8001830 ) + 800179c: 6b1b ldr r3, [r3, #48] ; 0x30 + 800179e: f003 0308 and.w r3, r3, #8 + 80017a2: 617b str r3, [r7, #20] + 80017a4: 697b ldr r3, [r7, #20] /**USART2 GPIO Configuration PD5 ------> USART2_TX PD6 ------> USART2_RX */ GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6; - 8000ef6: 2360 movs r3, #96 ; 0x60 - 8000ef8: 61fb str r3, [r7, #28] + 80017a6: 2360 movs r3, #96 ; 0x60 + 80017a8: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 8000efa: 2302 movs r3, #2 - 8000efc: 623b str r3, [r7, #32] + 80017aa: 2302 movs r3, #2 + 80017ac: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000efe: 2300 movs r3, #0 - 8000f00: 627b str r3, [r7, #36] ; 0x24 + 80017ae: 2300 movs r3, #0 + 80017b0: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - 8000f02: 2303 movs r3, #3 - 8000f04: 62bb str r3, [r7, #40] ; 0x28 + 80017b2: 2303 movs r3, #3 + 80017b4: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Alternate = GPIO_AF7_USART2; - 8000f06: 2307 movs r3, #7 - 8000f08: 62fb str r3, [r7, #44] ; 0x2c + 80017b6: 2307 movs r3, #7 + 80017b8: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - 8000f0a: f107 031c add.w r3, r7, #28 - 8000f0e: 4619 mov r1, r3 - 8000f10: 481c ldr r0, [pc, #112] ; (8000f84 ) - 8000f12: f000 fd5d bl 80019d0 + 80017ba: f107 031c add.w r3, r7, #28 + 80017be: 4619 mov r1, r3 + 80017c0: 481c ldr r0, [pc, #112] ; (8001834 ) + 80017c2: f000 ff5b bl 800267c /* USER CODE BEGIN USART3_MspInit 1 */ /* USER CODE END USART3_MspInit 1 */ } } - 8000f16: e02d b.n 8000f74 + 80017c6: e02d b.n 8001824 else if(huart->Instance==USART3) - 8000f18: 687b ldr r3, [r7, #4] - 8000f1a: 681b ldr r3, [r3, #0] - 8000f1c: 4a1a ldr r2, [pc, #104] ; (8000f88 ) - 8000f1e: 4293 cmp r3, r2 - 8000f20: d128 bne.n 8000f74 + 80017c8: 687b ldr r3, [r7, #4] + 80017ca: 681b ldr r3, [r3, #0] + 80017cc: 4a1a ldr r2, [pc, #104] ; (8001838 ) + 80017ce: 4293 cmp r3, r2 + 80017d0: d128 bne.n 8001824 __HAL_RCC_USART3_CLK_ENABLE(); - 8000f22: 4b17 ldr r3, [pc, #92] ; (8000f80 ) - 8000f24: 6c1b ldr r3, [r3, #64] ; 0x40 - 8000f26: 4a16 ldr r2, [pc, #88] ; (8000f80 ) - 8000f28: f443 2380 orr.w r3, r3, #262144 ; 0x40000 - 8000f2c: 6413 str r3, [r2, #64] ; 0x40 - 8000f2e: 4b14 ldr r3, [pc, #80] ; (8000f80 ) - 8000f30: 6c1b ldr r3, [r3, #64] ; 0x40 - 8000f32: f403 2380 and.w r3, r3, #262144 ; 0x40000 - 8000f36: 613b str r3, [r7, #16] - 8000f38: 693b ldr r3, [r7, #16] + 80017d2: 4b17 ldr r3, [pc, #92] ; (8001830 ) + 80017d4: 6c1b ldr r3, [r3, #64] ; 0x40 + 80017d6: 4a16 ldr r2, [pc, #88] ; (8001830 ) + 80017d8: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 80017dc: 6413 str r3, [r2, #64] ; 0x40 + 80017de: 4b14 ldr r3, [pc, #80] ; (8001830 ) + 80017e0: 6c1b ldr r3, [r3, #64] ; 0x40 + 80017e2: f403 2380 and.w r3, r3, #262144 ; 0x40000 + 80017e6: 613b str r3, [r7, #16] + 80017e8: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOD_CLK_ENABLE(); - 8000f3a: 4b11 ldr r3, [pc, #68] ; (8000f80 ) - 8000f3c: 6b1b ldr r3, [r3, #48] ; 0x30 - 8000f3e: 4a10 ldr r2, [pc, #64] ; (8000f80 ) - 8000f40: f043 0308 orr.w r3, r3, #8 - 8000f44: 6313 str r3, [r2, #48] ; 0x30 - 8000f46: 4b0e ldr r3, [pc, #56] ; (8000f80 ) - 8000f48: 6b1b ldr r3, [r3, #48] ; 0x30 - 8000f4a: f003 0308 and.w r3, r3, #8 - 8000f4e: 60fb str r3, [r7, #12] - 8000f50: 68fb ldr r3, [r7, #12] + 80017ea: 4b11 ldr r3, [pc, #68] ; (8001830 ) + 80017ec: 6b1b ldr r3, [r3, #48] ; 0x30 + 80017ee: 4a10 ldr r2, [pc, #64] ; (8001830 ) + 80017f0: f043 0308 orr.w r3, r3, #8 + 80017f4: 6313 str r3, [r2, #48] ; 0x30 + 80017f6: 4b0e ldr r3, [pc, #56] ; (8001830 ) + 80017f8: 6b1b ldr r3, [r3, #48] ; 0x30 + 80017fa: f003 0308 and.w r3, r3, #8 + 80017fe: 60fb str r3, [r7, #12] + 8001800: 68fb ldr r3, [r7, #12] GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; - 8000f52: f44f 7340 mov.w r3, #768 ; 0x300 - 8000f56: 61fb str r3, [r7, #28] + 8001802: f44f 7340 mov.w r3, #768 ; 0x300 + 8001806: 61fb str r3, [r7, #28] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 8000f58: 2302 movs r3, #2 - 8000f5a: 623b str r3, [r7, #32] + 8001808: 2302 movs r3, #2 + 800180a: 623b str r3, [r7, #32] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000f5c: 2300 movs r3, #0 - 8000f5e: 627b str r3, [r7, #36] ; 0x24 + 800180c: 2300 movs r3, #0 + 800180e: 627b str r3, [r7, #36] ; 0x24 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - 8000f60: 2303 movs r3, #3 - 8000f62: 62bb str r3, [r7, #40] ; 0x28 + 8001810: 2303 movs r3, #3 + 8001812: 62bb str r3, [r7, #40] ; 0x28 GPIO_InitStruct.Alternate = GPIO_AF7_USART3; - 8000f64: 2307 movs r3, #7 - 8000f66: 62fb str r3, [r7, #44] ; 0x2c + 8001814: 2307 movs r3, #7 + 8001816: 62fb str r3, [r7, #44] ; 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - 8000f68: f107 031c add.w r3, r7, #28 - 8000f6c: 4619 mov r1, r3 - 8000f6e: 4805 ldr r0, [pc, #20] ; (8000f84 ) - 8000f70: f000 fd2e bl 80019d0 + 8001818: f107 031c add.w r3, r7, #28 + 800181c: 4619 mov r1, r3 + 800181e: 4805 ldr r0, [pc, #20] ; (8001834 ) + 8001820: f000 ff2c bl 800267c } - 8000f74: bf00 nop - 8000f76: 3730 adds r7, #48 ; 0x30 - 8000f78: 46bd mov sp, r7 - 8000f7a: bd80 pop {r7, pc} - 8000f7c: 40004400 .word 0x40004400 - 8000f80: 40023800 .word 0x40023800 - 8000f84: 40020c00 .word 0x40020c00 - 8000f88: 40004800 .word 0x40004800 - -08000f8c : + 8001824: bf00 nop + 8001826: 3730 adds r7, #48 ; 0x30 + 8001828: 46bd mov sp, r7 + 800182a: bd80 pop {r7, pc} + 800182c: 40004400 .word 0x40004400 + 8001830: 40023800 .word 0x40023800 + 8001834: 40020c00 .word 0x40020c00 + 8001838: 40004800 .word 0x40004800 + +0800183c : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { - 8000f8c: b480 push {r7} - 8000f8e: af00 add r7, sp, #0 + 800183c: b480 push {r7} + 800183e: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) - 8000f90: e7fe b.n 8000f90 + 8001840: e7fe b.n 8001840 -08000f92 : +08001842 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { - 8000f92: b480 push {r7} - 8000f94: af00 add r7, sp, #0 + 8001842: b480 push {r7} + 8001844: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) - 8000f96: e7fe b.n 8000f96 + 8001846: e7fe b.n 8001846 -08000f98 : +08001848 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { - 8000f98: b480 push {r7} - 8000f9a: af00 add r7, sp, #0 + 8001848: b480 push {r7} + 800184a: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) - 8000f9c: e7fe b.n 8000f9c + 800184c: e7fe b.n 800184c -08000f9e : +0800184e : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { - 8000f9e: b480 push {r7} - 8000fa0: af00 add r7, sp, #0 + 800184e: b480 push {r7} + 8001850: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) - 8000fa2: e7fe b.n 8000fa2 + 8001852: e7fe b.n 8001852 -08000fa4 : +08001854 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { - 8000fa4: b480 push {r7} - 8000fa6: af00 add r7, sp, #0 + 8001854: b480 push {r7} + 8001856: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) - 8000fa8: e7fe b.n 8000fa8 + 8001858: e7fe b.n 8001858 -08000faa : +0800185a : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { - 8000faa: b480 push {r7} - 8000fac: af00 add r7, sp, #0 + 800185a: b480 push {r7} + 800185c: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } - 8000fae: bf00 nop - 8000fb0: 46bd mov sp, r7 - 8000fb2: f85d 7b04 ldr.w r7, [sp], #4 - 8000fb6: 4770 bx lr + 800185e: bf00 nop + 8001860: 46bd mov sp, r7 + 8001862: f85d 7b04 ldr.w r7, [sp], #4 + 8001866: 4770 bx lr -08000fb8 : +08001868 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { - 8000fb8: b480 push {r7} - 8000fba: af00 add r7, sp, #0 + 8001868: b480 push {r7} + 800186a: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } - 8000fbc: bf00 nop - 8000fbe: 46bd mov sp, r7 - 8000fc0: f85d 7b04 ldr.w r7, [sp], #4 - 8000fc4: 4770 bx lr + 800186c: bf00 nop + 800186e: 46bd mov sp, r7 + 8001870: f85d 7b04 ldr.w r7, [sp], #4 + 8001874: 4770 bx lr -08000fc6 : +08001876 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { - 8000fc6: b480 push {r7} - 8000fc8: af00 add r7, sp, #0 + 8001876: b480 push {r7} + 8001878: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } - 8000fca: bf00 nop - 8000fcc: 46bd mov sp, r7 - 8000fce: f85d 7b04 ldr.w r7, [sp], #4 - 8000fd2: 4770 bx lr + 800187a: bf00 nop + 800187c: 46bd mov sp, r7 + 800187e: f85d 7b04 ldr.w r7, [sp], #4 + 8001882: 4770 bx lr -08000fd4 : +08001884 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { - 8000fd4: b580 push {r7, lr} - 8000fd6: af00 add r7, sp, #0 + 8001884: b580 push {r7, lr} + 8001886: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); - 8000fd8: f000 f91e bl 8001218 + 8001888: f000 f91e bl 8001ac8 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } - 8000fdc: bf00 nop - 8000fde: bd80 pop {r7, pc} + 800188c: bf00 nop + 800188e: bd80 pop {r7, pc} -08000fe0 <_read>: +08001890 <_read>: _kill(status, -1); while (1) {} /* Make sure we hang here */ } __attribute__((weak)) int _read(int file, char *ptr, int len) { - 8000fe0: b580 push {r7, lr} - 8000fe2: b086 sub sp, #24 - 8000fe4: af00 add r7, sp, #0 - 8000fe6: 60f8 str r0, [r7, #12] - 8000fe8: 60b9 str r1, [r7, #8] - 8000fea: 607a str r2, [r7, #4] + 8001890: b580 push {r7, lr} + 8001892: b086 sub sp, #24 + 8001894: af00 add r7, sp, #0 + 8001896: 60f8 str r0, [r7, #12] + 8001898: 60b9 str r1, [r7, #8] + 800189a: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) - 8000fec: 2300 movs r3, #0 - 8000fee: 617b str r3, [r7, #20] - 8000ff0: e00a b.n 8001008 <_read+0x28> + 800189c: 2300 movs r3, #0 + 800189e: 617b str r3, [r7, #20] + 80018a0: e00a b.n 80018b8 <_read+0x28> { *ptr++ = __io_getchar(); - 8000ff2: f3af 8000 nop.w - 8000ff6: 4601 mov r1, r0 - 8000ff8: 68bb ldr r3, [r7, #8] - 8000ffa: 1c5a adds r2, r3, #1 - 8000ffc: 60ba str r2, [r7, #8] - 8000ffe: b2ca uxtb r2, r1 - 8001000: 701a strb r2, [r3, #0] + 80018a2: f3af 8000 nop.w + 80018a6: 4601 mov r1, r0 + 80018a8: 68bb ldr r3, [r7, #8] + 80018aa: 1c5a adds r2, r3, #1 + 80018ac: 60ba str r2, [r7, #8] + 80018ae: b2ca uxtb r2, r1 + 80018b0: 701a strb r2, [r3, #0] for (DataIdx = 0; DataIdx < len; DataIdx++) - 8001002: 697b ldr r3, [r7, #20] - 8001004: 3301 adds r3, #1 - 8001006: 617b str r3, [r7, #20] - 8001008: 697a ldr r2, [r7, #20] - 800100a: 687b ldr r3, [r7, #4] - 800100c: 429a cmp r2, r3 - 800100e: dbf0 blt.n 8000ff2 <_read+0x12> + 80018b2: 697b ldr r3, [r7, #20] + 80018b4: 3301 adds r3, #1 + 80018b6: 617b str r3, [r7, #20] + 80018b8: 697a ldr r2, [r7, #20] + 80018ba: 687b ldr r3, [r7, #4] + 80018bc: 429a cmp r2, r3 + 80018be: dbf0 blt.n 80018a2 <_read+0x12> } return len; - 8001010: 687b ldr r3, [r7, #4] + 80018c0: 687b ldr r3, [r7, #4] } - 8001012: 4618 mov r0, r3 - 8001014: 3718 adds r7, #24 - 8001016: 46bd mov sp, r7 - 8001018: bd80 pop {r7, pc} + 80018c2: 4618 mov r0, r3 + 80018c4: 3718 adds r7, #24 + 80018c6: 46bd mov sp, r7 + 80018c8: bd80 pop {r7, pc} -0800101a <_write>: +080018ca <_write>: __attribute__((weak)) int _write(int file, char *ptr, int len) { - 800101a: b580 push {r7, lr} - 800101c: b086 sub sp, #24 - 800101e: af00 add r7, sp, #0 - 8001020: 60f8 str r0, [r7, #12] - 8001022: 60b9 str r1, [r7, #8] - 8001024: 607a str r2, [r7, #4] + 80018ca: b580 push {r7, lr} + 80018cc: b086 sub sp, #24 + 80018ce: af00 add r7, sp, #0 + 80018d0: 60f8 str r0, [r7, #12] + 80018d2: 60b9 str r1, [r7, #8] + 80018d4: 607a str r2, [r7, #4] int DataIdx; for (DataIdx = 0; DataIdx < len; DataIdx++) - 8001026: 2300 movs r3, #0 - 8001028: 617b str r3, [r7, #20] - 800102a: e009 b.n 8001040 <_write+0x26> + 80018d6: 2300 movs r3, #0 + 80018d8: 617b str r3, [r7, #20] + 80018da: e009 b.n 80018f0 <_write+0x26> { __io_putchar(*ptr++); - 800102c: 68bb ldr r3, [r7, #8] - 800102e: 1c5a adds r2, r3, #1 - 8001030: 60ba str r2, [r7, #8] - 8001032: 781b ldrb r3, [r3, #0] - 8001034: 4618 mov r0, r3 - 8001036: f7ff fedf bl 8000df8 <__io_putchar> + 80018dc: 68bb ldr r3, [r7, #8] + 80018de: 1c5a adds r2, r3, #1 + 80018e0: 60ba str r2, [r7, #8] + 80018e2: 781b ldrb r3, [r3, #0] + 80018e4: 4618 mov r0, r3 + 80018e6: f7ff febf bl 8001668 <__io_putchar> for (DataIdx = 0; DataIdx < len; DataIdx++) - 800103a: 697b ldr r3, [r7, #20] - 800103c: 3301 adds r3, #1 - 800103e: 617b str r3, [r7, #20] - 8001040: 697a ldr r2, [r7, #20] - 8001042: 687b ldr r3, [r7, #4] - 8001044: 429a cmp r2, r3 - 8001046: dbf1 blt.n 800102c <_write+0x12> + 80018ea: 697b ldr r3, [r7, #20] + 80018ec: 3301 adds r3, #1 + 80018ee: 617b str r3, [r7, #20] + 80018f0: 697a ldr r2, [r7, #20] + 80018f2: 687b ldr r3, [r7, #4] + 80018f4: 429a cmp r2, r3 + 80018f6: dbf1 blt.n 80018dc <_write+0x12> } return len; - 8001048: 687b ldr r3, [r7, #4] + 80018f8: 687b ldr r3, [r7, #4] } - 800104a: 4618 mov r0, r3 - 800104c: 3718 adds r7, #24 - 800104e: 46bd mov sp, r7 - 8001050: bd80 pop {r7, pc} + 80018fa: 4618 mov r0, r3 + 80018fc: 3718 adds r7, #24 + 80018fe: 46bd mov sp, r7 + 8001900: bd80 pop {r7, pc} -08001052 <_close>: +08001902 <_close>: int _close(int file) { - 8001052: b480 push {r7} - 8001054: b083 sub sp, #12 - 8001056: af00 add r7, sp, #0 - 8001058: 6078 str r0, [r7, #4] + 8001902: b480 push {r7} + 8001904: b083 sub sp, #12 + 8001906: af00 add r7, sp, #0 + 8001908: 6078 str r0, [r7, #4] return -1; - 800105a: f04f 33ff mov.w r3, #4294967295 + 800190a: f04f 33ff mov.w r3, #4294967295 } - 800105e: 4618 mov r0, r3 - 8001060: 370c adds r7, #12 - 8001062: 46bd mov sp, r7 - 8001064: f85d 7b04 ldr.w r7, [sp], #4 - 8001068: 4770 bx lr + 800190e: 4618 mov r0, r3 + 8001910: 370c adds r7, #12 + 8001912: 46bd mov sp, r7 + 8001914: f85d 7b04 ldr.w r7, [sp], #4 + 8001918: 4770 bx lr -0800106a <_fstat>: +0800191a <_fstat>: int _fstat(int file, struct stat *st) { - 800106a: b480 push {r7} - 800106c: b083 sub sp, #12 - 800106e: af00 add r7, sp, #0 - 8001070: 6078 str r0, [r7, #4] - 8001072: 6039 str r1, [r7, #0] + 800191a: b480 push {r7} + 800191c: b083 sub sp, #12 + 800191e: af00 add r7, sp, #0 + 8001920: 6078 str r0, [r7, #4] + 8001922: 6039 str r1, [r7, #0] st->st_mode = S_IFCHR; - 8001074: 683b ldr r3, [r7, #0] - 8001076: f44f 5200 mov.w r2, #8192 ; 0x2000 - 800107a: 605a str r2, [r3, #4] + 8001924: 683b ldr r3, [r7, #0] + 8001926: f44f 5200 mov.w r2, #8192 ; 0x2000 + 800192a: 605a str r2, [r3, #4] return 0; - 800107c: 2300 movs r3, #0 + 800192c: 2300 movs r3, #0 } - 800107e: 4618 mov r0, r3 - 8001080: 370c adds r7, #12 - 8001082: 46bd mov sp, r7 - 8001084: f85d 7b04 ldr.w r7, [sp], #4 - 8001088: 4770 bx lr + 800192e: 4618 mov r0, r3 + 8001930: 370c adds r7, #12 + 8001932: 46bd mov sp, r7 + 8001934: f85d 7b04 ldr.w r7, [sp], #4 + 8001938: 4770 bx lr -0800108a <_isatty>: +0800193a <_isatty>: int _isatty(int file) { - 800108a: b480 push {r7} - 800108c: b083 sub sp, #12 - 800108e: af00 add r7, sp, #0 - 8001090: 6078 str r0, [r7, #4] + 800193a: b480 push {r7} + 800193c: b083 sub sp, #12 + 800193e: af00 add r7, sp, #0 + 8001940: 6078 str r0, [r7, #4] return 1; - 8001092: 2301 movs r3, #1 + 8001942: 2301 movs r3, #1 } - 8001094: 4618 mov r0, r3 - 8001096: 370c adds r7, #12 - 8001098: 46bd mov sp, r7 - 800109a: f85d 7b04 ldr.w r7, [sp], #4 - 800109e: 4770 bx lr + 8001944: 4618 mov r0, r3 + 8001946: 370c adds r7, #12 + 8001948: 46bd mov sp, r7 + 800194a: f85d 7b04 ldr.w r7, [sp], #4 + 800194e: 4770 bx lr -080010a0 <_lseek>: +08001950 <_lseek>: int _lseek(int file, int ptr, int dir) { - 80010a0: b480 push {r7} - 80010a2: b085 sub sp, #20 - 80010a4: af00 add r7, sp, #0 - 80010a6: 60f8 str r0, [r7, #12] - 80010a8: 60b9 str r1, [r7, #8] - 80010aa: 607a str r2, [r7, #4] + 8001950: b480 push {r7} + 8001952: b085 sub sp, #20 + 8001954: af00 add r7, sp, #0 + 8001956: 60f8 str r0, [r7, #12] + 8001958: 60b9 str r1, [r7, #8] + 800195a: 607a str r2, [r7, #4] return 0; - 80010ac: 2300 movs r3, #0 + 800195c: 2300 movs r3, #0 } - 80010ae: 4618 mov r0, r3 - 80010b0: 3714 adds r7, #20 - 80010b2: 46bd mov sp, r7 - 80010b4: f85d 7b04 ldr.w r7, [sp], #4 - 80010b8: 4770 bx lr + 800195e: 4618 mov r0, r3 + 8001960: 3714 adds r7, #20 + 8001962: 46bd mov sp, r7 + 8001964: f85d 7b04 ldr.w r7, [sp], #4 + 8001968: 4770 bx lr ... -080010bc <_sbrk>: +0800196c <_sbrk>: * * @param incr Memory size * @return Pointer to allocated memory */ void *_sbrk(ptrdiff_t incr) { - 80010bc: b580 push {r7, lr} - 80010be: b086 sub sp, #24 - 80010c0: af00 add r7, sp, #0 - 80010c2: 6078 str r0, [r7, #4] + 800196c: b580 push {r7, lr} + 800196e: b086 sub sp, #24 + 8001970: af00 add r7, sp, #0 + 8001972: 6078 str r0, [r7, #4] extern uint8_t _end; /* Symbol defined in the linker script */ extern uint8_t _estack; /* Symbol defined in the linker script */ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; - 80010c4: 4a14 ldr r2, [pc, #80] ; (8001118 <_sbrk+0x5c>) - 80010c6: 4b15 ldr r3, [pc, #84] ; (800111c <_sbrk+0x60>) - 80010c8: 1ad3 subs r3, r2, r3 - 80010ca: 617b str r3, [r7, #20] + 8001974: 4a14 ldr r2, [pc, #80] ; (80019c8 <_sbrk+0x5c>) + 8001976: 4b15 ldr r3, [pc, #84] ; (80019cc <_sbrk+0x60>) + 8001978: 1ad3 subs r3, r2, r3 + 800197a: 617b str r3, [r7, #20] const uint8_t *max_heap = (uint8_t *)stack_limit; - 80010cc: 697b ldr r3, [r7, #20] - 80010ce: 613b str r3, [r7, #16] + 800197c: 697b ldr r3, [r7, #20] + 800197e: 613b str r3, [r7, #16] uint8_t *prev_heap_end; /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) - 80010d0: 4b13 ldr r3, [pc, #76] ; (8001120 <_sbrk+0x64>) - 80010d2: 681b ldr r3, [r3, #0] - 80010d4: 2b00 cmp r3, #0 - 80010d6: d102 bne.n 80010de <_sbrk+0x22> + 8001980: 4b13 ldr r3, [pc, #76] ; (80019d0 <_sbrk+0x64>) + 8001982: 681b ldr r3, [r3, #0] + 8001984: 2b00 cmp r3, #0 + 8001986: d102 bne.n 800198e <_sbrk+0x22> { __sbrk_heap_end = &_end; - 80010d8: 4b11 ldr r3, [pc, #68] ; (8001120 <_sbrk+0x64>) - 80010da: 4a12 ldr r2, [pc, #72] ; (8001124 <_sbrk+0x68>) - 80010dc: 601a str r2, [r3, #0] + 8001988: 4b11 ldr r3, [pc, #68] ; (80019d0 <_sbrk+0x64>) + 800198a: 4a12 ldr r2, [pc, #72] ; (80019d4 <_sbrk+0x68>) + 800198c: 601a str r2, [r3, #0] } /* Protect heap from growing into the reserved MSP stack */ if (__sbrk_heap_end + incr > max_heap) - 80010de: 4b10 ldr r3, [pc, #64] ; (8001120 <_sbrk+0x64>) - 80010e0: 681a ldr r2, [r3, #0] - 80010e2: 687b ldr r3, [r7, #4] - 80010e4: 4413 add r3, r2 - 80010e6: 693a ldr r2, [r7, #16] - 80010e8: 429a cmp r2, r3 - 80010ea: d207 bcs.n 80010fc <_sbrk+0x40> + 800198e: 4b10 ldr r3, [pc, #64] ; (80019d0 <_sbrk+0x64>) + 8001990: 681a ldr r2, [r3, #0] + 8001992: 687b ldr r3, [r7, #4] + 8001994: 4413 add r3, r2 + 8001996: 693a ldr r2, [r7, #16] + 8001998: 429a cmp r2, r3 + 800199a: d207 bcs.n 80019ac <_sbrk+0x40> { errno = ENOMEM; - 80010ec: f002 fc76 bl 80039dc <__errno> - 80010f0: 4603 mov r3, r0 - 80010f2: 220c movs r2, #12 - 80010f4: 601a str r2, [r3, #0] + 800199c: f002 fe74 bl 8004688 <__errno> + 80019a0: 4603 mov r3, r0 + 80019a2: 220c movs r2, #12 + 80019a4: 601a str r2, [r3, #0] return (void *)-1; - 80010f6: f04f 33ff mov.w r3, #4294967295 - 80010fa: e009 b.n 8001110 <_sbrk+0x54> + 80019a6: f04f 33ff mov.w r3, #4294967295 + 80019aa: e009 b.n 80019c0 <_sbrk+0x54> } prev_heap_end = __sbrk_heap_end; - 80010fc: 4b08 ldr r3, [pc, #32] ; (8001120 <_sbrk+0x64>) - 80010fe: 681b ldr r3, [r3, #0] - 8001100: 60fb str r3, [r7, #12] + 80019ac: 4b08 ldr r3, [pc, #32] ; (80019d0 <_sbrk+0x64>) + 80019ae: 681b ldr r3, [r3, #0] + 80019b0: 60fb str r3, [r7, #12] __sbrk_heap_end += incr; - 8001102: 4b07 ldr r3, [pc, #28] ; (8001120 <_sbrk+0x64>) - 8001104: 681a ldr r2, [r3, #0] - 8001106: 687b ldr r3, [r7, #4] - 8001108: 4413 add r3, r2 - 800110a: 4a05 ldr r2, [pc, #20] ; (8001120 <_sbrk+0x64>) - 800110c: 6013 str r3, [r2, #0] + 80019b2: 4b07 ldr r3, [pc, #28] ; (80019d0 <_sbrk+0x64>) + 80019b4: 681a ldr r2, [r3, #0] + 80019b6: 687b ldr r3, [r7, #4] + 80019b8: 4413 add r3, r2 + 80019ba: 4a05 ldr r2, [pc, #20] ; (80019d0 <_sbrk+0x64>) + 80019bc: 6013 str r3, [r2, #0] return (void *)prev_heap_end; - 800110e: 68fb ldr r3, [r7, #12] + 80019be: 68fb ldr r3, [r7, #12] } - 8001110: 4618 mov r0, r3 - 8001112: 3718 adds r7, #24 - 8001114: 46bd mov sp, r7 - 8001116: bd80 pop {r7, pc} - 8001118: 20080000 .word 0x20080000 - 800111c: 00000400 .word 0x00000400 - 8001120: 200004a4 .word 0x200004a4 - 8001124: 200005e8 .word 0x200005e8 - -08001128 : + 80019c0: 4618 mov r0, r3 + 80019c2: 3718 adds r7, #24 + 80019c4: 46bd mov sp, r7 + 80019c6: bd80 pop {r7, pc} + 80019c8: 20080000 .word 0x20080000 + 80019cc: 00000400 .word 0x00000400 + 80019d0: 200004ac .word 0x200004ac + 80019d4: 20000618 .word 0x20000618 + +080019d8 : * SystemFrequency variable. * @param None * @retval None */ void SystemInit(void) { - 8001128: b480 push {r7} - 800112a: af00 add r7, sp, #0 + 80019d8: b480 push {r7} + 80019da: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - 800112c: 4b06 ldr r3, [pc, #24] ; (8001148 ) - 800112e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8001132: 4a05 ldr r2, [pc, #20] ; (8001148 ) - 8001134: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 - 8001138: f8c2 3088 str.w r3, [r2, #136] ; 0x88 + 80019dc: 4b06 ldr r3, [pc, #24] ; (80019f8 ) + 80019de: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 80019e2: 4a05 ldr r2, [pc, #20] ; (80019f8 ) + 80019e4: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 + 80019e8: f8c2 3088 str.w r3, [r2, #136] ; 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } - 800113c: bf00 nop - 800113e: 46bd mov sp, r7 - 8001140: f85d 7b04 ldr.w r7, [sp], #4 - 8001144: 4770 bx lr - 8001146: bf00 nop - 8001148: e000ed00 .word 0xe000ed00 + 80019ec: bf00 nop + 80019ee: 46bd mov sp, r7 + 80019f0: f85d 7b04 ldr.w r7, [sp], #4 + 80019f4: 4770 bx lr + 80019f6: bf00 nop + 80019f8: e000ed00 .word 0xe000ed00 -0800114c : +080019fc : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ - 800114c: f8df d034 ldr.w sp, [pc, #52] ; 8001184 + 80019fc: f8df d034 ldr.w sp, [pc, #52] ; 8001a34 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata - 8001150: 480d ldr r0, [pc, #52] ; (8001188 ) + 8001a00: 480d ldr r0, [pc, #52] ; (8001a38 ) ldr r1, =_edata - 8001152: 490e ldr r1, [pc, #56] ; (800118c ) + 8001a02: 490e ldr r1, [pc, #56] ; (8001a3c ) ldr r2, =_sidata - 8001154: 4a0e ldr r2, [pc, #56] ; (8001190 ) + 8001a04: 4a0e ldr r2, [pc, #56] ; (8001a40 ) movs r3, #0 - 8001156: 2300 movs r3, #0 + 8001a06: 2300 movs r3, #0 b LoopCopyDataInit - 8001158: e002 b.n 8001160 + 8001a08: e002 b.n 8001a10 -0800115a : +08001a0a : CopyDataInit: ldr r4, [r2, r3] - 800115a: 58d4 ldr r4, [r2, r3] + 8001a0a: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] - 800115c: 50c4 str r4, [r0, r3] + 8001a0c: 50c4 str r4, [r0, r3] adds r3, r3, #4 - 800115e: 3304 adds r3, #4 + 8001a0e: 3304 adds r3, #4 -08001160 : +08001a10 : LoopCopyDataInit: adds r4, r0, r3 - 8001160: 18c4 adds r4, r0, r3 + 8001a10: 18c4 adds r4, r0, r3 cmp r4, r1 - 8001162: 428c cmp r4, r1 + 8001a12: 428c cmp r4, r1 bcc CopyDataInit - 8001164: d3f9 bcc.n 800115a + 8001a14: d3f9 bcc.n 8001a0a /* Zero fill the bss segment. */ ldr r2, =_sbss - 8001166: 4a0b ldr r2, [pc, #44] ; (8001194 ) + 8001a16: 4a0b ldr r2, [pc, #44] ; (8001a44 ) ldr r4, =_ebss - 8001168: 4c0b ldr r4, [pc, #44] ; (8001198 ) + 8001a18: 4c0b ldr r4, [pc, #44] ; (8001a48 ) movs r3, #0 - 800116a: 2300 movs r3, #0 + 8001a1a: 2300 movs r3, #0 b LoopFillZerobss - 800116c: e001 b.n 8001172 + 8001a1c: e001 b.n 8001a22 -0800116e : +08001a1e : FillZerobss: str r3, [r2] - 800116e: 6013 str r3, [r2, #0] + 8001a1e: 6013 str r3, [r2, #0] adds r2, r2, #4 - 8001170: 3204 adds r2, #4 + 8001a20: 3204 adds r2, #4 -08001172 : +08001a22 : LoopFillZerobss: cmp r2, r4 - 8001172: 42a2 cmp r2, r4 + 8001a22: 42a2 cmp r2, r4 bcc FillZerobss - 8001174: d3fb bcc.n 800116e + 8001a24: d3fb bcc.n 8001a1e /* Call the clock system initialization function.*/ bl SystemInit - 8001176: f7ff ffd7 bl 8001128 + 8001a26: f7ff ffd7 bl 80019d8 /* Call static constructors */ bl __libc_init_array - 800117a: f002 fc35 bl 80039e8 <__libc_init_array> + 8001a2a: f002 fe33 bl 8004694 <__libc_init_array> /* Call the application's entry point.*/ bl main - 800117e: f7ff fcad bl 8000adc
+ 8001a2e: f7ff fc25 bl 800127c
bx lr - 8001182: 4770 bx lr + 8001a32: 4770 bx lr ldr sp, =_estack /* set stack pointer */ - 8001184: 20080000 .word 0x20080000 + 8001a34: 20080000 .word 0x20080000 ldr r0, =_sdata - 8001188: 20000000 .word 0x20000000 + 8001a38: 20000000 .word 0x20000000 ldr r1, =_edata - 800118c: 20000070 .word 0x20000070 + 8001a3c: 20000074 .word 0x20000074 ldr r2, =_sidata - 8001190: 08004cbc .word 0x08004cbc + 8001a40: 08005bc4 .word 0x08005bc4 ldr r2, =_sbss - 8001194: 20000070 .word 0x20000070 + 8001a44: 20000074 .word 0x20000074 ldr r4, =_ebss - 8001198: 200005e8 .word 0x200005e8 + 8001a48: 20000614 .word 0x20000614 -0800119c : +08001a4c : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop - 800119c: e7fe b.n 800119c + 8001a4c: e7fe b.n 8001a4c -0800119e : +08001a4e : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { - 800119e: b580 push {r7, lr} - 80011a0: af00 add r7, sp, #0 + 8001a4e: b580 push {r7, lr} + 8001a50: af00 add r7, sp, #0 #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - 80011a2: 2003 movs r0, #3 - 80011a4: f000 f920 bl 80013e8 + 8001a52: 2003 movs r0, #3 + 8001a54: f000 f920 bl 8001c98 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); - 80011a8: 2000 movs r0, #0 - 80011aa: f000 f805 bl 80011b8 + 8001a58: 2000 movs r0, #0 + 8001a5a: f000 f805 bl 8001a68 /* Init the low level hardware */ HAL_MspInit(); - 80011ae: f7ff fe55 bl 8000e5c + 8001a5e: f7ff fe35 bl 80016cc /* Return function status */ return HAL_OK; - 80011b2: 2300 movs r3, #0 + 8001a62: 2300 movs r3, #0 } - 80011b4: 4618 mov r0, r3 - 80011b6: bd80 pop {r7, pc} + 8001a64: 4618 mov r0, r3 + 8001a66: bd80 pop {r7, pc} -080011b8 : +08001a68 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - 80011b8: b580 push {r7, lr} - 80011ba: b082 sub sp, #8 - 80011bc: af00 add r7, sp, #0 - 80011be: 6078 str r0, [r7, #4] + 8001a68: b580 push {r7, lr} + 8001a6a: b082 sub sp, #8 + 8001a6c: af00 add r7, sp, #0 + 8001a6e: 6078 str r0, [r7, #4] /* Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) - 80011c0: 4b12 ldr r3, [pc, #72] ; (800120c ) - 80011c2: 681a ldr r2, [r3, #0] - 80011c4: 4b12 ldr r3, [pc, #72] ; (8001210 ) - 80011c6: 781b ldrb r3, [r3, #0] - 80011c8: 4619 mov r1, r3 - 80011ca: f44f 737a mov.w r3, #1000 ; 0x3e8 - 80011ce: fbb3 f3f1 udiv r3, r3, r1 - 80011d2: fbb2 f3f3 udiv r3, r2, r3 - 80011d6: 4618 mov r0, r3 - 80011d8: f000 f931 bl 800143e - 80011dc: 4603 mov r3, r0 - 80011de: 2b00 cmp r3, #0 - 80011e0: d001 beq.n 80011e6 + 8001a70: 4b12 ldr r3, [pc, #72] ; (8001abc ) + 8001a72: 681a ldr r2, [r3, #0] + 8001a74: 4b12 ldr r3, [pc, #72] ; (8001ac0 ) + 8001a76: 781b ldrb r3, [r3, #0] + 8001a78: 4619 mov r1, r3 + 8001a7a: f44f 737a mov.w r3, #1000 ; 0x3e8 + 8001a7e: fbb3 f3f1 udiv r3, r3, r1 + 8001a82: fbb2 f3f3 udiv r3, r2, r3 + 8001a86: 4618 mov r0, r3 + 8001a88: f000 f931 bl 8001cee + 8001a8c: 4603 mov r3, r0 + 8001a8e: 2b00 cmp r3, #0 + 8001a90: d001 beq.n 8001a96 { return HAL_ERROR; - 80011e2: 2301 movs r3, #1 - 80011e4: e00e b.n 8001204 + 8001a92: 2301 movs r3, #1 + 8001a94: e00e b.n 8001ab4 } /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - 80011e6: 687b ldr r3, [r7, #4] - 80011e8: 2b0f cmp r3, #15 - 80011ea: d80a bhi.n 8001202 + 8001a96: 687b ldr r3, [r7, #4] + 8001a98: 2b0f cmp r3, #15 + 8001a9a: d80a bhi.n 8001ab2 { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - 80011ec: 2200 movs r2, #0 - 80011ee: 6879 ldr r1, [r7, #4] - 80011f0: f04f 30ff mov.w r0, #4294967295 - 80011f4: f000 f903 bl 80013fe + 8001a9c: 2200 movs r2, #0 + 8001a9e: 6879 ldr r1, [r7, #4] + 8001aa0: f04f 30ff mov.w r0, #4294967295 + 8001aa4: f000 f903 bl 8001cae uwTickPrio = TickPriority; - 80011f8: 4a06 ldr r2, [pc, #24] ; (8001214 ) - 80011fa: 687b ldr r3, [r7, #4] - 80011fc: 6013 str r3, [r2, #0] + 8001aa8: 4a06 ldr r2, [pc, #24] ; (8001ac4 ) + 8001aaa: 687b ldr r3, [r7, #4] + 8001aac: 6013 str r3, [r2, #0] { return HAL_ERROR; } /* Return function status */ return HAL_OK; - 80011fe: 2300 movs r3, #0 - 8001200: e000 b.n 8001204 + 8001aae: 2300 movs r3, #0 + 8001ab0: e000 b.n 8001ab4 return HAL_ERROR; - 8001202: 2301 movs r3, #1 + 8001ab2: 2301 movs r3, #1 } - 8001204: 4618 mov r0, r3 - 8001206: 3708 adds r7, #8 - 8001208: 46bd mov sp, r7 - 800120a: bd80 pop {r7, pc} - 800120c: 20000000 .word 0x20000000 - 8001210: 20000008 .word 0x20000008 - 8001214: 20000004 .word 0x20000004 - -08001218 : + 8001ab4: 4618 mov r0, r3 + 8001ab6: 3708 adds r7, #8 + 8001ab8: 46bd mov sp, r7 + 8001aba: bd80 pop {r7, pc} + 8001abc: 20000004 .word 0x20000004 + 8001ac0: 2000000c .word 0x2000000c + 8001ac4: 20000008 .word 0x20000008 + +08001ac8 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { - 8001218: b480 push {r7} - 800121a: af00 add r7, sp, #0 + 8001ac8: b480 push {r7} + 8001aca: af00 add r7, sp, #0 uwTick += uwTickFreq; - 800121c: 4b06 ldr r3, [pc, #24] ; (8001238 ) - 800121e: 781b ldrb r3, [r3, #0] - 8001220: 461a mov r2, r3 - 8001222: 4b06 ldr r3, [pc, #24] ; (800123c ) - 8001224: 681b ldr r3, [r3, #0] - 8001226: 4413 add r3, r2 - 8001228: 4a04 ldr r2, [pc, #16] ; (800123c ) - 800122a: 6013 str r3, [r2, #0] + 8001acc: 4b06 ldr r3, [pc, #24] ; (8001ae8 ) + 8001ace: 781b ldrb r3, [r3, #0] + 8001ad0: 461a mov r2, r3 + 8001ad2: 4b06 ldr r3, [pc, #24] ; (8001aec ) + 8001ad4: 681b ldr r3, [r3, #0] + 8001ad6: 4413 add r3, r2 + 8001ad8: 4a04 ldr r2, [pc, #16] ; (8001aec ) + 8001ada: 6013 str r3, [r2, #0] } - 800122c: bf00 nop - 800122e: 46bd mov sp, r7 - 8001230: f85d 7b04 ldr.w r7, [sp], #4 - 8001234: 4770 bx lr - 8001236: bf00 nop - 8001238: 20000008 .word 0x20000008 - 800123c: 200005b8 .word 0x200005b8 - -08001240 : + 8001adc: bf00 nop + 8001ade: 46bd mov sp, r7 + 8001ae0: f85d 7b04 ldr.w r7, [sp], #4 + 8001ae4: 4770 bx lr + 8001ae6: bf00 nop + 8001ae8: 2000000c .word 0x2000000c + 8001aec: 200005e4 .word 0x200005e4 + +08001af0 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { - 8001240: b480 push {r7} - 8001242: af00 add r7, sp, #0 + 8001af0: b480 push {r7} + 8001af2: af00 add r7, sp, #0 return uwTick; - 8001244: 4b03 ldr r3, [pc, #12] ; (8001254 ) - 8001246: 681b ldr r3, [r3, #0] + 8001af4: 4b03 ldr r3, [pc, #12] ; (8001b04 ) + 8001af6: 681b ldr r3, [r3, #0] } - 8001248: 4618 mov r0, r3 - 800124a: 46bd mov sp, r7 - 800124c: f85d 7b04 ldr.w r7, [sp], #4 - 8001250: 4770 bx lr - 8001252: bf00 nop - 8001254: 200005b8 .word 0x200005b8 - -08001258 <__NVIC_SetPriorityGrouping>: + 8001af8: 4618 mov r0, r3 + 8001afa: 46bd mov sp, r7 + 8001afc: f85d 7b04 ldr.w r7, [sp], #4 + 8001b00: 4770 bx lr + 8001b02: bf00 nop + 8001b04: 200005e4 .word 0x200005e4 + +08001b08 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - 8001258: b480 push {r7} - 800125a: b085 sub sp, #20 - 800125c: af00 add r7, sp, #0 - 800125e: 6078 str r0, [r7, #4] + 8001b08: b480 push {r7} + 8001b0a: b085 sub sp, #20 + 8001b0c: af00 add r7, sp, #0 + 8001b0e: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 8001260: 687b ldr r3, [r7, #4] - 8001262: f003 0307 and.w r3, r3, #7 - 8001266: 60fb str r3, [r7, #12] + 8001b10: 687b ldr r3, [r7, #4] + 8001b12: f003 0307 and.w r3, r3, #7 + 8001b16: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ - 8001268: 4b0b ldr r3, [pc, #44] ; (8001298 <__NVIC_SetPriorityGrouping+0x40>) - 800126a: 68db ldr r3, [r3, #12] - 800126c: 60bb str r3, [r7, #8] + 8001b18: 4b0b ldr r3, [pc, #44] ; (8001b48 <__NVIC_SetPriorityGrouping+0x40>) + 8001b1a: 68db ldr r3, [r3, #12] + 8001b1c: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - 800126e: 68ba ldr r2, [r7, #8] - 8001270: f64f 03ff movw r3, #63743 ; 0xf8ff - 8001274: 4013 ands r3, r2 - 8001276: 60bb str r3, [r7, #8] + 8001b1e: 68ba ldr r2, [r7, #8] + 8001b20: f64f 03ff movw r3, #63743 ; 0xf8ff + 8001b24: 4013 ands r3, r2 + 8001b26: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - 8001278: 68fb ldr r3, [r7, #12] - 800127a: 021a lsls r2, r3, #8 + 8001b28: 68fb ldr r3, [r7, #12] + 8001b2a: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - 800127c: 68bb ldr r3, [r7, #8] - 800127e: 431a orrs r2, r3 + 8001b2c: 68bb ldr r3, [r7, #8] + 8001b2e: 431a orrs r2, r3 reg_value = (reg_value | - 8001280: 4b06 ldr r3, [pc, #24] ; (800129c <__NVIC_SetPriorityGrouping+0x44>) - 8001282: 4313 orrs r3, r2 - 8001284: 60bb str r3, [r7, #8] + 8001b30: 4b06 ldr r3, [pc, #24] ; (8001b4c <__NVIC_SetPriorityGrouping+0x44>) + 8001b32: 4313 orrs r3, r2 + 8001b34: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; - 8001286: 4a04 ldr r2, [pc, #16] ; (8001298 <__NVIC_SetPriorityGrouping+0x40>) - 8001288: 68bb ldr r3, [r7, #8] - 800128a: 60d3 str r3, [r2, #12] + 8001b36: 4a04 ldr r2, [pc, #16] ; (8001b48 <__NVIC_SetPriorityGrouping+0x40>) + 8001b38: 68bb ldr r3, [r7, #8] + 8001b3a: 60d3 str r3, [r2, #12] } - 800128c: bf00 nop - 800128e: 3714 adds r7, #20 - 8001290: 46bd mov sp, r7 - 8001292: f85d 7b04 ldr.w r7, [sp], #4 - 8001296: 4770 bx lr - 8001298: e000ed00 .word 0xe000ed00 - 800129c: 05fa0000 .word 0x05fa0000 - -080012a0 <__NVIC_GetPriorityGrouping>: + 8001b3c: bf00 nop + 8001b3e: 3714 adds r7, #20 + 8001b40: 46bd mov sp, r7 + 8001b42: f85d 7b04 ldr.w r7, [sp], #4 + 8001b46: 4770 bx lr + 8001b48: e000ed00 .word 0xe000ed00 + 8001b4c: 05fa0000 .word 0x05fa0000 + +08001b50 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { - 80012a0: b480 push {r7} - 80012a2: af00 add r7, sp, #0 + 8001b50: b480 push {r7} + 8001b52: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); - 80012a4: 4b04 ldr r3, [pc, #16] ; (80012b8 <__NVIC_GetPriorityGrouping+0x18>) - 80012a6: 68db ldr r3, [r3, #12] - 80012a8: 0a1b lsrs r3, r3, #8 - 80012aa: f003 0307 and.w r3, r3, #7 + 8001b54: 4b04 ldr r3, [pc, #16] ; (8001b68 <__NVIC_GetPriorityGrouping+0x18>) + 8001b56: 68db ldr r3, [r3, #12] + 8001b58: 0a1b lsrs r3, r3, #8 + 8001b5a: f003 0307 and.w r3, r3, #7 } - 80012ae: 4618 mov r0, r3 - 80012b0: 46bd mov sp, r7 - 80012b2: f85d 7b04 ldr.w r7, [sp], #4 - 80012b6: 4770 bx lr - 80012b8: e000ed00 .word 0xe000ed00 + 8001b5e: 4618 mov r0, r3 + 8001b60: 46bd mov sp, r7 + 8001b62: f85d 7b04 ldr.w r7, [sp], #4 + 8001b66: 4770 bx lr + 8001b68: e000ed00 .word 0xe000ed00 -080012bc <__NVIC_SetPriority>: +08001b6c <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - 80012bc: b480 push {r7} - 80012be: b083 sub sp, #12 - 80012c0: af00 add r7, sp, #0 - 80012c2: 4603 mov r3, r0 - 80012c4: 6039 str r1, [r7, #0] - 80012c6: 71fb strb r3, [r7, #7] + 8001b6c: b480 push {r7} + 8001b6e: b083 sub sp, #12 + 8001b70: af00 add r7, sp, #0 + 8001b72: 4603 mov r3, r0 + 8001b74: 6039 str r1, [r7, #0] + 8001b76: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) - 80012c8: f997 3007 ldrsb.w r3, [r7, #7] - 80012cc: 2b00 cmp r3, #0 - 80012ce: db0a blt.n 80012e6 <__NVIC_SetPriority+0x2a> + 8001b78: f997 3007 ldrsb.w r3, [r7, #7] + 8001b7c: 2b00 cmp r3, #0 + 8001b7e: db0a blt.n 8001b96 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 80012d0: 683b ldr r3, [r7, #0] - 80012d2: b2da uxtb r2, r3 - 80012d4: 490c ldr r1, [pc, #48] ; (8001308 <__NVIC_SetPriority+0x4c>) - 80012d6: f997 3007 ldrsb.w r3, [r7, #7] - 80012da: 0112 lsls r2, r2, #4 - 80012dc: b2d2 uxtb r2, r2 - 80012de: 440b add r3, r1 - 80012e0: f883 2300 strb.w r2, [r3, #768] ; 0x300 + 8001b80: 683b ldr r3, [r7, #0] + 8001b82: b2da uxtb r2, r3 + 8001b84: 490c ldr r1, [pc, #48] ; (8001bb8 <__NVIC_SetPriority+0x4c>) + 8001b86: f997 3007 ldrsb.w r3, [r7, #7] + 8001b8a: 0112 lsls r2, r2, #4 + 8001b8c: b2d2 uxtb r2, r2 + 8001b8e: 440b add r3, r1 + 8001b90: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } - 80012e4: e00a b.n 80012fc <__NVIC_SetPriority+0x40> + 8001b94: e00a b.n 8001bac <__NVIC_SetPriority+0x40> SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 80012e6: 683b ldr r3, [r7, #0] - 80012e8: b2da uxtb r2, r3 - 80012ea: 4908 ldr r1, [pc, #32] ; (800130c <__NVIC_SetPriority+0x50>) - 80012ec: 79fb ldrb r3, [r7, #7] - 80012ee: f003 030f and.w r3, r3, #15 - 80012f2: 3b04 subs r3, #4 - 80012f4: 0112 lsls r2, r2, #4 - 80012f6: b2d2 uxtb r2, r2 - 80012f8: 440b add r3, r1 - 80012fa: 761a strb r2, [r3, #24] + 8001b96: 683b ldr r3, [r7, #0] + 8001b98: b2da uxtb r2, r3 + 8001b9a: 4908 ldr r1, [pc, #32] ; (8001bbc <__NVIC_SetPriority+0x50>) + 8001b9c: 79fb ldrb r3, [r7, #7] + 8001b9e: f003 030f and.w r3, r3, #15 + 8001ba2: 3b04 subs r3, #4 + 8001ba4: 0112 lsls r2, r2, #4 + 8001ba6: b2d2 uxtb r2, r2 + 8001ba8: 440b add r3, r1 + 8001baa: 761a strb r2, [r3, #24] } - 80012fc: bf00 nop - 80012fe: 370c adds r7, #12 - 8001300: 46bd mov sp, r7 - 8001302: f85d 7b04 ldr.w r7, [sp], #4 - 8001306: 4770 bx lr - 8001308: e000e100 .word 0xe000e100 - 800130c: e000ed00 .word 0xe000ed00 - -08001310 : + 8001bac: bf00 nop + 8001bae: 370c adds r7, #12 + 8001bb0: 46bd mov sp, r7 + 8001bb2: f85d 7b04 ldr.w r7, [sp], #4 + 8001bb6: 4770 bx lr + 8001bb8: e000e100 .word 0xe000e100 + 8001bbc: e000ed00 .word 0xe000ed00 + +08001bc0 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { - 8001310: b480 push {r7} - 8001312: b089 sub sp, #36 ; 0x24 - 8001314: af00 add r7, sp, #0 - 8001316: 60f8 str r0, [r7, #12] - 8001318: 60b9 str r1, [r7, #8] - 800131a: 607a str r2, [r7, #4] + 8001bc0: b480 push {r7} + 8001bc2: b089 sub sp, #36 ; 0x24 + 8001bc4: af00 add r7, sp, #0 + 8001bc6: 60f8 str r0, [r7, #12] + 8001bc8: 60b9 str r1, [r7, #8] + 8001bca: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 800131c: 68fb ldr r3, [r7, #12] - 800131e: f003 0307 and.w r3, r3, #7 - 8001322: 61fb str r3, [r7, #28] + 8001bcc: 68fb ldr r3, [r7, #12] + 8001bce: f003 0307 and.w r3, r3, #7 + 8001bd2: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - 8001324: 69fb ldr r3, [r7, #28] - 8001326: f1c3 0307 rsb r3, r3, #7 - 800132a: 2b04 cmp r3, #4 - 800132c: bf28 it cs - 800132e: 2304 movcs r3, #4 - 8001330: 61bb str r3, [r7, #24] + 8001bd4: 69fb ldr r3, [r7, #28] + 8001bd6: f1c3 0307 rsb r3, r3, #7 + 8001bda: 2b04 cmp r3, #4 + 8001bdc: bf28 it cs + 8001bde: 2304 movcs r3, #4 + 8001be0: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - 8001332: 69fb ldr r3, [r7, #28] - 8001334: 3304 adds r3, #4 - 8001336: 2b06 cmp r3, #6 - 8001338: d902 bls.n 8001340 - 800133a: 69fb ldr r3, [r7, #28] - 800133c: 3b03 subs r3, #3 - 800133e: e000 b.n 8001342 - 8001340: 2300 movs r3, #0 - 8001342: 617b str r3, [r7, #20] + 8001be2: 69fb ldr r3, [r7, #28] + 8001be4: 3304 adds r3, #4 + 8001be6: 2b06 cmp r3, #6 + 8001be8: d902 bls.n 8001bf0 + 8001bea: 69fb ldr r3, [r7, #28] + 8001bec: 3b03 subs r3, #3 + 8001bee: e000 b.n 8001bf2 + 8001bf0: 2300 movs r3, #0 + 8001bf2: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 8001344: f04f 32ff mov.w r2, #4294967295 - 8001348: 69bb ldr r3, [r7, #24] - 800134a: fa02 f303 lsl.w r3, r2, r3 - 800134e: 43da mvns r2, r3 - 8001350: 68bb ldr r3, [r7, #8] - 8001352: 401a ands r2, r3 - 8001354: 697b ldr r3, [r7, #20] - 8001356: 409a lsls r2, r3 + 8001bf4: f04f 32ff mov.w r2, #4294967295 + 8001bf8: 69bb ldr r3, [r7, #24] + 8001bfa: fa02 f303 lsl.w r3, r2, r3 + 8001bfe: 43da mvns r2, r3 + 8001c00: 68bb ldr r3, [r7, #8] + 8001c02: 401a ands r2, r3 + 8001c04: 697b ldr r3, [r7, #20] + 8001c06: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - 8001358: f04f 31ff mov.w r1, #4294967295 - 800135c: 697b ldr r3, [r7, #20] - 800135e: fa01 f303 lsl.w r3, r1, r3 - 8001362: 43d9 mvns r1, r3 - 8001364: 687b ldr r3, [r7, #4] - 8001366: 400b ands r3, r1 + 8001c08: f04f 31ff mov.w r1, #4294967295 + 8001c0c: 697b ldr r3, [r7, #20] + 8001c0e: fa01 f303 lsl.w r3, r1, r3 + 8001c12: 43d9 mvns r1, r3 + 8001c14: 687b ldr r3, [r7, #4] + 8001c16: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 8001368: 4313 orrs r3, r2 + 8001c18: 4313 orrs r3, r2 ); } - 800136a: 4618 mov r0, r3 - 800136c: 3724 adds r7, #36 ; 0x24 - 800136e: 46bd mov sp, r7 - 8001370: f85d 7b04 ldr.w r7, [sp], #4 - 8001374: 4770 bx lr + 8001c1a: 4618 mov r0, r3 + 8001c1c: 3724 adds r7, #36 ; 0x24 + 8001c1e: 46bd mov sp, r7 + 8001c20: f85d 7b04 ldr.w r7, [sp], #4 + 8001c24: 4770 bx lr ... -08001378 <__NVIC_SystemReset>: +08001c28 <__NVIC_SystemReset>: /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { - 8001378: b480 push {r7} - 800137a: af00 add r7, sp, #0 + 8001c28: b480 push {r7} + 8001c2a: af00 add r7, sp, #0 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); - 800137c: f3bf 8f4f dsb sy + 8001c2c: f3bf 8f4f dsb sy } - 8001380: bf00 nop + 8001c30: bf00 nop __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - 8001382: 4b06 ldr r3, [pc, #24] ; (800139c <__NVIC_SystemReset+0x24>) - 8001384: 68db ldr r3, [r3, #12] - 8001386: f403 62e0 and.w r2, r3, #1792 ; 0x700 + 8001c32: 4b06 ldr r3, [pc, #24] ; (8001c4c <__NVIC_SystemReset+0x24>) + 8001c34: 68db ldr r3, [r3, #12] + 8001c36: f403 62e0 and.w r2, r3, #1792 ; 0x700 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - 800138a: 4904 ldr r1, [pc, #16] ; (800139c <__NVIC_SystemReset+0x24>) - 800138c: 4b04 ldr r3, [pc, #16] ; (80013a0 <__NVIC_SystemReset+0x28>) - 800138e: 4313 orrs r3, r2 - 8001390: 60cb str r3, [r1, #12] + 8001c3a: 4904 ldr r1, [pc, #16] ; (8001c4c <__NVIC_SystemReset+0x24>) + 8001c3c: 4b04 ldr r3, [pc, #16] ; (8001c50 <__NVIC_SystemReset+0x28>) + 8001c3e: 4313 orrs r3, r2 + 8001c40: 60cb str r3, [r1, #12] __ASM volatile ("dsb 0xF":::"memory"); - 8001392: f3bf 8f4f dsb sy + 8001c42: f3bf 8f4f dsb sy } - 8001396: bf00 nop + 8001c46: bf00 nop SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); - 8001398: bf00 nop - 800139a: e7fd b.n 8001398 <__NVIC_SystemReset+0x20> - 800139c: e000ed00 .word 0xe000ed00 - 80013a0: 05fa0004 .word 0x05fa0004 + 8001c48: bf00 nop + 8001c4a: e7fd b.n 8001c48 <__NVIC_SystemReset+0x20> + 8001c4c: e000ed00 .word 0xe000ed00 + 8001c50: 05fa0004 .word 0x05fa0004 -080013a4 : +08001c54 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - 80013a4: b580 push {r7, lr} - 80013a6: b082 sub sp, #8 - 80013a8: af00 add r7, sp, #0 - 80013aa: 6078 str r0, [r7, #4] + 8001c54: b580 push {r7, lr} + 8001c56: b082 sub sp, #8 + 8001c58: af00 add r7, sp, #0 + 8001c5a: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - 80013ac: 687b ldr r3, [r7, #4] - 80013ae: 3b01 subs r3, #1 - 80013b0: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 - 80013b4: d301 bcc.n 80013ba + 8001c5c: 687b ldr r3, [r7, #4] + 8001c5e: 3b01 subs r3, #1 + 8001c60: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 + 8001c64: d301 bcc.n 8001c6a { return (1UL); /* Reload value impossible */ - 80013b6: 2301 movs r3, #1 - 80013b8: e00f b.n 80013da + 8001c66: 2301 movs r3, #1 + 8001c68: e00f b.n 8001c8a } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - 80013ba: 4a0a ldr r2, [pc, #40] ; (80013e4 ) - 80013bc: 687b ldr r3, [r7, #4] - 80013be: 3b01 subs r3, #1 - 80013c0: 6053 str r3, [r2, #4] + 8001c6a: 4a0a ldr r2, [pc, #40] ; (8001c94 ) + 8001c6c: 687b ldr r3, [r7, #4] + 8001c6e: 3b01 subs r3, #1 + 8001c70: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - 80013c2: 210f movs r1, #15 - 80013c4: f04f 30ff mov.w r0, #4294967295 - 80013c8: f7ff ff78 bl 80012bc <__NVIC_SetPriority> + 8001c72: 210f movs r1, #15 + 8001c74: f04f 30ff mov.w r0, #4294967295 + 8001c78: f7ff ff78 bl 8001b6c <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - 80013cc: 4b05 ldr r3, [pc, #20] ; (80013e4 ) - 80013ce: 2200 movs r2, #0 - 80013d0: 609a str r2, [r3, #8] + 8001c7c: 4b05 ldr r3, [pc, #20] ; (8001c94 ) + 8001c7e: 2200 movs r2, #0 + 8001c80: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - 80013d2: 4b04 ldr r3, [pc, #16] ; (80013e4 ) - 80013d4: 2207 movs r2, #7 - 80013d6: 601a str r2, [r3, #0] + 8001c82: 4b04 ldr r3, [pc, #16] ; (8001c94 ) + 8001c84: 2207 movs r2, #7 + 8001c86: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ - 80013d8: 2300 movs r3, #0 + 8001c88: 2300 movs r3, #0 } - 80013da: 4618 mov r0, r3 - 80013dc: 3708 adds r7, #8 - 80013de: 46bd mov sp, r7 - 80013e0: bd80 pop {r7, pc} - 80013e2: bf00 nop - 80013e4: e000e010 .word 0xe000e010 - -080013e8 : + 8001c8a: 4618 mov r0, r3 + 8001c8c: 3708 adds r7, #8 + 8001c8e: 46bd mov sp, r7 + 8001c90: bd80 pop {r7, pc} + 8001c92: bf00 nop + 8001c94: e000e010 .word 0xe000e010 + +08001c98 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - 80013e8: b580 push {r7, lr} - 80013ea: b082 sub sp, #8 - 80013ec: af00 add r7, sp, #0 - 80013ee: 6078 str r0, [r7, #4] + 8001c98: b580 push {r7, lr} + 8001c9a: b082 sub sp, #8 + 8001c9c: af00 add r7, sp, #0 + 8001c9e: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); - 80013f0: 6878 ldr r0, [r7, #4] - 80013f2: f7ff ff31 bl 8001258 <__NVIC_SetPriorityGrouping> + 8001ca0: 6878 ldr r0, [r7, #4] + 8001ca2: f7ff ff31 bl 8001b08 <__NVIC_SetPriorityGrouping> } - 80013f6: bf00 nop - 80013f8: 3708 adds r7, #8 - 80013fa: 46bd mov sp, r7 - 80013fc: bd80 pop {r7, pc} + 8001ca6: bf00 nop + 8001ca8: 3708 adds r7, #8 + 8001caa: 46bd mov sp, r7 + 8001cac: bd80 pop {r7, pc} -080013fe : +08001cae : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { - 80013fe: b580 push {r7, lr} - 8001400: b086 sub sp, #24 - 8001402: af00 add r7, sp, #0 - 8001404: 4603 mov r3, r0 - 8001406: 60b9 str r1, [r7, #8] - 8001408: 607a str r2, [r7, #4] - 800140a: 73fb strb r3, [r7, #15] + 8001cae: b580 push {r7, lr} + 8001cb0: b086 sub sp, #24 + 8001cb2: af00 add r7, sp, #0 + 8001cb4: 4603 mov r3, r0 + 8001cb6: 60b9 str r1, [r7, #8] + 8001cb8: 607a str r2, [r7, #4] + 8001cba: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00; - 800140c: 2300 movs r3, #0 - 800140e: 617b str r3, [r7, #20] + 8001cbc: 2300 movs r3, #0 + 8001cbe: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); - 8001410: f7ff ff46 bl 80012a0 <__NVIC_GetPriorityGrouping> - 8001414: 6178 str r0, [r7, #20] + 8001cc0: f7ff ff46 bl 8001b50 <__NVIC_GetPriorityGrouping> + 8001cc4: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); - 8001416: 687a ldr r2, [r7, #4] - 8001418: 68b9 ldr r1, [r7, #8] - 800141a: 6978 ldr r0, [r7, #20] - 800141c: f7ff ff78 bl 8001310 - 8001420: 4602 mov r2, r0 - 8001422: f997 300f ldrsb.w r3, [r7, #15] - 8001426: 4611 mov r1, r2 - 8001428: 4618 mov r0, r3 - 800142a: f7ff ff47 bl 80012bc <__NVIC_SetPriority> + 8001cc6: 687a ldr r2, [r7, #4] + 8001cc8: 68b9 ldr r1, [r7, #8] + 8001cca: 6978 ldr r0, [r7, #20] + 8001ccc: f7ff ff78 bl 8001bc0 + 8001cd0: 4602 mov r2, r0 + 8001cd2: f997 300f ldrsb.w r3, [r7, #15] + 8001cd6: 4611 mov r1, r2 + 8001cd8: 4618 mov r0, r3 + 8001cda: f7ff ff47 bl 8001b6c <__NVIC_SetPriority> } - 800142e: bf00 nop - 8001430: 3718 adds r7, #24 - 8001432: 46bd mov sp, r7 - 8001434: bd80 pop {r7, pc} + 8001cde: bf00 nop + 8001ce0: 3718 adds r7, #24 + 8001ce2: 46bd mov sp, r7 + 8001ce4: bd80 pop {r7, pc} -08001436 : +08001ce6 : /** * @brief Initiates a system reset request to reset the MCU. * @retval None */ void HAL_NVIC_SystemReset(void) { - 8001436: b580 push {r7, lr} - 8001438: af00 add r7, sp, #0 + 8001ce6: b580 push {r7, lr} + 8001ce8: af00 add r7, sp, #0 /* System Reset */ NVIC_SystemReset(); - 800143a: f7ff ff9d bl 8001378 <__NVIC_SystemReset> + 8001cea: f7ff ff9d bl 8001c28 <__NVIC_SystemReset> -0800143e : +08001cee : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { - 800143e: b580 push {r7, lr} - 8001440: b082 sub sp, #8 - 8001442: af00 add r7, sp, #0 - 8001444: 6078 str r0, [r7, #4] + 8001cee: b580 push {r7, lr} + 8001cf0: b082 sub sp, #8 + 8001cf2: af00 add r7, sp, #0 + 8001cf4: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); - 8001446: 6878 ldr r0, [r7, #4] - 8001448: f7ff ffac bl 80013a4 - 800144c: 4603 mov r3, r0 + 8001cf6: 6878 ldr r0, [r7, #4] + 8001cf8: f7ff ffac bl 8001c54 + 8001cfc: 4603 mov r3, r0 } - 800144e: 4618 mov r0, r3 - 8001450: 3708 adds r7, #8 - 8001452: 46bd mov sp, r7 - 8001454: bd80 pop {r7, pc} + 8001cfe: 4618 mov r0, r3 + 8001d00: 3708 adds r7, #8 + 8001d02: 46bd mov sp, r7 + 8001d04: bd80 pop {r7, pc} ... -08001458 : +08001d08 : + * parameters in the CRC_InitTypeDef and create the associated handle. + * @param hcrc CRC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) +{ + 8001d08: b580 push {r7, lr} + 8001d0a: b082 sub sp, #8 + 8001d0c: af00 add r7, sp, #0 + 8001d0e: 6078 str r0, [r7, #4] + /* Check the CRC handle allocation */ + if (hcrc == NULL) + 8001d10: 687b ldr r3, [r7, #4] + 8001d12: 2b00 cmp r3, #0 + 8001d14: d101 bne.n 8001d1a + { + return HAL_ERROR; + 8001d16: 2301 movs r3, #1 + 8001d18: e054 b.n 8001dc4 + } + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); + + if (hcrc->State == HAL_CRC_STATE_RESET) + 8001d1a: 687b ldr r3, [r7, #4] + 8001d1c: 7f5b ldrb r3, [r3, #29] + 8001d1e: b2db uxtb r3, r3 + 8001d20: 2b00 cmp r3, #0 + 8001d22: d105 bne.n 8001d30 + { + /* Allocate lock resource and initialize it */ + hcrc->Lock = HAL_UNLOCKED; + 8001d24: 687b ldr r3, [r7, #4] + 8001d26: 2200 movs r2, #0 + 8001d28: 771a strb r2, [r3, #28] + /* Init the low level hardware */ + HAL_CRC_MspInit(hcrc); + 8001d2a: 6878 ldr r0, [r7, #4] + 8001d2c: f7ff fcf2 bl 8001714 + } + + hcrc->State = HAL_CRC_STATE_BUSY; + 8001d30: 687b ldr r3, [r7, #4] + 8001d32: 2202 movs r2, #2 + 8001d34: 775a strb r2, [r3, #29] + + /* check whether or not non-default generating polynomial has been + * picked up by user */ + assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); + if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) + 8001d36: 687b ldr r3, [r7, #4] + 8001d38: 791b ldrb r3, [r3, #4] + 8001d3a: 2b00 cmp r3, #0 + 8001d3c: d10c bne.n 8001d58 + { + /* initialize peripheral with default generating polynomial */ + WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); + 8001d3e: 687b ldr r3, [r7, #4] + 8001d40: 681b ldr r3, [r3, #0] + 8001d42: 4a22 ldr r2, [pc, #136] ; (8001dcc ) + 8001d44: 615a str r2, [r3, #20] + MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); + 8001d46: 687b ldr r3, [r7, #4] + 8001d48: 681b ldr r3, [r3, #0] + 8001d4a: 689a ldr r2, [r3, #8] + 8001d4c: 687b ldr r3, [r7, #4] + 8001d4e: 681b ldr r3, [r3, #0] + 8001d50: f022 0218 bic.w r2, r2, #24 + 8001d54: 609a str r2, [r3, #8] + 8001d56: e00c b.n 8001d72 + } + else + { + /* initialize CRC peripheral with generating polynomial defined by user */ + if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK) + 8001d58: 687b ldr r3, [r7, #4] + 8001d5a: 6899 ldr r1, [r3, #8] + 8001d5c: 687b ldr r3, [r7, #4] + 8001d5e: 68db ldr r3, [r3, #12] + 8001d60: 461a mov r2, r3 + 8001d62: 6878 ldr r0, [r7, #4] + 8001d64: f000 f948 bl 8001ff8 + 8001d68: 4603 mov r3, r0 + 8001d6a: 2b00 cmp r3, #0 + 8001d6c: d001 beq.n 8001d72 + { + return HAL_ERROR; + 8001d6e: 2301 movs r3, #1 + 8001d70: e028 b.n 8001dc4 + } + + /* check whether or not non-default CRC initial value has been + * picked up by user */ + assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse)); + if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) + 8001d72: 687b ldr r3, [r7, #4] + 8001d74: 795b ldrb r3, [r3, #5] + 8001d76: 2b00 cmp r3, #0 + 8001d78: d105 bne.n 8001d86 + { + WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); + 8001d7a: 687b ldr r3, [r7, #4] + 8001d7c: 681b ldr r3, [r3, #0] + 8001d7e: f04f 32ff mov.w r2, #4294967295 + 8001d82: 611a str r2, [r3, #16] + 8001d84: e004 b.n 8001d90 + } + else + { + WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); + 8001d86: 687b ldr r3, [r7, #4] + 8001d88: 681b ldr r3, [r3, #0] + 8001d8a: 687a ldr r2, [r7, #4] + 8001d8c: 6912 ldr r2, [r2, #16] + 8001d8e: 611a str r2, [r3, #16] + } + + + /* set input data inversion mode */ + assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); + 8001d90: 687b ldr r3, [r7, #4] + 8001d92: 681b ldr r3, [r3, #0] + 8001d94: 689b ldr r3, [r3, #8] + 8001d96: f023 0160 bic.w r1, r3, #96 ; 0x60 + 8001d9a: 687b ldr r3, [r7, #4] + 8001d9c: 695a ldr r2, [r3, #20] + 8001d9e: 687b ldr r3, [r7, #4] + 8001da0: 681b ldr r3, [r3, #0] + 8001da2: 430a orrs r2, r1 + 8001da4: 609a str r2, [r3, #8] + + /* set output data inversion mode */ + assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); + 8001da6: 687b ldr r3, [r7, #4] + 8001da8: 681b ldr r3, [r3, #0] + 8001daa: 689b ldr r3, [r3, #8] + 8001dac: f023 0180 bic.w r1, r3, #128 ; 0x80 + 8001db0: 687b ldr r3, [r7, #4] + 8001db2: 699a ldr r2, [r3, #24] + 8001db4: 687b ldr r3, [r7, #4] + 8001db6: 681b ldr r3, [r3, #0] + 8001db8: 430a orrs r2, r1 + 8001dba: 609a str r2, [r3, #8] + /* makes sure the input data format (bytes, halfwords or words stream) + * is properly specified by user */ + assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat)); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + 8001dbc: 687b ldr r3, [r7, #4] + 8001dbe: 2201 movs r2, #1 + 8001dc0: 775a strb r2, [r3, #29] + + /* Return function status */ + return HAL_OK; + 8001dc2: 2300 movs r3, #0 +} + 8001dc4: 4618 mov r0, r3 + 8001dc6: 3708 adds r7, #8 + 8001dc8: 46bd mov sp, r7 + 8001dca: bd80 pop {r7, pc} + 8001dcc: 04c11db7 .word 0x04c11db7 + +08001dd0 : + * and the API will internally adjust its input data processing based on the + * handle field hcrc->InputDataFormat. + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +{ + 8001dd0: b580 push {r7, lr} + 8001dd2: b086 sub sp, #24 + 8001dd4: af00 add r7, sp, #0 + 8001dd6: 60f8 str r0, [r7, #12] + 8001dd8: 60b9 str r1, [r7, #8] + 8001dda: 607a str r2, [r7, #4] + uint32_t index; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ + 8001ddc: 2300 movs r3, #0 + 8001dde: 613b str r3, [r7, #16] + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + 8001de0: 68fb ldr r3, [r7, #12] + 8001de2: 2202 movs r2, #2 + 8001de4: 775a strb r2, [r3, #29] + + /* Reset CRC Calculation Unit (hcrc->Instance->INIT is + * written in hcrc->Instance->DR) */ + __HAL_CRC_DR_RESET(hcrc); + 8001de6: 68fb ldr r3, [r7, #12] + 8001de8: 681b ldr r3, [r3, #0] + 8001dea: 689a ldr r2, [r3, #8] + 8001dec: 68fb ldr r3, [r7, #12] + 8001dee: 681b ldr r3, [r3, #0] + 8001df0: f042 0201 orr.w r2, r2, #1 + 8001df4: 609a str r2, [r3, #8] + + switch (hcrc->InputDataFormat) + 8001df6: 68fb ldr r3, [r7, #12] + 8001df8: 6a1b ldr r3, [r3, #32] + 8001dfa: 2b03 cmp r3, #3 + 8001dfc: d006 beq.n 8001e0c + 8001dfe: 2b03 cmp r3, #3 + 8001e00: d829 bhi.n 8001e56 + 8001e02: 2b01 cmp r3, #1 + 8001e04: d019 beq.n 8001e3a + 8001e06: 2b02 cmp r3, #2 + 8001e08: d01e beq.n 8001e48 + /* Specific 16-bit input data handling */ + temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ + break; + + default: + break; + 8001e0a: e024 b.n 8001e56 + for (index = 0U; index < BufferLength; index++) + 8001e0c: 2300 movs r3, #0 + 8001e0e: 617b str r3, [r7, #20] + 8001e10: e00a b.n 8001e28 + hcrc->Instance->DR = pBuffer[index]; + 8001e12: 697b ldr r3, [r7, #20] + 8001e14: 009b lsls r3, r3, #2 + 8001e16: 68ba ldr r2, [r7, #8] + 8001e18: 441a add r2, r3 + 8001e1a: 68fb ldr r3, [r7, #12] + 8001e1c: 681b ldr r3, [r3, #0] + 8001e1e: 6812 ldr r2, [r2, #0] + 8001e20: 601a str r2, [r3, #0] + for (index = 0U; index < BufferLength; index++) + 8001e22: 697b ldr r3, [r7, #20] + 8001e24: 3301 adds r3, #1 + 8001e26: 617b str r3, [r7, #20] + 8001e28: 697a ldr r2, [r7, #20] + 8001e2a: 687b ldr r3, [r7, #4] + 8001e2c: 429a cmp r2, r3 + 8001e2e: d3f0 bcc.n 8001e12 + temp = hcrc->Instance->DR; + 8001e30: 68fb ldr r3, [r7, #12] + 8001e32: 681b ldr r3, [r3, #0] + 8001e34: 681b ldr r3, [r3, #0] + 8001e36: 613b str r3, [r7, #16] + break; + 8001e38: e00e b.n 8001e58 + temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); + 8001e3a: 687a ldr r2, [r7, #4] + 8001e3c: 68b9 ldr r1, [r7, #8] + 8001e3e: 68f8 ldr r0, [r7, #12] + 8001e40: f000 f812 bl 8001e68 + 8001e44: 6138 str r0, [r7, #16] + break; + 8001e46: e007 b.n 8001e58 + temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ + 8001e48: 687a ldr r2, [r7, #4] + 8001e4a: 68b9 ldr r1, [r7, #8] + 8001e4c: 68f8 ldr r0, [r7, #12] + 8001e4e: f000 f899 bl 8001f84 + 8001e52: 6138 str r0, [r7, #16] + break; + 8001e54: e000 b.n 8001e58 + break; + 8001e56: bf00 nop + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + 8001e58: 68fb ldr r3, [r7, #12] + 8001e5a: 2201 movs r2, #1 + 8001e5c: 775a strb r2, [r3, #29] + + /* Return the CRC computed value */ + return temp; + 8001e5e: 693b ldr r3, [r7, #16] +} + 8001e60: 4618 mov r0, r3 + 8001e62: 3718 adds r7, #24 + 8001e64: 46bd mov sp, r7 + 8001e66: bd80 pop {r7, pc} + +08001e68 : + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) +{ + 8001e68: b480 push {r7} + 8001e6a: b089 sub sp, #36 ; 0x24 + 8001e6c: af00 add r7, sp, #0 + 8001e6e: 60f8 str r0, [r7, #12] + 8001e70: 60b9 str r1, [r7, #8] + 8001e72: 607a str r2, [r7, #4] + __IO uint16_t *pReg; + + /* Processing time optimization: 4 bytes are entered in a row with a single word write, + * last bytes must be carefully fed to the CRC calculator to ensure a correct type + * handling by the peripheral */ + for (i = 0U; i < (BufferLength / 4U); i++) + 8001e74: 2300 movs r3, #0 + 8001e76: 61fb str r3, [r7, #28] + 8001e78: e023 b.n 8001ec2 + { + hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ + 8001e7a: 69fb ldr r3, [r7, #28] + 8001e7c: 009b lsls r3, r3, #2 + 8001e7e: 68ba ldr r2, [r7, #8] + 8001e80: 4413 add r3, r2 + 8001e82: 781b ldrb r3, [r3, #0] + 8001e84: 061a lsls r2, r3, #24 + ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ + 8001e86: 69fb ldr r3, [r7, #28] + 8001e88: 009b lsls r3, r3, #2 + 8001e8a: 3301 adds r3, #1 + 8001e8c: 68b9 ldr r1, [r7, #8] + 8001e8e: 440b add r3, r1 + 8001e90: 781b ldrb r3, [r3, #0] + 8001e92: 041b lsls r3, r3, #16 + hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ + 8001e94: 431a orrs r2, r3 + ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ + 8001e96: 69fb ldr r3, [r7, #28] + 8001e98: 009b lsls r3, r3, #2 + 8001e9a: 3302 adds r3, #2 + 8001e9c: 68b9 ldr r1, [r7, #8] + 8001e9e: 440b add r3, r1 + 8001ea0: 781b ldrb r3, [r3, #0] + 8001ea2: 021b lsls r3, r3, #8 + ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ + 8001ea4: 431a orrs r2, r3 + (uint32_t)pBuffer[(4U * i) + 3U]; + 8001ea6: 69fb ldr r3, [r7, #28] + 8001ea8: 009b lsls r3, r3, #2 + 8001eaa: 3303 adds r3, #3 + 8001eac: 68b9 ldr r1, [r7, #8] + 8001eae: 440b add r3, r1 + 8001eb0: 781b ldrb r3, [r3, #0] + 8001eb2: 4619 mov r1, r3 + hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ + 8001eb4: 68fb ldr r3, [r7, #12] + 8001eb6: 681b ldr r3, [r3, #0] + ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ + 8001eb8: 430a orrs r2, r1 + hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ + 8001eba: 601a str r2, [r3, #0] + for (i = 0U; i < (BufferLength / 4U); i++) + 8001ebc: 69fb ldr r3, [r7, #28] + 8001ebe: 3301 adds r3, #1 + 8001ec0: 61fb str r3, [r7, #28] + 8001ec2: 687b ldr r3, [r7, #4] + 8001ec4: 089b lsrs r3, r3, #2 + 8001ec6: 69fa ldr r2, [r7, #28] + 8001ec8: 429a cmp r2, r3 + 8001eca: d3d6 bcc.n 8001e7a + } + /* last bytes specific handling */ + if ((BufferLength % 4U) != 0U) + 8001ecc: 687b ldr r3, [r7, #4] + 8001ece: f003 0303 and.w r3, r3, #3 + 8001ed2: 2b00 cmp r3, #0 + 8001ed4: d04d beq.n 8001f72 + { + if ((BufferLength % 4U) == 1U) + 8001ed6: 687b ldr r3, [r7, #4] + 8001ed8: f003 0303 and.w r3, r3, #3 + 8001edc: 2b01 cmp r3, #1 + 8001ede: d107 bne.n 8001ef0 + { + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ + 8001ee0: 69fb ldr r3, [r7, #28] + 8001ee2: 009b lsls r3, r3, #2 + 8001ee4: 68ba ldr r2, [r7, #8] + 8001ee6: 4413 add r3, r2 + 8001ee8: 68fa ldr r2, [r7, #12] + 8001eea: 6812 ldr r2, [r2, #0] + 8001eec: 781b ldrb r3, [r3, #0] + 8001eee: 7013 strb r3, [r2, #0] + } + if ((BufferLength % 4U) == 2U) + 8001ef0: 687b ldr r3, [r7, #4] + 8001ef2: f003 0303 and.w r3, r3, #3 + 8001ef6: 2b02 cmp r3, #2 + 8001ef8: d116 bne.n 8001f28 + { + data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; + 8001efa: 69fb ldr r3, [r7, #28] + 8001efc: 009b lsls r3, r3, #2 + 8001efe: 68ba ldr r2, [r7, #8] + 8001f00: 4413 add r3, r2 + 8001f02: 781b ldrb r3, [r3, #0] + 8001f04: 021b lsls r3, r3, #8 + 8001f06: b21a sxth r2, r3 + 8001f08: 69fb ldr r3, [r7, #28] + 8001f0a: 009b lsls r3, r3, #2 + 8001f0c: 3301 adds r3, #1 + 8001f0e: 68b9 ldr r1, [r7, #8] + 8001f10: 440b add r3, r1 + 8001f12: 781b ldrb r3, [r3, #0] + 8001f14: b21b sxth r3, r3 + 8001f16: 4313 orrs r3, r2 + 8001f18: b21b sxth r3, r3 + 8001f1a: 837b strh r3, [r7, #26] + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ + 8001f1c: 68fb ldr r3, [r7, #12] + 8001f1e: 681b ldr r3, [r3, #0] + 8001f20: 617b str r3, [r7, #20] + *pReg = data; + 8001f22: 697b ldr r3, [r7, #20] + 8001f24: 8b7a ldrh r2, [r7, #26] + 8001f26: 801a strh r2, [r3, #0] + } + if ((BufferLength % 4U) == 3U) + 8001f28: 687b ldr r3, [r7, #4] + 8001f2a: f003 0303 and.w r3, r3, #3 + 8001f2e: 2b03 cmp r3, #3 + 8001f30: d11f bne.n 8001f72 + { + data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; + 8001f32: 69fb ldr r3, [r7, #28] + 8001f34: 009b lsls r3, r3, #2 + 8001f36: 68ba ldr r2, [r7, #8] + 8001f38: 4413 add r3, r2 + 8001f3a: 781b ldrb r3, [r3, #0] + 8001f3c: 021b lsls r3, r3, #8 + 8001f3e: b21a sxth r2, r3 + 8001f40: 69fb ldr r3, [r7, #28] + 8001f42: 009b lsls r3, r3, #2 + 8001f44: 3301 adds r3, #1 + 8001f46: 68b9 ldr r1, [r7, #8] + 8001f48: 440b add r3, r1 + 8001f4a: 781b ldrb r3, [r3, #0] + 8001f4c: b21b sxth r3, r3 + 8001f4e: 4313 orrs r3, r2 + 8001f50: b21b sxth r3, r3 + 8001f52: 837b strh r3, [r7, #26] + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ + 8001f54: 68fb ldr r3, [r7, #12] + 8001f56: 681b ldr r3, [r3, #0] + 8001f58: 617b str r3, [r7, #20] + *pReg = data; + 8001f5a: 697b ldr r3, [r7, #20] + 8001f5c: 8b7a ldrh r2, [r7, #26] + 8001f5e: 801a strh r2, [r3, #0] + + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ + 8001f60: 69fb ldr r3, [r7, #28] + 8001f62: 009b lsls r3, r3, #2 + 8001f64: 3302 adds r3, #2 + 8001f66: 68ba ldr r2, [r7, #8] + 8001f68: 4413 add r3, r2 + 8001f6a: 68fa ldr r2, [r7, #12] + 8001f6c: 6812 ldr r2, [r2, #0] + 8001f6e: 781b ldrb r3, [r3, #0] + 8001f70: 7013 strb r3, [r2, #0] + } + } + + /* Return the CRC computed value */ + return hcrc->Instance->DR; + 8001f72: 68fb ldr r3, [r7, #12] + 8001f74: 681b ldr r3, [r3, #0] + 8001f76: 681b ldr r3, [r3, #0] +} + 8001f78: 4618 mov r0, r3 + 8001f7a: 3724 adds r7, #36 ; 0x24 + 8001f7c: 46bd mov sp, r7 + 8001f7e: f85d 7b04 ldr.w r7, [sp], #4 + 8001f82: 4770 bx lr + +08001f84 : + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) +{ + 8001f84: b480 push {r7} + 8001f86: b087 sub sp, #28 + 8001f88: af00 add r7, sp, #0 + 8001f8a: 60f8 str r0, [r7, #12] + 8001f8c: 60b9 str r1, [r7, #8] + 8001f8e: 607a str r2, [r7, #4] + __IO uint16_t *pReg; + + /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, + * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure + * a correct type handling by the peripheral */ + for (i = 0U; i < (BufferLength / 2U); i++) + 8001f90: 2300 movs r3, #0 + 8001f92: 617b str r3, [r7, #20] + 8001f94: e013 b.n 8001fbe + { + hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U]; + 8001f96: 697b ldr r3, [r7, #20] + 8001f98: 009b lsls r3, r3, #2 + 8001f9a: 68ba ldr r2, [r7, #8] + 8001f9c: 4413 add r3, r2 + 8001f9e: 881b ldrh r3, [r3, #0] + 8001fa0: 041a lsls r2, r3, #16 + 8001fa2: 697b ldr r3, [r7, #20] + 8001fa4: 009b lsls r3, r3, #2 + 8001fa6: 3302 adds r3, #2 + 8001fa8: 68b9 ldr r1, [r7, #8] + 8001faa: 440b add r3, r1 + 8001fac: 881b ldrh r3, [r3, #0] + 8001fae: 4619 mov r1, r3 + 8001fb0: 68fb ldr r3, [r7, #12] + 8001fb2: 681b ldr r3, [r3, #0] + 8001fb4: 430a orrs r2, r1 + 8001fb6: 601a str r2, [r3, #0] + for (i = 0U; i < (BufferLength / 2U); i++) + 8001fb8: 697b ldr r3, [r7, #20] + 8001fba: 3301 adds r3, #1 + 8001fbc: 617b str r3, [r7, #20] + 8001fbe: 687b ldr r3, [r7, #4] + 8001fc0: 085b lsrs r3, r3, #1 + 8001fc2: 697a ldr r2, [r7, #20] + 8001fc4: 429a cmp r2, r3 + 8001fc6: d3e6 bcc.n 8001f96 + } + if ((BufferLength % 2U) != 0U) + 8001fc8: 687b ldr r3, [r7, #4] + 8001fca: f003 0301 and.w r3, r3, #1 + 8001fce: 2b00 cmp r3, #0 + 8001fd0: d009 beq.n 8001fe6 + { + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ + 8001fd2: 68fb ldr r3, [r7, #12] + 8001fd4: 681b ldr r3, [r3, #0] + 8001fd6: 613b str r3, [r7, #16] + *pReg = pBuffer[2U * i]; + 8001fd8: 697b ldr r3, [r7, #20] + 8001fda: 009b lsls r3, r3, #2 + 8001fdc: 68ba ldr r2, [r7, #8] + 8001fde: 4413 add r3, r2 + 8001fe0: 881a ldrh r2, [r3, #0] + 8001fe2: 693b ldr r3, [r7, #16] + 8001fe4: 801a strh r2, [r3, #0] + } + + /* Return the CRC computed value */ + return hcrc->Instance->DR; + 8001fe6: 68fb ldr r3, [r7, #12] + 8001fe8: 681b ldr r3, [r3, #0] + 8001fea: 681b ldr r3, [r3, #0] +} + 8001fec: 4618 mov r0, r3 + 8001fee: 371c adds r7, #28 + 8001ff0: 46bd mov sp, r7 + 8001ff2: f85d 7b04 ldr.w r7, [sp], #4 + 8001ff6: 4770 bx lr + +08001ff8 : + * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16) + * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) +{ + 8001ff8: b480 push {r7} + 8001ffa: b087 sub sp, #28 + 8001ffc: af00 add r7, sp, #0 + 8001ffe: 60f8 str r0, [r7, #12] + 8002000: 60b9 str r1, [r7, #8] + 8002002: 607a str r2, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8002004: 2300 movs r3, #0 + 8002006: 75fb strb r3, [r7, #23] + uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */ + 8002008: 231f movs r3, #31 + 800200a: 613b str r3, [r7, #16] + * definition. HAL_ERROR is reported if Pol degree is + * larger than that indicated by PolyLength. + * Look for MSB position: msb will contain the degree of + * the second to the largest polynomial member. E.g., for + * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ + while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) + 800200c: bf00 nop + 800200e: 693b ldr r3, [r7, #16] + 8002010: 1e5a subs r2, r3, #1 + 8002012: 613a str r2, [r7, #16] + 8002014: 2b00 cmp r3, #0 + 8002016: d009 beq.n 800202c + 8002018: 693b ldr r3, [r7, #16] + 800201a: f003 031f and.w r3, r3, #31 + 800201e: 68ba ldr r2, [r7, #8] + 8002020: fa22 f303 lsr.w r3, r2, r3 + 8002024: f003 0301 and.w r3, r3, #1 + 8002028: 2b00 cmp r3, #0 + 800202a: d0f0 beq.n 800200e + 800202c: 687b ldr r3, [r7, #4] + 800202e: 2b18 cmp r3, #24 + 8002030: d846 bhi.n 80020c0 + 8002032: a201 add r2, pc, #4 ; (adr r2, 8002038 ) + 8002034: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8002038: 080020c7 .word 0x080020c7 + 800203c: 080020c1 .word 0x080020c1 + 8002040: 080020c1 .word 0x080020c1 + 8002044: 080020c1 .word 0x080020c1 + 8002048: 080020c1 .word 0x080020c1 + 800204c: 080020c1 .word 0x080020c1 + 8002050: 080020c1 .word 0x080020c1 + 8002054: 080020c1 .word 0x080020c1 + 8002058: 080020b5 .word 0x080020b5 + 800205c: 080020c1 .word 0x080020c1 + 8002060: 080020c1 .word 0x080020c1 + 8002064: 080020c1 .word 0x080020c1 + 8002068: 080020c1 .word 0x080020c1 + 800206c: 080020c1 .word 0x080020c1 + 8002070: 080020c1 .word 0x080020c1 + 8002074: 080020c1 .word 0x080020c1 + 8002078: 080020a9 .word 0x080020a9 + 800207c: 080020c1 .word 0x080020c1 + 8002080: 080020c1 .word 0x080020c1 + 8002084: 080020c1 .word 0x080020c1 + 8002088: 080020c1 .word 0x080020c1 + 800208c: 080020c1 .word 0x080020c1 + 8002090: 080020c1 .word 0x080020c1 + 8002094: 080020c1 .word 0x080020c1 + 8002098: 0800209d .word 0x0800209d + } + + switch (PolyLength) + { + case CRC_POLYLENGTH_7B: + if (msb >= HAL_CRC_LENGTH_7B) + 800209c: 693b ldr r3, [r7, #16] + 800209e: 2b06 cmp r3, #6 + 80020a0: d913 bls.n 80020ca + { + status = HAL_ERROR; + 80020a2: 2301 movs r3, #1 + 80020a4: 75fb strb r3, [r7, #23] + } + break; + 80020a6: e010 b.n 80020ca + case CRC_POLYLENGTH_8B: + if (msb >= HAL_CRC_LENGTH_8B) + 80020a8: 693b ldr r3, [r7, #16] + 80020aa: 2b07 cmp r3, #7 + 80020ac: d90f bls.n 80020ce + { + status = HAL_ERROR; + 80020ae: 2301 movs r3, #1 + 80020b0: 75fb strb r3, [r7, #23] + } + break; + 80020b2: e00c b.n 80020ce + case CRC_POLYLENGTH_16B: + if (msb >= HAL_CRC_LENGTH_16B) + 80020b4: 693b ldr r3, [r7, #16] + 80020b6: 2b0f cmp r3, #15 + 80020b8: d90b bls.n 80020d2 + { + status = HAL_ERROR; + 80020ba: 2301 movs r3, #1 + 80020bc: 75fb strb r3, [r7, #23] + } + break; + 80020be: e008 b.n 80020d2 + + case CRC_POLYLENGTH_32B: + /* no polynomial definition vs. polynomial length issue possible */ + break; + default: + status = HAL_ERROR; + 80020c0: 2301 movs r3, #1 + 80020c2: 75fb strb r3, [r7, #23] + break; + 80020c4: e006 b.n 80020d4 + break; + 80020c6: bf00 nop + 80020c8: e004 b.n 80020d4 + break; + 80020ca: bf00 nop + 80020cc: e002 b.n 80020d4 + break; + 80020ce: bf00 nop + 80020d0: e000 b.n 80020d4 + break; + 80020d2: bf00 nop + } + if (status == HAL_OK) + 80020d4: 7dfb ldrb r3, [r7, #23] + 80020d6: 2b00 cmp r3, #0 + 80020d8: d10d bne.n 80020f6 + { + /* set generating polynomial */ + WRITE_REG(hcrc->Instance->POL, Pol); + 80020da: 68fb ldr r3, [r7, #12] + 80020dc: 681b ldr r3, [r3, #0] + 80020de: 68ba ldr r2, [r7, #8] + 80020e0: 615a str r2, [r3, #20] + + /* set generating polynomial size */ + MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); + 80020e2: 68fb ldr r3, [r7, #12] + 80020e4: 681b ldr r3, [r3, #0] + 80020e6: 689b ldr r3, [r3, #8] + 80020e8: f023 0118 bic.w r1, r3, #24 + 80020ec: 68fb ldr r3, [r7, #12] + 80020ee: 681b ldr r3, [r3, #0] + 80020f0: 687a ldr r2, [r7, #4] + 80020f2: 430a orrs r2, r1 + 80020f4: 609a str r2, [r3, #8] + } + /* Return function status */ + return status; + 80020f6: 7dfb ldrb r3, [r7, #23] +} + 80020f8: 4618 mov r0, r3 + 80020fa: 371c adds r7, #28 + 80020fc: 46bd mov sp, r7 + 80020fe: f85d 7b04 ldr.w r7, [sp], #4 + 8002102: 4770 bx lr + +08002104 : * @param Data specifies the data to be programmed * * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) { - 8001458: b580 push {r7, lr} - 800145a: b086 sub sp, #24 - 800145c: af00 add r7, sp, #0 - 800145e: 60f8 str r0, [r7, #12] - 8001460: 60b9 str r1, [r7, #8] - 8001462: e9c7 2300 strd r2, r3, [r7] + 8002104: b580 push {r7, lr} + 8002106: b086 sub sp, #24 + 8002108: af00 add r7, sp, #0 + 800210a: 60f8 str r0, [r7, #12] + 800210c: 60b9 str r1, [r7, #8] + 800210e: e9c7 2300 strd r2, r3, [r7] HAL_StatusTypeDef status = HAL_ERROR; - 8001466: 2301 movs r3, #1 - 8001468: 75fb strb r3, [r7, #23] + 8002112: 2301 movs r3, #1 + 8002114: 75fb strb r3, [r7, #23] /* Process Locked */ __HAL_LOCK(&pFlash); - 800146a: 4b27 ldr r3, [pc, #156] ; (8001508 ) - 800146c: 7d1b ldrb r3, [r3, #20] - 800146e: 2b01 cmp r3, #1 - 8001470: d101 bne.n 8001476 - 8001472: 2302 movs r3, #2 - 8001474: e043 b.n 80014fe - 8001476: 4b24 ldr r3, [pc, #144] ; (8001508 ) - 8001478: 2201 movs r2, #1 - 800147a: 751a strb r2, [r3, #20] + 8002116: 4b27 ldr r3, [pc, #156] ; (80021b4 ) + 8002118: 7d1b ldrb r3, [r3, #20] + 800211a: 2b01 cmp r3, #1 + 800211c: d101 bne.n 8002122 + 800211e: 2302 movs r3, #2 + 8002120: e043 b.n 80021aa + 8002122: 4b24 ldr r3, [pc, #144] ; (80021b4 ) + 8002124: 2201 movs r2, #1 + 8002126: 751a strb r2, [r3, #20] /* Check the parameters */ assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - 800147c: f24c 3050 movw r0, #50000 ; 0xc350 - 8001480: f000 f878 bl 8001574 - 8001484: 4603 mov r3, r0 - 8001486: 75fb strb r3, [r7, #23] + 8002128: f24c 3050 movw r0, #50000 ; 0xc350 + 800212c: f000 f878 bl 8002220 + 8002130: 4603 mov r3, r0 + 8002132: 75fb strb r3, [r7, #23] if(status == HAL_OK) - 8001488: 7dfb ldrb r3, [r7, #23] - 800148a: 2b00 cmp r3, #0 - 800148c: d133 bne.n 80014f6 - 800148e: 68fb ldr r3, [r7, #12] - 8001490: 2b03 cmp r3, #3 - 8001492: d823 bhi.n 80014dc - 8001494: a201 add r2, pc, #4 ; (adr r2, 800149c ) - 8001496: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 800149a: bf00 nop - 800149c: 080014ad .word 0x080014ad - 80014a0: 080014b9 .word 0x080014b9 - 80014a4: 080014c5 .word 0x080014c5 - 80014a8: 080014d1 .word 0x080014d1 + 8002134: 7dfb ldrb r3, [r7, #23] + 8002136: 2b00 cmp r3, #0 + 8002138: d133 bne.n 80021a2 + 800213a: 68fb ldr r3, [r7, #12] + 800213c: 2b03 cmp r3, #3 + 800213e: d823 bhi.n 8002188 + 8002140: a201 add r2, pc, #4 ; (adr r2, 8002148 ) + 8002142: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8002146: bf00 nop + 8002148: 08002159 .word 0x08002159 + 800214c: 08002165 .word 0x08002165 + 8002150: 08002171 .word 0x08002171 + 8002154: 0800217d .word 0x0800217d switch(TypeProgram) { case FLASH_TYPEPROGRAM_BYTE : { /*Program byte (8-bit) at a specified address.*/ FLASH_Program_Byte(Address, (uint8_t) Data); - 80014ac: 783b ldrb r3, [r7, #0] - 80014ae: 4619 mov r1, r3 - 80014b0: 68b8 ldr r0, [r7, #8] - 80014b2: f000 f921 bl 80016f8 + 8002158: 783b ldrb r3, [r7, #0] + 800215a: 4619 mov r1, r3 + 800215c: 68b8 ldr r0, [r7, #8] + 800215e: f000 f921 bl 80023a4 break; - 80014b6: e012 b.n 80014de + 8002162: e012 b.n 800218a } case FLASH_TYPEPROGRAM_HALFWORD : { /*Program halfword (16-bit) at a specified address.*/ FLASH_Program_HalfWord(Address, (uint16_t) Data); - 80014b8: 883b ldrh r3, [r7, #0] - 80014ba: 4619 mov r1, r3 - 80014bc: 68b8 ldr r0, [r7, #8] - 80014be: f000 f8f5 bl 80016ac + 8002164: 883b ldrh r3, [r7, #0] + 8002166: 4619 mov r1, r3 + 8002168: 68b8 ldr r0, [r7, #8] + 800216a: f000 f8f5 bl 8002358 break; - 80014c2: e00c b.n 80014de + 800216e: e00c b.n 800218a } case FLASH_TYPEPROGRAM_WORD : { /*Program word (32-bit) at a specified address.*/ FLASH_Program_Word(Address, (uint32_t) Data); - 80014c4: 683b ldr r3, [r7, #0] - 80014c6: 4619 mov r1, r3 - 80014c8: 68b8 ldr r0, [r7, #8] - 80014ca: f000 f8c9 bl 8001660 + 8002170: 683b ldr r3, [r7, #0] + 8002172: 4619 mov r1, r3 + 8002174: 68b8 ldr r0, [r7, #8] + 8002176: f000 f8c9 bl 800230c break; - 80014ce: e006 b.n 80014de + 800217a: e006 b.n 800218a } case FLASH_TYPEPROGRAM_DOUBLEWORD : { /*Program double word (64-bit) at a specified address.*/ FLASH_Program_DoubleWord(Address, Data); - 80014d0: e9d7 2300 ldrd r2, r3, [r7] - 80014d4: 68b8 ldr r0, [r7, #8] - 80014d6: f000 f88d bl 80015f4 + 800217c: e9d7 2300 ldrd r2, r3, [r7] + 8002180: 68b8 ldr r0, [r7, #8] + 8002182: f000 f88d bl 80022a0 break; - 80014da: e000 b.n 80014de + 8002186: e000 b.n 800218a } default : break; - 80014dc: bf00 nop + 8002188: bf00 nop } /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - 80014de: f24c 3050 movw r0, #50000 ; 0xc350 - 80014e2: f000 f847 bl 8001574 - 80014e6: 4603 mov r3, r0 - 80014e8: 75fb strb r3, [r7, #23] + 800218a: f24c 3050 movw r0, #50000 ; 0xc350 + 800218e: f000 f847 bl 8002220 + 8002192: 4603 mov r3, r0 + 8002194: 75fb strb r3, [r7, #23] /* If the program operation is completed, disable the PG Bit */ FLASH->CR &= (~FLASH_CR_PG); - 80014ea: 4b08 ldr r3, [pc, #32] ; (800150c ) - 80014ec: 691b ldr r3, [r3, #16] - 80014ee: 4a07 ldr r2, [pc, #28] ; (800150c ) - 80014f0: f023 0301 bic.w r3, r3, #1 - 80014f4: 6113 str r3, [r2, #16] + 8002196: 4b08 ldr r3, [pc, #32] ; (80021b8 ) + 8002198: 691b ldr r3, [r3, #16] + 800219a: 4a07 ldr r2, [pc, #28] ; (80021b8 ) + 800219c: f023 0301 bic.w r3, r3, #1 + 80021a0: 6113 str r3, [r2, #16] } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); - 80014f6: 4b04 ldr r3, [pc, #16] ; (8001508 ) - 80014f8: 2200 movs r2, #0 - 80014fa: 751a strb r2, [r3, #20] + 80021a2: 4b04 ldr r3, [pc, #16] ; (80021b4 ) + 80021a4: 2200 movs r2, #0 + 80021a6: 751a strb r2, [r3, #20] return status; - 80014fc: 7dfb ldrb r3, [r7, #23] + 80021a8: 7dfb ldrb r3, [r7, #23] } - 80014fe: 4618 mov r0, r3 - 8001500: 3718 adds r7, #24 - 8001502: 46bd mov sp, r7 - 8001504: bd80 pop {r7, pc} - 8001506: bf00 nop - 8001508: 200005bc .word 0x200005bc - 800150c: 40023c00 .word 0x40023c00 - -08001510 : + 80021aa: 4618 mov r0, r3 + 80021ac: 3718 adds r7, #24 + 80021ae: 46bd mov sp, r7 + 80021b0: bd80 pop {r7, pc} + 80021b2: bf00 nop + 80021b4: 200005e8 .word 0x200005e8 + 80021b8: 40023c00 .word 0x40023c00 + +080021bc : /** * @brief Unlock the FLASH control register access * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { - 8001510: b480 push {r7} - 8001512: b083 sub sp, #12 - 8001514: af00 add r7, sp, #0 + 80021bc: b480 push {r7} + 80021be: b083 sub sp, #12 + 80021c0: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; - 8001516: 2300 movs r3, #0 - 8001518: 71fb strb r3, [r7, #7] + 80021c2: 2300 movs r3, #0 + 80021c4: 71fb strb r3, [r7, #7] if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) - 800151a: 4b0b ldr r3, [pc, #44] ; (8001548 ) - 800151c: 691b ldr r3, [r3, #16] - 800151e: 2b00 cmp r3, #0 - 8001520: da0b bge.n 800153a + 80021c6: 4b0b ldr r3, [pc, #44] ; (80021f4 ) + 80021c8: 691b ldr r3, [r3, #16] + 80021ca: 2b00 cmp r3, #0 + 80021cc: da0b bge.n 80021e6 { /* Authorize the FLASH Registers access */ WRITE_REG(FLASH->KEYR, FLASH_KEY1); - 8001522: 4b09 ldr r3, [pc, #36] ; (8001548 ) - 8001524: 4a09 ldr r2, [pc, #36] ; (800154c ) - 8001526: 605a str r2, [r3, #4] + 80021ce: 4b09 ldr r3, [pc, #36] ; (80021f4 ) + 80021d0: 4a09 ldr r2, [pc, #36] ; (80021f8 ) + 80021d2: 605a str r2, [r3, #4] WRITE_REG(FLASH->KEYR, FLASH_KEY2); - 8001528: 4b07 ldr r3, [pc, #28] ; (8001548 ) - 800152a: 4a09 ldr r2, [pc, #36] ; (8001550 ) - 800152c: 605a str r2, [r3, #4] + 80021d4: 4b07 ldr r3, [pc, #28] ; (80021f4 ) + 80021d6: 4a09 ldr r2, [pc, #36] ; (80021fc ) + 80021d8: 605a str r2, [r3, #4] /* Verify Flash is unlocked */ if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) - 800152e: 4b06 ldr r3, [pc, #24] ; (8001548 ) - 8001530: 691b ldr r3, [r3, #16] - 8001532: 2b00 cmp r3, #0 - 8001534: da01 bge.n 800153a + 80021da: 4b06 ldr r3, [pc, #24] ; (80021f4 ) + 80021dc: 691b ldr r3, [r3, #16] + 80021de: 2b00 cmp r3, #0 + 80021e0: da01 bge.n 80021e6 { status = HAL_ERROR; - 8001536: 2301 movs r3, #1 - 8001538: 71fb strb r3, [r7, #7] + 80021e2: 2301 movs r3, #1 + 80021e4: 71fb strb r3, [r7, #7] } } return status; - 800153a: 79fb ldrb r3, [r7, #7] + 80021e6: 79fb ldrb r3, [r7, #7] } - 800153c: 4618 mov r0, r3 - 800153e: 370c adds r7, #12 - 8001540: 46bd mov sp, r7 - 8001542: f85d 7b04 ldr.w r7, [sp], #4 - 8001546: 4770 bx lr - 8001548: 40023c00 .word 0x40023c00 - 800154c: 45670123 .word 0x45670123 - 8001550: cdef89ab .word 0xcdef89ab - -08001554 : + 80021e8: 4618 mov r0, r3 + 80021ea: 370c adds r7, #12 + 80021ec: 46bd mov sp, r7 + 80021ee: f85d 7b04 ldr.w r7, [sp], #4 + 80021f2: 4770 bx lr + 80021f4: 40023c00 .word 0x40023c00 + 80021f8: 45670123 .word 0x45670123 + 80021fc: cdef89ab .word 0xcdef89ab + +08002200 : /** * @brief Locks the FLASH control register access * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASH_Lock(void) { - 8001554: b480 push {r7} - 8001556: af00 add r7, sp, #0 + 8002200: b480 push {r7} + 8002202: af00 add r7, sp, #0 /* Set the LOCK Bit to lock the FLASH Registers access */ FLASH->CR |= FLASH_CR_LOCK; - 8001558: 4b05 ldr r3, [pc, #20] ; (8001570 ) - 800155a: 691b ldr r3, [r3, #16] - 800155c: 4a04 ldr r2, [pc, #16] ; (8001570 ) - 800155e: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 - 8001562: 6113 str r3, [r2, #16] + 8002204: 4b05 ldr r3, [pc, #20] ; (800221c ) + 8002206: 691b ldr r3, [r3, #16] + 8002208: 4a04 ldr r2, [pc, #16] ; (800221c ) + 800220a: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 800220e: 6113 str r3, [r2, #16] return HAL_OK; - 8001564: 2300 movs r3, #0 + 8002210: 2300 movs r3, #0 } - 8001566: 4618 mov r0, r3 - 8001568: 46bd mov sp, r7 - 800156a: f85d 7b04 ldr.w r7, [sp], #4 - 800156e: 4770 bx lr - 8001570: 40023c00 .word 0x40023c00 + 8002212: 4618 mov r0, r3 + 8002214: 46bd mov sp, r7 + 8002216: f85d 7b04 ldr.w r7, [sp], #4 + 800221a: 4770 bx lr + 800221c: 40023c00 .word 0x40023c00 -08001574 : +08002220 : * @brief Wait for a FLASH operation to complete. * @param Timeout maximum flash operationtimeout * @retval HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { - 8001574: b580 push {r7, lr} - 8001576: b084 sub sp, #16 - 8001578: af00 add r7, sp, #0 - 800157a: 6078 str r0, [r7, #4] + 8002220: b580 push {r7, lr} + 8002222: b084 sub sp, #16 + 8002224: af00 add r7, sp, #0 + 8002226: 6078 str r0, [r7, #4] uint32_t tickstart = 0; - 800157c: 2300 movs r3, #0 - 800157e: 60fb str r3, [r7, #12] + 8002228: 2300 movs r3, #0 + 800222a: 60fb str r3, [r7, #12] /* Clear Error Code */ pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - 8001580: 4b1a ldr r3, [pc, #104] ; (80015ec ) - 8001582: 2200 movs r2, #0 - 8001584: 619a str r2, [r3, #24] + 800222c: 4b1a ldr r3, [pc, #104] ; (8002298 ) + 800222e: 2200 movs r2, #0 + 8002230: 619a str r2, [r3, #24] /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ /* Get tick */ tickstart = HAL_GetTick(); - 8001586: f7ff fe5b bl 8001240 - 800158a: 60f8 str r0, [r7, #12] + 8002232: f7ff fc5d bl 8001af0 + 8002236: 60f8 str r0, [r7, #12] while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) - 800158c: e010 b.n 80015b0 + 8002238: e010 b.n 800225c { if(Timeout != HAL_MAX_DELAY) - 800158e: 687b ldr r3, [r7, #4] - 8001590: f1b3 3fff cmp.w r3, #4294967295 - 8001594: d00c beq.n 80015b0 + 800223a: 687b ldr r3, [r7, #4] + 800223c: f1b3 3fff cmp.w r3, #4294967295 + 8002240: d00c beq.n 800225c { if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - 8001596: 687b ldr r3, [r7, #4] - 8001598: 2b00 cmp r3, #0 - 800159a: d007 beq.n 80015ac - 800159c: f7ff fe50 bl 8001240 - 80015a0: 4602 mov r2, r0 - 80015a2: 68fb ldr r3, [r7, #12] - 80015a4: 1ad3 subs r3, r2, r3 - 80015a6: 687a ldr r2, [r7, #4] - 80015a8: 429a cmp r2, r3 - 80015aa: d201 bcs.n 80015b0 + 8002242: 687b ldr r3, [r7, #4] + 8002244: 2b00 cmp r3, #0 + 8002246: d007 beq.n 8002258 + 8002248: f7ff fc52 bl 8001af0 + 800224c: 4602 mov r2, r0 + 800224e: 68fb ldr r3, [r7, #12] + 8002250: 1ad3 subs r3, r2, r3 + 8002252: 687a ldr r2, [r7, #4] + 8002254: 429a cmp r2, r3 + 8002256: d201 bcs.n 800225c { return HAL_TIMEOUT; - 80015ac: 2303 movs r3, #3 - 80015ae: e019 b.n 80015e4 + 8002258: 2303 movs r3, #3 + 800225a: e019 b.n 8002290 while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) - 80015b0: 4b0f ldr r3, [pc, #60] ; (80015f0 ) - 80015b2: 68db ldr r3, [r3, #12] - 80015b4: f403 3380 and.w r3, r3, #65536 ; 0x10000 - 80015b8: 2b00 cmp r3, #0 - 80015ba: d1e8 bne.n 800158e + 800225c: 4b0f ldr r3, [pc, #60] ; (800229c ) + 800225e: 68db ldr r3, [r3, #12] + 8002260: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8002264: 2b00 cmp r3, #0 + 8002266: d1e8 bne.n 800223a } } } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET) - 80015bc: 4b0c ldr r3, [pc, #48] ; (80015f0 ) - 80015be: 68db ldr r3, [r3, #12] - 80015c0: f003 03f2 and.w r3, r3, #242 ; 0xf2 - 80015c4: 2b00 cmp r3, #0 - 80015c6: d003 beq.n 80015d0 + 8002268: 4b0c ldr r3, [pc, #48] ; (800229c ) + 800226a: 68db ldr r3, [r3, #12] + 800226c: f003 03f2 and.w r3, r3, #242 ; 0xf2 + 8002270: 2b00 cmp r3, #0 + 8002272: d003 beq.n 800227c { /*Save the error code*/ FLASH_SetErrorCode(); - 80015c8: f000 f8ba bl 8001740 + 8002274: f000 f8ba bl 80023ec return HAL_ERROR; - 80015cc: 2301 movs r3, #1 - 80015ce: e009 b.n 80015e4 + 8002278: 2301 movs r3, #1 + 800227a: e009 b.n 8002290 } /* Check FLASH End of Operation flag */ if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) - 80015d0: 4b07 ldr r3, [pc, #28] ; (80015f0 ) - 80015d2: 68db ldr r3, [r3, #12] - 80015d4: f003 0301 and.w r3, r3, #1 - 80015d8: 2b00 cmp r3, #0 - 80015da: d002 beq.n 80015e2 + 800227c: 4b07 ldr r3, [pc, #28] ; (800229c ) + 800227e: 68db ldr r3, [r3, #12] + 8002280: f003 0301 and.w r3, r3, #1 + 8002284: 2b00 cmp r3, #0 + 8002286: d002 beq.n 800228e { /* Clear FLASH End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - 80015dc: 4b04 ldr r3, [pc, #16] ; (80015f0 ) - 80015de: 2201 movs r2, #1 - 80015e0: 60da str r2, [r3, #12] + 8002288: 4b04 ldr r3, [pc, #16] ; (800229c ) + 800228a: 2201 movs r2, #1 + 800228c: 60da str r2, [r3, #12] } /* If there is an error flag set */ return HAL_OK; - 80015e2: 2300 movs r3, #0 + 800228e: 2300 movs r3, #0 } - 80015e4: 4618 mov r0, r3 - 80015e6: 3710 adds r7, #16 - 80015e8: 46bd mov sp, r7 - 80015ea: bd80 pop {r7, pc} - 80015ec: 200005bc .word 0x200005bc - 80015f0: 40023c00 .word 0x40023c00 - -080015f4 : + 8002290: 4618 mov r0, r3 + 8002292: 3710 adds r7, #16 + 8002294: 46bd mov sp, r7 + 8002296: bd80 pop {r7, pc} + 8002298: 200005e8 .word 0x200005e8 + 800229c: 40023c00 .word 0x40023c00 + +080022a0 : * @param Address specifies the address to be programmed. * @param Data specifies the data to be programmed. * @retval None */ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) { - 80015f4: b480 push {r7} - 80015f6: b085 sub sp, #20 - 80015f8: af00 add r7, sp, #0 - 80015fa: 60f8 str r0, [r7, #12] - 80015fc: e9c7 2300 strd r2, r3, [r7] + 80022a0: b480 push {r7} + 80022a2: b085 sub sp, #20 + 80022a4: af00 add r7, sp, #0 + 80022a6: 60f8 str r0, [r7, #12] + 80022a8: e9c7 2300 strd r2, r3, [r7] /* Check the parameters */ assert_param(IS_FLASH_ADDRESS(Address)); /* If the previous operation is completed, proceed to program the new data */ FLASH->CR &= CR_PSIZE_MASK; - 8001600: 4b16 ldr r3, [pc, #88] ; (800165c ) - 8001602: 691b ldr r3, [r3, #16] - 8001604: 4a15 ldr r2, [pc, #84] ; (800165c ) - 8001606: f423 7340 bic.w r3, r3, #768 ; 0x300 - 800160a: 6113 str r3, [r2, #16] + 80022ac: 4b16 ldr r3, [pc, #88] ; (8002308 ) + 80022ae: 691b ldr r3, [r3, #16] + 80022b0: 4a15 ldr r2, [pc, #84] ; (8002308 ) + 80022b2: f423 7340 bic.w r3, r3, #768 ; 0x300 + 80022b6: 6113 str r3, [r2, #16] FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; - 800160c: 4b13 ldr r3, [pc, #76] ; (800165c ) - 800160e: 691b ldr r3, [r3, #16] - 8001610: 4a12 ldr r2, [pc, #72] ; (800165c ) - 8001612: f443 7340 orr.w r3, r3, #768 ; 0x300 - 8001616: 6113 str r3, [r2, #16] + 80022b8: 4b13 ldr r3, [pc, #76] ; (8002308 ) + 80022ba: 691b ldr r3, [r3, #16] + 80022bc: 4a12 ldr r2, [pc, #72] ; (8002308 ) + 80022be: f443 7340 orr.w r3, r3, #768 ; 0x300 + 80022c2: 6113 str r3, [r2, #16] FLASH->CR |= FLASH_CR_PG; - 8001618: 4b10 ldr r3, [pc, #64] ; (800165c ) - 800161a: 691b ldr r3, [r3, #16] - 800161c: 4a0f ldr r2, [pc, #60] ; (800165c ) - 800161e: f043 0301 orr.w r3, r3, #1 - 8001622: 6113 str r3, [r2, #16] + 80022c4: 4b10 ldr r3, [pc, #64] ; (8002308 ) + 80022c6: 691b ldr r3, [r3, #16] + 80022c8: 4a0f ldr r2, [pc, #60] ; (8002308 ) + 80022ca: f043 0301 orr.w r3, r3, #1 + 80022ce: 6113 str r3, [r2, #16] /* Program first word */ *(__IO uint32_t*)Address = (uint32_t)Data; - 8001624: 68fb ldr r3, [r7, #12] - 8001626: 683a ldr r2, [r7, #0] - 8001628: 601a str r2, [r3, #0] + 80022d0: 68fb ldr r3, [r7, #12] + 80022d2: 683a ldr r2, [r7, #0] + 80022d4: 601a str r2, [r3, #0] __ASM volatile ("isb 0xF":::"memory"); - 800162a: f3bf 8f6f isb sy + 80022d6: f3bf 8f6f isb sy } - 800162e: bf00 nop + 80022da: bf00 nop /* Barrier to ensure programming is performed in 2 steps, in right order (independently of compiler optimization behavior) */ __ISB(); /* Program second word */ *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32); - 8001630: e9d7 0100 ldrd r0, r1, [r7] - 8001634: f04f 0200 mov.w r2, #0 - 8001638: f04f 0300 mov.w r3, #0 - 800163c: 000a movs r2, r1 - 800163e: 2300 movs r3, #0 - 8001640: 68f9 ldr r1, [r7, #12] - 8001642: 3104 adds r1, #4 - 8001644: 4613 mov r3, r2 - 8001646: 600b str r3, [r1, #0] + 80022dc: e9d7 0100 ldrd r0, r1, [r7] + 80022e0: f04f 0200 mov.w r2, #0 + 80022e4: f04f 0300 mov.w r3, #0 + 80022e8: 000a movs r2, r1 + 80022ea: 2300 movs r3, #0 + 80022ec: 68f9 ldr r1, [r7, #12] + 80022ee: 3104 adds r1, #4 + 80022f0: 4613 mov r3, r2 + 80022f2: 600b str r3, [r1, #0] __ASM volatile ("dsb 0xF":::"memory"); - 8001648: f3bf 8f4f dsb sy + 80022f4: f3bf 8f4f dsb sy } - 800164c: bf00 nop + 80022f8: bf00 nop /* Data synchronous Barrier (DSB) Just after the write operation This will force the CPU to respect the sequence of instruction (no optimization).*/ __DSB(); } - 800164e: bf00 nop - 8001650: 3714 adds r7, #20 - 8001652: 46bd mov sp, r7 - 8001654: f85d 7b04 ldr.w r7, [sp], #4 - 8001658: 4770 bx lr - 800165a: bf00 nop - 800165c: 40023c00 .word 0x40023c00 - -08001660 : + 80022fa: bf00 nop + 80022fc: 3714 adds r7, #20 + 80022fe: 46bd mov sp, r7 + 8002300: f85d 7b04 ldr.w r7, [sp], #4 + 8002304: 4770 bx lr + 8002306: bf00 nop + 8002308: 40023c00 .word 0x40023c00 + +0800230c : * @param Address specifies the address to be programmed. * @param Data specifies the data to be programmed. * @retval None */ static void FLASH_Program_Word(uint32_t Address, uint32_t Data) { - 8001660: b480 push {r7} - 8001662: b083 sub sp, #12 - 8001664: af00 add r7, sp, #0 - 8001666: 6078 str r0, [r7, #4] - 8001668: 6039 str r1, [r7, #0] + 800230c: b480 push {r7} + 800230e: b083 sub sp, #12 + 8002310: af00 add r7, sp, #0 + 8002312: 6078 str r0, [r7, #4] + 8002314: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_FLASH_ADDRESS(Address)); /* If the previous operation is completed, proceed to program the new data */ FLASH->CR &= CR_PSIZE_MASK; - 800166a: 4b0f ldr r3, [pc, #60] ; (80016a8 ) - 800166c: 691b ldr r3, [r3, #16] - 800166e: 4a0e ldr r2, [pc, #56] ; (80016a8 ) - 8001670: f423 7340 bic.w r3, r3, #768 ; 0x300 - 8001674: 6113 str r3, [r2, #16] + 8002316: 4b0f ldr r3, [pc, #60] ; (8002354 ) + 8002318: 691b ldr r3, [r3, #16] + 800231a: 4a0e ldr r2, [pc, #56] ; (8002354 ) + 800231c: f423 7340 bic.w r3, r3, #768 ; 0x300 + 8002320: 6113 str r3, [r2, #16] FLASH->CR |= FLASH_PSIZE_WORD; - 8001676: 4b0c ldr r3, [pc, #48] ; (80016a8 ) - 8001678: 691b ldr r3, [r3, #16] - 800167a: 4a0b ldr r2, [pc, #44] ; (80016a8 ) - 800167c: f443 7300 orr.w r3, r3, #512 ; 0x200 - 8001680: 6113 str r3, [r2, #16] + 8002322: 4b0c ldr r3, [pc, #48] ; (8002354 ) + 8002324: 691b ldr r3, [r3, #16] + 8002326: 4a0b ldr r2, [pc, #44] ; (8002354 ) + 8002328: f443 7300 orr.w r3, r3, #512 ; 0x200 + 800232c: 6113 str r3, [r2, #16] FLASH->CR |= FLASH_CR_PG; - 8001682: 4b09 ldr r3, [pc, #36] ; (80016a8 ) - 8001684: 691b ldr r3, [r3, #16] - 8001686: 4a08 ldr r2, [pc, #32] ; (80016a8 ) - 8001688: f043 0301 orr.w r3, r3, #1 - 800168c: 6113 str r3, [r2, #16] + 800232e: 4b09 ldr r3, [pc, #36] ; (8002354 ) + 8002330: 691b ldr r3, [r3, #16] + 8002332: 4a08 ldr r2, [pc, #32] ; (8002354 ) + 8002334: f043 0301 orr.w r3, r3, #1 + 8002338: 6113 str r3, [r2, #16] *(__IO uint32_t*)Address = Data; - 800168e: 687b ldr r3, [r7, #4] - 8001690: 683a ldr r2, [r7, #0] - 8001692: 601a str r2, [r3, #0] + 800233a: 687b ldr r3, [r7, #4] + 800233c: 683a ldr r2, [r7, #0] + 800233e: 601a str r2, [r3, #0] __ASM volatile ("dsb 0xF":::"memory"); - 8001694: f3bf 8f4f dsb sy + 8002340: f3bf 8f4f dsb sy } - 8001698: bf00 nop + 8002344: bf00 nop /* Data synchronous Barrier (DSB) Just after the write operation This will force the CPU to respect the sequence of instruction (no optimization).*/ __DSB(); } - 800169a: bf00 nop - 800169c: 370c adds r7, #12 - 800169e: 46bd mov sp, r7 - 80016a0: f85d 7b04 ldr.w r7, [sp], #4 - 80016a4: 4770 bx lr - 80016a6: bf00 nop - 80016a8: 40023c00 .word 0x40023c00 - -080016ac : + 8002346: bf00 nop + 8002348: 370c adds r7, #12 + 800234a: 46bd mov sp, r7 + 800234c: f85d 7b04 ldr.w r7, [sp], #4 + 8002350: 4770 bx lr + 8002352: bf00 nop + 8002354: 40023c00 .word 0x40023c00 + +08002358 : * @param Address specifies the address to be programmed. * @param Data specifies the data to be programmed. * @retval None */ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) { - 80016ac: b480 push {r7} - 80016ae: b083 sub sp, #12 - 80016b0: af00 add r7, sp, #0 - 80016b2: 6078 str r0, [r7, #4] - 80016b4: 460b mov r3, r1 - 80016b6: 807b strh r3, [r7, #2] + 8002358: b480 push {r7} + 800235a: b083 sub sp, #12 + 800235c: af00 add r7, sp, #0 + 800235e: 6078 str r0, [r7, #4] + 8002360: 460b mov r3, r1 + 8002362: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_FLASH_ADDRESS(Address)); /* If the previous operation is completed, proceed to program the new data */ FLASH->CR &= CR_PSIZE_MASK; - 80016b8: 4b0e ldr r3, [pc, #56] ; (80016f4 ) - 80016ba: 691b ldr r3, [r3, #16] - 80016bc: 4a0d ldr r2, [pc, #52] ; (80016f4 ) - 80016be: f423 7340 bic.w r3, r3, #768 ; 0x300 - 80016c2: 6113 str r3, [r2, #16] + 8002364: 4b0e ldr r3, [pc, #56] ; (80023a0 ) + 8002366: 691b ldr r3, [r3, #16] + 8002368: 4a0d ldr r2, [pc, #52] ; (80023a0 ) + 800236a: f423 7340 bic.w r3, r3, #768 ; 0x300 + 800236e: 6113 str r3, [r2, #16] FLASH->CR |= FLASH_PSIZE_HALF_WORD; - 80016c4: 4b0b ldr r3, [pc, #44] ; (80016f4 ) - 80016c6: 691b ldr r3, [r3, #16] - 80016c8: 4a0a ldr r2, [pc, #40] ; (80016f4 ) - 80016ca: f443 7380 orr.w r3, r3, #256 ; 0x100 - 80016ce: 6113 str r3, [r2, #16] + 8002370: 4b0b ldr r3, [pc, #44] ; (80023a0 ) + 8002372: 691b ldr r3, [r3, #16] + 8002374: 4a0a ldr r2, [pc, #40] ; (80023a0 ) + 8002376: f443 7380 orr.w r3, r3, #256 ; 0x100 + 800237a: 6113 str r3, [r2, #16] FLASH->CR |= FLASH_CR_PG; - 80016d0: 4b08 ldr r3, [pc, #32] ; (80016f4 ) - 80016d2: 691b ldr r3, [r3, #16] - 80016d4: 4a07 ldr r2, [pc, #28] ; (80016f4 ) - 80016d6: f043 0301 orr.w r3, r3, #1 - 80016da: 6113 str r3, [r2, #16] + 800237c: 4b08 ldr r3, [pc, #32] ; (80023a0 ) + 800237e: 691b ldr r3, [r3, #16] + 8002380: 4a07 ldr r2, [pc, #28] ; (80023a0 ) + 8002382: f043 0301 orr.w r3, r3, #1 + 8002386: 6113 str r3, [r2, #16] *(__IO uint16_t*)Address = Data; - 80016dc: 687b ldr r3, [r7, #4] - 80016de: 887a ldrh r2, [r7, #2] - 80016e0: 801a strh r2, [r3, #0] + 8002388: 687b ldr r3, [r7, #4] + 800238a: 887a ldrh r2, [r7, #2] + 800238c: 801a strh r2, [r3, #0] __ASM volatile ("dsb 0xF":::"memory"); - 80016e2: f3bf 8f4f dsb sy + 800238e: f3bf 8f4f dsb sy } - 80016e6: bf00 nop + 8002392: bf00 nop /* Data synchronous Barrier (DSB) Just after the write operation This will force the CPU to respect the sequence of instruction (no optimization).*/ __DSB(); } - 80016e8: bf00 nop - 80016ea: 370c adds r7, #12 - 80016ec: 46bd mov sp, r7 - 80016ee: f85d 7b04 ldr.w r7, [sp], #4 - 80016f2: 4770 bx lr - 80016f4: 40023c00 .word 0x40023c00 - -080016f8 : + 8002394: bf00 nop + 8002396: 370c adds r7, #12 + 8002398: 46bd mov sp, r7 + 800239a: f85d 7b04 ldr.w r7, [sp], #4 + 800239e: 4770 bx lr + 80023a0: 40023c00 .word 0x40023c00 + +080023a4 : * @param Address specifies the address to be programmed. * @param Data specifies the data to be programmed. * @retval None */ static void FLASH_Program_Byte(uint32_t Address, uint8_t Data) { - 80016f8: b480 push {r7} - 80016fa: b083 sub sp, #12 - 80016fc: af00 add r7, sp, #0 - 80016fe: 6078 str r0, [r7, #4] - 8001700: 460b mov r3, r1 - 8001702: 70fb strb r3, [r7, #3] + 80023a4: b480 push {r7} + 80023a6: b083 sub sp, #12 + 80023a8: af00 add r7, sp, #0 + 80023aa: 6078 str r0, [r7, #4] + 80023ac: 460b mov r3, r1 + 80023ae: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_FLASH_ADDRESS(Address)); /* If the previous operation is completed, proceed to program the new data */ FLASH->CR &= CR_PSIZE_MASK; - 8001704: 4b0d ldr r3, [pc, #52] ; (800173c ) - 8001706: 691b ldr r3, [r3, #16] - 8001708: 4a0c ldr r2, [pc, #48] ; (800173c ) - 800170a: f423 7340 bic.w r3, r3, #768 ; 0x300 - 800170e: 6113 str r3, [r2, #16] + 80023b0: 4b0d ldr r3, [pc, #52] ; (80023e8 ) + 80023b2: 691b ldr r3, [r3, #16] + 80023b4: 4a0c ldr r2, [pc, #48] ; (80023e8 ) + 80023b6: f423 7340 bic.w r3, r3, #768 ; 0x300 + 80023ba: 6113 str r3, [r2, #16] FLASH->CR |= FLASH_PSIZE_BYTE; - 8001710: 4b0a ldr r3, [pc, #40] ; (800173c ) - 8001712: 4a0a ldr r2, [pc, #40] ; (800173c ) - 8001714: 691b ldr r3, [r3, #16] - 8001716: 6113 str r3, [r2, #16] + 80023bc: 4b0a ldr r3, [pc, #40] ; (80023e8 ) + 80023be: 4a0a ldr r2, [pc, #40] ; (80023e8 ) + 80023c0: 691b ldr r3, [r3, #16] + 80023c2: 6113 str r3, [r2, #16] FLASH->CR |= FLASH_CR_PG; - 8001718: 4b08 ldr r3, [pc, #32] ; (800173c ) - 800171a: 691b ldr r3, [r3, #16] - 800171c: 4a07 ldr r2, [pc, #28] ; (800173c ) - 800171e: f043 0301 orr.w r3, r3, #1 - 8001722: 6113 str r3, [r2, #16] + 80023c4: 4b08 ldr r3, [pc, #32] ; (80023e8 ) + 80023c6: 691b ldr r3, [r3, #16] + 80023c8: 4a07 ldr r2, [pc, #28] ; (80023e8 ) + 80023ca: f043 0301 orr.w r3, r3, #1 + 80023ce: 6113 str r3, [r2, #16] *(__IO uint8_t*)Address = Data; - 8001724: 687b ldr r3, [r7, #4] - 8001726: 78fa ldrb r2, [r7, #3] - 8001728: 701a strb r2, [r3, #0] + 80023d0: 687b ldr r3, [r7, #4] + 80023d2: 78fa ldrb r2, [r7, #3] + 80023d4: 701a strb r2, [r3, #0] __ASM volatile ("dsb 0xF":::"memory"); - 800172a: f3bf 8f4f dsb sy + 80023d6: f3bf 8f4f dsb sy } - 800172e: bf00 nop + 80023da: bf00 nop /* Data synchronous Barrier (DSB) Just after the write operation This will force the CPU to respect the sequence of instruction (no optimization).*/ __DSB(); } - 8001730: bf00 nop - 8001732: 370c adds r7, #12 - 8001734: 46bd mov sp, r7 - 8001736: f85d 7b04 ldr.w r7, [sp], #4 - 800173a: 4770 bx lr - 800173c: 40023c00 .word 0x40023c00 - -08001740 : + 80023dc: bf00 nop + 80023de: 370c adds r7, #12 + 80023e0: 46bd mov sp, r7 + 80023e2: f85d 7b04 ldr.w r7, [sp], #4 + 80023e6: 4770 bx lr + 80023e8: 40023c00 .word 0x40023c00 + +080023ec : /** * @brief Set the specific FLASH error flag. * @retval None */ static void FLASH_SetErrorCode(void) { - 8001740: b480 push {r7} - 8001742: af00 add r7, sp, #0 + 80023ec: b480 push {r7} + 80023ee: af00 add r7, sp, #0 if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET) - 8001744: 4b21 ldr r3, [pc, #132] ; (80017cc ) - 8001746: 68db ldr r3, [r3, #12] - 8001748: f003 0302 and.w r3, r3, #2 - 800174c: 2b00 cmp r3, #0 - 800174e: d005 beq.n 800175c + 80023f0: 4b21 ldr r3, [pc, #132] ; (8002478 ) + 80023f2: 68db ldr r3, [r3, #12] + 80023f4: f003 0302 and.w r3, r3, #2 + 80023f8: 2b00 cmp r3, #0 + 80023fa: d005 beq.n 8002408 { pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION; - 8001750: 4b1f ldr r3, [pc, #124] ; (80017d0 ) - 8001752: 699b ldr r3, [r3, #24] - 8001754: f043 0320 orr.w r3, r3, #32 - 8001758: 4a1d ldr r2, [pc, #116] ; (80017d0 ) - 800175a: 6193 str r3, [r2, #24] + 80023fc: 4b1f ldr r3, [pc, #124] ; (800247c ) + 80023fe: 699b ldr r3, [r3, #24] + 8002400: f043 0320 orr.w r3, r3, #32 + 8002404: 4a1d ldr r2, [pc, #116] ; (800247c ) + 8002406: 6193 str r3, [r2, #24] } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) - 800175c: 4b1b ldr r3, [pc, #108] ; (80017cc ) - 800175e: 68db ldr r3, [r3, #12] - 8001760: f003 0310 and.w r3, r3, #16 - 8001764: 2b00 cmp r3, #0 - 8001766: d005 beq.n 8001774 + 8002408: 4b1b ldr r3, [pc, #108] ; (8002478 ) + 800240a: 68db ldr r3, [r3, #12] + 800240c: f003 0310 and.w r3, r3, #16 + 8002410: 2b00 cmp r3, #0 + 8002412: d005 beq.n 8002420 { pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; - 8001768: 4b19 ldr r3, [pc, #100] ; (80017d0 ) - 800176a: 699b ldr r3, [r3, #24] - 800176c: f043 0310 orr.w r3, r3, #16 - 8001770: 4a17 ldr r2, [pc, #92] ; (80017d0 ) - 8001772: 6193 str r3, [r2, #24] + 8002414: 4b19 ldr r3, [pc, #100] ; (800247c ) + 8002416: 699b ldr r3, [r3, #24] + 8002418: f043 0310 orr.w r3, r3, #16 + 800241c: 4a17 ldr r2, [pc, #92] ; (800247c ) + 800241e: 6193 str r3, [r2, #24] } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) - 8001774: 4b15 ldr r3, [pc, #84] ; (80017cc ) - 8001776: 68db ldr r3, [r3, #12] - 8001778: f003 0320 and.w r3, r3, #32 - 800177c: 2b00 cmp r3, #0 - 800177e: d005 beq.n 800178c + 8002420: 4b15 ldr r3, [pc, #84] ; (8002478 ) + 8002422: 68db ldr r3, [r3, #12] + 8002424: f003 0320 and.w r3, r3, #32 + 8002428: 2b00 cmp r3, #0 + 800242a: d005 beq.n 8002438 { pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; - 8001780: 4b13 ldr r3, [pc, #76] ; (80017d0 ) - 8001782: 699b ldr r3, [r3, #24] - 8001784: f043 0308 orr.w r3, r3, #8 - 8001788: 4a11 ldr r2, [pc, #68] ; (80017d0 ) - 800178a: 6193 str r3, [r2, #24] + 800242c: 4b13 ldr r3, [pc, #76] ; (800247c ) + 800242e: 699b ldr r3, [r3, #24] + 8002430: f043 0308 orr.w r3, r3, #8 + 8002434: 4a11 ldr r2, [pc, #68] ; (800247c ) + 8002436: 6193 str r3, [r2, #24] } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET) - 800178c: 4b0f ldr r3, [pc, #60] ; (80017cc ) - 800178e: 68db ldr r3, [r3, #12] - 8001790: f003 0340 and.w r3, r3, #64 ; 0x40 - 8001794: 2b00 cmp r3, #0 - 8001796: d005 beq.n 80017a4 + 8002438: 4b0f ldr r3, [pc, #60] ; (8002478 ) + 800243a: 68db ldr r3, [r3, #12] + 800243c: f003 0340 and.w r3, r3, #64 ; 0x40 + 8002440: 2b00 cmp r3, #0 + 8002442: d005 beq.n 8002450 { pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP; - 8001798: 4b0d ldr r3, [pc, #52] ; (80017d0 ) - 800179a: 699b ldr r3, [r3, #24] - 800179c: f043 0304 orr.w r3, r3, #4 - 80017a0: 4a0b ldr r2, [pc, #44] ; (80017d0 ) - 80017a2: 6193 str r3, [r2, #24] + 8002444: 4b0d ldr r3, [pc, #52] ; (800247c ) + 8002446: 699b ldr r3, [r3, #24] + 8002448: f043 0304 orr.w r3, r3, #4 + 800244c: 4a0b ldr r2, [pc, #44] ; (800247c ) + 800244e: 6193 str r3, [r2, #24] } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ERSERR) != RESET) - 80017a4: 4b09 ldr r3, [pc, #36] ; (80017cc ) - 80017a6: 68db ldr r3, [r3, #12] - 80017a8: f003 0380 and.w r3, r3, #128 ; 0x80 - 80017ac: 2b00 cmp r3, #0 - 80017ae: d005 beq.n 80017bc + 8002450: 4b09 ldr r3, [pc, #36] ; (8002478 ) + 8002452: 68db ldr r3, [r3, #12] + 8002454: f003 0380 and.w r3, r3, #128 ; 0x80 + 8002458: 2b00 cmp r3, #0 + 800245a: d005 beq.n 8002468 { pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS; - 80017b0: 4b07 ldr r3, [pc, #28] ; (80017d0 ) - 80017b2: 699b ldr r3, [r3, #24] - 80017b4: f043 0302 orr.w r3, r3, #2 - 80017b8: 4a05 ldr r2, [pc, #20] ; (80017d0 ) - 80017ba: 6193 str r3, [r2, #24] + 800245c: 4b07 ldr r3, [pc, #28] ; (800247c ) + 800245e: 699b ldr r3, [r3, #24] + 8002460: f043 0302 orr.w r3, r3, #2 + 8002464: 4a05 ldr r2, [pc, #20] ; (800247c ) + 8002466: 6193 str r3, [r2, #24] pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; } #endif /* FLASH_OPTCR2_PCROP */ /* Clear error programming flags */ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); - 80017bc: 4b03 ldr r3, [pc, #12] ; (80017cc ) - 80017be: 22f2 movs r2, #242 ; 0xf2 - 80017c0: 60da str r2, [r3, #12] + 8002468: 4b03 ldr r3, [pc, #12] ; (8002478 ) + 800246a: 22f2 movs r2, #242 ; 0xf2 + 800246c: 60da str r2, [r3, #12] } - 80017c2: bf00 nop - 80017c4: 46bd mov sp, r7 - 80017c6: f85d 7b04 ldr.w r7, [sp], #4 - 80017ca: 4770 bx lr - 80017cc: 40023c00 .word 0x40023c00 - 80017d0: 200005bc .word 0x200005bc - -080017d4 : + 800246e: bf00 nop + 8002470: 46bd mov sp, r7 + 8002472: f85d 7b04 ldr.w r7, [sp], #4 + 8002476: 4770 bx lr + 8002478: 40023c00 .word 0x40023c00 + 800247c: 200005e8 .word 0x200005e8 + +08002480 : * (0xFFFFFFFF means that all the sectors have been correctly erased) * * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError) { - 80017d4: b580 push {r7, lr} - 80017d6: b084 sub sp, #16 - 80017d8: af00 add r7, sp, #0 - 80017da: 6078 str r0, [r7, #4] - 80017dc: 6039 str r1, [r7, #0] + 8002480: b580 push {r7, lr} + 8002482: b084 sub sp, #16 + 8002484: af00 add r7, sp, #0 + 8002486: 6078 str r0, [r7, #4] + 8002488: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_ERROR; - 80017de: 2301 movs r3, #1 - 80017e0: 73fb strb r3, [r7, #15] + 800248a: 2301 movs r3, #1 + 800248c: 73fb strb r3, [r7, #15] uint32_t index = 0; - 80017e2: 2300 movs r3, #0 - 80017e4: 60bb str r3, [r7, #8] + 800248e: 2300 movs r3, #0 + 8002490: 60bb str r3, [r7, #8] /* Process Locked */ __HAL_LOCK(&pFlash); - 80017e6: 4b30 ldr r3, [pc, #192] ; (80018a8 ) - 80017e8: 7d1b ldrb r3, [r3, #20] - 80017ea: 2b01 cmp r3, #1 - 80017ec: d101 bne.n 80017f2 - 80017ee: 2302 movs r3, #2 - 80017f0: e056 b.n 80018a0 - 80017f2: 4b2d ldr r3, [pc, #180] ; (80018a8 ) - 80017f4: 2201 movs r2, #1 - 80017f6: 751a strb r2, [r3, #20] + 8002492: 4b30 ldr r3, [pc, #192] ; (8002554 ) + 8002494: 7d1b ldrb r3, [r3, #20] + 8002496: 2b01 cmp r3, #1 + 8002498: d101 bne.n 800249e + 800249a: 2302 movs r3, #2 + 800249c: e056 b.n 800254c + 800249e: 4b2d ldr r3, [pc, #180] ; (8002554 ) + 80024a0: 2201 movs r2, #1 + 80024a2: 751a strb r2, [r3, #20] /* Check the parameters */ assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - 80017f8: f24c 3050 movw r0, #50000 ; 0xc350 - 80017fc: f7ff feba bl 8001574 - 8001800: 4603 mov r3, r0 - 8001802: 73fb strb r3, [r7, #15] + 80024a4: f24c 3050 movw r0, #50000 ; 0xc350 + 80024a8: f7ff feba bl 8002220 + 80024ac: 4603 mov r3, r0 + 80024ae: 73fb strb r3, [r7, #15] if(status == HAL_OK) - 8001804: 7bfb ldrb r3, [r7, #15] - 8001806: 2b00 cmp r3, #0 - 8001808: d146 bne.n 8001898 + 80024b0: 7bfb ldrb r3, [r7, #15] + 80024b2: 2b00 cmp r3, #0 + 80024b4: d146 bne.n 8002544 { /*Initialization of SectorError variable*/ *SectorError = 0xFFFFFFFFU; - 800180a: 683b ldr r3, [r7, #0] - 800180c: f04f 32ff mov.w r2, #4294967295 - 8001810: 601a str r2, [r3, #0] + 80024b6: 683b ldr r3, [r7, #0] + 80024b8: f04f 32ff mov.w r2, #4294967295 + 80024bc: 601a str r2, [r3, #0] if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) - 8001812: 687b ldr r3, [r7, #4] - 8001814: 681b ldr r3, [r3, #0] - 8001816: 2b01 cmp r3, #1 - 8001818: d115 bne.n 8001846 + 80024be: 687b ldr r3, [r7, #4] + 80024c0: 681b ldr r3, [r3, #0] + 80024c2: 2b01 cmp r3, #1 + 80024c4: d115 bne.n 80024f2 { /*Mass erase to be done*/ #if defined (FLASH_OPTCR_nDBANK) FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); - 800181a: 687b ldr r3, [r7, #4] - 800181c: 691b ldr r3, [r3, #16] - 800181e: b2da uxtb r2, r3 - 8001820: 687b ldr r3, [r7, #4] - 8001822: 685b ldr r3, [r3, #4] - 8001824: 4619 mov r1, r3 - 8001826: 4610 mov r0, r2 - 8001828: f000 f844 bl 80018b4 + 80024c6: 687b ldr r3, [r7, #4] + 80024c8: 691b ldr r3, [r3, #16] + 80024ca: b2da uxtb r2, r3 + 80024cc: 687b ldr r3, [r7, #4] + 80024ce: 685b ldr r3, [r3, #4] + 80024d0: 4619 mov r1, r3 + 80024d2: 4610 mov r0, r2 + 80024d4: f000 f844 bl 8002560 #else FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); #endif /* FLASH_OPTCR_nDBANK */ /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - 800182c: f24c 3050 movw r0, #50000 ; 0xc350 - 8001830: f7ff fea0 bl 8001574 - 8001834: 4603 mov r3, r0 - 8001836: 73fb strb r3, [r7, #15] + 80024d8: f24c 3050 movw r0, #50000 ; 0xc350 + 80024dc: f7ff fea0 bl 8002220 + 80024e0: 4603 mov r3, r0 + 80024e2: 73fb strb r3, [r7, #15] /* if the erase operation is completed, disable the MER Bit */ FLASH->CR &= (~FLASH_MER_BIT); - 8001838: 4b1c ldr r3, [pc, #112] ; (80018ac ) - 800183a: 691a ldr r2, [r3, #16] - 800183c: 491b ldr r1, [pc, #108] ; (80018ac ) - 800183e: 4b1c ldr r3, [pc, #112] ; (80018b0 ) - 8001840: 4013 ands r3, r2 - 8001842: 610b str r3, [r1, #16] - 8001844: e028 b.n 8001898 + 80024e4: 4b1c ldr r3, [pc, #112] ; (8002558 ) + 80024e6: 691a ldr r2, [r3, #16] + 80024e8: 491b ldr r1, [pc, #108] ; (8002558 ) + 80024ea: 4b1c ldr r3, [pc, #112] ; (800255c ) + 80024ec: 4013 ands r3, r2 + 80024ee: 610b str r3, [r1, #16] + 80024f0: e028 b.n 8002544 { /* Check the parameters */ assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); /* Erase by sector by sector to be done*/ for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++) - 8001846: 687b ldr r3, [r7, #4] - 8001848: 689b ldr r3, [r3, #8] - 800184a: 60bb str r3, [r7, #8] - 800184c: e01c b.n 8001888 + 80024f2: 687b ldr r3, [r7, #4] + 80024f4: 689b ldr r3, [r3, #8] + 80024f6: 60bb str r3, [r7, #8] + 80024f8: e01c b.n 8002534 { FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange); - 800184e: 687b ldr r3, [r7, #4] - 8001850: 691b ldr r3, [r3, #16] - 8001852: b2db uxtb r3, r3 - 8001854: 4619 mov r1, r3 - 8001856: 68b8 ldr r0, [r7, #8] - 8001858: f000 f868 bl 800192c + 80024fa: 687b ldr r3, [r7, #4] + 80024fc: 691b ldr r3, [r3, #16] + 80024fe: b2db uxtb r3, r3 + 8002500: 4619 mov r1, r3 + 8002502: 68b8 ldr r0, [r7, #8] + 8002504: f000 f868 bl 80025d8 /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - 800185c: f24c 3050 movw r0, #50000 ; 0xc350 - 8001860: f7ff fe88 bl 8001574 - 8001864: 4603 mov r3, r0 - 8001866: 73fb strb r3, [r7, #15] + 8002508: f24c 3050 movw r0, #50000 ; 0xc350 + 800250c: f7ff fe88 bl 8002220 + 8002510: 4603 mov r3, r0 + 8002512: 73fb strb r3, [r7, #15] /* If the erase operation is completed, disable the SER Bit and SNB Bits */ CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); - 8001868: 4b10 ldr r3, [pc, #64] ; (80018ac ) - 800186a: 691b ldr r3, [r3, #16] - 800186c: 4a0f ldr r2, [pc, #60] ; (80018ac ) - 800186e: f023 03fa bic.w r3, r3, #250 ; 0xfa - 8001872: 6113 str r3, [r2, #16] + 8002514: 4b10 ldr r3, [pc, #64] ; (8002558 ) + 8002516: 691b ldr r3, [r3, #16] + 8002518: 4a0f ldr r2, [pc, #60] ; (8002558 ) + 800251a: f023 03fa bic.w r3, r3, #250 ; 0xfa + 800251e: 6113 str r3, [r2, #16] if(status != HAL_OK) - 8001874: 7bfb ldrb r3, [r7, #15] - 8001876: 2b00 cmp r3, #0 - 8001878: d003 beq.n 8001882 + 8002520: 7bfb ldrb r3, [r7, #15] + 8002522: 2b00 cmp r3, #0 + 8002524: d003 beq.n 800252e { /* In case of error, stop erase procedure and return the faulty sector*/ *SectorError = index; - 800187a: 683b ldr r3, [r7, #0] - 800187c: 68ba ldr r2, [r7, #8] - 800187e: 601a str r2, [r3, #0] + 8002526: 683b ldr r3, [r7, #0] + 8002528: 68ba ldr r2, [r7, #8] + 800252a: 601a str r2, [r3, #0] break; - 8001880: e00a b.n 8001898 + 800252c: e00a b.n 8002544 for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++) - 8001882: 68bb ldr r3, [r7, #8] - 8001884: 3301 adds r3, #1 - 8001886: 60bb str r3, [r7, #8] - 8001888: 687b ldr r3, [r7, #4] - 800188a: 68da ldr r2, [r3, #12] - 800188c: 687b ldr r3, [r7, #4] - 800188e: 689b ldr r3, [r3, #8] - 8001890: 4413 add r3, r2 - 8001892: 68ba ldr r2, [r7, #8] - 8001894: 429a cmp r2, r3 - 8001896: d3da bcc.n 800184e + 800252e: 68bb ldr r3, [r7, #8] + 8002530: 3301 adds r3, #1 + 8002532: 60bb str r3, [r7, #8] + 8002534: 687b ldr r3, [r7, #4] + 8002536: 68da ldr r2, [r3, #12] + 8002538: 687b ldr r3, [r7, #4] + 800253a: 689b ldr r3, [r3, #8] + 800253c: 4413 add r3, r2 + 800253e: 68ba ldr r2, [r7, #8] + 8002540: 429a cmp r2, r3 + 8002542: d3da bcc.n 80024fa } } } /* Process Unlocked */ __HAL_UNLOCK(&pFlash); - 8001898: 4b03 ldr r3, [pc, #12] ; (80018a8 ) - 800189a: 2200 movs r2, #0 - 800189c: 751a strb r2, [r3, #20] + 8002544: 4b03 ldr r3, [pc, #12] ; (8002554 ) + 8002546: 2200 movs r2, #0 + 8002548: 751a strb r2, [r3, #20] return status; - 800189e: 7bfb ldrb r3, [r7, #15] + 800254a: 7bfb ldrb r3, [r7, #15] } - 80018a0: 4618 mov r0, r3 - 80018a2: 3710 adds r7, #16 - 80018a4: 46bd mov sp, r7 - 80018a6: bd80 pop {r7, pc} - 80018a8: 200005bc .word 0x200005bc - 80018ac: 40023c00 .word 0x40023c00 - 80018b0: ffff7ffb .word 0xffff7ffb - -080018b4 : + 800254c: 4618 mov r0, r3 + 800254e: 3710 adds r7, #16 + 8002550: 46bd mov sp, r7 + 8002552: bd80 pop {r7, pc} + 8002554: 200005e8 .word 0x200005e8 + 8002558: 40023c00 .word 0x40023c00 + 800255c: ffff7ffb .word 0xffff7ffb + +08002560 : * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased * * @retval HAL Status */ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) { - 80018b4: b480 push {r7} - 80018b6: b083 sub sp, #12 - 80018b8: af00 add r7, sp, #0 - 80018ba: 4603 mov r3, r0 - 80018bc: 6039 str r1, [r7, #0] - 80018be: 71fb strb r3, [r7, #7] + 8002560: b480 push {r7} + 8002562: b083 sub sp, #12 + 8002564: af00 add r7, sp, #0 + 8002566: 4603 mov r3, r0 + 8002568: 6039 str r1, [r7, #0] + 800256a: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_VOLTAGERANGE(VoltageRange)); assert_param(IS_FLASH_BANK(Banks)); /* if the previous operation is completed, proceed to erase all sectors */ FLASH->CR &= CR_PSIZE_MASK; - 80018c0: 4b19 ldr r3, [pc, #100] ; (8001928 ) - 80018c2: 691b ldr r3, [r3, #16] - 80018c4: 4a18 ldr r2, [pc, #96] ; (8001928 ) - 80018c6: f423 7340 bic.w r3, r3, #768 ; 0x300 - 80018ca: 6113 str r3, [r2, #16] + 800256c: 4b19 ldr r3, [pc, #100] ; (80025d4 ) + 800256e: 691b ldr r3, [r3, #16] + 8002570: 4a18 ldr r2, [pc, #96] ; (80025d4 ) + 8002572: f423 7340 bic.w r3, r3, #768 ; 0x300 + 8002576: 6113 str r3, [r2, #16] if(Banks == FLASH_BANK_BOTH) - 80018cc: 683b ldr r3, [r7, #0] - 80018ce: 2b03 cmp r3, #3 - 80018d0: d107 bne.n 80018e2 + 8002578: 683b ldr r3, [r7, #0] + 800257a: 2b03 cmp r3, #3 + 800257c: d107 bne.n 800258e { /* bank1 & bank2 will be erased*/ FLASH->CR |= FLASH_MER_BIT; - 80018d2: 4b15 ldr r3, [pc, #84] ; (8001928 ) - 80018d4: 691a ldr r2, [r3, #16] - 80018d6: 4914 ldr r1, [pc, #80] ; (8001928 ) - 80018d8: f248 0304 movw r3, #32772 ; 0x8004 - 80018dc: 4313 orrs r3, r2 - 80018de: 610b str r3, [r1, #16] - 80018e0: e00f b.n 8001902 + 800257e: 4b15 ldr r3, [pc, #84] ; (80025d4 ) + 8002580: 691a ldr r2, [r3, #16] + 8002582: 4914 ldr r1, [pc, #80] ; (80025d4 ) + 8002584: f248 0304 movw r3, #32772 ; 0x8004 + 8002588: 4313 orrs r3, r2 + 800258a: 610b str r3, [r1, #16] + 800258c: e00f b.n 80025ae } else if(Banks == FLASH_BANK_2) - 80018e2: 683b ldr r3, [r7, #0] - 80018e4: 2b02 cmp r3, #2 - 80018e6: d106 bne.n 80018f6 + 800258e: 683b ldr r3, [r7, #0] + 8002590: 2b02 cmp r3, #2 + 8002592: d106 bne.n 80025a2 { /*Only bank2 will be erased*/ FLASH->CR |= FLASH_CR_MER2; - 80018e8: 4b0f ldr r3, [pc, #60] ; (8001928 ) - 80018ea: 691b ldr r3, [r3, #16] - 80018ec: 4a0e ldr r2, [pc, #56] ; (8001928 ) - 80018ee: f443 4300 orr.w r3, r3, #32768 ; 0x8000 - 80018f2: 6113 str r3, [r2, #16] - 80018f4: e005 b.n 8001902 + 8002594: 4b0f ldr r3, [pc, #60] ; (80025d4 ) + 8002596: 691b ldr r3, [r3, #16] + 8002598: 4a0e ldr r2, [pc, #56] ; (80025d4 ) + 800259a: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800259e: 6113 str r3, [r2, #16] + 80025a0: e005 b.n 80025ae } else { /*Only bank1 will be erased*/ FLASH->CR |= FLASH_CR_MER1; - 80018f6: 4b0c ldr r3, [pc, #48] ; (8001928 ) - 80018f8: 691b ldr r3, [r3, #16] - 80018fa: 4a0b ldr r2, [pc, #44] ; (8001928 ) - 80018fc: f043 0304 orr.w r3, r3, #4 - 8001900: 6113 str r3, [r2, #16] + 80025a2: 4b0c ldr r3, [pc, #48] ; (80025d4 ) + 80025a4: 691b ldr r3, [r3, #16] + 80025a6: 4a0b ldr r2, [pc, #44] ; (80025d4 ) + 80025a8: f043 0304 orr.w r3, r3, #4 + 80025ac: 6113 str r3, [r2, #16] } FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8); - 8001902: 4b09 ldr r3, [pc, #36] ; (8001928 ) - 8001904: 691a ldr r2, [r3, #16] - 8001906: 79fb ldrb r3, [r7, #7] - 8001908: 021b lsls r3, r3, #8 - 800190a: 4313 orrs r3, r2 - 800190c: 4a06 ldr r2, [pc, #24] ; (8001928 ) - 800190e: f443 3380 orr.w r3, r3, #65536 ; 0x10000 - 8001912: 6113 str r3, [r2, #16] + 80025ae: 4b09 ldr r3, [pc, #36] ; (80025d4 ) + 80025b0: 691a ldr r2, [r3, #16] + 80025b2: 79fb ldrb r3, [r7, #7] + 80025b4: 021b lsls r3, r3, #8 + 80025b6: 4313 orrs r3, r2 + 80025b8: 4a06 ldr r2, [pc, #24] ; (80025d4 ) + 80025ba: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 80025be: 6113 str r3, [r2, #16] __ASM volatile ("dsb 0xF":::"memory"); - 8001914: f3bf 8f4f dsb sy + 80025c0: f3bf 8f4f dsb sy } - 8001918: bf00 nop + 80025c4: bf00 nop /* Data synchronous Barrier (DSB) Just after the write operation This will force the CPU to respect the sequence of instruction (no optimization).*/ __DSB(); } - 800191a: bf00 nop - 800191c: 370c adds r7, #12 - 800191e: 46bd mov sp, r7 - 8001920: f85d 7b04 ldr.w r7, [sp], #4 - 8001924: 4770 bx lr - 8001926: bf00 nop - 8001928: 40023c00 .word 0x40023c00 - -0800192c : + 80025c6: bf00 nop + 80025c8: 370c adds r7, #12 + 80025ca: 46bd mov sp, r7 + 80025cc: f85d 7b04 ldr.w r7, [sp], #4 + 80025d0: 4770 bx lr + 80025d2: bf00 nop + 80025d4: 40023c00 .word 0x40023c00 + +080025d8 : * the operation will be done by double word (64-bit) * * @retval None */ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) { - 800192c: b480 push {r7} - 800192e: b085 sub sp, #20 - 8001930: af00 add r7, sp, #0 - 8001932: 6078 str r0, [r7, #4] - 8001934: 460b mov r3, r1 - 8001936: 70fb strb r3, [r7, #3] + 80025d8: b480 push {r7} + 80025da: b085 sub sp, #20 + 80025dc: af00 add r7, sp, #0 + 80025de: 6078 str r0, [r7, #4] + 80025e0: 460b mov r3, r1 + 80025e2: 70fb strb r3, [r7, #3] uint32_t tmp_psize = 0; - 8001938: 2300 movs r3, #0 - 800193a: 60fb str r3, [r7, #12] + 80025e4: 2300 movs r3, #0 + 80025e6: 60fb str r3, [r7, #12] /* Check the parameters */ assert_param(IS_FLASH_SECTOR(Sector)); assert_param(IS_VOLTAGERANGE(VoltageRange)); if(VoltageRange == FLASH_VOLTAGE_RANGE_1) - 800193c: 78fb ldrb r3, [r7, #3] - 800193e: 2b00 cmp r3, #0 - 8001940: d102 bne.n 8001948 + 80025e8: 78fb ldrb r3, [r7, #3] + 80025ea: 2b00 cmp r3, #0 + 80025ec: d102 bne.n 80025f4 { tmp_psize = FLASH_PSIZE_BYTE; - 8001942: 2300 movs r3, #0 - 8001944: 60fb str r3, [r7, #12] - 8001946: e010 b.n 800196a + 80025ee: 2300 movs r3, #0 + 80025f0: 60fb str r3, [r7, #12] + 80025f2: e010 b.n 8002616 } else if(VoltageRange == FLASH_VOLTAGE_RANGE_2) - 8001948: 78fb ldrb r3, [r7, #3] - 800194a: 2b01 cmp r3, #1 - 800194c: d103 bne.n 8001956 + 80025f4: 78fb ldrb r3, [r7, #3] + 80025f6: 2b01 cmp r3, #1 + 80025f8: d103 bne.n 8002602 { tmp_psize = FLASH_PSIZE_HALF_WORD; - 800194e: f44f 7380 mov.w r3, #256 ; 0x100 - 8001952: 60fb str r3, [r7, #12] - 8001954: e009 b.n 800196a + 80025fa: f44f 7380 mov.w r3, #256 ; 0x100 + 80025fe: 60fb str r3, [r7, #12] + 8002600: e009 b.n 8002616 } else if(VoltageRange == FLASH_VOLTAGE_RANGE_3) - 8001956: 78fb ldrb r3, [r7, #3] - 8001958: 2b02 cmp r3, #2 - 800195a: d103 bne.n 8001964 + 8002602: 78fb ldrb r3, [r7, #3] + 8002604: 2b02 cmp r3, #2 + 8002606: d103 bne.n 8002610 { tmp_psize = FLASH_PSIZE_WORD; - 800195c: f44f 7300 mov.w r3, #512 ; 0x200 - 8001960: 60fb str r3, [r7, #12] - 8001962: e002 b.n 800196a + 8002608: f44f 7300 mov.w r3, #512 ; 0x200 + 800260c: 60fb str r3, [r7, #12] + 800260e: e002 b.n 8002616 } else { tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - 8001964: f44f 7340 mov.w r3, #768 ; 0x300 - 8001968: 60fb str r3, [r7, #12] + 8002610: f44f 7340 mov.w r3, #768 ; 0x300 + 8002614: 60fb str r3, [r7, #12] } /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */ if(Sector > FLASH_SECTOR_11) - 800196a: 687b ldr r3, [r7, #4] - 800196c: 2b0b cmp r3, #11 - 800196e: d902 bls.n 8001976 + 8002616: 687b ldr r3, [r7, #4] + 8002618: 2b0b cmp r3, #11 + 800261a: d902 bls.n 8002622 { Sector += 4; - 8001970: 687b ldr r3, [r7, #4] - 8001972: 3304 adds r3, #4 - 8001974: 607b str r3, [r7, #4] + 800261c: 687b ldr r3, [r7, #4] + 800261e: 3304 adds r3, #4 + 8002620: 607b str r3, [r7, #4] } /* If the previous operation is completed, proceed to erase the sector */ FLASH->CR &= CR_PSIZE_MASK; - 8001976: 4b15 ldr r3, [pc, #84] ; (80019cc ) - 8001978: 691b ldr r3, [r3, #16] - 800197a: 4a14 ldr r2, [pc, #80] ; (80019cc ) - 800197c: f423 7340 bic.w r3, r3, #768 ; 0x300 - 8001980: 6113 str r3, [r2, #16] + 8002622: 4b15 ldr r3, [pc, #84] ; (8002678 ) + 8002624: 691b ldr r3, [r3, #16] + 8002626: 4a14 ldr r2, [pc, #80] ; (8002678 ) + 8002628: f423 7340 bic.w r3, r3, #768 ; 0x300 + 800262c: 6113 str r3, [r2, #16] FLASH->CR |= tmp_psize; - 8001982: 4b12 ldr r3, [pc, #72] ; (80019cc ) - 8001984: 691a ldr r2, [r3, #16] - 8001986: 4911 ldr r1, [pc, #68] ; (80019cc ) - 8001988: 68fb ldr r3, [r7, #12] - 800198a: 4313 orrs r3, r2 - 800198c: 610b str r3, [r1, #16] + 800262e: 4b12 ldr r3, [pc, #72] ; (8002678 ) + 8002630: 691a ldr r2, [r3, #16] + 8002632: 4911 ldr r1, [pc, #68] ; (8002678 ) + 8002634: 68fb ldr r3, [r7, #12] + 8002636: 4313 orrs r3, r2 + 8002638: 610b str r3, [r1, #16] CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); - 800198e: 4b0f ldr r3, [pc, #60] ; (80019cc ) - 8001990: 691b ldr r3, [r3, #16] - 8001992: 4a0e ldr r2, [pc, #56] ; (80019cc ) - 8001994: f023 03f8 bic.w r3, r3, #248 ; 0xf8 - 8001998: 6113 str r3, [r2, #16] + 800263a: 4b0f ldr r3, [pc, #60] ; (8002678 ) + 800263c: 691b ldr r3, [r3, #16] + 800263e: 4a0e ldr r2, [pc, #56] ; (8002678 ) + 8002640: f023 03f8 bic.w r3, r3, #248 ; 0xf8 + 8002644: 6113 str r3, [r2, #16] FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); - 800199a: 4b0c ldr r3, [pc, #48] ; (80019cc ) - 800199c: 691a ldr r2, [r3, #16] - 800199e: 687b ldr r3, [r7, #4] - 80019a0: 00db lsls r3, r3, #3 - 80019a2: 4313 orrs r3, r2 - 80019a4: 4a09 ldr r2, [pc, #36] ; (80019cc ) - 80019a6: f043 0302 orr.w r3, r3, #2 - 80019aa: 6113 str r3, [r2, #16] + 8002646: 4b0c ldr r3, [pc, #48] ; (8002678 ) + 8002648: 691a ldr r2, [r3, #16] + 800264a: 687b ldr r3, [r7, #4] + 800264c: 00db lsls r3, r3, #3 + 800264e: 4313 orrs r3, r2 + 8002650: 4a09 ldr r2, [pc, #36] ; (8002678 ) + 8002652: f043 0302 orr.w r3, r3, #2 + 8002656: 6113 str r3, [r2, #16] FLASH->CR |= FLASH_CR_STRT; - 80019ac: 4b07 ldr r3, [pc, #28] ; (80019cc ) - 80019ae: 691b ldr r3, [r3, #16] - 80019b0: 4a06 ldr r2, [pc, #24] ; (80019cc ) - 80019b2: f443 3380 orr.w r3, r3, #65536 ; 0x10000 - 80019b6: 6113 str r3, [r2, #16] + 8002658: 4b07 ldr r3, [pc, #28] ; (8002678 ) + 800265a: 691b ldr r3, [r3, #16] + 800265c: 4a06 ldr r2, [pc, #24] ; (8002678 ) + 800265e: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8002662: 6113 str r3, [r2, #16] __ASM volatile ("dsb 0xF":::"memory"); - 80019b8: f3bf 8f4f dsb sy + 8002664: f3bf 8f4f dsb sy } - 80019bc: bf00 nop + 8002668: bf00 nop /* Data synchronous Barrier (DSB) Just after the write operation This will force the CPU to respect the sequence of instruction (no optimization).*/ __DSB(); } - 80019be: bf00 nop - 80019c0: 3714 adds r7, #20 - 80019c2: 46bd mov sp, r7 - 80019c4: f85d 7b04 ldr.w r7, [sp], #4 - 80019c8: 4770 bx lr - 80019ca: bf00 nop - 80019cc: 40023c00 .word 0x40023c00 - -080019d0 : + 800266a: bf00 nop + 800266c: 3714 adds r7, #20 + 800266e: 46bd mov sp, r7 + 8002670: f85d 7b04 ldr.w r7, [sp], #4 + 8002674: 4770 bx lr + 8002676: bf00 nop + 8002678: 40023c00 .word 0x40023c00 + +0800267c : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { - 80019d0: b480 push {r7} - 80019d2: b089 sub sp, #36 ; 0x24 - 80019d4: af00 add r7, sp, #0 - 80019d6: 6078 str r0, [r7, #4] - 80019d8: 6039 str r1, [r7, #0] + 800267c: b480 push {r7} + 800267e: b089 sub sp, #36 ; 0x24 + 8002680: af00 add r7, sp, #0 + 8002682: 6078 str r0, [r7, #4] + 8002684: 6039 str r1, [r7, #0] uint32_t position = 0x00; - 80019da: 2300 movs r3, #0 - 80019dc: 61fb str r3, [r7, #28] + 8002686: 2300 movs r3, #0 + 8002688: 61fb str r3, [r7, #28] uint32_t ioposition = 0x00; - 80019de: 2300 movs r3, #0 - 80019e0: 617b str r3, [r7, #20] + 800268a: 2300 movs r3, #0 + 800268c: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00; - 80019e2: 2300 movs r3, #0 - 80019e4: 613b str r3, [r7, #16] + 800268e: 2300 movs r3, #0 + 8002690: 613b str r3, [r7, #16] uint32_t temp = 0x00; - 80019e6: 2300 movs r3, #0 - 80019e8: 61bb str r3, [r7, #24] + 8002692: 2300 movs r3, #0 + 8002694: 61bb str r3, [r7, #24] assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ for(position = 0; position < GPIO_NUMBER; position++) - 80019ea: 2300 movs r3, #0 - 80019ec: 61fb str r3, [r7, #28] - 80019ee: e175 b.n 8001cdc + 8002696: 2300 movs r3, #0 + 8002698: 61fb str r3, [r7, #28] + 800269a: e175 b.n 8002988 { /* Get the IO position */ ioposition = ((uint32_t)0x01) << position; - 80019f0: 2201 movs r2, #1 - 80019f2: 69fb ldr r3, [r7, #28] - 80019f4: fa02 f303 lsl.w r3, r2, r3 - 80019f8: 617b str r3, [r7, #20] + 800269c: 2201 movs r2, #1 + 800269e: 69fb ldr r3, [r7, #28] + 80026a0: fa02 f303 lsl.w r3, r2, r3 + 80026a4: 617b str r3, [r7, #20] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; - 80019fa: 683b ldr r3, [r7, #0] - 80019fc: 681b ldr r3, [r3, #0] - 80019fe: 697a ldr r2, [r7, #20] - 8001a00: 4013 ands r3, r2 - 8001a02: 613b str r3, [r7, #16] + 80026a6: 683b ldr r3, [r7, #0] + 80026a8: 681b ldr r3, [r3, #0] + 80026aa: 697a ldr r2, [r7, #20] + 80026ac: 4013 ands r3, r2 + 80026ae: 613b str r3, [r7, #16] if(iocurrent == ioposition) - 8001a04: 693a ldr r2, [r7, #16] - 8001a06: 697b ldr r3, [r7, #20] - 8001a08: 429a cmp r2, r3 - 8001a0a: f040 8164 bne.w 8001cd6 + 80026b0: 693a ldr r2, [r7, #16] + 80026b2: 697b ldr r3, [r7, #20] + 80026b4: 429a cmp r2, r3 + 80026b6: f040 8164 bne.w 8002982 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || - 8001a0e: 683b ldr r3, [r7, #0] - 8001a10: 685b ldr r3, [r3, #4] - 8001a12: 2b01 cmp r3, #1 - 8001a14: d00b beq.n 8001a2e - 8001a16: 683b ldr r3, [r7, #0] - 8001a18: 685b ldr r3, [r3, #4] - 8001a1a: 2b02 cmp r3, #2 - 8001a1c: d007 beq.n 8001a2e + 80026ba: 683b ldr r3, [r7, #0] + 80026bc: 685b ldr r3, [r3, #4] + 80026be: 2b01 cmp r3, #1 + 80026c0: d00b beq.n 80026da + 80026c2: 683b ldr r3, [r7, #0] + 80026c4: 685b ldr r3, [r3, #4] + 80026c6: 2b02 cmp r3, #2 + 80026c8: d007 beq.n 80026da (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - 8001a1e: 683b ldr r3, [r7, #0] - 8001a20: 685b ldr r3, [r3, #4] + 80026ca: 683b ldr r3, [r7, #0] + 80026cc: 685b ldr r3, [r3, #4] if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || - 8001a22: 2b11 cmp r3, #17 - 8001a24: d003 beq.n 8001a2e + 80026ce: 2b11 cmp r3, #17 + 80026d0: d003 beq.n 80026da (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - 8001a26: 683b ldr r3, [r7, #0] - 8001a28: 685b ldr r3, [r3, #4] - 8001a2a: 2b12 cmp r3, #18 - 8001a2c: d130 bne.n 8001a90 + 80026d2: 683b ldr r3, [r7, #0] + 80026d4: 685b ldr r3, [r3, #4] + 80026d6: 2b12 cmp r3, #18 + 80026d8: d130 bne.n 800273c { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; - 8001a2e: 687b ldr r3, [r7, #4] - 8001a30: 689b ldr r3, [r3, #8] - 8001a32: 61bb str r3, [r7, #24] + 80026da: 687b ldr r3, [r7, #4] + 80026dc: 689b ldr r3, [r3, #8] + 80026de: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); - 8001a34: 69fb ldr r3, [r7, #28] - 8001a36: 005b lsls r3, r3, #1 - 8001a38: 2203 movs r2, #3 - 8001a3a: fa02 f303 lsl.w r3, r2, r3 - 8001a3e: 43db mvns r3, r3 - 8001a40: 69ba ldr r2, [r7, #24] - 8001a42: 4013 ands r3, r2 - 8001a44: 61bb str r3, [r7, #24] + 80026e0: 69fb ldr r3, [r7, #28] + 80026e2: 005b lsls r3, r3, #1 + 80026e4: 2203 movs r2, #3 + 80026e6: fa02 f303 lsl.w r3, r2, r3 + 80026ea: 43db mvns r3, r3 + 80026ec: 69ba ldr r2, [r7, #24] + 80026ee: 4013 ands r3, r2 + 80026f0: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2)); - 8001a46: 683b ldr r3, [r7, #0] - 8001a48: 68da ldr r2, [r3, #12] - 8001a4a: 69fb ldr r3, [r7, #28] - 8001a4c: 005b lsls r3, r3, #1 - 8001a4e: fa02 f303 lsl.w r3, r2, r3 - 8001a52: 69ba ldr r2, [r7, #24] - 8001a54: 4313 orrs r3, r2 - 8001a56: 61bb str r3, [r7, #24] + 80026f2: 683b ldr r3, [r7, #0] + 80026f4: 68da ldr r2, [r3, #12] + 80026f6: 69fb ldr r3, [r7, #28] + 80026f8: 005b lsls r3, r3, #1 + 80026fa: fa02 f303 lsl.w r3, r2, r3 + 80026fe: 69ba ldr r2, [r7, #24] + 8002700: 4313 orrs r3, r2 + 8002702: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; - 8001a58: 687b ldr r3, [r7, #4] - 8001a5a: 69ba ldr r2, [r7, #24] - 8001a5c: 609a str r2, [r3, #8] + 8002704: 687b ldr r3, [r7, #4] + 8002706: 69ba ldr r2, [r7, #24] + 8002708: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; - 8001a5e: 687b ldr r3, [r7, #4] - 8001a60: 685b ldr r3, [r3, #4] - 8001a62: 61bb str r3, [r7, #24] + 800270a: 687b ldr r3, [r7, #4] + 800270c: 685b ldr r3, [r3, #4] + 800270e: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT_0 << position) ; - 8001a64: 2201 movs r2, #1 - 8001a66: 69fb ldr r3, [r7, #28] - 8001a68: fa02 f303 lsl.w r3, r2, r3 - 8001a6c: 43db mvns r3, r3 - 8001a6e: 69ba ldr r2, [r7, #24] - 8001a70: 4013 ands r3, r2 - 8001a72: 61bb str r3, [r7, #24] + 8002710: 2201 movs r2, #1 + 8002712: 69fb ldr r3, [r7, #28] + 8002714: fa02 f303 lsl.w r3, r2, r3 + 8002718: 43db mvns r3, r3 + 800271a: 69ba ldr r2, [r7, #24] + 800271c: 4013 ands r3, r2 + 800271e: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); - 8001a74: 683b ldr r3, [r7, #0] - 8001a76: 685b ldr r3, [r3, #4] - 8001a78: 091b lsrs r3, r3, #4 - 8001a7a: f003 0201 and.w r2, r3, #1 - 8001a7e: 69fb ldr r3, [r7, #28] - 8001a80: fa02 f303 lsl.w r3, r2, r3 - 8001a84: 69ba ldr r2, [r7, #24] - 8001a86: 4313 orrs r3, r2 - 8001a88: 61bb str r3, [r7, #24] + 8002720: 683b ldr r3, [r7, #0] + 8002722: 685b ldr r3, [r3, #4] + 8002724: 091b lsrs r3, r3, #4 + 8002726: f003 0201 and.w r2, r3, #1 + 800272a: 69fb ldr r3, [r7, #28] + 800272c: fa02 f303 lsl.w r3, r2, r3 + 8002730: 69ba ldr r2, [r7, #24] + 8002732: 4313 orrs r3, r2 + 8002734: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; - 8001a8a: 687b ldr r3, [r7, #4] - 8001a8c: 69ba ldr r2, [r7, #24] - 8001a8e: 605a str r2, [r3, #4] + 8002736: 687b ldr r3, [r7, #4] + 8002738: 69ba ldr r2, [r7, #24] + 800273a: 605a str r2, [r3, #4] } /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; - 8001a90: 687b ldr r3, [r7, #4] - 8001a92: 68db ldr r3, [r3, #12] - 8001a94: 61bb str r3, [r7, #24] + 800273c: 687b ldr r3, [r7, #4] + 800273e: 68db ldr r3, [r3, #12] + 8002740: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); - 8001a96: 69fb ldr r3, [r7, #28] - 8001a98: 005b lsls r3, r3, #1 - 8001a9a: 2203 movs r2, #3 - 8001a9c: fa02 f303 lsl.w r3, r2, r3 - 8001aa0: 43db mvns r3, r3 - 8001aa2: 69ba ldr r2, [r7, #24] - 8001aa4: 4013 ands r3, r2 - 8001aa6: 61bb str r3, [r7, #24] + 8002742: 69fb ldr r3, [r7, #28] + 8002744: 005b lsls r3, r3, #1 + 8002746: 2203 movs r2, #3 + 8002748: fa02 f303 lsl.w r3, r2, r3 + 800274c: 43db mvns r3, r3 + 800274e: 69ba ldr r2, [r7, #24] + 8002750: 4013 ands r3, r2 + 8002752: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2)); - 8001aa8: 683b ldr r3, [r7, #0] - 8001aaa: 689a ldr r2, [r3, #8] - 8001aac: 69fb ldr r3, [r7, #28] - 8001aae: 005b lsls r3, r3, #1 - 8001ab0: fa02 f303 lsl.w r3, r2, r3 - 8001ab4: 69ba ldr r2, [r7, #24] - 8001ab6: 4313 orrs r3, r2 - 8001ab8: 61bb str r3, [r7, #24] + 8002754: 683b ldr r3, [r7, #0] + 8002756: 689a ldr r2, [r3, #8] + 8002758: 69fb ldr r3, [r7, #28] + 800275a: 005b lsls r3, r3, #1 + 800275c: fa02 f303 lsl.w r3, r2, r3 + 8002760: 69ba ldr r2, [r7, #24] + 8002762: 4313 orrs r3, r2 + 8002764: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; - 8001aba: 687b ldr r3, [r7, #4] - 8001abc: 69ba ldr r2, [r7, #24] - 8001abe: 60da str r2, [r3, #12] + 8002766: 687b ldr r3, [r7, #4] + 8002768: 69ba ldr r2, [r7, #24] + 800276a: 60da str r2, [r3, #12] /* In case of Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - 8001ac0: 683b ldr r3, [r7, #0] - 8001ac2: 685b ldr r3, [r3, #4] - 8001ac4: 2b02 cmp r3, #2 - 8001ac6: d003 beq.n 8001ad0 - 8001ac8: 683b ldr r3, [r7, #0] - 8001aca: 685b ldr r3, [r3, #4] - 8001acc: 2b12 cmp r3, #18 - 8001ace: d123 bne.n 8001b18 + 800276c: 683b ldr r3, [r7, #0] + 800276e: 685b ldr r3, [r3, #4] + 8002770: 2b02 cmp r3, #2 + 8002772: d003 beq.n 800277c + 8002774: 683b ldr r3, [r7, #0] + 8002776: 685b ldr r3, [r3, #4] + 8002778: 2b12 cmp r3, #18 + 800277a: d123 bne.n 80027c4 { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3]; - 8001ad0: 69fb ldr r3, [r7, #28] - 8001ad2: 08da lsrs r2, r3, #3 - 8001ad4: 687b ldr r3, [r7, #4] - 8001ad6: 3208 adds r2, #8 - 8001ad8: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 8001adc: 61bb str r3, [r7, #24] + 800277c: 69fb ldr r3, [r7, #28] + 800277e: 08da lsrs r2, r3, #3 + 8002780: 687b ldr r3, [r7, #4] + 8002782: 3208 adds r2, #8 + 8002784: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8002788: 61bb str r3, [r7, #24] temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; - 8001ade: 69fb ldr r3, [r7, #28] - 8001ae0: f003 0307 and.w r3, r3, #7 - 8001ae4: 009b lsls r3, r3, #2 - 8001ae6: 220f movs r2, #15 - 8001ae8: fa02 f303 lsl.w r3, r2, r3 - 8001aec: 43db mvns r3, r3 - 8001aee: 69ba ldr r2, [r7, #24] - 8001af0: 4013 ands r3, r2 - 8001af2: 61bb str r3, [r7, #24] + 800278a: 69fb ldr r3, [r7, #28] + 800278c: f003 0307 and.w r3, r3, #7 + 8002790: 009b lsls r3, r3, #2 + 8002792: 220f movs r2, #15 + 8002794: fa02 f303 lsl.w r3, r2, r3 + 8002798: 43db mvns r3, r3 + 800279a: 69ba ldr r2, [r7, #24] + 800279c: 4013 ands r3, r2 + 800279e: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); - 8001af4: 683b ldr r3, [r7, #0] - 8001af6: 691a ldr r2, [r3, #16] - 8001af8: 69fb ldr r3, [r7, #28] - 8001afa: f003 0307 and.w r3, r3, #7 - 8001afe: 009b lsls r3, r3, #2 - 8001b00: fa02 f303 lsl.w r3, r2, r3 - 8001b04: 69ba ldr r2, [r7, #24] - 8001b06: 4313 orrs r3, r2 - 8001b08: 61bb str r3, [r7, #24] + 80027a0: 683b ldr r3, [r7, #0] + 80027a2: 691a ldr r2, [r3, #16] + 80027a4: 69fb ldr r3, [r7, #28] + 80027a6: f003 0307 and.w r3, r3, #7 + 80027aa: 009b lsls r3, r3, #2 + 80027ac: fa02 f303 lsl.w r3, r2, r3 + 80027b0: 69ba ldr r2, [r7, #24] + 80027b2: 4313 orrs r3, r2 + 80027b4: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3] = temp; - 8001b0a: 69fb ldr r3, [r7, #28] - 8001b0c: 08da lsrs r2, r3, #3 - 8001b0e: 687b ldr r3, [r7, #4] - 8001b10: 3208 adds r2, #8 - 8001b12: 69b9 ldr r1, [r7, #24] - 8001b14: f843 1022 str.w r1, [r3, r2, lsl #2] + 80027b6: 69fb ldr r3, [r7, #28] + 80027b8: 08da lsrs r2, r3, #3 + 80027ba: 687b ldr r3, [r7, #4] + 80027bc: 3208 adds r2, #8 + 80027be: 69b9 ldr r1, [r7, #24] + 80027c0: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; - 8001b18: 687b ldr r3, [r7, #4] - 8001b1a: 681b ldr r3, [r3, #0] - 8001b1c: 61bb str r3, [r7, #24] + 80027c4: 687b ldr r3, [r7, #4] + 80027c6: 681b ldr r3, [r3, #0] + 80027c8: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2)); - 8001b1e: 69fb ldr r3, [r7, #28] - 8001b20: 005b lsls r3, r3, #1 - 8001b22: 2203 movs r2, #3 - 8001b24: fa02 f303 lsl.w r3, r2, r3 - 8001b28: 43db mvns r3, r3 - 8001b2a: 69ba ldr r2, [r7, #24] - 8001b2c: 4013 ands r3, r2 - 8001b2e: 61bb str r3, [r7, #24] + 80027ca: 69fb ldr r3, [r7, #28] + 80027cc: 005b lsls r3, r3, #1 + 80027ce: 2203 movs r2, #3 + 80027d0: fa02 f303 lsl.w r3, r2, r3 + 80027d4: 43db mvns r3, r3 + 80027d6: 69ba ldr r2, [r7, #24] + 80027d8: 4013 ands r3, r2 + 80027da: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); - 8001b30: 683b ldr r3, [r7, #0] - 8001b32: 685b ldr r3, [r3, #4] - 8001b34: f003 0203 and.w r2, r3, #3 - 8001b38: 69fb ldr r3, [r7, #28] - 8001b3a: 005b lsls r3, r3, #1 - 8001b3c: fa02 f303 lsl.w r3, r2, r3 - 8001b40: 69ba ldr r2, [r7, #24] - 8001b42: 4313 orrs r3, r2 - 8001b44: 61bb str r3, [r7, #24] + 80027dc: 683b ldr r3, [r7, #0] + 80027de: 685b ldr r3, [r3, #4] + 80027e0: f003 0203 and.w r2, r3, #3 + 80027e4: 69fb ldr r3, [r7, #28] + 80027e6: 005b lsls r3, r3, #1 + 80027e8: fa02 f303 lsl.w r3, r2, r3 + 80027ec: 69ba ldr r2, [r7, #24] + 80027ee: 4313 orrs r3, r2 + 80027f0: 61bb str r3, [r7, #24] GPIOx->MODER = temp; - 8001b46: 687b ldr r3, [r7, #4] - 8001b48: 69ba ldr r2, [r7, #24] - 8001b4a: 601a str r2, [r3, #0] + 80027f2: 687b ldr r3, [r7, #4] + 80027f4: 69ba ldr r2, [r7, #24] + 80027f6: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) - 8001b4c: 683b ldr r3, [r7, #0] - 8001b4e: 685b ldr r3, [r3, #4] - 8001b50: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8001b54: 2b00 cmp r3, #0 - 8001b56: f000 80be beq.w 8001cd6 + 80027f8: 683b ldr r3, [r7, #0] + 80027fa: 685b ldr r3, [r3, #4] + 80027fc: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8002800: 2b00 cmp r3, #0 + 8002802: f000 80be beq.w 8002982 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - 8001b5a: 4b66 ldr r3, [pc, #408] ; (8001cf4 ) - 8001b5c: 6c5b ldr r3, [r3, #68] ; 0x44 - 8001b5e: 4a65 ldr r2, [pc, #404] ; (8001cf4 ) - 8001b60: f443 4380 orr.w r3, r3, #16384 ; 0x4000 - 8001b64: 6453 str r3, [r2, #68] ; 0x44 - 8001b66: 4b63 ldr r3, [pc, #396] ; (8001cf4 ) - 8001b68: 6c5b ldr r3, [r3, #68] ; 0x44 - 8001b6a: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 8001b6e: 60fb str r3, [r7, #12] - 8001b70: 68fb ldr r3, [r7, #12] + 8002806: 4b66 ldr r3, [pc, #408] ; (80029a0 ) + 8002808: 6c5b ldr r3, [r3, #68] ; 0x44 + 800280a: 4a65 ldr r2, [pc, #404] ; (80029a0 ) + 800280c: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 8002810: 6453 str r3, [r2, #68] ; 0x44 + 8002812: 4b63 ldr r3, [pc, #396] ; (80029a0 ) + 8002814: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002816: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 800281a: 60fb str r3, [r7, #12] + 800281c: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2]; - 8001b72: 4a61 ldr r2, [pc, #388] ; (8001cf8 ) - 8001b74: 69fb ldr r3, [r7, #28] - 8001b76: 089b lsrs r3, r3, #2 - 8001b78: 3302 adds r3, #2 - 8001b7a: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 8001b7e: 61bb str r3, [r7, #24] + 800281e: 4a61 ldr r2, [pc, #388] ; (80029a4 ) + 8002820: 69fb ldr r3, [r7, #28] + 8002822: 089b lsrs r3, r3, #2 + 8002824: 3302 adds r3, #2 + 8002826: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800282a: 61bb str r3, [r7, #24] temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); - 8001b80: 69fb ldr r3, [r7, #28] - 8001b82: f003 0303 and.w r3, r3, #3 - 8001b86: 009b lsls r3, r3, #2 - 8001b88: 220f movs r2, #15 - 8001b8a: fa02 f303 lsl.w r3, r2, r3 - 8001b8e: 43db mvns r3, r3 - 8001b90: 69ba ldr r2, [r7, #24] - 8001b92: 4013 ands r3, r2 - 8001b94: 61bb str r3, [r7, #24] + 800282c: 69fb ldr r3, [r7, #28] + 800282e: f003 0303 and.w r3, r3, #3 + 8002832: 009b lsls r3, r3, #2 + 8002834: 220f movs r2, #15 + 8002836: fa02 f303 lsl.w r3, r2, r3 + 800283a: 43db mvns r3, r3 + 800283c: 69ba ldr r2, [r7, #24] + 800283e: 4013 ands r3, r2 + 8002840: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); - 8001b96: 687b ldr r3, [r7, #4] - 8001b98: 4a58 ldr r2, [pc, #352] ; (8001cfc ) - 8001b9a: 4293 cmp r3, r2 - 8001b9c: d037 beq.n 8001c0e - 8001b9e: 687b ldr r3, [r7, #4] - 8001ba0: 4a57 ldr r2, [pc, #348] ; (8001d00 ) - 8001ba2: 4293 cmp r3, r2 - 8001ba4: d031 beq.n 8001c0a - 8001ba6: 687b ldr r3, [r7, #4] - 8001ba8: 4a56 ldr r2, [pc, #344] ; (8001d04 ) - 8001baa: 4293 cmp r3, r2 - 8001bac: d02b beq.n 8001c06 - 8001bae: 687b ldr r3, [r7, #4] - 8001bb0: 4a55 ldr r2, [pc, #340] ; (8001d08 ) - 8001bb2: 4293 cmp r3, r2 - 8001bb4: d025 beq.n 8001c02 - 8001bb6: 687b ldr r3, [r7, #4] - 8001bb8: 4a54 ldr r2, [pc, #336] ; (8001d0c ) - 8001bba: 4293 cmp r3, r2 - 8001bbc: d01f beq.n 8001bfe - 8001bbe: 687b ldr r3, [r7, #4] - 8001bc0: 4a53 ldr r2, [pc, #332] ; (8001d10 ) - 8001bc2: 4293 cmp r3, r2 - 8001bc4: d019 beq.n 8001bfa - 8001bc6: 687b ldr r3, [r7, #4] - 8001bc8: 4a52 ldr r2, [pc, #328] ; (8001d14 ) - 8001bca: 4293 cmp r3, r2 - 8001bcc: d013 beq.n 8001bf6 - 8001bce: 687b ldr r3, [r7, #4] - 8001bd0: 4a51 ldr r2, [pc, #324] ; (8001d18 ) - 8001bd2: 4293 cmp r3, r2 - 8001bd4: d00d beq.n 8001bf2 - 8001bd6: 687b ldr r3, [r7, #4] - 8001bd8: 4a50 ldr r2, [pc, #320] ; (8001d1c ) - 8001bda: 4293 cmp r3, r2 - 8001bdc: d007 beq.n 8001bee - 8001bde: 687b ldr r3, [r7, #4] - 8001be0: 4a4f ldr r2, [pc, #316] ; (8001d20 ) - 8001be2: 4293 cmp r3, r2 - 8001be4: d101 bne.n 8001bea - 8001be6: 2309 movs r3, #9 - 8001be8: e012 b.n 8001c10 - 8001bea: 230a movs r3, #10 - 8001bec: e010 b.n 8001c10 - 8001bee: 2308 movs r3, #8 - 8001bf0: e00e b.n 8001c10 - 8001bf2: 2307 movs r3, #7 - 8001bf4: e00c b.n 8001c10 - 8001bf6: 2306 movs r3, #6 - 8001bf8: e00a b.n 8001c10 - 8001bfa: 2305 movs r3, #5 - 8001bfc: e008 b.n 8001c10 - 8001bfe: 2304 movs r3, #4 - 8001c00: e006 b.n 8001c10 - 8001c02: 2303 movs r3, #3 - 8001c04: e004 b.n 8001c10 - 8001c06: 2302 movs r3, #2 - 8001c08: e002 b.n 8001c10 - 8001c0a: 2301 movs r3, #1 - 8001c0c: e000 b.n 8001c10 - 8001c0e: 2300 movs r3, #0 - 8001c10: 69fa ldr r2, [r7, #28] - 8001c12: f002 0203 and.w r2, r2, #3 - 8001c16: 0092 lsls r2, r2, #2 - 8001c18: 4093 lsls r3, r2 - 8001c1a: 69ba ldr r2, [r7, #24] - 8001c1c: 4313 orrs r3, r2 - 8001c1e: 61bb str r3, [r7, #24] + 8002842: 687b ldr r3, [r7, #4] + 8002844: 4a58 ldr r2, [pc, #352] ; (80029a8 ) + 8002846: 4293 cmp r3, r2 + 8002848: d037 beq.n 80028ba + 800284a: 687b ldr r3, [r7, #4] + 800284c: 4a57 ldr r2, [pc, #348] ; (80029ac ) + 800284e: 4293 cmp r3, r2 + 8002850: d031 beq.n 80028b6 + 8002852: 687b ldr r3, [r7, #4] + 8002854: 4a56 ldr r2, [pc, #344] ; (80029b0 ) + 8002856: 4293 cmp r3, r2 + 8002858: d02b beq.n 80028b2 + 800285a: 687b ldr r3, [r7, #4] + 800285c: 4a55 ldr r2, [pc, #340] ; (80029b4 ) + 800285e: 4293 cmp r3, r2 + 8002860: d025 beq.n 80028ae + 8002862: 687b ldr r3, [r7, #4] + 8002864: 4a54 ldr r2, [pc, #336] ; (80029b8 ) + 8002866: 4293 cmp r3, r2 + 8002868: d01f beq.n 80028aa + 800286a: 687b ldr r3, [r7, #4] + 800286c: 4a53 ldr r2, [pc, #332] ; (80029bc ) + 800286e: 4293 cmp r3, r2 + 8002870: d019 beq.n 80028a6 + 8002872: 687b ldr r3, [r7, #4] + 8002874: 4a52 ldr r2, [pc, #328] ; (80029c0 ) + 8002876: 4293 cmp r3, r2 + 8002878: d013 beq.n 80028a2 + 800287a: 687b ldr r3, [r7, #4] + 800287c: 4a51 ldr r2, [pc, #324] ; (80029c4 ) + 800287e: 4293 cmp r3, r2 + 8002880: d00d beq.n 800289e + 8002882: 687b ldr r3, [r7, #4] + 8002884: 4a50 ldr r2, [pc, #320] ; (80029c8 ) + 8002886: 4293 cmp r3, r2 + 8002888: d007 beq.n 800289a + 800288a: 687b ldr r3, [r7, #4] + 800288c: 4a4f ldr r2, [pc, #316] ; (80029cc ) + 800288e: 4293 cmp r3, r2 + 8002890: d101 bne.n 8002896 + 8002892: 2309 movs r3, #9 + 8002894: e012 b.n 80028bc + 8002896: 230a movs r3, #10 + 8002898: e010 b.n 80028bc + 800289a: 2308 movs r3, #8 + 800289c: e00e b.n 80028bc + 800289e: 2307 movs r3, #7 + 80028a0: e00c b.n 80028bc + 80028a2: 2306 movs r3, #6 + 80028a4: e00a b.n 80028bc + 80028a6: 2305 movs r3, #5 + 80028a8: e008 b.n 80028bc + 80028aa: 2304 movs r3, #4 + 80028ac: e006 b.n 80028bc + 80028ae: 2303 movs r3, #3 + 80028b0: e004 b.n 80028bc + 80028b2: 2302 movs r3, #2 + 80028b4: e002 b.n 80028bc + 80028b6: 2301 movs r3, #1 + 80028b8: e000 b.n 80028bc + 80028ba: 2300 movs r3, #0 + 80028bc: 69fa ldr r2, [r7, #28] + 80028be: f002 0203 and.w r2, r2, #3 + 80028c2: 0092 lsls r2, r2, #2 + 80028c4: 4093 lsls r3, r2 + 80028c6: 69ba ldr r2, [r7, #24] + 80028c8: 4313 orrs r3, r2 + 80028ca: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2] = temp; - 8001c20: 4935 ldr r1, [pc, #212] ; (8001cf8 ) - 8001c22: 69fb ldr r3, [r7, #28] - 8001c24: 089b lsrs r3, r3, #2 - 8001c26: 3302 adds r3, #2 - 8001c28: 69ba ldr r2, [r7, #24] - 8001c2a: f841 2023 str.w r2, [r1, r3, lsl #2] + 80028cc: 4935 ldr r1, [pc, #212] ; (80029a4 ) + 80028ce: 69fb ldr r3, [r7, #28] + 80028d0: 089b lsrs r3, r3, #2 + 80028d2: 3302 adds r3, #2 + 80028d4: 69ba ldr r2, [r7, #24] + 80028d6: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear EXTI line configuration */ temp = EXTI->IMR; - 8001c2e: 4b3d ldr r3, [pc, #244] ; (8001d24 ) - 8001c30: 681b ldr r3, [r3, #0] - 8001c32: 61bb str r3, [r7, #24] + 80028da: 4b3d ldr r3, [pc, #244] ; (80029d0 ) + 80028dc: 681b ldr r3, [r3, #0] + 80028de: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); - 8001c34: 693b ldr r3, [r7, #16] - 8001c36: 43db mvns r3, r3 - 8001c38: 69ba ldr r2, [r7, #24] - 8001c3a: 4013 ands r3, r2 - 8001c3c: 61bb str r3, [r7, #24] + 80028e0: 693b ldr r3, [r7, #16] + 80028e2: 43db mvns r3, r3 + 80028e4: 69ba ldr r2, [r7, #24] + 80028e6: 4013 ands r3, r2 + 80028e8: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) - 8001c3e: 683b ldr r3, [r7, #0] - 8001c40: 685b ldr r3, [r3, #4] - 8001c42: f403 3380 and.w r3, r3, #65536 ; 0x10000 - 8001c46: 2b00 cmp r3, #0 - 8001c48: d003 beq.n 8001c52 + 80028ea: 683b ldr r3, [r7, #0] + 80028ec: 685b ldr r3, [r3, #4] + 80028ee: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 80028f2: 2b00 cmp r3, #0 + 80028f4: d003 beq.n 80028fe { temp |= iocurrent; - 8001c4a: 69ba ldr r2, [r7, #24] - 8001c4c: 693b ldr r3, [r7, #16] - 8001c4e: 4313 orrs r3, r2 - 8001c50: 61bb str r3, [r7, #24] + 80028f6: 69ba ldr r2, [r7, #24] + 80028f8: 693b ldr r3, [r7, #16] + 80028fa: 4313 orrs r3, r2 + 80028fc: 61bb str r3, [r7, #24] } EXTI->IMR = temp; - 8001c52: 4a34 ldr r2, [pc, #208] ; (8001d24 ) - 8001c54: 69bb ldr r3, [r7, #24] - 8001c56: 6013 str r3, [r2, #0] + 80028fe: 4a34 ldr r2, [pc, #208] ; (80029d0 ) + 8002900: 69bb ldr r3, [r7, #24] + 8002902: 6013 str r3, [r2, #0] temp = EXTI->EMR; - 8001c58: 4b32 ldr r3, [pc, #200] ; (8001d24 ) - 8001c5a: 685b ldr r3, [r3, #4] - 8001c5c: 61bb str r3, [r7, #24] + 8002904: 4b32 ldr r3, [pc, #200] ; (80029d0 ) + 8002906: 685b ldr r3, [r3, #4] + 8002908: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); - 8001c5e: 693b ldr r3, [r7, #16] - 8001c60: 43db mvns r3, r3 - 8001c62: 69ba ldr r2, [r7, #24] - 8001c64: 4013 ands r3, r2 - 8001c66: 61bb str r3, [r7, #24] + 800290a: 693b ldr r3, [r7, #16] + 800290c: 43db mvns r3, r3 + 800290e: 69ba ldr r2, [r7, #24] + 8002910: 4013 ands r3, r2 + 8002912: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) - 8001c68: 683b ldr r3, [r7, #0] - 8001c6a: 685b ldr r3, [r3, #4] - 8001c6c: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 8001c70: 2b00 cmp r3, #0 - 8001c72: d003 beq.n 8001c7c + 8002914: 683b ldr r3, [r7, #0] + 8002916: 685b ldr r3, [r3, #4] + 8002918: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 800291c: 2b00 cmp r3, #0 + 800291e: d003 beq.n 8002928 { temp |= iocurrent; - 8001c74: 69ba ldr r2, [r7, #24] - 8001c76: 693b ldr r3, [r7, #16] - 8001c78: 4313 orrs r3, r2 - 8001c7a: 61bb str r3, [r7, #24] + 8002920: 69ba ldr r2, [r7, #24] + 8002922: 693b ldr r3, [r7, #16] + 8002924: 4313 orrs r3, r2 + 8002926: 61bb str r3, [r7, #24] } EXTI->EMR = temp; - 8001c7c: 4a29 ldr r2, [pc, #164] ; (8001d24 ) - 8001c7e: 69bb ldr r3, [r7, #24] - 8001c80: 6053 str r3, [r2, #4] + 8002928: 4a29 ldr r2, [pc, #164] ; (80029d0 ) + 800292a: 69bb ldr r3, [r7, #24] + 800292c: 6053 str r3, [r2, #4] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; - 8001c82: 4b28 ldr r3, [pc, #160] ; (8001d24 ) - 8001c84: 689b ldr r3, [r3, #8] - 8001c86: 61bb str r3, [r7, #24] + 800292e: 4b28 ldr r3, [pc, #160] ; (80029d0 ) + 8002930: 689b ldr r3, [r3, #8] + 8002932: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); - 8001c88: 693b ldr r3, [r7, #16] - 8001c8a: 43db mvns r3, r3 - 8001c8c: 69ba ldr r2, [r7, #24] - 8001c8e: 4013 ands r3, r2 - 8001c90: 61bb str r3, [r7, #24] + 8002934: 693b ldr r3, [r7, #16] + 8002936: 43db mvns r3, r3 + 8002938: 69ba ldr r2, [r7, #24] + 800293a: 4013 ands r3, r2 + 800293c: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) - 8001c92: 683b ldr r3, [r7, #0] - 8001c94: 685b ldr r3, [r3, #4] - 8001c96: f403 1380 and.w r3, r3, #1048576 ; 0x100000 - 8001c9a: 2b00 cmp r3, #0 - 8001c9c: d003 beq.n 8001ca6 + 800293e: 683b ldr r3, [r7, #0] + 8002940: 685b ldr r3, [r3, #4] + 8002942: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 8002946: 2b00 cmp r3, #0 + 8002948: d003 beq.n 8002952 { temp |= iocurrent; - 8001c9e: 69ba ldr r2, [r7, #24] - 8001ca0: 693b ldr r3, [r7, #16] - 8001ca2: 4313 orrs r3, r2 - 8001ca4: 61bb str r3, [r7, #24] + 800294a: 69ba ldr r2, [r7, #24] + 800294c: 693b ldr r3, [r7, #16] + 800294e: 4313 orrs r3, r2 + 8002950: 61bb str r3, [r7, #24] } EXTI->RTSR = temp; - 8001ca6: 4a1f ldr r2, [pc, #124] ; (8001d24 ) - 8001ca8: 69bb ldr r3, [r7, #24] - 8001caa: 6093 str r3, [r2, #8] + 8002952: 4a1f ldr r2, [pc, #124] ; (80029d0 ) + 8002954: 69bb ldr r3, [r7, #24] + 8002956: 6093 str r3, [r2, #8] temp = EXTI->FTSR; - 8001cac: 4b1d ldr r3, [pc, #116] ; (8001d24 ) - 8001cae: 68db ldr r3, [r3, #12] - 8001cb0: 61bb str r3, [r7, #24] + 8002958: 4b1d ldr r3, [pc, #116] ; (80029d0 ) + 800295a: 68db ldr r3, [r3, #12] + 800295c: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); - 8001cb2: 693b ldr r3, [r7, #16] - 8001cb4: 43db mvns r3, r3 - 8001cb6: 69ba ldr r2, [r7, #24] - 8001cb8: 4013 ands r3, r2 - 8001cba: 61bb str r3, [r7, #24] + 800295e: 693b ldr r3, [r7, #16] + 8002960: 43db mvns r3, r3 + 8002962: 69ba ldr r2, [r7, #24] + 8002964: 4013 ands r3, r2 + 8002966: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) - 8001cbc: 683b ldr r3, [r7, #0] - 8001cbe: 685b ldr r3, [r3, #4] - 8001cc0: f403 1300 and.w r3, r3, #2097152 ; 0x200000 - 8001cc4: 2b00 cmp r3, #0 - 8001cc6: d003 beq.n 8001cd0 + 8002968: 683b ldr r3, [r7, #0] + 800296a: 685b ldr r3, [r3, #4] + 800296c: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8002970: 2b00 cmp r3, #0 + 8002972: d003 beq.n 800297c { temp |= iocurrent; - 8001cc8: 69ba ldr r2, [r7, #24] - 8001cca: 693b ldr r3, [r7, #16] - 8001ccc: 4313 orrs r3, r2 - 8001cce: 61bb str r3, [r7, #24] + 8002974: 69ba ldr r2, [r7, #24] + 8002976: 693b ldr r3, [r7, #16] + 8002978: 4313 orrs r3, r2 + 800297a: 61bb str r3, [r7, #24] } EXTI->FTSR = temp; - 8001cd0: 4a14 ldr r2, [pc, #80] ; (8001d24 ) - 8001cd2: 69bb ldr r3, [r7, #24] - 8001cd4: 60d3 str r3, [r2, #12] + 800297c: 4a14 ldr r2, [pc, #80] ; (80029d0 ) + 800297e: 69bb ldr r3, [r7, #24] + 8002980: 60d3 str r3, [r2, #12] for(position = 0; position < GPIO_NUMBER; position++) - 8001cd6: 69fb ldr r3, [r7, #28] - 8001cd8: 3301 adds r3, #1 - 8001cda: 61fb str r3, [r7, #28] - 8001cdc: 69fb ldr r3, [r7, #28] - 8001cde: 2b0f cmp r3, #15 - 8001ce0: f67f ae86 bls.w 80019f0 + 8002982: 69fb ldr r3, [r7, #28] + 8002984: 3301 adds r3, #1 + 8002986: 61fb str r3, [r7, #28] + 8002988: 69fb ldr r3, [r7, #28] + 800298a: 2b0f cmp r3, #15 + 800298c: f67f ae86 bls.w 800269c } } } } - 8001ce4: bf00 nop - 8001ce6: bf00 nop - 8001ce8: 3724 adds r7, #36 ; 0x24 - 8001cea: 46bd mov sp, r7 - 8001cec: f85d 7b04 ldr.w r7, [sp], #4 - 8001cf0: 4770 bx lr - 8001cf2: bf00 nop - 8001cf4: 40023800 .word 0x40023800 - 8001cf8: 40013800 .word 0x40013800 - 8001cfc: 40020000 .word 0x40020000 - 8001d00: 40020400 .word 0x40020400 - 8001d04: 40020800 .word 0x40020800 - 8001d08: 40020c00 .word 0x40020c00 - 8001d0c: 40021000 .word 0x40021000 - 8001d10: 40021400 .word 0x40021400 - 8001d14: 40021800 .word 0x40021800 - 8001d18: 40021c00 .word 0x40021c00 - 8001d1c: 40022000 .word 0x40022000 - 8001d20: 40022400 .word 0x40022400 - 8001d24: 40013c00 .word 0x40013c00 - -08001d28 : + 8002990: bf00 nop + 8002992: bf00 nop + 8002994: 3724 adds r7, #36 ; 0x24 + 8002996: 46bd mov sp, r7 + 8002998: f85d 7b04 ldr.w r7, [sp], #4 + 800299c: 4770 bx lr + 800299e: bf00 nop + 80029a0: 40023800 .word 0x40023800 + 80029a4: 40013800 .word 0x40013800 + 80029a8: 40020000 .word 0x40020000 + 80029ac: 40020400 .word 0x40020400 + 80029b0: 40020800 .word 0x40020800 + 80029b4: 40020c00 .word 0x40020c00 + 80029b8: 40021000 .word 0x40021000 + 80029bc: 40021400 .word 0x40021400 + 80029c0: 40021800 .word 0x40021800 + 80029c4: 40021c00 .word 0x40021c00 + 80029c8: 40022000 .word 0x40022000 + 80029cc: 40022400 .word 0x40022400 + 80029d0: 40013c00 .word 0x40013c00 + +080029d4 : * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { - 8001d28: b480 push {r7} - 8001d2a: b085 sub sp, #20 - 8001d2c: af00 add r7, sp, #0 - 8001d2e: 6078 str r0, [r7, #4] - 8001d30: 460b mov r3, r1 - 8001d32: 807b strh r3, [r7, #2] + 80029d4: b480 push {r7} + 80029d6: b085 sub sp, #20 + 80029d8: af00 add r7, sp, #0 + 80029da: 6078 str r0, [r7, #4] + 80029dc: 460b mov r3, r1 + 80029de: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) - 8001d34: 687b ldr r3, [r7, #4] - 8001d36: 691a ldr r2, [r3, #16] - 8001d38: 887b ldrh r3, [r7, #2] - 8001d3a: 4013 ands r3, r2 - 8001d3c: 2b00 cmp r3, #0 - 8001d3e: d002 beq.n 8001d46 + 80029e0: 687b ldr r3, [r7, #4] + 80029e2: 691a ldr r2, [r3, #16] + 80029e4: 887b ldrh r3, [r7, #2] + 80029e6: 4013 ands r3, r2 + 80029e8: 2b00 cmp r3, #0 + 80029ea: d002 beq.n 80029f2 { bitstatus = GPIO_PIN_SET; - 8001d40: 2301 movs r3, #1 - 8001d42: 73fb strb r3, [r7, #15] - 8001d44: e001 b.n 8001d4a + 80029ec: 2301 movs r3, #1 + 80029ee: 73fb strb r3, [r7, #15] + 80029f0: e001 b.n 80029f6 } else { bitstatus = GPIO_PIN_RESET; - 8001d46: 2300 movs r3, #0 - 8001d48: 73fb strb r3, [r7, #15] + 80029f2: 2300 movs r3, #0 + 80029f4: 73fb strb r3, [r7, #15] } return bitstatus; - 8001d4a: 7bfb ldrb r3, [r7, #15] + 80029f6: 7bfb ldrb r3, [r7, #15] } - 8001d4c: 4618 mov r0, r3 - 8001d4e: 3714 adds r7, #20 - 8001d50: 46bd mov sp, r7 - 8001d52: f85d 7b04 ldr.w r7, [sp], #4 - 8001d56: 4770 bx lr + 80029f8: 4618 mov r0, r3 + 80029fa: 3714 adds r7, #20 + 80029fc: 46bd mov sp, r7 + 80029fe: f85d 7b04 ldr.w r7, [sp], #4 + 8002a02: 4770 bx lr -08001d58 : +08002a04 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { - 8001d58: b480 push {r7} - 8001d5a: b083 sub sp, #12 - 8001d5c: af00 add r7, sp, #0 - 8001d5e: 6078 str r0, [r7, #4] - 8001d60: 460b mov r3, r1 - 8001d62: 807b strh r3, [r7, #2] - 8001d64: 4613 mov r3, r2 - 8001d66: 707b strb r3, [r7, #1] + 8002a04: b480 push {r7} + 8002a06: b083 sub sp, #12 + 8002a08: af00 add r7, sp, #0 + 8002a0a: 6078 str r0, [r7, #4] + 8002a0c: 460b mov r3, r1 + 8002a0e: 807b strh r3, [r7, #2] + 8002a10: 4613 mov r3, r2 + 8002a12: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) - 8001d68: 787b ldrb r3, [r7, #1] - 8001d6a: 2b00 cmp r3, #0 - 8001d6c: d003 beq.n 8001d76 + 8002a14: 787b ldrb r3, [r7, #1] + 8002a16: 2b00 cmp r3, #0 + 8002a18: d003 beq.n 8002a22 { GPIOx->BSRR = GPIO_Pin; - 8001d6e: 887a ldrh r2, [r7, #2] - 8001d70: 687b ldr r3, [r7, #4] - 8001d72: 619a str r2, [r3, #24] + 8002a1a: 887a ldrh r2, [r7, #2] + 8002a1c: 687b ldr r3, [r7, #4] + 8002a1e: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; } } - 8001d74: e003 b.n 8001d7e + 8002a20: e003 b.n 8002a2a GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; - 8001d76: 887b ldrh r3, [r7, #2] - 8001d78: 041a lsls r2, r3, #16 - 8001d7a: 687b ldr r3, [r7, #4] - 8001d7c: 619a str r2, [r3, #24] + 8002a22: 887b ldrh r3, [r7, #2] + 8002a24: 041a lsls r2, r3, #16 + 8002a26: 687b ldr r3, [r7, #4] + 8002a28: 619a str r2, [r3, #24] } - 8001d7e: bf00 nop - 8001d80: 370c adds r7, #12 - 8001d82: 46bd mov sp, r7 - 8001d84: f85d 7b04 ldr.w r7, [sp], #4 - 8001d88: 4770 bx lr + 8002a2a: bf00 nop + 8002a2c: 370c adds r7, #12 + 8002a2e: 46bd mov sp, r7 + 8002a30: f85d 7b04 ldr.w r7, [sp], #4 + 8002a34: 4770 bx lr ... -08001d8c : +08002a38 : * supported by this function. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - 8001d8c: b580 push {r7, lr} - 8001d8e: b086 sub sp, #24 - 8001d90: af00 add r7, sp, #0 - 8001d92: 6078 str r0, [r7, #4] + 8002a38: b580 push {r7, lr} + 8002a3a: b086 sub sp, #24 + 8002a3c: af00 add r7, sp, #0 + 8002a3e: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; FlagStatus pwrclkchanged = RESET; - 8001d94: 2300 movs r3, #0 - 8001d96: 75fb strb r3, [r7, #23] + 8002a40: 2300 movs r3, #0 + 8002a42: 75fb strb r3, [r7, #23] /* Check Null pointer */ if (RCC_OscInitStruct == NULL) - 8001d98: 687b ldr r3, [r7, #4] - 8001d9a: 2b00 cmp r3, #0 - 8001d9c: d101 bne.n 8001da2 + 8002a44: 687b ldr r3, [r7, #4] + 8002a46: 2b00 cmp r3, #0 + 8002a48: d101 bne.n 8002a4e { return HAL_ERROR; - 8001d9e: 2301 movs r3, #1 - 8001da0: e29b b.n 80022da + 8002a4a: 2301 movs r3, #1 + 8002a4c: e29b b.n 8002f86 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - 8001da2: 687b ldr r3, [r7, #4] - 8001da4: 681b ldr r3, [r3, #0] - 8001da6: f003 0301 and.w r3, r3, #1 - 8001daa: 2b00 cmp r3, #0 - 8001dac: f000 8087 beq.w 8001ebe + 8002a4e: 687b ldr r3, [r7, #4] + 8002a50: 681b ldr r3, [r3, #0] + 8002a52: f003 0301 and.w r3, r3, #1 + 8002a56: 2b00 cmp r3, #0 + 8002a58: f000 8087 beq.w 8002b6a { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) - 8001db0: 4b96 ldr r3, [pc, #600] ; (800200c ) - 8001db2: 689b ldr r3, [r3, #8] - 8001db4: f003 030c and.w r3, r3, #12 - 8001db8: 2b04 cmp r3, #4 - 8001dba: d00c beq.n 8001dd6 + 8002a5c: 4b96 ldr r3, [pc, #600] ; (8002cb8 ) + 8002a5e: 689b ldr r3, [r3, #8] + 8002a60: f003 030c and.w r3, r3, #12 + 8002a64: 2b04 cmp r3, #4 + 8002a66: d00c beq.n 8002a82 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) - 8001dbc: 4b93 ldr r3, [pc, #588] ; (800200c ) - 8001dbe: 689b ldr r3, [r3, #8] - 8001dc0: f003 030c and.w r3, r3, #12 - 8001dc4: 2b08 cmp r3, #8 - 8001dc6: d112 bne.n 8001dee - 8001dc8: 4b90 ldr r3, [pc, #576] ; (800200c ) - 8001dca: 685b ldr r3, [r3, #4] - 8001dcc: f403 0380 and.w r3, r3, #4194304 ; 0x400000 - 8001dd0: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 - 8001dd4: d10b bne.n 8001dee + 8002a68: 4b93 ldr r3, [pc, #588] ; (8002cb8 ) + 8002a6a: 689b ldr r3, [r3, #8] + 8002a6c: f003 030c and.w r3, r3, #12 + 8002a70: 2b08 cmp r3, #8 + 8002a72: d112 bne.n 8002a9a + 8002a74: 4b90 ldr r3, [pc, #576] ; (8002cb8 ) + 8002a76: 685b ldr r3, [r3, #4] + 8002a78: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8002a7c: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 8002a80: d10b bne.n 8002a9a { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 8001dd6: 4b8d ldr r3, [pc, #564] ; (800200c ) - 8001dd8: 681b ldr r3, [r3, #0] - 8001dda: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 8001dde: 2b00 cmp r3, #0 - 8001de0: d06c beq.n 8001ebc - 8001de2: 687b ldr r3, [r7, #4] - 8001de4: 685b ldr r3, [r3, #4] - 8001de6: 2b00 cmp r3, #0 - 8001de8: d168 bne.n 8001ebc + 8002a82: 4b8d ldr r3, [pc, #564] ; (8002cb8 ) + 8002a84: 681b ldr r3, [r3, #0] + 8002a86: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8002a8a: 2b00 cmp r3, #0 + 8002a8c: d06c beq.n 8002b68 + 8002a8e: 687b ldr r3, [r7, #4] + 8002a90: 685b ldr r3, [r3, #4] + 8002a92: 2b00 cmp r3, #0 + 8002a94: d168 bne.n 8002b68 { return HAL_ERROR; - 8001dea: 2301 movs r3, #1 - 8001dec: e275 b.n 80022da + 8002a96: 2301 movs r3, #1 + 8002a98: e275 b.n 8002f86 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - 8001dee: 687b ldr r3, [r7, #4] - 8001df0: 685b ldr r3, [r3, #4] - 8001df2: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 - 8001df6: d106 bne.n 8001e06 - 8001df8: 4b84 ldr r3, [pc, #528] ; (800200c ) - 8001dfa: 681b ldr r3, [r3, #0] - 8001dfc: 4a83 ldr r2, [pc, #524] ; (800200c ) - 8001dfe: f443 3380 orr.w r3, r3, #65536 ; 0x10000 - 8001e02: 6013 str r3, [r2, #0] - 8001e04: e02e b.n 8001e64 - 8001e06: 687b ldr r3, [r7, #4] - 8001e08: 685b ldr r3, [r3, #4] - 8001e0a: 2b00 cmp r3, #0 - 8001e0c: d10c bne.n 8001e28 - 8001e0e: 4b7f ldr r3, [pc, #508] ; (800200c ) - 8001e10: 681b ldr r3, [r3, #0] - 8001e12: 4a7e ldr r2, [pc, #504] ; (800200c ) - 8001e14: f423 3380 bic.w r3, r3, #65536 ; 0x10000 - 8001e18: 6013 str r3, [r2, #0] - 8001e1a: 4b7c ldr r3, [pc, #496] ; (800200c ) - 8001e1c: 681b ldr r3, [r3, #0] - 8001e1e: 4a7b ldr r2, [pc, #492] ; (800200c ) - 8001e20: f423 2380 bic.w r3, r3, #262144 ; 0x40000 - 8001e24: 6013 str r3, [r2, #0] - 8001e26: e01d b.n 8001e64 - 8001e28: 687b ldr r3, [r7, #4] - 8001e2a: 685b ldr r3, [r3, #4] - 8001e2c: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 - 8001e30: d10c bne.n 8001e4c - 8001e32: 4b76 ldr r3, [pc, #472] ; (800200c ) - 8001e34: 681b ldr r3, [r3, #0] - 8001e36: 4a75 ldr r2, [pc, #468] ; (800200c ) - 8001e38: f443 2380 orr.w r3, r3, #262144 ; 0x40000 - 8001e3c: 6013 str r3, [r2, #0] - 8001e3e: 4b73 ldr r3, [pc, #460] ; (800200c ) - 8001e40: 681b ldr r3, [r3, #0] - 8001e42: 4a72 ldr r2, [pc, #456] ; (800200c ) - 8001e44: f443 3380 orr.w r3, r3, #65536 ; 0x10000 - 8001e48: 6013 str r3, [r2, #0] - 8001e4a: e00b b.n 8001e64 - 8001e4c: 4b6f ldr r3, [pc, #444] ; (800200c ) - 8001e4e: 681b ldr r3, [r3, #0] - 8001e50: 4a6e ldr r2, [pc, #440] ; (800200c ) - 8001e52: f423 3380 bic.w r3, r3, #65536 ; 0x10000 - 8001e56: 6013 str r3, [r2, #0] - 8001e58: 4b6c ldr r3, [pc, #432] ; (800200c ) - 8001e5a: 681b ldr r3, [r3, #0] - 8001e5c: 4a6b ldr r2, [pc, #428] ; (800200c ) - 8001e5e: f423 2380 bic.w r3, r3, #262144 ; 0x40000 - 8001e62: 6013 str r3, [r2, #0] + 8002a9a: 687b ldr r3, [r7, #4] + 8002a9c: 685b ldr r3, [r3, #4] + 8002a9e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8002aa2: d106 bne.n 8002ab2 + 8002aa4: 4b84 ldr r3, [pc, #528] ; (8002cb8 ) + 8002aa6: 681b ldr r3, [r3, #0] + 8002aa8: 4a83 ldr r2, [pc, #524] ; (8002cb8 ) + 8002aaa: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8002aae: 6013 str r3, [r2, #0] + 8002ab0: e02e b.n 8002b10 + 8002ab2: 687b ldr r3, [r7, #4] + 8002ab4: 685b ldr r3, [r3, #4] + 8002ab6: 2b00 cmp r3, #0 + 8002ab8: d10c bne.n 8002ad4 + 8002aba: 4b7f ldr r3, [pc, #508] ; (8002cb8 ) + 8002abc: 681b ldr r3, [r3, #0] + 8002abe: 4a7e ldr r2, [pc, #504] ; (8002cb8 ) + 8002ac0: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8002ac4: 6013 str r3, [r2, #0] + 8002ac6: 4b7c ldr r3, [pc, #496] ; (8002cb8 ) + 8002ac8: 681b ldr r3, [r3, #0] + 8002aca: 4a7b ldr r2, [pc, #492] ; (8002cb8 ) + 8002acc: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 8002ad0: 6013 str r3, [r2, #0] + 8002ad2: e01d b.n 8002b10 + 8002ad4: 687b ldr r3, [r7, #4] + 8002ad6: 685b ldr r3, [r3, #4] + 8002ad8: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 + 8002adc: d10c bne.n 8002af8 + 8002ade: 4b76 ldr r3, [pc, #472] ; (8002cb8 ) + 8002ae0: 681b ldr r3, [r3, #0] + 8002ae2: 4a75 ldr r2, [pc, #468] ; (8002cb8 ) + 8002ae4: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 8002ae8: 6013 str r3, [r2, #0] + 8002aea: 4b73 ldr r3, [pc, #460] ; (8002cb8 ) + 8002aec: 681b ldr r3, [r3, #0] + 8002aee: 4a72 ldr r2, [pc, #456] ; (8002cb8 ) + 8002af0: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8002af4: 6013 str r3, [r2, #0] + 8002af6: e00b b.n 8002b10 + 8002af8: 4b6f ldr r3, [pc, #444] ; (8002cb8 ) + 8002afa: 681b ldr r3, [r3, #0] + 8002afc: 4a6e ldr r2, [pc, #440] ; (8002cb8 ) + 8002afe: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8002b02: 6013 str r3, [r2, #0] + 8002b04: 4b6c ldr r3, [pc, #432] ; (8002cb8 ) + 8002b06: 681b ldr r3, [r3, #0] + 8002b08: 4a6b ldr r2, [pc, #428] ; (8002cb8 ) + 8002b0a: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 8002b0e: 6013 str r3, [r2, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - 8001e64: 687b ldr r3, [r7, #4] - 8001e66: 685b ldr r3, [r3, #4] - 8001e68: 2b00 cmp r3, #0 - 8001e6a: d013 beq.n 8001e94 + 8002b10: 687b ldr r3, [r7, #4] + 8002b12: 685b ldr r3, [r3, #4] + 8002b14: 2b00 cmp r3, #0 + 8002b16: d013 beq.n 8002b40 { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001e6c: f7ff f9e8 bl 8001240 - 8001e70: 6138 str r0, [r7, #16] + 8002b18: f7fe ffea bl 8001af0 + 8002b1c: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 8001e72: e008 b.n 8001e86 + 8002b1e: e008 b.n 8002b32 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - 8001e74: f7ff f9e4 bl 8001240 - 8001e78: 4602 mov r2, r0 - 8001e7a: 693b ldr r3, [r7, #16] - 8001e7c: 1ad3 subs r3, r2, r3 - 8001e7e: 2b64 cmp r3, #100 ; 0x64 - 8001e80: d901 bls.n 8001e86 + 8002b20: f7fe ffe6 bl 8001af0 + 8002b24: 4602 mov r2, r0 + 8002b26: 693b ldr r3, [r7, #16] + 8002b28: 1ad3 subs r3, r2, r3 + 8002b2a: 2b64 cmp r3, #100 ; 0x64 + 8002b2c: d901 bls.n 8002b32 { return HAL_TIMEOUT; - 8001e82: 2303 movs r3, #3 - 8001e84: e229 b.n 80022da + 8002b2e: 2303 movs r3, #3 + 8002b30: e229 b.n 8002f86 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 8001e86: 4b61 ldr r3, [pc, #388] ; (800200c ) - 8001e88: 681b ldr r3, [r3, #0] - 8001e8a: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 8001e8e: 2b00 cmp r3, #0 - 8001e90: d0f0 beq.n 8001e74 - 8001e92: e014 b.n 8001ebe + 8002b32: 4b61 ldr r3, [pc, #388] ; (8002cb8 ) + 8002b34: 681b ldr r3, [r3, #0] + 8002b36: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8002b3a: 2b00 cmp r3, #0 + 8002b3c: d0f0 beq.n 8002b20 + 8002b3e: e014 b.n 8002b6a } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001e94: f7ff f9d4 bl 8001240 - 8001e98: 6138 str r0, [r7, #16] + 8002b40: f7fe ffd6 bl 8001af0 + 8002b44: 6138 str r0, [r7, #16] /* Wait till HSE is bypassed or disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - 8001e9a: e008 b.n 8001eae + 8002b46: e008 b.n 8002b5a { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - 8001e9c: f7ff f9d0 bl 8001240 - 8001ea0: 4602 mov r2, r0 - 8001ea2: 693b ldr r3, [r7, #16] - 8001ea4: 1ad3 subs r3, r2, r3 - 8001ea6: 2b64 cmp r3, #100 ; 0x64 - 8001ea8: d901 bls.n 8001eae + 8002b48: f7fe ffd2 bl 8001af0 + 8002b4c: 4602 mov r2, r0 + 8002b4e: 693b ldr r3, [r7, #16] + 8002b50: 1ad3 subs r3, r2, r3 + 8002b52: 2b64 cmp r3, #100 ; 0x64 + 8002b54: d901 bls.n 8002b5a { return HAL_TIMEOUT; - 8001eaa: 2303 movs r3, #3 - 8001eac: e215 b.n 80022da + 8002b56: 2303 movs r3, #3 + 8002b58: e215 b.n 8002f86 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - 8001eae: 4b57 ldr r3, [pc, #348] ; (800200c ) - 8001eb0: 681b ldr r3, [r3, #0] - 8001eb2: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 8001eb6: 2b00 cmp r3, #0 - 8001eb8: d1f0 bne.n 8001e9c - 8001eba: e000 b.n 8001ebe + 8002b5a: 4b57 ldr r3, [pc, #348] ; (8002cb8 ) + 8002b5c: 681b ldr r3, [r3, #0] + 8002b5e: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8002b62: 2b00 cmp r3, #0 + 8002b64: d1f0 bne.n 8002b48 + 8002b66: e000 b.n 8002b6a if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 8001ebc: bf00 nop + 8002b68: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - 8001ebe: 687b ldr r3, [r7, #4] - 8001ec0: 681b ldr r3, [r3, #0] - 8001ec2: f003 0302 and.w r3, r3, #2 - 8001ec6: 2b00 cmp r3, #0 - 8001ec8: d069 beq.n 8001f9e + 8002b6a: 687b ldr r3, [r7, #4] + 8002b6c: 681b ldr r3, [r3, #0] + 8002b6e: f003 0302 and.w r3, r3, #2 + 8002b72: 2b00 cmp r3, #0 + 8002b74: d069 beq.n 8002c4a /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) - 8001eca: 4b50 ldr r3, [pc, #320] ; (800200c ) - 8001ecc: 689b ldr r3, [r3, #8] - 8001ece: f003 030c and.w r3, r3, #12 - 8001ed2: 2b00 cmp r3, #0 - 8001ed4: d00b beq.n 8001eee + 8002b76: 4b50 ldr r3, [pc, #320] ; (8002cb8 ) + 8002b78: 689b ldr r3, [r3, #8] + 8002b7a: f003 030c and.w r3, r3, #12 + 8002b7e: 2b00 cmp r3, #0 + 8002b80: d00b beq.n 8002b9a || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) - 8001ed6: 4b4d ldr r3, [pc, #308] ; (800200c ) - 8001ed8: 689b ldr r3, [r3, #8] - 8001eda: f003 030c and.w r3, r3, #12 - 8001ede: 2b08 cmp r3, #8 - 8001ee0: d11c bne.n 8001f1c - 8001ee2: 4b4a ldr r3, [pc, #296] ; (800200c ) - 8001ee4: 685b ldr r3, [r3, #4] - 8001ee6: f403 0380 and.w r3, r3, #4194304 ; 0x400000 - 8001eea: 2b00 cmp r3, #0 - 8001eec: d116 bne.n 8001f1c + 8002b82: 4b4d ldr r3, [pc, #308] ; (8002cb8 ) + 8002b84: 689b ldr r3, [r3, #8] + 8002b86: f003 030c and.w r3, r3, #12 + 8002b8a: 2b08 cmp r3, #8 + 8002b8c: d11c bne.n 8002bc8 + 8002b8e: 4b4a ldr r3, [pc, #296] ; (8002cb8 ) + 8002b90: 685b ldr r3, [r3, #4] + 8002b92: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8002b96: 2b00 cmp r3, #0 + 8002b98: d116 bne.n 8002bc8 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - 8001eee: 4b47 ldr r3, [pc, #284] ; (800200c ) - 8001ef0: 681b ldr r3, [r3, #0] - 8001ef2: f003 0302 and.w r3, r3, #2 - 8001ef6: 2b00 cmp r3, #0 - 8001ef8: d005 beq.n 8001f06 - 8001efa: 687b ldr r3, [r7, #4] - 8001efc: 68db ldr r3, [r3, #12] - 8001efe: 2b01 cmp r3, #1 - 8001f00: d001 beq.n 8001f06 + 8002b9a: 4b47 ldr r3, [pc, #284] ; (8002cb8 ) + 8002b9c: 681b ldr r3, [r3, #0] + 8002b9e: f003 0302 and.w r3, r3, #2 + 8002ba2: 2b00 cmp r3, #0 + 8002ba4: d005 beq.n 8002bb2 + 8002ba6: 687b ldr r3, [r7, #4] + 8002ba8: 68db ldr r3, [r3, #12] + 8002baa: 2b01 cmp r3, #1 + 8002bac: d001 beq.n 8002bb2 { return HAL_ERROR; - 8001f02: 2301 movs r3, #1 - 8001f04: e1e9 b.n 80022da + 8002bae: 2301 movs r3, #1 + 8002bb0: e1e9 b.n 8002f86 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 8001f06: 4b41 ldr r3, [pc, #260] ; (800200c ) - 8001f08: 681b ldr r3, [r3, #0] - 8001f0a: f023 02f8 bic.w r2, r3, #248 ; 0xf8 - 8001f0e: 687b ldr r3, [r7, #4] - 8001f10: 691b ldr r3, [r3, #16] - 8001f12: 00db lsls r3, r3, #3 - 8001f14: 493d ldr r1, [pc, #244] ; (800200c ) - 8001f16: 4313 orrs r3, r2 - 8001f18: 600b str r3, [r1, #0] + 8002bb2: 4b41 ldr r3, [pc, #260] ; (8002cb8 ) + 8002bb4: 681b ldr r3, [r3, #0] + 8002bb6: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 8002bba: 687b ldr r3, [r7, #4] + 8002bbc: 691b ldr r3, [r3, #16] + 8002bbe: 00db lsls r3, r3, #3 + 8002bc0: 493d ldr r1, [pc, #244] ; (8002cb8 ) + 8002bc2: 4313 orrs r3, r2 + 8002bc4: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - 8001f1a: e040 b.n 8001f9e + 8002bc6: e040 b.n 8002c4a } } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) - 8001f1c: 687b ldr r3, [r7, #4] - 8001f1e: 68db ldr r3, [r3, #12] - 8001f20: 2b00 cmp r3, #0 - 8001f22: d023 beq.n 8001f6c + 8002bc8: 687b ldr r3, [r7, #4] + 8002bca: 68db ldr r3, [r3, #12] + 8002bcc: 2b00 cmp r3, #0 + 8002bce: d023 beq.n 8002c18 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); - 8001f24: 4b39 ldr r3, [pc, #228] ; (800200c ) - 8001f26: 681b ldr r3, [r3, #0] - 8001f28: 4a38 ldr r2, [pc, #224] ; (800200c ) - 8001f2a: f043 0301 orr.w r3, r3, #1 - 8001f2e: 6013 str r3, [r2, #0] + 8002bd0: 4b39 ldr r3, [pc, #228] ; (8002cb8 ) + 8002bd2: 681b ldr r3, [r3, #0] + 8002bd4: 4a38 ldr r2, [pc, #224] ; (8002cb8 ) + 8002bd6: f043 0301 orr.w r3, r3, #1 + 8002bda: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001f30: f7ff f986 bl 8001240 - 8001f34: 6138 str r0, [r7, #16] + 8002bdc: f7fe ff88 bl 8001af0 + 8002be0: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 8001f36: e008 b.n 8001f4a + 8002be2: e008 b.n 8002bf6 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - 8001f38: f7ff f982 bl 8001240 - 8001f3c: 4602 mov r2, r0 - 8001f3e: 693b ldr r3, [r7, #16] - 8001f40: 1ad3 subs r3, r2, r3 - 8001f42: 2b02 cmp r3, #2 - 8001f44: d901 bls.n 8001f4a + 8002be4: f7fe ff84 bl 8001af0 + 8002be8: 4602 mov r2, r0 + 8002bea: 693b ldr r3, [r7, #16] + 8002bec: 1ad3 subs r3, r2, r3 + 8002bee: 2b02 cmp r3, #2 + 8002bf0: d901 bls.n 8002bf6 { return HAL_TIMEOUT; - 8001f46: 2303 movs r3, #3 - 8001f48: e1c7 b.n 80022da + 8002bf2: 2303 movs r3, #3 + 8002bf4: e1c7 b.n 8002f86 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 8001f4a: 4b30 ldr r3, [pc, #192] ; (800200c ) - 8001f4c: 681b ldr r3, [r3, #0] - 8001f4e: f003 0302 and.w r3, r3, #2 - 8001f52: 2b00 cmp r3, #0 - 8001f54: d0f0 beq.n 8001f38 + 8002bf6: 4b30 ldr r3, [pc, #192] ; (8002cb8 ) + 8002bf8: 681b ldr r3, [r3, #0] + 8002bfa: f003 0302 and.w r3, r3, #2 + 8002bfe: 2b00 cmp r3, #0 + 8002c00: d0f0 beq.n 8002be4 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 8001f56: 4b2d ldr r3, [pc, #180] ; (800200c ) - 8001f58: 681b ldr r3, [r3, #0] - 8001f5a: f023 02f8 bic.w r2, r3, #248 ; 0xf8 - 8001f5e: 687b ldr r3, [r7, #4] - 8001f60: 691b ldr r3, [r3, #16] - 8001f62: 00db lsls r3, r3, #3 - 8001f64: 4929 ldr r1, [pc, #164] ; (800200c ) - 8001f66: 4313 orrs r3, r2 - 8001f68: 600b str r3, [r1, #0] - 8001f6a: e018 b.n 8001f9e + 8002c02: 4b2d ldr r3, [pc, #180] ; (8002cb8 ) + 8002c04: 681b ldr r3, [r3, #0] + 8002c06: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 8002c0a: 687b ldr r3, [r7, #4] + 8002c0c: 691b ldr r3, [r3, #16] + 8002c0e: 00db lsls r3, r3, #3 + 8002c10: 4929 ldr r1, [pc, #164] ; (8002cb8 ) + 8002c12: 4313 orrs r3, r2 + 8002c14: 600b str r3, [r1, #0] + 8002c16: e018 b.n 8002c4a } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); - 8001f6c: 4b27 ldr r3, [pc, #156] ; (800200c ) - 8001f6e: 681b ldr r3, [r3, #0] - 8001f70: 4a26 ldr r2, [pc, #152] ; (800200c ) - 8001f72: f023 0301 bic.w r3, r3, #1 - 8001f76: 6013 str r3, [r2, #0] + 8002c18: 4b27 ldr r3, [pc, #156] ; (8002cb8 ) + 8002c1a: 681b ldr r3, [r3, #0] + 8002c1c: 4a26 ldr r2, [pc, #152] ; (8002cb8 ) + 8002c1e: f023 0301 bic.w r3, r3, #1 + 8002c22: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001f78: f7ff f962 bl 8001240 - 8001f7c: 6138 str r0, [r7, #16] + 8002c24: f7fe ff64 bl 8001af0 + 8002c28: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - 8001f7e: e008 b.n 8001f92 + 8002c2a: e008 b.n 8002c3e { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - 8001f80: f7ff f95e bl 8001240 - 8001f84: 4602 mov r2, r0 - 8001f86: 693b ldr r3, [r7, #16] - 8001f88: 1ad3 subs r3, r2, r3 - 8001f8a: 2b02 cmp r3, #2 - 8001f8c: d901 bls.n 8001f92 + 8002c2c: f7fe ff60 bl 8001af0 + 8002c30: 4602 mov r2, r0 + 8002c32: 693b ldr r3, [r7, #16] + 8002c34: 1ad3 subs r3, r2, r3 + 8002c36: 2b02 cmp r3, #2 + 8002c38: d901 bls.n 8002c3e { return HAL_TIMEOUT; - 8001f8e: 2303 movs r3, #3 - 8001f90: e1a3 b.n 80022da + 8002c3a: 2303 movs r3, #3 + 8002c3c: e1a3 b.n 8002f86 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - 8001f92: 4b1e ldr r3, [pc, #120] ; (800200c ) - 8001f94: 681b ldr r3, [r3, #0] - 8001f96: f003 0302 and.w r3, r3, #2 - 8001f9a: 2b00 cmp r3, #0 - 8001f9c: d1f0 bne.n 8001f80 + 8002c3e: 4b1e ldr r3, [pc, #120] ; (8002cb8 ) + 8002c40: 681b ldr r3, [r3, #0] + 8002c42: f003 0302 and.w r3, r3, #2 + 8002c46: 2b00 cmp r3, #0 + 8002c48: d1f0 bne.n 8002c2c } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - 8001f9e: 687b ldr r3, [r7, #4] - 8001fa0: 681b ldr r3, [r3, #0] - 8001fa2: f003 0308 and.w r3, r3, #8 - 8001fa6: 2b00 cmp r3, #0 - 8001fa8: d038 beq.n 800201c + 8002c4a: 687b ldr r3, [r7, #4] + 8002c4c: 681b ldr r3, [r3, #0] + 8002c4e: f003 0308 and.w r3, r3, #8 + 8002c52: 2b00 cmp r3, #0 + 8002c54: d038 beq.n 8002cc8 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) - 8001faa: 687b ldr r3, [r7, #4] - 8001fac: 695b ldr r3, [r3, #20] - 8001fae: 2b00 cmp r3, #0 - 8001fb0: d019 beq.n 8001fe6 + 8002c56: 687b ldr r3, [r7, #4] + 8002c58: 695b ldr r3, [r3, #20] + 8002c5a: 2b00 cmp r3, #0 + 8002c5c: d019 beq.n 8002c92 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); - 8001fb2: 4b16 ldr r3, [pc, #88] ; (800200c ) - 8001fb4: 6f5b ldr r3, [r3, #116] ; 0x74 - 8001fb6: 4a15 ldr r2, [pc, #84] ; (800200c ) - 8001fb8: f043 0301 orr.w r3, r3, #1 - 8001fbc: 6753 str r3, [r2, #116] ; 0x74 + 8002c5e: 4b16 ldr r3, [pc, #88] ; (8002cb8 ) + 8002c60: 6f5b ldr r3, [r3, #116] ; 0x74 + 8002c62: 4a15 ldr r2, [pc, #84] ; (8002cb8 ) + 8002c64: f043 0301 orr.w r3, r3, #1 + 8002c68: 6753 str r3, [r2, #116] ; 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001fbe: f7ff f93f bl 8001240 - 8001fc2: 6138 str r0, [r7, #16] + 8002c6a: f7fe ff41 bl 8001af0 + 8002c6e: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - 8001fc4: e008 b.n 8001fd8 + 8002c70: e008 b.n 8002c84 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - 8001fc6: f7ff f93b bl 8001240 - 8001fca: 4602 mov r2, r0 - 8001fcc: 693b ldr r3, [r7, #16] - 8001fce: 1ad3 subs r3, r2, r3 - 8001fd0: 2b02 cmp r3, #2 - 8001fd2: d901 bls.n 8001fd8 + 8002c72: f7fe ff3d bl 8001af0 + 8002c76: 4602 mov r2, r0 + 8002c78: 693b ldr r3, [r7, #16] + 8002c7a: 1ad3 subs r3, r2, r3 + 8002c7c: 2b02 cmp r3, #2 + 8002c7e: d901 bls.n 8002c84 { return HAL_TIMEOUT; - 8001fd4: 2303 movs r3, #3 - 8001fd6: e180 b.n 80022da + 8002c80: 2303 movs r3, #3 + 8002c82: e180 b.n 8002f86 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - 8001fd8: 4b0c ldr r3, [pc, #48] ; (800200c ) - 8001fda: 6f5b ldr r3, [r3, #116] ; 0x74 - 8001fdc: f003 0302 and.w r3, r3, #2 - 8001fe0: 2b00 cmp r3, #0 - 8001fe2: d0f0 beq.n 8001fc6 - 8001fe4: e01a b.n 800201c + 8002c84: 4b0c ldr r3, [pc, #48] ; (8002cb8 ) + 8002c86: 6f5b ldr r3, [r3, #116] ; 0x74 + 8002c88: f003 0302 and.w r3, r3, #2 + 8002c8c: 2b00 cmp r3, #0 + 8002c8e: d0f0 beq.n 8002c72 + 8002c90: e01a b.n 8002cc8 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); - 8001fe6: 4b09 ldr r3, [pc, #36] ; (800200c ) - 8001fe8: 6f5b ldr r3, [r3, #116] ; 0x74 - 8001fea: 4a08 ldr r2, [pc, #32] ; (800200c ) - 8001fec: f023 0301 bic.w r3, r3, #1 - 8001ff0: 6753 str r3, [r2, #116] ; 0x74 + 8002c92: 4b09 ldr r3, [pc, #36] ; (8002cb8 ) + 8002c94: 6f5b ldr r3, [r3, #116] ; 0x74 + 8002c96: 4a08 ldr r2, [pc, #32] ; (8002cb8 ) + 8002c98: f023 0301 bic.w r3, r3, #1 + 8002c9c: 6753 str r3, [r2, #116] ; 0x74 /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001ff2: f7ff f925 bl 8001240 - 8001ff6: 6138 str r0, [r7, #16] + 8002c9e: f7fe ff27 bl 8001af0 + 8002ca2: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - 8001ff8: e00a b.n 8002010 + 8002ca4: e00a b.n 8002cbc { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - 8001ffa: f7ff f921 bl 8001240 - 8001ffe: 4602 mov r2, r0 - 8002000: 693b ldr r3, [r7, #16] - 8002002: 1ad3 subs r3, r2, r3 - 8002004: 2b02 cmp r3, #2 - 8002006: d903 bls.n 8002010 + 8002ca6: f7fe ff23 bl 8001af0 + 8002caa: 4602 mov r2, r0 + 8002cac: 693b ldr r3, [r7, #16] + 8002cae: 1ad3 subs r3, r2, r3 + 8002cb0: 2b02 cmp r3, #2 + 8002cb2: d903 bls.n 8002cbc { return HAL_TIMEOUT; - 8002008: 2303 movs r3, #3 - 800200a: e166 b.n 80022da - 800200c: 40023800 .word 0x40023800 + 8002cb4: 2303 movs r3, #3 + 8002cb6: e166 b.n 8002f86 + 8002cb8: 40023800 .word 0x40023800 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - 8002010: 4b92 ldr r3, [pc, #584] ; (800225c ) - 8002012: 6f5b ldr r3, [r3, #116] ; 0x74 - 8002014: f003 0302 and.w r3, r3, #2 - 8002018: 2b00 cmp r3, #0 - 800201a: d1ee bne.n 8001ffa + 8002cbc: 4b92 ldr r3, [pc, #584] ; (8002f08 ) + 8002cbe: 6f5b ldr r3, [r3, #116] ; 0x74 + 8002cc0: f003 0302 and.w r3, r3, #2 + 8002cc4: 2b00 cmp r3, #0 + 8002cc6: d1ee bne.n 8002ca6 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - 800201c: 687b ldr r3, [r7, #4] - 800201e: 681b ldr r3, [r3, #0] - 8002020: f003 0304 and.w r3, r3, #4 - 8002024: 2b00 cmp r3, #0 - 8002026: f000 80a4 beq.w 8002172 + 8002cc8: 687b ldr r3, [r7, #4] + 8002cca: 681b ldr r3, [r3, #0] + 8002ccc: f003 0304 and.w r3, r3, #4 + 8002cd0: 2b00 cmp r3, #0 + 8002cd2: f000 80a4 beq.w 8002e1e /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) - 800202a: 4b8c ldr r3, [pc, #560] ; (800225c ) - 800202c: 6c1b ldr r3, [r3, #64] ; 0x40 - 800202e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8002032: 2b00 cmp r3, #0 - 8002034: d10d bne.n 8002052 + 8002cd6: 4b8c ldr r3, [pc, #560] ; (8002f08 ) + 8002cd8: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002cda: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8002cde: 2b00 cmp r3, #0 + 8002ce0: d10d bne.n 8002cfe { /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - 8002036: 4b89 ldr r3, [pc, #548] ; (800225c ) - 8002038: 6c1b ldr r3, [r3, #64] ; 0x40 - 800203a: 4a88 ldr r2, [pc, #544] ; (800225c ) - 800203c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 8002040: 6413 str r3, [r2, #64] ; 0x40 - 8002042: 4b86 ldr r3, [pc, #536] ; (800225c ) - 8002044: 6c1b ldr r3, [r3, #64] ; 0x40 - 8002046: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 800204a: 60bb str r3, [r7, #8] - 800204c: 68bb ldr r3, [r7, #8] + 8002ce2: 4b89 ldr r3, [pc, #548] ; (8002f08 ) + 8002ce4: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002ce6: 4a88 ldr r2, [pc, #544] ; (8002f08 ) + 8002ce8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8002cec: 6413 str r3, [r2, #64] ; 0x40 + 8002cee: 4b86 ldr r3, [pc, #536] ; (8002f08 ) + 8002cf0: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002cf2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8002cf6: 60bb str r3, [r7, #8] + 8002cf8: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; - 800204e: 2301 movs r3, #1 - 8002050: 75fb strb r3, [r7, #23] + 8002cfa: 2301 movs r3, #1 + 8002cfc: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - 8002052: 4b83 ldr r3, [pc, #524] ; (8002260 ) - 8002054: 681b ldr r3, [r3, #0] - 8002056: f403 7380 and.w r3, r3, #256 ; 0x100 - 800205a: 2b00 cmp r3, #0 - 800205c: d118 bne.n 8002090 + 8002cfe: 4b83 ldr r3, [pc, #524] ; (8002f0c ) + 8002d00: 681b ldr r3, [r3, #0] + 8002d02: f403 7380 and.w r3, r3, #256 ; 0x100 + 8002d06: 2b00 cmp r3, #0 + 8002d08: d118 bne.n 8002d3c { /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; - 800205e: 4b80 ldr r3, [pc, #512] ; (8002260 ) - 8002060: 681b ldr r3, [r3, #0] - 8002062: 4a7f ldr r2, [pc, #508] ; (8002260 ) - 8002064: f443 7380 orr.w r3, r3, #256 ; 0x100 - 8002068: 6013 str r3, [r2, #0] + 8002d0a: 4b80 ldr r3, [pc, #512] ; (8002f0c ) + 8002d0c: 681b ldr r3, [r3, #0] + 8002d0e: 4a7f ldr r2, [pc, #508] ; (8002f0c ) + 8002d10: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8002d14: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - 800206a: f7ff f8e9 bl 8001240 - 800206e: 6138 str r0, [r7, #16] + 8002d16: f7fe feeb bl 8001af0 + 8002d1a: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - 8002070: e008 b.n 8002084 + 8002d1c: e008 b.n 8002d30 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - 8002072: f7ff f8e5 bl 8001240 - 8002076: 4602 mov r2, r0 - 8002078: 693b ldr r3, [r7, #16] - 800207a: 1ad3 subs r3, r2, r3 - 800207c: 2b64 cmp r3, #100 ; 0x64 - 800207e: d901 bls.n 8002084 + 8002d1e: f7fe fee7 bl 8001af0 + 8002d22: 4602 mov r2, r0 + 8002d24: 693b ldr r3, [r7, #16] + 8002d26: 1ad3 subs r3, r2, r3 + 8002d28: 2b64 cmp r3, #100 ; 0x64 + 8002d2a: d901 bls.n 8002d30 { return HAL_TIMEOUT; - 8002080: 2303 movs r3, #3 - 8002082: e12a b.n 80022da + 8002d2c: 2303 movs r3, #3 + 8002d2e: e12a b.n 8002f86 while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - 8002084: 4b76 ldr r3, [pc, #472] ; (8002260 ) - 8002086: 681b ldr r3, [r3, #0] - 8002088: f403 7380 and.w r3, r3, #256 ; 0x100 - 800208c: 2b00 cmp r3, #0 - 800208e: d0f0 beq.n 8002072 + 8002d30: 4b76 ldr r3, [pc, #472] ; (8002f0c ) + 8002d32: 681b ldr r3, [r3, #0] + 8002d34: f403 7380 and.w r3, r3, #256 ; 0x100 + 8002d38: 2b00 cmp r3, #0 + 8002d3a: d0f0 beq.n 8002d1e } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - 8002090: 687b ldr r3, [r7, #4] - 8002092: 689b ldr r3, [r3, #8] - 8002094: 2b01 cmp r3, #1 - 8002096: d106 bne.n 80020a6 - 8002098: 4b70 ldr r3, [pc, #448] ; (800225c ) - 800209a: 6f1b ldr r3, [r3, #112] ; 0x70 - 800209c: 4a6f ldr r2, [pc, #444] ; (800225c ) - 800209e: f043 0301 orr.w r3, r3, #1 - 80020a2: 6713 str r3, [r2, #112] ; 0x70 - 80020a4: e02d b.n 8002102 - 80020a6: 687b ldr r3, [r7, #4] - 80020a8: 689b ldr r3, [r3, #8] - 80020aa: 2b00 cmp r3, #0 - 80020ac: d10c bne.n 80020c8 - 80020ae: 4b6b ldr r3, [pc, #428] ; (800225c ) - 80020b0: 6f1b ldr r3, [r3, #112] ; 0x70 - 80020b2: 4a6a ldr r2, [pc, #424] ; (800225c ) - 80020b4: f023 0301 bic.w r3, r3, #1 - 80020b8: 6713 str r3, [r2, #112] ; 0x70 - 80020ba: 4b68 ldr r3, [pc, #416] ; (800225c ) - 80020bc: 6f1b ldr r3, [r3, #112] ; 0x70 - 80020be: 4a67 ldr r2, [pc, #412] ; (800225c ) - 80020c0: f023 0304 bic.w r3, r3, #4 - 80020c4: 6713 str r3, [r2, #112] ; 0x70 - 80020c6: e01c b.n 8002102 - 80020c8: 687b ldr r3, [r7, #4] - 80020ca: 689b ldr r3, [r3, #8] - 80020cc: 2b05 cmp r3, #5 - 80020ce: d10c bne.n 80020ea - 80020d0: 4b62 ldr r3, [pc, #392] ; (800225c ) - 80020d2: 6f1b ldr r3, [r3, #112] ; 0x70 - 80020d4: 4a61 ldr r2, [pc, #388] ; (800225c ) - 80020d6: f043 0304 orr.w r3, r3, #4 - 80020da: 6713 str r3, [r2, #112] ; 0x70 - 80020dc: 4b5f ldr r3, [pc, #380] ; (800225c ) - 80020de: 6f1b ldr r3, [r3, #112] ; 0x70 - 80020e0: 4a5e ldr r2, [pc, #376] ; (800225c ) - 80020e2: f043 0301 orr.w r3, r3, #1 - 80020e6: 6713 str r3, [r2, #112] ; 0x70 - 80020e8: e00b b.n 8002102 - 80020ea: 4b5c ldr r3, [pc, #368] ; (800225c ) - 80020ec: 6f1b ldr r3, [r3, #112] ; 0x70 - 80020ee: 4a5b ldr r2, [pc, #364] ; (800225c ) - 80020f0: f023 0301 bic.w r3, r3, #1 - 80020f4: 6713 str r3, [r2, #112] ; 0x70 - 80020f6: 4b59 ldr r3, [pc, #356] ; (800225c ) - 80020f8: 6f1b ldr r3, [r3, #112] ; 0x70 - 80020fa: 4a58 ldr r2, [pc, #352] ; (800225c ) - 80020fc: f023 0304 bic.w r3, r3, #4 - 8002100: 6713 str r3, [r2, #112] ; 0x70 + 8002d3c: 687b ldr r3, [r7, #4] + 8002d3e: 689b ldr r3, [r3, #8] + 8002d40: 2b01 cmp r3, #1 + 8002d42: d106 bne.n 8002d52 + 8002d44: 4b70 ldr r3, [pc, #448] ; (8002f08 ) + 8002d46: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002d48: 4a6f ldr r2, [pc, #444] ; (8002f08 ) + 8002d4a: f043 0301 orr.w r3, r3, #1 + 8002d4e: 6713 str r3, [r2, #112] ; 0x70 + 8002d50: e02d b.n 8002dae + 8002d52: 687b ldr r3, [r7, #4] + 8002d54: 689b ldr r3, [r3, #8] + 8002d56: 2b00 cmp r3, #0 + 8002d58: d10c bne.n 8002d74 + 8002d5a: 4b6b ldr r3, [pc, #428] ; (8002f08 ) + 8002d5c: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002d5e: 4a6a ldr r2, [pc, #424] ; (8002f08 ) + 8002d60: f023 0301 bic.w r3, r3, #1 + 8002d64: 6713 str r3, [r2, #112] ; 0x70 + 8002d66: 4b68 ldr r3, [pc, #416] ; (8002f08 ) + 8002d68: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002d6a: 4a67 ldr r2, [pc, #412] ; (8002f08 ) + 8002d6c: f023 0304 bic.w r3, r3, #4 + 8002d70: 6713 str r3, [r2, #112] ; 0x70 + 8002d72: e01c b.n 8002dae + 8002d74: 687b ldr r3, [r7, #4] + 8002d76: 689b ldr r3, [r3, #8] + 8002d78: 2b05 cmp r3, #5 + 8002d7a: d10c bne.n 8002d96 + 8002d7c: 4b62 ldr r3, [pc, #392] ; (8002f08 ) + 8002d7e: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002d80: 4a61 ldr r2, [pc, #388] ; (8002f08 ) + 8002d82: f043 0304 orr.w r3, r3, #4 + 8002d86: 6713 str r3, [r2, #112] ; 0x70 + 8002d88: 4b5f ldr r3, [pc, #380] ; (8002f08 ) + 8002d8a: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002d8c: 4a5e ldr r2, [pc, #376] ; (8002f08 ) + 8002d8e: f043 0301 orr.w r3, r3, #1 + 8002d92: 6713 str r3, [r2, #112] ; 0x70 + 8002d94: e00b b.n 8002dae + 8002d96: 4b5c ldr r3, [pc, #368] ; (8002f08 ) + 8002d98: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002d9a: 4a5b ldr r2, [pc, #364] ; (8002f08 ) + 8002d9c: f023 0301 bic.w r3, r3, #1 + 8002da0: 6713 str r3, [r2, #112] ; 0x70 + 8002da2: 4b59 ldr r3, [pc, #356] ; (8002f08 ) + 8002da4: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002da6: 4a58 ldr r2, [pc, #352] ; (8002f08 ) + 8002da8: f023 0304 bic.w r3, r3, #4 + 8002dac: 6713 str r3, [r2, #112] ; 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) - 8002102: 687b ldr r3, [r7, #4] - 8002104: 689b ldr r3, [r3, #8] - 8002106: 2b00 cmp r3, #0 - 8002108: d015 beq.n 8002136 + 8002dae: 687b ldr r3, [r7, #4] + 8002db0: 689b ldr r3, [r3, #8] + 8002db2: 2b00 cmp r3, #0 + 8002db4: d015 beq.n 8002de2 { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 800210a: f7ff f899 bl 8001240 - 800210e: 6138 str r0, [r7, #16] + 8002db6: f7fe fe9b bl 8001af0 + 8002dba: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 8002110: e00a b.n 8002128 + 8002dbc: e00a b.n 8002dd4 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 8002112: f7ff f895 bl 8001240 - 8002116: 4602 mov r2, r0 - 8002118: 693b ldr r3, [r7, #16] - 800211a: 1ad3 subs r3, r2, r3 - 800211c: f241 3288 movw r2, #5000 ; 0x1388 - 8002120: 4293 cmp r3, r2 - 8002122: d901 bls.n 8002128 + 8002dbe: f7fe fe97 bl 8001af0 + 8002dc2: 4602 mov r2, r0 + 8002dc4: 693b ldr r3, [r7, #16] + 8002dc6: 1ad3 subs r3, r2, r3 + 8002dc8: f241 3288 movw r2, #5000 ; 0x1388 + 8002dcc: 4293 cmp r3, r2 + 8002dce: d901 bls.n 8002dd4 { return HAL_TIMEOUT; - 8002124: 2303 movs r3, #3 - 8002126: e0d8 b.n 80022da + 8002dd0: 2303 movs r3, #3 + 8002dd2: e0d8 b.n 8002f86 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 8002128: 4b4c ldr r3, [pc, #304] ; (800225c ) - 800212a: 6f1b ldr r3, [r3, #112] ; 0x70 - 800212c: f003 0302 and.w r3, r3, #2 - 8002130: 2b00 cmp r3, #0 - 8002132: d0ee beq.n 8002112 - 8002134: e014 b.n 8002160 + 8002dd4: 4b4c ldr r3, [pc, #304] ; (8002f08 ) + 8002dd6: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002dd8: f003 0302 and.w r3, r3, #2 + 8002ddc: 2b00 cmp r3, #0 + 8002dde: d0ee beq.n 8002dbe + 8002de0: e014 b.n 8002e0c } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8002136: f7ff f883 bl 8001240 - 800213a: 6138 str r0, [r7, #16] + 8002de2: f7fe fe85 bl 8001af0 + 8002de6: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - 800213c: e00a b.n 8002154 + 8002de8: e00a b.n 8002e00 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - 800213e: f7ff f87f bl 8001240 - 8002142: 4602 mov r2, r0 - 8002144: 693b ldr r3, [r7, #16] - 8002146: 1ad3 subs r3, r2, r3 - 8002148: f241 3288 movw r2, #5000 ; 0x1388 - 800214c: 4293 cmp r3, r2 - 800214e: d901 bls.n 8002154 + 8002dea: f7fe fe81 bl 8001af0 + 8002dee: 4602 mov r2, r0 + 8002df0: 693b ldr r3, [r7, #16] + 8002df2: 1ad3 subs r3, r2, r3 + 8002df4: f241 3288 movw r2, #5000 ; 0x1388 + 8002df8: 4293 cmp r3, r2 + 8002dfa: d901 bls.n 8002e00 { return HAL_TIMEOUT; - 8002150: 2303 movs r3, #3 - 8002152: e0c2 b.n 80022da + 8002dfc: 2303 movs r3, #3 + 8002dfe: e0c2 b.n 8002f86 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - 8002154: 4b41 ldr r3, [pc, #260] ; (800225c ) - 8002156: 6f1b ldr r3, [r3, #112] ; 0x70 - 8002158: f003 0302 and.w r3, r3, #2 - 800215c: 2b00 cmp r3, #0 - 800215e: d1ee bne.n 800213e + 8002e00: 4b41 ldr r3, [pc, #260] ; (8002f08 ) + 8002e02: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002e04: f003 0302 and.w r3, r3, #2 + 8002e08: 2b00 cmp r3, #0 + 8002e0a: d1ee bne.n 8002dea } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) - 8002160: 7dfb ldrb r3, [r7, #23] - 8002162: 2b01 cmp r3, #1 - 8002164: d105 bne.n 8002172 + 8002e0c: 7dfb ldrb r3, [r7, #23] + 8002e0e: 2b01 cmp r3, #1 + 8002e10: d105 bne.n 8002e1e { __HAL_RCC_PWR_CLK_DISABLE(); - 8002166: 4b3d ldr r3, [pc, #244] ; (800225c ) - 8002168: 6c1b ldr r3, [r3, #64] ; 0x40 - 800216a: 4a3c ldr r2, [pc, #240] ; (800225c ) - 800216c: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 - 8002170: 6413 str r3, [r2, #64] ; 0x40 + 8002e12: 4b3d ldr r3, [pc, #244] ; (8002f08 ) + 8002e14: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002e16: 4a3c ldr r2, [pc, #240] ; (8002f08 ) + 8002e18: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 8002e1c: 6413 str r3, [r2, #64] ; 0x40 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) - 8002172: 687b ldr r3, [r7, #4] - 8002174: 699b ldr r3, [r3, #24] - 8002176: 2b00 cmp r3, #0 - 8002178: f000 80ae beq.w 80022d8 + 8002e1e: 687b ldr r3, [r7, #4] + 8002e20: 699b ldr r3, [r3, #24] + 8002e22: 2b00 cmp r3, #0 + 8002e24: f000 80ae beq.w 8002f84 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - 800217c: 4b37 ldr r3, [pc, #220] ; (800225c ) - 800217e: 689b ldr r3, [r3, #8] - 8002180: f003 030c and.w r3, r3, #12 - 8002184: 2b08 cmp r3, #8 - 8002186: d06d beq.n 8002264 + 8002e28: 4b37 ldr r3, [pc, #220] ; (8002f08 ) + 8002e2a: 689b ldr r3, [r3, #8] + 8002e2c: f003 030c and.w r3, r3, #12 + 8002e30: 2b08 cmp r3, #8 + 8002e32: d06d beq.n 8002f10 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) - 8002188: 687b ldr r3, [r7, #4] - 800218a: 699b ldr r3, [r3, #24] - 800218c: 2b02 cmp r3, #2 - 800218e: d14b bne.n 8002228 + 8002e34: 687b ldr r3, [r7, #4] + 8002e36: 699b ldr r3, [r3, #24] + 8002e38: 2b02 cmp r3, #2 + 8002e3a: d14b bne.n 8002ed4 #if defined (RCC_PLLCFGR_PLLR) assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); #endif /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - 8002190: 4b32 ldr r3, [pc, #200] ; (800225c ) - 8002192: 681b ldr r3, [r3, #0] - 8002194: 4a31 ldr r2, [pc, #196] ; (800225c ) - 8002196: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 - 800219a: 6013 str r3, [r2, #0] + 8002e3c: 4b32 ldr r3, [pc, #200] ; (8002f08 ) + 8002e3e: 681b ldr r3, [r3, #0] + 8002e40: 4a31 ldr r2, [pc, #196] ; (8002f08 ) + 8002e42: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 8002e46: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 800219c: f7ff f850 bl 8001240 - 80021a0: 6138 str r0, [r7, #16] + 8002e48: f7fe fe52 bl 8001af0 + 8002e4c: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 80021a2: e008 b.n 80021b6 + 8002e4e: e008 b.n 8002e62 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - 80021a4: f7ff f84c bl 8001240 - 80021a8: 4602 mov r2, r0 - 80021aa: 693b ldr r3, [r7, #16] - 80021ac: 1ad3 subs r3, r2, r3 - 80021ae: 2b02 cmp r3, #2 - 80021b0: d901 bls.n 80021b6 + 8002e50: f7fe fe4e bl 8001af0 + 8002e54: 4602 mov r2, r0 + 8002e56: 693b ldr r3, [r7, #16] + 8002e58: 1ad3 subs r3, r2, r3 + 8002e5a: 2b02 cmp r3, #2 + 8002e5c: d901 bls.n 8002e62 { return HAL_TIMEOUT; - 80021b2: 2303 movs r3, #3 - 80021b4: e091 b.n 80022da + 8002e5e: 2303 movs r3, #3 + 8002e60: e091 b.n 8002f86 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 80021b6: 4b29 ldr r3, [pc, #164] ; (800225c ) - 80021b8: 681b ldr r3, [r3, #0] - 80021ba: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 80021be: 2b00 cmp r3, #0 - 80021c0: d1f0 bne.n 80021a4 + 8002e62: 4b29 ldr r3, [pc, #164] ; (8002f08 ) + 8002e64: 681b ldr r3, [r3, #0] + 8002e66: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8002e6a: 2b00 cmp r3, #0 + 8002e6c: d1f0 bne.n 8002e50 } } /* Configure the main PLL clock source, multiplication and division factors. */ #if defined (RCC_PLLCFGR_PLLR) __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - 80021c2: 687b ldr r3, [r7, #4] - 80021c4: 69da ldr r2, [r3, #28] - 80021c6: 687b ldr r3, [r7, #4] - 80021c8: 6a1b ldr r3, [r3, #32] - 80021ca: 431a orrs r2, r3 - 80021cc: 687b ldr r3, [r7, #4] - 80021ce: 6a5b ldr r3, [r3, #36] ; 0x24 - 80021d0: 019b lsls r3, r3, #6 - 80021d2: 431a orrs r2, r3 - 80021d4: 687b ldr r3, [r7, #4] - 80021d6: 6a9b ldr r3, [r3, #40] ; 0x28 - 80021d8: 085b lsrs r3, r3, #1 - 80021da: 3b01 subs r3, #1 - 80021dc: 041b lsls r3, r3, #16 - 80021de: 431a orrs r2, r3 - 80021e0: 687b ldr r3, [r7, #4] - 80021e2: 6adb ldr r3, [r3, #44] ; 0x2c - 80021e4: 061b lsls r3, r3, #24 - 80021e6: 431a orrs r2, r3 - 80021e8: 687b ldr r3, [r7, #4] - 80021ea: 6b1b ldr r3, [r3, #48] ; 0x30 - 80021ec: 071b lsls r3, r3, #28 - 80021ee: 491b ldr r1, [pc, #108] ; (800225c ) - 80021f0: 4313 orrs r3, r2 - 80021f2: 604b str r3, [r1, #4] + 8002e6e: 687b ldr r3, [r7, #4] + 8002e70: 69da ldr r2, [r3, #28] + 8002e72: 687b ldr r3, [r7, #4] + 8002e74: 6a1b ldr r3, [r3, #32] + 8002e76: 431a orrs r2, r3 + 8002e78: 687b ldr r3, [r7, #4] + 8002e7a: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002e7c: 019b lsls r3, r3, #6 + 8002e7e: 431a orrs r2, r3 + 8002e80: 687b ldr r3, [r7, #4] + 8002e82: 6a9b ldr r3, [r3, #40] ; 0x28 + 8002e84: 085b lsrs r3, r3, #1 + 8002e86: 3b01 subs r3, #1 + 8002e88: 041b lsls r3, r3, #16 + 8002e8a: 431a orrs r2, r3 + 8002e8c: 687b ldr r3, [r7, #4] + 8002e8e: 6adb ldr r3, [r3, #44] ; 0x2c + 8002e90: 061b lsls r3, r3, #24 + 8002e92: 431a orrs r2, r3 + 8002e94: 687b ldr r3, [r7, #4] + 8002e96: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002e98: 071b lsls r3, r3, #28 + 8002e9a: 491b ldr r1, [pc, #108] ; (8002f08 ) + 8002e9c: 4313 orrs r3, r2 + 8002e9e: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ); #endif /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); - 80021f4: 4b19 ldr r3, [pc, #100] ; (800225c ) - 80021f6: 681b ldr r3, [r3, #0] - 80021f8: 4a18 ldr r2, [pc, #96] ; (800225c ) - 80021fa: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 - 80021fe: 6013 str r3, [r2, #0] + 8002ea0: 4b19 ldr r3, [pc, #100] ; (8002f08 ) + 8002ea2: 681b ldr r3, [r3, #0] + 8002ea4: 4a18 ldr r2, [pc, #96] ; (8002f08 ) + 8002ea6: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 + 8002eaa: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8002200: f7ff f81e bl 8001240 - 8002204: 6138 str r0, [r7, #16] + 8002eac: f7fe fe20 bl 8001af0 + 8002eb0: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 8002206: e008 b.n 800221a + 8002eb2: e008 b.n 8002ec6 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - 8002208: f7ff f81a bl 8001240 - 800220c: 4602 mov r2, r0 - 800220e: 693b ldr r3, [r7, #16] - 8002210: 1ad3 subs r3, r2, r3 - 8002212: 2b02 cmp r3, #2 - 8002214: d901 bls.n 800221a + 8002eb4: f7fe fe1c bl 8001af0 + 8002eb8: 4602 mov r2, r0 + 8002eba: 693b ldr r3, [r7, #16] + 8002ebc: 1ad3 subs r3, r2, r3 + 8002ebe: 2b02 cmp r3, #2 + 8002ec0: d901 bls.n 8002ec6 { return HAL_TIMEOUT; - 8002216: 2303 movs r3, #3 - 8002218: e05f b.n 80022da + 8002ec2: 2303 movs r3, #3 + 8002ec4: e05f b.n 8002f86 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 800221a: 4b10 ldr r3, [pc, #64] ; (800225c ) - 800221c: 681b ldr r3, [r3, #0] - 800221e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 8002222: 2b00 cmp r3, #0 - 8002224: d0f0 beq.n 8002208 - 8002226: e057 b.n 80022d8 + 8002ec6: 4b10 ldr r3, [pc, #64] ; (8002f08 ) + 8002ec8: 681b ldr r3, [r3, #0] + 8002eca: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8002ece: 2b00 cmp r3, #0 + 8002ed0: d0f0 beq.n 8002eb4 + 8002ed2: e057 b.n 8002f84 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - 8002228: 4b0c ldr r3, [pc, #48] ; (800225c ) - 800222a: 681b ldr r3, [r3, #0] - 800222c: 4a0b ldr r2, [pc, #44] ; (800225c ) - 800222e: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 - 8002232: 6013 str r3, [r2, #0] + 8002ed4: 4b0c ldr r3, [pc, #48] ; (8002f08 ) + 8002ed6: 681b ldr r3, [r3, #0] + 8002ed8: 4a0b ldr r2, [pc, #44] ; (8002f08 ) + 8002eda: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 8002ede: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8002234: f7ff f804 bl 8001240 - 8002238: 6138 str r0, [r7, #16] + 8002ee0: f7fe fe06 bl 8001af0 + 8002ee4: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 800223a: e008 b.n 800224e + 8002ee6: e008 b.n 8002efa { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - 800223c: f7ff f800 bl 8001240 - 8002240: 4602 mov r2, r0 - 8002242: 693b ldr r3, [r7, #16] - 8002244: 1ad3 subs r3, r2, r3 - 8002246: 2b02 cmp r3, #2 - 8002248: d901 bls.n 800224e + 8002ee8: f7fe fe02 bl 8001af0 + 8002eec: 4602 mov r2, r0 + 8002eee: 693b ldr r3, [r7, #16] + 8002ef0: 1ad3 subs r3, r2, r3 + 8002ef2: 2b02 cmp r3, #2 + 8002ef4: d901 bls.n 8002efa { return HAL_TIMEOUT; - 800224a: 2303 movs r3, #3 - 800224c: e045 b.n 80022da + 8002ef6: 2303 movs r3, #3 + 8002ef8: e045 b.n 8002f86 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 800224e: 4b03 ldr r3, [pc, #12] ; (800225c ) - 8002250: 681b ldr r3, [r3, #0] - 8002252: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 8002256: 2b00 cmp r3, #0 - 8002258: d1f0 bne.n 800223c - 800225a: e03d b.n 80022d8 - 800225c: 40023800 .word 0x40023800 - 8002260: 40007000 .word 0x40007000 + 8002efa: 4b03 ldr r3, [pc, #12] ; (8002f08 ) + 8002efc: 681b ldr r3, [r3, #0] + 8002efe: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8002f02: 2b00 cmp r3, #0 + 8002f04: d1f0 bne.n 8002ee8 + 8002f06: e03d b.n 8002f84 + 8002f08: 40023800 .word 0x40023800 + 8002f0c: 40007000 .word 0x40007000 } } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->PLLCFGR; - 8002264: 4b1f ldr r3, [pc, #124] ; (80022e4 ) - 8002266: 685b ldr r3, [r3, #4] - 8002268: 60fb str r3, [r7, #12] + 8002f10: 4b1f ldr r3, [pc, #124] ; (8002f90 ) + 8002f12: 685b ldr r3, [r3, #4] + 8002f14: 60fb str r3, [r7, #12] #if defined (RCC_PLLCFGR_PLLR) if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || - 800226a: 687b ldr r3, [r7, #4] - 800226c: 699b ldr r3, [r3, #24] - 800226e: 2b01 cmp r3, #1 - 8002270: d030 beq.n 80022d4 + 8002f16: 687b ldr r3, [r7, #4] + 8002f18: 699b ldr r3, [r3, #24] + 8002f1a: 2b01 cmp r3, #1 + 8002f1c: d030 beq.n 8002f80 (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 8002272: 68fb ldr r3, [r7, #12] - 8002274: f403 0280 and.w r2, r3, #4194304 ; 0x400000 - 8002278: 687b ldr r3, [r7, #4] - 800227a: 69db ldr r3, [r3, #28] + 8002f1e: 68fb ldr r3, [r7, #12] + 8002f20: f403 0280 and.w r2, r3, #4194304 ; 0x400000 + 8002f24: 687b ldr r3, [r7, #4] + 8002f26: 69db ldr r3, [r3, #28] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || - 800227c: 429a cmp r2, r3 - 800227e: d129 bne.n 80022d4 + 8002f28: 429a cmp r2, r3 + 8002f2a: d129 bne.n 8002f80 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || - 8002280: 68fb ldr r3, [r7, #12] - 8002282: f003 023f and.w r2, r3, #63 ; 0x3f - 8002286: 687b ldr r3, [r7, #4] - 8002288: 6a1b ldr r3, [r3, #32] + 8002f2c: 68fb ldr r3, [r7, #12] + 8002f2e: f003 023f and.w r2, r3, #63 ; 0x3f + 8002f32: 687b ldr r3, [r7, #4] + 8002f34: 6a1b ldr r3, [r3, #32] (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 800228a: 429a cmp r2, r3 - 800228c: d122 bne.n 80022d4 + 8002f36: 429a cmp r2, r3 + 8002f38: d122 bne.n 8002f80 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || - 800228e: 68fa ldr r2, [r7, #12] - 8002290: f647 73c0 movw r3, #32704 ; 0x7fc0 - 8002294: 4013 ands r3, r2 - 8002296: 687a ldr r2, [r7, #4] - 8002298: 6a52 ldr r2, [r2, #36] ; 0x24 - 800229a: 0192 lsls r2, r2, #6 + 8002f3a: 68fa ldr r2, [r7, #12] + 8002f3c: f647 73c0 movw r3, #32704 ; 0x7fc0 + 8002f40: 4013 ands r3, r2 + 8002f42: 687a ldr r2, [r7, #4] + 8002f44: 6a52 ldr r2, [r2, #36] ; 0x24 + 8002f46: 0192 lsls r2, r2, #6 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || - 800229c: 4293 cmp r3, r2 - 800229e: d119 bne.n 80022d4 + 8002f48: 4293 cmp r3, r2 + 8002f4a: d119 bne.n 8002f80 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || - 80022a0: 68fb ldr r3, [r7, #12] - 80022a2: f403 3240 and.w r2, r3, #196608 ; 0x30000 - 80022a6: 687b ldr r3, [r7, #4] - 80022a8: 6a9b ldr r3, [r3, #40] ; 0x28 - 80022aa: 085b lsrs r3, r3, #1 - 80022ac: 3b01 subs r3, #1 - 80022ae: 041b lsls r3, r3, #16 + 8002f4c: 68fb ldr r3, [r7, #12] + 8002f4e: f403 3240 and.w r2, r3, #196608 ; 0x30000 + 8002f52: 687b ldr r3, [r7, #4] + 8002f54: 6a9b ldr r3, [r3, #40] ; 0x28 + 8002f56: 085b lsrs r3, r3, #1 + 8002f58: 3b01 subs r3, #1 + 8002f5a: 041b lsls r3, r3, #16 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || - 80022b0: 429a cmp r2, r3 - 80022b2: d10f bne.n 80022d4 + 8002f5c: 429a cmp r2, r3 + 8002f5e: d10f bne.n 8002f80 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || - 80022b4: 68fb ldr r3, [r7, #12] - 80022b6: f003 6270 and.w r2, r3, #251658240 ; 0xf000000 - 80022ba: 687b ldr r3, [r7, #4] - 80022bc: 6adb ldr r3, [r3, #44] ; 0x2c - 80022be: 061b lsls r3, r3, #24 + 8002f60: 68fb ldr r3, [r7, #12] + 8002f62: f003 6270 and.w r2, r3, #251658240 ; 0xf000000 + 8002f66: 687b ldr r3, [r7, #4] + 8002f68: 6adb ldr r3, [r3, #44] ; 0x2c + 8002f6a: 061b lsls r3, r3, #24 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || - 80022c0: 429a cmp r2, r3 - 80022c2: d107 bne.n 80022d4 + 8002f6c: 429a cmp r2, r3 + 8002f6e: d107 bne.n 8002f80 (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) - 80022c4: 68fb ldr r3, [r7, #12] - 80022c6: f003 42e0 and.w r2, r3, #1879048192 ; 0x70000000 - 80022ca: 687b ldr r3, [r7, #4] - 80022cc: 6b1b ldr r3, [r3, #48] ; 0x30 - 80022ce: 071b lsls r3, r3, #28 + 8002f70: 68fb ldr r3, [r7, #12] + 8002f72: f003 42e0 and.w r2, r3, #1879048192 ; 0x70000000 + 8002f76: 687b ldr r3, [r7, #4] + 8002f78: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002f7a: 071b lsls r3, r3, #28 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || - 80022d0: 429a cmp r2, r3 - 80022d2: d001 beq.n 80022d8 + 8002f7c: 429a cmp r2, r3 + 8002f7e: d001 beq.n 8002f84 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) #endif { return HAL_ERROR; - 80022d4: 2301 movs r3, #1 - 80022d6: e000 b.n 80022da + 8002f80: 2301 movs r3, #1 + 8002f82: e000 b.n 8002f86 } } } return HAL_OK; - 80022d8: 2300 movs r3, #0 + 8002f84: 2300 movs r3, #0 } - 80022da: 4618 mov r0, r3 - 80022dc: 3718 adds r7, #24 - 80022de: 46bd mov sp, r7 - 80022e0: bd80 pop {r7, pc} - 80022e2: bf00 nop - 80022e4: 40023800 .word 0x40023800 - -080022e8 : + 8002f86: 4618 mov r0, r3 + 8002f88: 3718 adds r7, #24 + 8002f8a: 46bd mov sp, r7 + 8002f8c: bd80 pop {r7, pc} + 8002f8e: bf00 nop + 8002f90: 40023800 .word 0x40023800 + +08002f94 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { - 80022e8: b580 push {r7, lr} - 80022ea: b084 sub sp, #16 - 80022ec: af00 add r7, sp, #0 - 80022ee: 6078 str r0, [r7, #4] - 80022f0: 6039 str r1, [r7, #0] + 8002f94: b580 push {r7, lr} + 8002f96: b084 sub sp, #16 + 8002f98: af00 add r7, sp, #0 + 8002f9a: 6078 str r0, [r7, #4] + 8002f9c: 6039 str r1, [r7, #0] uint32_t tickstart = 0; - 80022f2: 2300 movs r3, #0 - 80022f4: 60fb str r3, [r7, #12] + 8002f9e: 2300 movs r3, #0 + 8002fa0: 60fb str r3, [r7, #12] /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) - 80022f6: 687b ldr r3, [r7, #4] - 80022f8: 2b00 cmp r3, #0 - 80022fa: d101 bne.n 8002300 + 8002fa2: 687b ldr r3, [r7, #4] + 8002fa4: 2b00 cmp r3, #0 + 8002fa6: d101 bne.n 8002fac { return HAL_ERROR; - 80022fc: 2301 movs r3, #1 - 80022fe: e0d0 b.n 80024a2 + 8002fa8: 2301 movs r3, #1 + 8002faa: e0d0 b.n 800314e /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) - 8002300: 4b6a ldr r3, [pc, #424] ; (80024ac ) - 8002302: 681b ldr r3, [r3, #0] - 8002304: f003 030f and.w r3, r3, #15 - 8002308: 683a ldr r2, [r7, #0] - 800230a: 429a cmp r2, r3 - 800230c: d910 bls.n 8002330 + 8002fac: 4b6a ldr r3, [pc, #424] ; (8003158 ) + 8002fae: 681b ldr r3, [r3, #0] + 8002fb0: f003 030f and.w r3, r3, #15 + 8002fb4: 683a ldr r2, [r7, #0] + 8002fb6: 429a cmp r2, r3 + 8002fb8: d910 bls.n 8002fdc { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 800230e: 4b67 ldr r3, [pc, #412] ; (80024ac ) - 8002310: 681b ldr r3, [r3, #0] - 8002312: f023 020f bic.w r2, r3, #15 - 8002316: 4965 ldr r1, [pc, #404] ; (80024ac ) - 8002318: 683b ldr r3, [r7, #0] - 800231a: 4313 orrs r3, r2 - 800231c: 600b str r3, [r1, #0] + 8002fba: 4b67 ldr r3, [pc, #412] ; (8003158 ) + 8002fbc: 681b ldr r3, [r3, #0] + 8002fbe: f023 020f bic.w r2, r3, #15 + 8002fc2: 4965 ldr r1, [pc, #404] ; (8003158 ) + 8002fc4: 683b ldr r3, [r7, #0] + 8002fc6: 4313 orrs r3, r2 + 8002fc8: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) - 800231e: 4b63 ldr r3, [pc, #396] ; (80024ac ) - 8002320: 681b ldr r3, [r3, #0] - 8002322: f003 030f and.w r3, r3, #15 - 8002326: 683a ldr r2, [r7, #0] - 8002328: 429a cmp r2, r3 - 800232a: d001 beq.n 8002330 + 8002fca: 4b63 ldr r3, [pc, #396] ; (8003158 ) + 8002fcc: 681b ldr r3, [r3, #0] + 8002fce: f003 030f and.w r3, r3, #15 + 8002fd2: 683a ldr r2, [r7, #0] + 8002fd4: 429a cmp r2, r3 + 8002fd6: d001 beq.n 8002fdc { return HAL_ERROR; - 800232c: 2301 movs r3, #1 - 800232e: e0b8 b.n 80024a2 + 8002fd8: 2301 movs r3, #1 + 8002fda: e0b8 b.n 800314e } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - 8002330: 687b ldr r3, [r7, #4] - 8002332: 681b ldr r3, [r3, #0] - 8002334: f003 0302 and.w r3, r3, #2 - 8002338: 2b00 cmp r3, #0 - 800233a: d020 beq.n 800237e + 8002fdc: 687b ldr r3, [r7, #4] + 8002fde: 681b ldr r3, [r3, #0] + 8002fe0: f003 0302 and.w r3, r3, #2 + 8002fe4: 2b00 cmp r3, #0 + 8002fe6: d020 beq.n 800302a { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 800233c: 687b ldr r3, [r7, #4] - 800233e: 681b ldr r3, [r3, #0] - 8002340: f003 0304 and.w r3, r3, #4 - 8002344: 2b00 cmp r3, #0 - 8002346: d005 beq.n 8002354 + 8002fe8: 687b ldr r3, [r7, #4] + 8002fea: 681b ldr r3, [r3, #0] + 8002fec: f003 0304 and.w r3, r3, #4 + 8002ff0: 2b00 cmp r3, #0 + 8002ff2: d005 beq.n 8003000 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); - 8002348: 4b59 ldr r3, [pc, #356] ; (80024b0 ) - 800234a: 689b ldr r3, [r3, #8] - 800234c: 4a58 ldr r2, [pc, #352] ; (80024b0 ) - 800234e: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00 - 8002352: 6093 str r3, [r2, #8] + 8002ff4: 4b59 ldr r3, [pc, #356] ; (800315c ) + 8002ff6: 689b ldr r3, [r3, #8] + 8002ff8: 4a58 ldr r2, [pc, #352] ; (800315c ) + 8002ffa: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00 + 8002ffe: 6093 str r3, [r2, #8] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - 8002354: 687b ldr r3, [r7, #4] - 8002356: 681b ldr r3, [r3, #0] - 8002358: f003 0308 and.w r3, r3, #8 - 800235c: 2b00 cmp r3, #0 - 800235e: d005 beq.n 800236c + 8003000: 687b ldr r3, [r7, #4] + 8003002: 681b ldr r3, [r3, #0] + 8003004: f003 0308 and.w r3, r3, #8 + 8003008: 2b00 cmp r3, #0 + 800300a: d005 beq.n 8003018 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); - 8002360: 4b53 ldr r3, [pc, #332] ; (80024b0 ) - 8002362: 689b ldr r3, [r3, #8] - 8002364: 4a52 ldr r2, [pc, #328] ; (80024b0 ) - 8002366: f443 4360 orr.w r3, r3, #57344 ; 0xe000 - 800236a: 6093 str r3, [r2, #8] + 800300c: 4b53 ldr r3, [pc, #332] ; (800315c ) + 800300e: 689b ldr r3, [r3, #8] + 8003010: 4a52 ldr r2, [pc, #328] ; (800315c ) + 8003012: f443 4360 orr.w r3, r3, #57344 ; 0xe000 + 8003016: 6093 str r3, [r2, #8] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - 800236c: 4b50 ldr r3, [pc, #320] ; (80024b0 ) - 800236e: 689b ldr r3, [r3, #8] - 8002370: f023 02f0 bic.w r2, r3, #240 ; 0xf0 - 8002374: 687b ldr r3, [r7, #4] - 8002376: 689b ldr r3, [r3, #8] - 8002378: 494d ldr r1, [pc, #308] ; (80024b0 ) - 800237a: 4313 orrs r3, r2 - 800237c: 608b str r3, [r1, #8] + 8003018: 4b50 ldr r3, [pc, #320] ; (800315c ) + 800301a: 689b ldr r3, [r3, #8] + 800301c: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 8003020: 687b ldr r3, [r7, #4] + 8003022: 689b ldr r3, [r3, #8] + 8003024: 494d ldr r1, [pc, #308] ; (800315c ) + 8003026: 4313 orrs r3, r2 + 8003028: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - 800237e: 687b ldr r3, [r7, #4] - 8002380: 681b ldr r3, [r3, #0] - 8002382: f003 0301 and.w r3, r3, #1 - 8002386: 2b00 cmp r3, #0 - 8002388: d040 beq.n 800240c + 800302a: 687b ldr r3, [r7, #4] + 800302c: 681b ldr r3, [r3, #0] + 800302e: f003 0301 and.w r3, r3, #1 + 8003032: 2b00 cmp r3, #0 + 8003034: d040 beq.n 80030b8 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - 800238a: 687b ldr r3, [r7, #4] - 800238c: 685b ldr r3, [r3, #4] - 800238e: 2b01 cmp r3, #1 - 8002390: d107 bne.n 80023a2 + 8003036: 687b ldr r3, [r7, #4] + 8003038: 685b ldr r3, [r3, #4] + 800303a: 2b01 cmp r3, #1 + 800303c: d107 bne.n 800304e { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 8002392: 4b47 ldr r3, [pc, #284] ; (80024b0 ) - 8002394: 681b ldr r3, [r3, #0] - 8002396: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 800239a: 2b00 cmp r3, #0 - 800239c: d115 bne.n 80023ca + 800303e: 4b47 ldr r3, [pc, #284] ; (800315c ) + 8003040: 681b ldr r3, [r3, #0] + 8003042: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8003046: 2b00 cmp r3, #0 + 8003048: d115 bne.n 8003076 { return HAL_ERROR; - 800239e: 2301 movs r3, #1 - 80023a0: e07f b.n 80024a2 + 800304a: 2301 movs r3, #1 + 800304c: e07f b.n 800314e } } /* PLL is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - 80023a2: 687b ldr r3, [r7, #4] - 80023a4: 685b ldr r3, [r3, #4] - 80023a6: 2b02 cmp r3, #2 - 80023a8: d107 bne.n 80023ba + 800304e: 687b ldr r3, [r7, #4] + 8003050: 685b ldr r3, [r3, #4] + 8003052: 2b02 cmp r3, #2 + 8003054: d107 bne.n 8003066 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 80023aa: 4b41 ldr r3, [pc, #260] ; (80024b0 ) - 80023ac: 681b ldr r3, [r3, #0] - 80023ae: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 80023b2: 2b00 cmp r3, #0 - 80023b4: d109 bne.n 80023ca + 8003056: 4b41 ldr r3, [pc, #260] ; (800315c ) + 8003058: 681b ldr r3, [r3, #0] + 800305a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 800305e: 2b00 cmp r3, #0 + 8003060: d109 bne.n 8003076 { return HAL_ERROR; - 80023b6: 2301 movs r3, #1 - 80023b8: e073 b.n 80024a2 + 8003062: 2301 movs r3, #1 + 8003064: e073 b.n 800314e } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 80023ba: 4b3d ldr r3, [pc, #244] ; (80024b0 ) - 80023bc: 681b ldr r3, [r3, #0] - 80023be: f003 0302 and.w r3, r3, #2 - 80023c2: 2b00 cmp r3, #0 - 80023c4: d101 bne.n 80023ca + 8003066: 4b3d ldr r3, [pc, #244] ; (800315c ) + 8003068: 681b ldr r3, [r3, #0] + 800306a: f003 0302 and.w r3, r3, #2 + 800306e: 2b00 cmp r3, #0 + 8003070: d101 bne.n 8003076 { return HAL_ERROR; - 80023c6: 2301 movs r3, #1 - 80023c8: e06b b.n 80024a2 + 8003072: 2301 movs r3, #1 + 8003074: e06b b.n 800314e } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - 80023ca: 4b39 ldr r3, [pc, #228] ; (80024b0 ) - 80023cc: 689b ldr r3, [r3, #8] - 80023ce: f023 0203 bic.w r2, r3, #3 - 80023d2: 687b ldr r3, [r7, #4] - 80023d4: 685b ldr r3, [r3, #4] - 80023d6: 4936 ldr r1, [pc, #216] ; (80024b0 ) - 80023d8: 4313 orrs r3, r2 - 80023da: 608b str r3, [r1, #8] + 8003076: 4b39 ldr r3, [pc, #228] ; (800315c ) + 8003078: 689b ldr r3, [r3, #8] + 800307a: f023 0203 bic.w r2, r3, #3 + 800307e: 687b ldr r3, [r7, #4] + 8003080: 685b ldr r3, [r3, #4] + 8003082: 4936 ldr r1, [pc, #216] ; (800315c ) + 8003084: 4313 orrs r3, r2 + 8003086: 608b str r3, [r1, #8] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 80023dc: f7fe ff30 bl 8001240 - 80023e0: 60f8 str r0, [r7, #12] + 8003088: f7fe fd32 bl 8001af0 + 800308c: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 80023e2: e00a b.n 80023fa + 800308e: e00a b.n 80030a6 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - 80023e4: f7fe ff2c bl 8001240 - 80023e8: 4602 mov r2, r0 - 80023ea: 68fb ldr r3, [r7, #12] - 80023ec: 1ad3 subs r3, r2, r3 - 80023ee: f241 3288 movw r2, #5000 ; 0x1388 - 80023f2: 4293 cmp r3, r2 - 80023f4: d901 bls.n 80023fa + 8003090: f7fe fd2e bl 8001af0 + 8003094: 4602 mov r2, r0 + 8003096: 68fb ldr r3, [r7, #12] + 8003098: 1ad3 subs r3, r2, r3 + 800309a: f241 3288 movw r2, #5000 ; 0x1388 + 800309e: 4293 cmp r3, r2 + 80030a0: d901 bls.n 80030a6 { return HAL_TIMEOUT; - 80023f6: 2303 movs r3, #3 - 80023f8: e053 b.n 80024a2 + 80030a2: 2303 movs r3, #3 + 80030a4: e053 b.n 800314e while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 80023fa: 4b2d ldr r3, [pc, #180] ; (80024b0 ) - 80023fc: 689b ldr r3, [r3, #8] - 80023fe: f003 020c and.w r2, r3, #12 - 8002402: 687b ldr r3, [r7, #4] - 8002404: 685b ldr r3, [r3, #4] - 8002406: 009b lsls r3, r3, #2 - 8002408: 429a cmp r2, r3 - 800240a: d1eb bne.n 80023e4 + 80030a6: 4b2d ldr r3, [pc, #180] ; (800315c ) + 80030a8: 689b ldr r3, [r3, #8] + 80030aa: f003 020c and.w r2, r3, #12 + 80030ae: 687b ldr r3, [r7, #4] + 80030b0: 685b ldr r3, [r3, #4] + 80030b2: 009b lsls r3, r3, #2 + 80030b4: 429a cmp r2, r3 + 80030b6: d1eb bne.n 8003090 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) - 800240c: 4b27 ldr r3, [pc, #156] ; (80024ac ) - 800240e: 681b ldr r3, [r3, #0] - 8002410: f003 030f and.w r3, r3, #15 - 8002414: 683a ldr r2, [r7, #0] - 8002416: 429a cmp r2, r3 - 8002418: d210 bcs.n 800243c + 80030b8: 4b27 ldr r3, [pc, #156] ; (8003158 ) + 80030ba: 681b ldr r3, [r3, #0] + 80030bc: f003 030f and.w r3, r3, #15 + 80030c0: 683a ldr r2, [r7, #0] + 80030c2: 429a cmp r2, r3 + 80030c4: d210 bcs.n 80030e8 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 800241a: 4b24 ldr r3, [pc, #144] ; (80024ac ) - 800241c: 681b ldr r3, [r3, #0] - 800241e: f023 020f bic.w r2, r3, #15 - 8002422: 4922 ldr r1, [pc, #136] ; (80024ac ) - 8002424: 683b ldr r3, [r7, #0] - 8002426: 4313 orrs r3, r2 - 8002428: 600b str r3, [r1, #0] + 80030c6: 4b24 ldr r3, [pc, #144] ; (8003158 ) + 80030c8: 681b ldr r3, [r3, #0] + 80030ca: f023 020f bic.w r2, r3, #15 + 80030ce: 4922 ldr r1, [pc, #136] ; (8003158 ) + 80030d0: 683b ldr r3, [r7, #0] + 80030d2: 4313 orrs r3, r2 + 80030d4: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) - 800242a: 4b20 ldr r3, [pc, #128] ; (80024ac ) - 800242c: 681b ldr r3, [r3, #0] - 800242e: f003 030f and.w r3, r3, #15 - 8002432: 683a ldr r2, [r7, #0] - 8002434: 429a cmp r2, r3 - 8002436: d001 beq.n 800243c + 80030d6: 4b20 ldr r3, [pc, #128] ; (8003158 ) + 80030d8: 681b ldr r3, [r3, #0] + 80030da: f003 030f and.w r3, r3, #15 + 80030de: 683a ldr r2, [r7, #0] + 80030e0: 429a cmp r2, r3 + 80030e2: d001 beq.n 80030e8 { return HAL_ERROR; - 8002438: 2301 movs r3, #1 - 800243a: e032 b.n 80024a2 + 80030e4: 2301 movs r3, #1 + 80030e6: e032 b.n 800314e } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 800243c: 687b ldr r3, [r7, #4] - 800243e: 681b ldr r3, [r3, #0] - 8002440: f003 0304 and.w r3, r3, #4 - 8002444: 2b00 cmp r3, #0 - 8002446: d008 beq.n 800245a + 80030e8: 687b ldr r3, [r7, #4] + 80030ea: 681b ldr r3, [r3, #0] + 80030ec: f003 0304 and.w r3, r3, #4 + 80030f0: 2b00 cmp r3, #0 + 80030f2: d008 beq.n 8003106 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); - 8002448: 4b19 ldr r3, [pc, #100] ; (80024b0 ) - 800244a: 689b ldr r3, [r3, #8] - 800244c: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 - 8002450: 687b ldr r3, [r7, #4] - 8002452: 68db ldr r3, [r3, #12] - 8002454: 4916 ldr r1, [pc, #88] ; (80024b0 ) - 8002456: 4313 orrs r3, r2 - 8002458: 608b str r3, [r1, #8] + 80030f4: 4b19 ldr r3, [pc, #100] ; (800315c ) + 80030f6: 689b ldr r3, [r3, #8] + 80030f8: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 + 80030fc: 687b ldr r3, [r7, #4] + 80030fe: 68db ldr r3, [r3, #12] + 8003100: 4916 ldr r1, [pc, #88] ; (800315c ) + 8003102: 4313 orrs r3, r2 + 8003104: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - 800245a: 687b ldr r3, [r7, #4] - 800245c: 681b ldr r3, [r3, #0] - 800245e: f003 0308 and.w r3, r3, #8 - 8002462: 2b00 cmp r3, #0 - 8002464: d009 beq.n 800247a + 8003106: 687b ldr r3, [r7, #4] + 8003108: 681b ldr r3, [r3, #0] + 800310a: f003 0308 and.w r3, r3, #8 + 800310e: 2b00 cmp r3, #0 + 8003110: d009 beq.n 8003126 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); - 8002466: 4b12 ldr r3, [pc, #72] ; (80024b0 ) - 8002468: 689b ldr r3, [r3, #8] - 800246a: f423 4260 bic.w r2, r3, #57344 ; 0xe000 - 800246e: 687b ldr r3, [r7, #4] - 8002470: 691b ldr r3, [r3, #16] - 8002472: 00db lsls r3, r3, #3 - 8002474: 490e ldr r1, [pc, #56] ; (80024b0 ) - 8002476: 4313 orrs r3, r2 - 8002478: 608b str r3, [r1, #8] + 8003112: 4b12 ldr r3, [pc, #72] ; (800315c ) + 8003114: 689b ldr r3, [r3, #8] + 8003116: f423 4260 bic.w r2, r3, #57344 ; 0xe000 + 800311a: 687b ldr r3, [r7, #4] + 800311c: 691b ldr r3, [r3, #16] + 800311e: 00db lsls r3, r3, #3 + 8003120: 490e ldr r1, [pc, #56] ; (800315c ) + 8003122: 4313 orrs r3, r2 + 8003124: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; - 800247a: f000 f821 bl 80024c0 - 800247e: 4602 mov r2, r0 - 8002480: 4b0b ldr r3, [pc, #44] ; (80024b0 ) - 8002482: 689b ldr r3, [r3, #8] - 8002484: 091b lsrs r3, r3, #4 - 8002486: f003 030f and.w r3, r3, #15 - 800248a: 490a ldr r1, [pc, #40] ; (80024b4 ) - 800248c: 5ccb ldrb r3, [r1, r3] - 800248e: fa22 f303 lsr.w r3, r2, r3 - 8002492: 4a09 ldr r2, [pc, #36] ; (80024b8 ) - 8002494: 6013 str r3, [r2, #0] + 8003126: f000 f821 bl 800316c + 800312a: 4602 mov r2, r0 + 800312c: 4b0b ldr r3, [pc, #44] ; (800315c ) + 800312e: 689b ldr r3, [r3, #8] + 8003130: 091b lsrs r3, r3, #4 + 8003132: f003 030f and.w r3, r3, #15 + 8003136: 490a ldr r1, [pc, #40] ; (8003160 ) + 8003138: 5ccb ldrb r3, [r1, r3] + 800313a: fa22 f303 lsr.w r3, r2, r3 + 800313e: 4a09 ldr r2, [pc, #36] ; (8003164 ) + 8003140: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick(uwTickPrio); - 8002496: 4b09 ldr r3, [pc, #36] ; (80024bc ) - 8002498: 681b ldr r3, [r3, #0] - 800249a: 4618 mov r0, r3 - 800249c: f7fe fe8c bl 80011b8 + 8003142: 4b09 ldr r3, [pc, #36] ; (8003168 ) + 8003144: 681b ldr r3, [r3, #0] + 8003146: 4618 mov r0, r3 + 8003148: f7fe fc8e bl 8001a68 return HAL_OK; - 80024a0: 2300 movs r3, #0 + 800314c: 2300 movs r3, #0 } - 80024a2: 4618 mov r0, r3 - 80024a4: 3710 adds r7, #16 - 80024a6: 46bd mov sp, r7 - 80024a8: bd80 pop {r7, pc} - 80024aa: bf00 nop - 80024ac: 40023c00 .word 0x40023c00 - 80024b0: 40023800 .word 0x40023800 - 80024b4: 08004bfc .word 0x08004bfc - 80024b8: 20000000 .word 0x20000000 - 80024bc: 20000004 .word 0x20000004 - -080024c0 : + 800314e: 4618 mov r0, r3 + 8003150: 3710 adds r7, #16 + 8003152: 46bd mov sp, r7 + 8003154: bd80 pop {r7, pc} + 8003156: bf00 nop + 8003158: 40023c00 .word 0x40023c00 + 800315c: 40023800 .word 0x40023800 + 8003160: 08005b04 .word 0x08005b04 + 8003164: 20000004 .word 0x20000004 + 8003168: 20000008 .word 0x20000008 + +0800316c : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { - 80024c0: b5b0 push {r4, r5, r7, lr} - 80024c2: b084 sub sp, #16 - 80024c4: af00 add r7, sp, #0 + 800316c: b5b0 push {r4, r5, r7, lr} + 800316e: b084 sub sp, #16 + 8003170: af00 add r7, sp, #0 uint32_t pllm = 0, pllvco = 0, pllp = 0; - 80024c6: 2100 movs r1, #0 - 80024c8: 6079 str r1, [r7, #4] - 80024ca: 2100 movs r1, #0 - 80024cc: 60f9 str r1, [r7, #12] - 80024ce: 2100 movs r1, #0 - 80024d0: 6039 str r1, [r7, #0] + 8003172: 2100 movs r1, #0 + 8003174: 6079 str r1, [r7, #4] + 8003176: 2100 movs r1, #0 + 8003178: 60f9 str r1, [r7, #12] + 800317a: 2100 movs r1, #0 + 800317c: 6039 str r1, [r7, #0] uint32_t sysclockfreq = 0; - 80024d2: 2100 movs r1, #0 - 80024d4: 60b9 str r1, [r7, #8] + 800317e: 2100 movs r1, #0 + 8003180: 60b9 str r1, [r7, #8] /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) - 80024d6: 4952 ldr r1, [pc, #328] ; (8002620 ) - 80024d8: 6889 ldr r1, [r1, #8] - 80024da: f001 010c and.w r1, r1, #12 - 80024de: 2908 cmp r1, #8 - 80024e0: d00d beq.n 80024fe - 80024e2: 2908 cmp r1, #8 - 80024e4: f200 8094 bhi.w 8002610 - 80024e8: 2900 cmp r1, #0 - 80024ea: d002 beq.n 80024f2 - 80024ec: 2904 cmp r1, #4 - 80024ee: d003 beq.n 80024f8 - 80024f0: e08e b.n 8002610 + 8003182: 4952 ldr r1, [pc, #328] ; (80032cc ) + 8003184: 6889 ldr r1, [r1, #8] + 8003186: f001 010c and.w r1, r1, #12 + 800318a: 2908 cmp r1, #8 + 800318c: d00d beq.n 80031aa + 800318e: 2908 cmp r1, #8 + 8003190: f200 8094 bhi.w 80032bc + 8003194: 2900 cmp r1, #0 + 8003196: d002 beq.n 800319e + 8003198: 2904 cmp r1, #4 + 800319a: d003 beq.n 80031a4 + 800319c: e08e b.n 80032bc { case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; - 80024f2: 4b4c ldr r3, [pc, #304] ; (8002624 ) - 80024f4: 60bb str r3, [r7, #8] + 800319e: 4b4c ldr r3, [pc, #304] ; (80032d0 ) + 80031a0: 60bb str r3, [r7, #8] break; - 80024f6: e08e b.n 8002616 + 80031a2: e08e b.n 80032c2 } case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ { sysclockfreq = HSE_VALUE; - 80024f8: 4b4b ldr r3, [pc, #300] ; (8002628 ) - 80024fa: 60bb str r3, [r7, #8] + 80031a4: 4b4b ldr r3, [pc, #300] ; (80032d4 ) + 80031a6: 60bb str r3, [r7, #8] break; - 80024fc: e08b b.n 8002616 + 80031a8: e08b b.n 80032c2 } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - 80024fe: 4948 ldr r1, [pc, #288] ; (8002620 ) - 8002500: 6849 ldr r1, [r1, #4] - 8002502: f001 013f and.w r1, r1, #63 ; 0x3f - 8002506: 6079 str r1, [r7, #4] + 80031aa: 4948 ldr r1, [pc, #288] ; (80032cc ) + 80031ac: 6849 ldr r1, [r1, #4] + 80031ae: f001 013f and.w r1, r1, #63 ; 0x3f + 80031b2: 6079 str r1, [r7, #4] if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI) - 8002508: 4945 ldr r1, [pc, #276] ; (8002620 ) - 800250a: 6849 ldr r1, [r1, #4] - 800250c: f401 0180 and.w r1, r1, #4194304 ; 0x400000 - 8002510: 2900 cmp r1, #0 - 8002512: d024 beq.n 800255e + 80031b4: 4945 ldr r1, [pc, #276] ; (80032cc ) + 80031b6: 6849 ldr r1, [r1, #4] + 80031b8: f401 0180 and.w r1, r1, #4194304 ; 0x400000 + 80031bc: 2900 cmp r1, #0 + 80031be: d024 beq.n 800320a { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); - 8002514: 4942 ldr r1, [pc, #264] ; (8002620 ) - 8002516: 6849 ldr r1, [r1, #4] - 8002518: 0989 lsrs r1, r1, #6 - 800251a: 4608 mov r0, r1 - 800251c: f04f 0100 mov.w r1, #0 - 8002520: f240 14ff movw r4, #511 ; 0x1ff - 8002524: f04f 0500 mov.w r5, #0 - 8002528: ea00 0204 and.w r2, r0, r4 - 800252c: ea01 0305 and.w r3, r1, r5 - 8002530: 493d ldr r1, [pc, #244] ; (8002628 ) - 8002532: fb01 f003 mul.w r0, r1, r3 - 8002536: 2100 movs r1, #0 - 8002538: fb01 f102 mul.w r1, r1, r2 - 800253c: 1844 adds r4, r0, r1 - 800253e: 493a ldr r1, [pc, #232] ; (8002628 ) - 8002540: fba2 0101 umull r0, r1, r2, r1 - 8002544: 1863 adds r3, r4, r1 - 8002546: 4619 mov r1, r3 - 8002548: 687b ldr r3, [r7, #4] - 800254a: 461a mov r2, r3 - 800254c: f04f 0300 mov.w r3, #0 - 8002550: f7fd fec6 bl 80002e0 <__aeabi_uldivmod> - 8002554: 4602 mov r2, r0 - 8002556: 460b mov r3, r1 - 8002558: 4613 mov r3, r2 - 800255a: 60fb str r3, [r7, #12] - 800255c: e04a b.n 80025f4 + 80031c0: 4942 ldr r1, [pc, #264] ; (80032cc ) + 80031c2: 6849 ldr r1, [r1, #4] + 80031c4: 0989 lsrs r1, r1, #6 + 80031c6: 4608 mov r0, r1 + 80031c8: f04f 0100 mov.w r1, #0 + 80031cc: f240 14ff movw r4, #511 ; 0x1ff + 80031d0: f04f 0500 mov.w r5, #0 + 80031d4: ea00 0204 and.w r2, r0, r4 + 80031d8: ea01 0305 and.w r3, r1, r5 + 80031dc: 493d ldr r1, [pc, #244] ; (80032d4 ) + 80031de: fb01 f003 mul.w r0, r1, r3 + 80031e2: 2100 movs r1, #0 + 80031e4: fb01 f102 mul.w r1, r1, r2 + 80031e8: 1844 adds r4, r0, r1 + 80031ea: 493a ldr r1, [pc, #232] ; (80032d4 ) + 80031ec: fba2 0101 umull r0, r1, r2, r1 + 80031f0: 1863 adds r3, r4, r1 + 80031f2: 4619 mov r1, r3 + 80031f4: 687b ldr r3, [r7, #4] + 80031f6: 461a mov r2, r3 + 80031f8: f04f 0300 mov.w r3, #0 + 80031fc: f7fd f870 bl 80002e0 <__aeabi_uldivmod> + 8003200: 4602 mov r2, r0 + 8003202: 460b mov r3, r1 + 8003204: 4613 mov r3, r2 + 8003206: 60fb str r3, [r7, #12] + 8003208: e04a b.n 80032a0 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); - 800255e: 4b30 ldr r3, [pc, #192] ; (8002620 ) - 8002560: 685b ldr r3, [r3, #4] - 8002562: 099b lsrs r3, r3, #6 - 8002564: 461a mov r2, r3 - 8002566: f04f 0300 mov.w r3, #0 - 800256a: f240 10ff movw r0, #511 ; 0x1ff - 800256e: f04f 0100 mov.w r1, #0 - 8002572: ea02 0400 and.w r4, r2, r0 - 8002576: ea03 0501 and.w r5, r3, r1 - 800257a: 4620 mov r0, r4 - 800257c: 4629 mov r1, r5 - 800257e: f04f 0200 mov.w r2, #0 - 8002582: f04f 0300 mov.w r3, #0 - 8002586: 014b lsls r3, r1, #5 - 8002588: ea43 63d0 orr.w r3, r3, r0, lsr #27 - 800258c: 0142 lsls r2, r0, #5 - 800258e: 4610 mov r0, r2 - 8002590: 4619 mov r1, r3 - 8002592: 1b00 subs r0, r0, r4 - 8002594: eb61 0105 sbc.w r1, r1, r5 - 8002598: f04f 0200 mov.w r2, #0 - 800259c: f04f 0300 mov.w r3, #0 - 80025a0: 018b lsls r3, r1, #6 - 80025a2: ea43 6390 orr.w r3, r3, r0, lsr #26 - 80025a6: 0182 lsls r2, r0, #6 - 80025a8: 1a12 subs r2, r2, r0 - 80025aa: eb63 0301 sbc.w r3, r3, r1 - 80025ae: f04f 0000 mov.w r0, #0 - 80025b2: f04f 0100 mov.w r1, #0 - 80025b6: 00d9 lsls r1, r3, #3 - 80025b8: ea41 7152 orr.w r1, r1, r2, lsr #29 - 80025bc: 00d0 lsls r0, r2, #3 - 80025be: 4602 mov r2, r0 - 80025c0: 460b mov r3, r1 - 80025c2: 1912 adds r2, r2, r4 - 80025c4: eb45 0303 adc.w r3, r5, r3 - 80025c8: f04f 0000 mov.w r0, #0 - 80025cc: f04f 0100 mov.w r1, #0 - 80025d0: 0299 lsls r1, r3, #10 - 80025d2: ea41 5192 orr.w r1, r1, r2, lsr #22 - 80025d6: 0290 lsls r0, r2, #10 - 80025d8: 4602 mov r2, r0 - 80025da: 460b mov r3, r1 - 80025dc: 4610 mov r0, r2 - 80025de: 4619 mov r1, r3 - 80025e0: 687b ldr r3, [r7, #4] - 80025e2: 461a mov r2, r3 - 80025e4: f04f 0300 mov.w r3, #0 - 80025e8: f7fd fe7a bl 80002e0 <__aeabi_uldivmod> - 80025ec: 4602 mov r2, r0 - 80025ee: 460b mov r3, r1 - 80025f0: 4613 mov r3, r2 - 80025f2: 60fb str r3, [r7, #12] + 800320a: 4b30 ldr r3, [pc, #192] ; (80032cc ) + 800320c: 685b ldr r3, [r3, #4] + 800320e: 099b lsrs r3, r3, #6 + 8003210: 461a mov r2, r3 + 8003212: f04f 0300 mov.w r3, #0 + 8003216: f240 10ff movw r0, #511 ; 0x1ff + 800321a: f04f 0100 mov.w r1, #0 + 800321e: ea02 0400 and.w r4, r2, r0 + 8003222: ea03 0501 and.w r5, r3, r1 + 8003226: 4620 mov r0, r4 + 8003228: 4629 mov r1, r5 + 800322a: f04f 0200 mov.w r2, #0 + 800322e: f04f 0300 mov.w r3, #0 + 8003232: 014b lsls r3, r1, #5 + 8003234: ea43 63d0 orr.w r3, r3, r0, lsr #27 + 8003238: 0142 lsls r2, r0, #5 + 800323a: 4610 mov r0, r2 + 800323c: 4619 mov r1, r3 + 800323e: 1b00 subs r0, r0, r4 + 8003240: eb61 0105 sbc.w r1, r1, r5 + 8003244: f04f 0200 mov.w r2, #0 + 8003248: f04f 0300 mov.w r3, #0 + 800324c: 018b lsls r3, r1, #6 + 800324e: ea43 6390 orr.w r3, r3, r0, lsr #26 + 8003252: 0182 lsls r2, r0, #6 + 8003254: 1a12 subs r2, r2, r0 + 8003256: eb63 0301 sbc.w r3, r3, r1 + 800325a: f04f 0000 mov.w r0, #0 + 800325e: f04f 0100 mov.w r1, #0 + 8003262: 00d9 lsls r1, r3, #3 + 8003264: ea41 7152 orr.w r1, r1, r2, lsr #29 + 8003268: 00d0 lsls r0, r2, #3 + 800326a: 4602 mov r2, r0 + 800326c: 460b mov r3, r1 + 800326e: 1912 adds r2, r2, r4 + 8003270: eb45 0303 adc.w r3, r5, r3 + 8003274: f04f 0000 mov.w r0, #0 + 8003278: f04f 0100 mov.w r1, #0 + 800327c: 0299 lsls r1, r3, #10 + 800327e: ea41 5192 orr.w r1, r1, r2, lsr #22 + 8003282: 0290 lsls r0, r2, #10 + 8003284: 4602 mov r2, r0 + 8003286: 460b mov r3, r1 + 8003288: 4610 mov r0, r2 + 800328a: 4619 mov r1, r3 + 800328c: 687b ldr r3, [r7, #4] + 800328e: 461a mov r2, r3 + 8003290: f04f 0300 mov.w r3, #0 + 8003294: f7fd f824 bl 80002e0 <__aeabi_uldivmod> + 8003298: 4602 mov r2, r0 + 800329a: 460b mov r3, r1 + 800329c: 4613 mov r3, r2 + 800329e: 60fb str r3, [r7, #12] } pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2); - 80025f4: 4b0a ldr r3, [pc, #40] ; (8002620 ) - 80025f6: 685b ldr r3, [r3, #4] - 80025f8: 0c1b lsrs r3, r3, #16 - 80025fa: f003 0303 and.w r3, r3, #3 - 80025fe: 3301 adds r3, #1 - 8002600: 005b lsls r3, r3, #1 - 8002602: 603b str r3, [r7, #0] + 80032a0: 4b0a ldr r3, [pc, #40] ; (80032cc ) + 80032a2: 685b ldr r3, [r3, #4] + 80032a4: 0c1b lsrs r3, r3, #16 + 80032a6: f003 0303 and.w r3, r3, #3 + 80032aa: 3301 adds r3, #1 + 80032ac: 005b lsls r3, r3, #1 + 80032ae: 603b str r3, [r7, #0] sysclockfreq = pllvco / pllp; - 8002604: 68fa ldr r2, [r7, #12] - 8002606: 683b ldr r3, [r7, #0] - 8002608: fbb2 f3f3 udiv r3, r2, r3 - 800260c: 60bb str r3, [r7, #8] + 80032b0: 68fa ldr r2, [r7, #12] + 80032b2: 683b ldr r3, [r7, #0] + 80032b4: fbb2 f3f3 udiv r3, r2, r3 + 80032b8: 60bb str r3, [r7, #8] break; - 800260e: e002 b.n 8002616 + 80032ba: e002 b.n 80032c2 } default: { sysclockfreq = HSI_VALUE; - 8002610: 4b04 ldr r3, [pc, #16] ; (8002624 ) - 8002612: 60bb str r3, [r7, #8] + 80032bc: 4b04 ldr r3, [pc, #16] ; (80032d0 ) + 80032be: 60bb str r3, [r7, #8] break; - 8002614: bf00 nop + 80032c0: bf00 nop } } return sysclockfreq; - 8002616: 68bb ldr r3, [r7, #8] + 80032c2: 68bb ldr r3, [r7, #8] } - 8002618: 4618 mov r0, r3 - 800261a: 3710 adds r7, #16 - 800261c: 46bd mov sp, r7 - 800261e: bdb0 pop {r4, r5, r7, pc} - 8002620: 40023800 .word 0x40023800 - 8002624: 00f42400 .word 0x00f42400 - 8002628: 017d7840 .word 0x017d7840 - -0800262c : + 80032c4: 4618 mov r0, r3 + 80032c6: 3710 adds r7, #16 + 80032c8: 46bd mov sp, r7 + 80032ca: bdb0 pop {r4, r5, r7, pc} + 80032cc: 40023800 .word 0x40023800 + 80032d0: 00f42400 .word 0x00f42400 + 80032d4: 017d7840 .word 0x017d7840 + +080032d8 : * right HCLK value. Otherwise, any configuration based on this function will be incorrect. * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { - 800262c: b480 push {r7} - 800262e: af00 add r7, sp, #0 + 80032d8: b480 push {r7} + 80032da: af00 add r7, sp, #0 return SystemCoreClock; - 8002630: 4b03 ldr r3, [pc, #12] ; (8002640 ) - 8002632: 681b ldr r3, [r3, #0] + 80032dc: 4b03 ldr r3, [pc, #12] ; (80032ec ) + 80032de: 681b ldr r3, [r3, #0] } - 8002634: 4618 mov r0, r3 - 8002636: 46bd mov sp, r7 - 8002638: f85d 7b04 ldr.w r7, [sp], #4 - 800263c: 4770 bx lr - 800263e: bf00 nop - 8002640: 20000000 .word 0x20000000 - -08002644 : + 80032e0: 4618 mov r0, r3 + 80032e2: 46bd mov sp, r7 + 80032e4: f85d 7b04 ldr.w r7, [sp], #4 + 80032e8: 4770 bx lr + 80032ea: bf00 nop + 80032ec: 20000004 .word 0x20000004 + +080032f0 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { - 8002644: b580 push {r7, lr} - 8002646: af00 add r7, sp, #0 + 80032f0: b580 push {r7, lr} + 80032f2: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); - 8002648: f7ff fff0 bl 800262c - 800264c: 4602 mov r2, r0 - 800264e: 4b05 ldr r3, [pc, #20] ; (8002664 ) - 8002650: 689b ldr r3, [r3, #8] - 8002652: 0a9b lsrs r3, r3, #10 - 8002654: f003 0307 and.w r3, r3, #7 - 8002658: 4903 ldr r1, [pc, #12] ; (8002668 ) - 800265a: 5ccb ldrb r3, [r1, r3] - 800265c: fa22 f303 lsr.w r3, r2, r3 + 80032f4: f7ff fff0 bl 80032d8 + 80032f8: 4602 mov r2, r0 + 80032fa: 4b05 ldr r3, [pc, #20] ; (8003310 ) + 80032fc: 689b ldr r3, [r3, #8] + 80032fe: 0a9b lsrs r3, r3, #10 + 8003300: f003 0307 and.w r3, r3, #7 + 8003304: 4903 ldr r1, [pc, #12] ; (8003314 ) + 8003306: 5ccb ldrb r3, [r1, r3] + 8003308: fa22 f303 lsr.w r3, r2, r3 } - 8002660: 4618 mov r0, r3 - 8002662: bd80 pop {r7, pc} - 8002664: 40023800 .word 0x40023800 - 8002668: 08004c0c .word 0x08004c0c + 800330c: 4618 mov r0, r3 + 800330e: bd80 pop {r7, pc} + 8003310: 40023800 .word 0x40023800 + 8003314: 08005b14 .word 0x08005b14 -0800266c : +08003318 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { - 800266c: b580 push {r7, lr} - 800266e: af00 add r7, sp, #0 + 8003318: b580 push {r7, lr} + 800331a: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); - 8002670: f7ff ffdc bl 800262c - 8002674: 4602 mov r2, r0 - 8002676: 4b05 ldr r3, [pc, #20] ; (800268c ) - 8002678: 689b ldr r3, [r3, #8] - 800267a: 0b5b lsrs r3, r3, #13 - 800267c: f003 0307 and.w r3, r3, #7 - 8002680: 4903 ldr r1, [pc, #12] ; (8002690 ) - 8002682: 5ccb ldrb r3, [r1, r3] - 8002684: fa22 f303 lsr.w r3, r2, r3 + 800331c: f7ff ffdc bl 80032d8 + 8003320: 4602 mov r2, r0 + 8003322: 4b05 ldr r3, [pc, #20] ; (8003338 ) + 8003324: 689b ldr r3, [r3, #8] + 8003326: 0b5b lsrs r3, r3, #13 + 8003328: f003 0307 and.w r3, r3, #7 + 800332c: 4903 ldr r1, [pc, #12] ; (800333c ) + 800332e: 5ccb ldrb r3, [r1, r3] + 8003330: fa22 f303 lsr.w r3, r2, r3 } - 8002688: 4618 mov r0, r3 - 800268a: bd80 pop {r7, pc} - 800268c: 40023800 .word 0x40023800 - 8002690: 08004c0c .word 0x08004c0c + 8003334: 4618 mov r0, r3 + 8003336: bd80 pop {r7, pc} + 8003338: 40023800 .word 0x40023800 + 800333c: 08005b14 .word 0x08005b14 -08002694 : +08003340 : * the backup registers) are set to their reset values. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { - 8002694: b580 push {r7, lr} - 8002696: b088 sub sp, #32 - 8002698: af00 add r7, sp, #0 - 800269a: 6078 str r0, [r7, #4] + 8003340: b580 push {r7, lr} + 8003342: b088 sub sp, #32 + 8003344: af00 add r7, sp, #0 + 8003346: 6078 str r0, [r7, #4] uint32_t tickstart = 0; - 800269c: 2300 movs r3, #0 - 800269e: 617b str r3, [r7, #20] + 8003348: 2300 movs r3, #0 + 800334a: 617b str r3, [r7, #20] uint32_t tmpreg0 = 0; - 80026a0: 2300 movs r3, #0 - 80026a2: 613b str r3, [r7, #16] + 800334c: 2300 movs r3, #0 + 800334e: 613b str r3, [r7, #16] uint32_t tmpreg1 = 0; - 80026a4: 2300 movs r3, #0 - 80026a6: 60fb str r3, [r7, #12] + 8003350: 2300 movs r3, #0 + 8003352: 60fb str r3, [r7, #12] uint32_t plli2sused = 0; - 80026a8: 2300 movs r3, #0 - 80026aa: 61fb str r3, [r7, #28] + 8003354: 2300 movs r3, #0 + 8003356: 61fb str r3, [r7, #28] uint32_t pllsaiused = 0; - 80026ac: 2300 movs r3, #0 - 80026ae: 61bb str r3, [r7, #24] + 8003358: 2300 movs r3, #0 + 800335a: 61bb str r3, [r7, #24] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*----------------------------------- I2S configuration ----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) - 80026b0: 687b ldr r3, [r7, #4] - 80026b2: 681b ldr r3, [r3, #0] - 80026b4: f003 0301 and.w r3, r3, #1 - 80026b8: 2b00 cmp r3, #0 - 80026ba: d012 beq.n 80026e2 + 800335c: 687b ldr r3, [r7, #4] + 800335e: 681b ldr r3, [r3, #0] + 8003360: f003 0301 and.w r3, r3, #1 + 8003364: 2b00 cmp r3, #0 + 8003366: d012 beq.n 800338e { /* Check the parameters */ assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); /* Configure I2S Clock source */ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); - 80026bc: 4b69 ldr r3, [pc, #420] ; (8002864 ) - 80026be: 689b ldr r3, [r3, #8] - 80026c0: 4a68 ldr r2, [pc, #416] ; (8002864 ) - 80026c2: f423 0300 bic.w r3, r3, #8388608 ; 0x800000 - 80026c6: 6093 str r3, [r2, #8] - 80026c8: 4b66 ldr r3, [pc, #408] ; (8002864 ) - 80026ca: 689a ldr r2, [r3, #8] - 80026cc: 687b ldr r3, [r7, #4] - 80026ce: 6b5b ldr r3, [r3, #52] ; 0x34 - 80026d0: 4964 ldr r1, [pc, #400] ; (8002864 ) - 80026d2: 4313 orrs r3, r2 - 80026d4: 608b str r3, [r1, #8] + 8003368: 4b69 ldr r3, [pc, #420] ; (8003510 ) + 800336a: 689b ldr r3, [r3, #8] + 800336c: 4a68 ldr r2, [pc, #416] ; (8003510 ) + 800336e: f423 0300 bic.w r3, r3, #8388608 ; 0x800000 + 8003372: 6093 str r3, [r2, #8] + 8003374: 4b66 ldr r3, [pc, #408] ; (8003510 ) + 8003376: 689a ldr r2, [r3, #8] + 8003378: 687b ldr r3, [r7, #4] + 800337a: 6b5b ldr r3, [r3, #52] ; 0x34 + 800337c: 4964 ldr r1, [pc, #400] ; (8003510 ) + 800337e: 4313 orrs r3, r2 + 8003380: 608b str r3, [r1, #8] /* Enable the PLLI2S when it's used as clock source for I2S */ if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) - 80026d6: 687b ldr r3, [r7, #4] - 80026d8: 6b5b ldr r3, [r3, #52] ; 0x34 - 80026da: 2b00 cmp r3, #0 - 80026dc: d101 bne.n 80026e2 + 8003382: 687b ldr r3, [r7, #4] + 8003384: 6b5b ldr r3, [r3, #52] ; 0x34 + 8003386: 2b00 cmp r3, #0 + 8003388: d101 bne.n 800338e { plli2sused = 1; - 80026de: 2301 movs r3, #1 - 80026e0: 61fb str r3, [r7, #28] + 800338a: 2301 movs r3, #1 + 800338c: 61fb str r3, [r7, #28] } } /*------------------------------------ SAI1 configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) - 80026e2: 687b ldr r3, [r7, #4] - 80026e4: 681b ldr r3, [r3, #0] - 80026e6: f403 2300 and.w r3, r3, #524288 ; 0x80000 - 80026ea: 2b00 cmp r3, #0 - 80026ec: d017 beq.n 800271e + 800338e: 687b ldr r3, [r7, #4] + 8003390: 681b ldr r3, [r3, #0] + 8003392: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 8003396: 2b00 cmp r3, #0 + 8003398: d017 beq.n 80033ca { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); /* Configure SAI1 Clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); - 80026ee: 4b5d ldr r3, [pc, #372] ; (8002864 ) - 80026f0: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c - 80026f4: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 - 80026f8: 687b ldr r3, [r7, #4] - 80026fa: 6bdb ldr r3, [r3, #60] ; 0x3c - 80026fc: 4959 ldr r1, [pc, #356] ; (8002864 ) - 80026fe: 4313 orrs r3, r2 - 8002700: f8c1 308c str.w r3, [r1, #140] ; 0x8c + 800339a: 4b5d ldr r3, [pc, #372] ; (8003510 ) + 800339c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 80033a0: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 + 80033a4: 687b ldr r3, [r7, #4] + 80033a6: 6bdb ldr r3, [r3, #60] ; 0x3c + 80033a8: 4959 ldr r1, [pc, #356] ; (8003510 ) + 80033aa: 4313 orrs r3, r2 + 80033ac: f8c1 308c str.w r3, [r1, #140] ; 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) - 8002704: 687b ldr r3, [r7, #4] - 8002706: 6bdb ldr r3, [r3, #60] ; 0x3c - 8002708: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 - 800270c: d101 bne.n 8002712 + 80033b0: 687b ldr r3, [r7, #4] + 80033b2: 6bdb ldr r3, [r3, #60] ; 0x3c + 80033b4: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 80033b8: d101 bne.n 80033be { plli2sused = 1; - 800270e: 2301 movs r3, #1 - 8002710: 61fb str r3, [r7, #28] + 80033ba: 2301 movs r3, #1 + 80033bc: 61fb str r3, [r7, #28] } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) - 8002712: 687b ldr r3, [r7, #4] - 8002714: 6bdb ldr r3, [r3, #60] ; 0x3c - 8002716: 2b00 cmp r3, #0 - 8002718: d101 bne.n 800271e + 80033be: 687b ldr r3, [r7, #4] + 80033c0: 6bdb ldr r3, [r3, #60] ; 0x3c + 80033c2: 2b00 cmp r3, #0 + 80033c4: d101 bne.n 80033ca { pllsaiused = 1; - 800271a: 2301 movs r3, #1 - 800271c: 61bb str r3, [r7, #24] + 80033c6: 2301 movs r3, #1 + 80033c8: 61bb str r3, [r7, #24] } } /*------------------------------------ SAI2 configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) - 800271e: 687b ldr r3, [r7, #4] - 8002720: 681b ldr r3, [r3, #0] - 8002722: f403 1380 and.w r3, r3, #1048576 ; 0x100000 - 8002726: 2b00 cmp r3, #0 - 8002728: d017 beq.n 800275a + 80033ca: 687b ldr r3, [r7, #4] + 80033cc: 681b ldr r3, [r3, #0] + 80033ce: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 80033d2: 2b00 cmp r3, #0 + 80033d4: d017 beq.n 8003406 { /* Check the parameters */ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); /* Configure SAI2 Clock source */ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); - 800272a: 4b4e ldr r3, [pc, #312] ; (8002864 ) - 800272c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c - 8002730: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 - 8002734: 687b ldr r3, [r7, #4] - 8002736: 6c1b ldr r3, [r3, #64] ; 0x40 - 8002738: 494a ldr r1, [pc, #296] ; (8002864 ) - 800273a: 4313 orrs r3, r2 - 800273c: f8c1 308c str.w r3, [r1, #140] ; 0x8c + 80033d6: 4b4e ldr r3, [pc, #312] ; (8003510 ) + 80033d8: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 80033dc: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 + 80033e0: 687b ldr r3, [r7, #4] + 80033e2: 6c1b ldr r3, [r3, #64] ; 0x40 + 80033e4: 494a ldr r1, [pc, #296] ; (8003510 ) + 80033e6: 4313 orrs r3, r2 + 80033e8: f8c1 308c str.w r3, [r1, #140] ; 0x8c /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) - 8002740: 687b ldr r3, [r7, #4] - 8002742: 6c1b ldr r3, [r3, #64] ; 0x40 - 8002744: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 - 8002748: d101 bne.n 800274e + 80033ec: 687b ldr r3, [r7, #4] + 80033ee: 6c1b ldr r3, [r3, #64] ; 0x40 + 80033f0: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 80033f4: d101 bne.n 80033fa { plli2sused = 1; - 800274a: 2301 movs r3, #1 - 800274c: 61fb str r3, [r7, #28] + 80033f6: 2301 movs r3, #1 + 80033f8: 61fb str r3, [r7, #28] } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) - 800274e: 687b ldr r3, [r7, #4] - 8002750: 6c1b ldr r3, [r3, #64] ; 0x40 - 8002752: 2b00 cmp r3, #0 - 8002754: d101 bne.n 800275a + 80033fa: 687b ldr r3, [r7, #4] + 80033fc: 6c1b ldr r3, [r3, #64] ; 0x40 + 80033fe: 2b00 cmp r3, #0 + 8003400: d101 bne.n 8003406 { pllsaiused = 1; - 8002756: 2301 movs r3, #1 - 8002758: 61bb str r3, [r7, #24] + 8003402: 2301 movs r3, #1 + 8003404: 61bb str r3, [r7, #24] } } /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) - 800275a: 687b ldr r3, [r7, #4] - 800275c: 681b ldr r3, [r3, #0] - 800275e: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 - 8002762: 2b00 cmp r3, #0 - 8002764: d001 beq.n 800276a + 8003406: 687b ldr r3, [r7, #4] + 8003408: 681b ldr r3, [r3, #0] + 800340a: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 800340e: 2b00 cmp r3, #0 + 8003410: d001 beq.n 8003416 { plli2sused = 1; - 8002766: 2301 movs r3, #1 - 8002768: 61fb str r3, [r7, #28] + 8003412: 2301 movs r3, #1 + 8003414: 61fb str r3, [r7, #28] } /*------------------------------------ RTC configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) - 800276a: 687b ldr r3, [r7, #4] - 800276c: 681b ldr r3, [r3, #0] - 800276e: f003 0320 and.w r3, r3, #32 - 8002772: 2b00 cmp r3, #0 - 8002774: f000 808b beq.w 800288e + 8003416: 687b ldr r3, [r7, #4] + 8003418: 681b ldr r3, [r3, #0] + 800341a: f003 0320 and.w r3, r3, #32 + 800341e: 2b00 cmp r3, #0 + 8003420: f000 808b beq.w 800353a { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - 8002778: 4b3a ldr r3, [pc, #232] ; (8002864 ) - 800277a: 6c1b ldr r3, [r3, #64] ; 0x40 - 800277c: 4a39 ldr r2, [pc, #228] ; (8002864 ) - 800277e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 8002782: 6413 str r3, [r2, #64] ; 0x40 - 8002784: 4b37 ldr r3, [pc, #220] ; (8002864 ) - 8002786: 6c1b ldr r3, [r3, #64] ; 0x40 - 8002788: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 800278c: 60bb str r3, [r7, #8] - 800278e: 68bb ldr r3, [r7, #8] + 8003424: 4b3a ldr r3, [pc, #232] ; (8003510 ) + 8003426: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003428: 4a39 ldr r2, [pc, #228] ; (8003510 ) + 800342a: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 800342e: 6413 str r3, [r2, #64] ; 0x40 + 8003430: 4b37 ldr r3, [pc, #220] ; (8003510 ) + 8003432: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003434: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8003438: 60bb str r3, [r7, #8] + 800343a: 68bb ldr r3, [r7, #8] /* Enable write access to Backup domain */ PWR->CR1 |= PWR_CR1_DBP; - 8002790: 4b35 ldr r3, [pc, #212] ; (8002868 ) - 8002792: 681b ldr r3, [r3, #0] - 8002794: 4a34 ldr r2, [pc, #208] ; (8002868 ) - 8002796: f443 7380 orr.w r3, r3, #256 ; 0x100 - 800279a: 6013 str r3, [r2, #0] + 800343c: 4b35 ldr r3, [pc, #212] ; (8003514 ) + 800343e: 681b ldr r3, [r3, #0] + 8003440: 4a34 ldr r2, [pc, #208] ; (8003514 ) + 8003442: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8003446: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 800279c: f7fe fd50 bl 8001240 - 80027a0: 6178 str r0, [r7, #20] + 8003448: f7fe fb52 bl 8001af0 + 800344c: 6178 str r0, [r7, #20] /* Wait for Backup domain Write protection disable */ while((PWR->CR1 & PWR_CR1_DBP) == RESET) - 80027a2: e008 b.n 80027b6 + 800344e: e008 b.n 8003462 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - 80027a4: f7fe fd4c bl 8001240 - 80027a8: 4602 mov r2, r0 - 80027aa: 697b ldr r3, [r7, #20] - 80027ac: 1ad3 subs r3, r2, r3 - 80027ae: 2b64 cmp r3, #100 ; 0x64 - 80027b0: d901 bls.n 80027b6 + 8003450: f7fe fb4e bl 8001af0 + 8003454: 4602 mov r2, r0 + 8003456: 697b ldr r3, [r7, #20] + 8003458: 1ad3 subs r3, r2, r3 + 800345a: 2b64 cmp r3, #100 ; 0x64 + 800345c: d901 bls.n 8003462 { return HAL_TIMEOUT; - 80027b2: 2303 movs r3, #3 - 80027b4: e38f b.n 8002ed6 + 800345e: 2303 movs r3, #3 + 8003460: e38f b.n 8003b82 while((PWR->CR1 & PWR_CR1_DBP) == RESET) - 80027b6: 4b2c ldr r3, [pc, #176] ; (8002868 ) - 80027b8: 681b ldr r3, [r3, #0] - 80027ba: f403 7380 and.w r3, r3, #256 ; 0x100 - 80027be: 2b00 cmp r3, #0 - 80027c0: d0f0 beq.n 80027a4 + 8003462: 4b2c ldr r3, [pc, #176] ; (8003514 ) + 8003464: 681b ldr r3, [r3, #0] + 8003466: f403 7380 and.w r3, r3, #256 ; 0x100 + 800346a: 2b00 cmp r3, #0 + 800346c: d0f0 beq.n 8003450 } } /* Reset the Backup domain only if the RTC Clock source selection is modified */ tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL); - 80027c2: 4b28 ldr r3, [pc, #160] ; (8002864 ) - 80027c4: 6f1b ldr r3, [r3, #112] ; 0x70 - 80027c6: f403 7340 and.w r3, r3, #768 ; 0x300 - 80027ca: 613b str r3, [r7, #16] + 800346e: 4b28 ldr r3, [pc, #160] ; (8003510 ) + 8003470: 6f1b ldr r3, [r3, #112] ; 0x70 + 8003472: f403 7340 and.w r3, r3, #768 ; 0x300 + 8003476: 613b str r3, [r7, #16] if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) - 80027cc: 693b ldr r3, [r7, #16] - 80027ce: 2b00 cmp r3, #0 - 80027d0: d035 beq.n 800283e - 80027d2: 687b ldr r3, [r7, #4] - 80027d4: 6b1b ldr r3, [r3, #48] ; 0x30 - 80027d6: f403 7340 and.w r3, r3, #768 ; 0x300 - 80027da: 693a ldr r2, [r7, #16] - 80027dc: 429a cmp r2, r3 - 80027de: d02e beq.n 800283e + 8003478: 693b ldr r3, [r7, #16] + 800347a: 2b00 cmp r3, #0 + 800347c: d035 beq.n 80034ea + 800347e: 687b ldr r3, [r7, #4] + 8003480: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003482: f403 7340 and.w r3, r3, #768 ; 0x300 + 8003486: 693a ldr r2, [r7, #16] + 8003488: 429a cmp r2, r3 + 800348a: d02e beq.n 80034ea { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); - 80027e0: 4b20 ldr r3, [pc, #128] ; (8002864 ) - 80027e2: 6f1b ldr r3, [r3, #112] ; 0x70 - 80027e4: f423 7340 bic.w r3, r3, #768 ; 0x300 - 80027e8: 613b str r3, [r7, #16] + 800348c: 4b20 ldr r3, [pc, #128] ; (8003510 ) + 800348e: 6f1b ldr r3, [r3, #112] ; 0x70 + 8003490: f423 7340 bic.w r3, r3, #768 ; 0x300 + 8003494: 613b str r3, [r7, #16] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); - 80027ea: 4b1e ldr r3, [pc, #120] ; (8002864 ) - 80027ec: 6f1b ldr r3, [r3, #112] ; 0x70 - 80027ee: 4a1d ldr r2, [pc, #116] ; (8002864 ) - 80027f0: f443 3380 orr.w r3, r3, #65536 ; 0x10000 - 80027f4: 6713 str r3, [r2, #112] ; 0x70 + 8003496: 4b1e ldr r3, [pc, #120] ; (8003510 ) + 8003498: 6f1b ldr r3, [r3, #112] ; 0x70 + 800349a: 4a1d ldr r2, [pc, #116] ; (8003510 ) + 800349c: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 80034a0: 6713 str r3, [r2, #112] ; 0x70 __HAL_RCC_BACKUPRESET_RELEASE(); - 80027f6: 4b1b ldr r3, [pc, #108] ; (8002864 ) - 80027f8: 6f1b ldr r3, [r3, #112] ; 0x70 - 80027fa: 4a1a ldr r2, [pc, #104] ; (8002864 ) - 80027fc: f423 3380 bic.w r3, r3, #65536 ; 0x10000 - 8002800: 6713 str r3, [r2, #112] ; 0x70 + 80034a2: 4b1b ldr r3, [pc, #108] ; (8003510 ) + 80034a4: 6f1b ldr r3, [r3, #112] ; 0x70 + 80034a6: 4a1a ldr r2, [pc, #104] ; (8003510 ) + 80034a8: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 80034ac: 6713 str r3, [r2, #112] ; 0x70 /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg0; - 8002802: 4a18 ldr r2, [pc, #96] ; (8002864 ) - 8002804: 693b ldr r3, [r7, #16] - 8002806: 6713 str r3, [r2, #112] ; 0x70 + 80034ae: 4a18 ldr r2, [pc, #96] ; (8003510 ) + 80034b0: 693b ldr r3, [r7, #16] + 80034b2: 6713 str r3, [r2, #112] ; 0x70 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) - 8002808: 4b16 ldr r3, [pc, #88] ; (8002864 ) - 800280a: 6f1b ldr r3, [r3, #112] ; 0x70 - 800280c: f003 0301 and.w r3, r3, #1 - 8002810: 2b01 cmp r3, #1 - 8002812: d114 bne.n 800283e + 80034b4: 4b16 ldr r3, [pc, #88] ; (8003510 ) + 80034b6: 6f1b ldr r3, [r3, #112] ; 0x70 + 80034b8: f003 0301 and.w r3, r3, #1 + 80034bc: 2b01 cmp r3, #1 + 80034be: d114 bne.n 80034ea { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8002814: f7fe fd14 bl 8001240 - 8002818: 6178 str r0, [r7, #20] + 80034c0: f7fe fb16 bl 8001af0 + 80034c4: 6178 str r0, [r7, #20] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 800281a: e00a b.n 8002832 + 80034c6: e00a b.n 80034de { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - 800281c: f7fe fd10 bl 8001240 - 8002820: 4602 mov r2, r0 - 8002822: 697b ldr r3, [r7, #20] - 8002824: 1ad3 subs r3, r2, r3 - 8002826: f241 3288 movw r2, #5000 ; 0x1388 - 800282a: 4293 cmp r3, r2 - 800282c: d901 bls.n 8002832 + 80034c8: f7fe fb12 bl 8001af0 + 80034cc: 4602 mov r2, r0 + 80034ce: 697b ldr r3, [r7, #20] + 80034d0: 1ad3 subs r3, r2, r3 + 80034d2: f241 3288 movw r2, #5000 ; 0x1388 + 80034d6: 4293 cmp r3, r2 + 80034d8: d901 bls.n 80034de { return HAL_TIMEOUT; - 800282e: 2303 movs r3, #3 - 8002830: e351 b.n 8002ed6 + 80034da: 2303 movs r3, #3 + 80034dc: e351 b.n 8003b82 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 8002832: 4b0c ldr r3, [pc, #48] ; (8002864 ) - 8002834: 6f1b ldr r3, [r3, #112] ; 0x70 - 8002836: f003 0302 and.w r3, r3, #2 - 800283a: 2b00 cmp r3, #0 - 800283c: d0ee beq.n 800281c + 80034de: 4b0c ldr r3, [pc, #48] ; (8003510 ) + 80034e0: 6f1b ldr r3, [r3, #112] ; 0x70 + 80034e2: f003 0302 and.w r3, r3, #2 + 80034e6: 2b00 cmp r3, #0 + 80034e8: d0ee beq.n 80034c8 } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - 800283e: 687b ldr r3, [r7, #4] - 8002840: 6b1b ldr r3, [r3, #48] ; 0x30 - 8002842: f403 7340 and.w r3, r3, #768 ; 0x300 - 8002846: f5b3 7f40 cmp.w r3, #768 ; 0x300 - 800284a: d111 bne.n 8002870 - 800284c: 4b05 ldr r3, [pc, #20] ; (8002864 ) - 800284e: 689b ldr r3, [r3, #8] - 8002850: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000 - 8002854: 687b ldr r3, [r7, #4] - 8002856: 6b19 ldr r1, [r3, #48] ; 0x30 - 8002858: 4b04 ldr r3, [pc, #16] ; (800286c ) - 800285a: 400b ands r3, r1 - 800285c: 4901 ldr r1, [pc, #4] ; (8002864 ) - 800285e: 4313 orrs r3, r2 - 8002860: 608b str r3, [r1, #8] - 8002862: e00b b.n 800287c - 8002864: 40023800 .word 0x40023800 - 8002868: 40007000 .word 0x40007000 - 800286c: 0ffffcff .word 0x0ffffcff - 8002870: 4bb3 ldr r3, [pc, #716] ; (8002b40 ) - 8002872: 689b ldr r3, [r3, #8] - 8002874: 4ab2 ldr r2, [pc, #712] ; (8002b40 ) - 8002876: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000 - 800287a: 6093 str r3, [r2, #8] - 800287c: 4bb0 ldr r3, [pc, #704] ; (8002b40 ) - 800287e: 6f1a ldr r2, [r3, #112] ; 0x70 - 8002880: 687b ldr r3, [r7, #4] - 8002882: 6b1b ldr r3, [r3, #48] ; 0x30 - 8002884: f3c3 030b ubfx r3, r3, #0, #12 - 8002888: 49ad ldr r1, [pc, #692] ; (8002b40 ) - 800288a: 4313 orrs r3, r2 - 800288c: 670b str r3, [r1, #112] ; 0x70 + 80034ea: 687b ldr r3, [r7, #4] + 80034ec: 6b1b ldr r3, [r3, #48] ; 0x30 + 80034ee: f403 7340 and.w r3, r3, #768 ; 0x300 + 80034f2: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 80034f6: d111 bne.n 800351c + 80034f8: 4b05 ldr r3, [pc, #20] ; (8003510 ) + 80034fa: 689b ldr r3, [r3, #8] + 80034fc: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000 + 8003500: 687b ldr r3, [r7, #4] + 8003502: 6b19 ldr r1, [r3, #48] ; 0x30 + 8003504: 4b04 ldr r3, [pc, #16] ; (8003518 ) + 8003506: 400b ands r3, r1 + 8003508: 4901 ldr r1, [pc, #4] ; (8003510 ) + 800350a: 4313 orrs r3, r2 + 800350c: 608b str r3, [r1, #8] + 800350e: e00b b.n 8003528 + 8003510: 40023800 .word 0x40023800 + 8003514: 40007000 .word 0x40007000 + 8003518: 0ffffcff .word 0x0ffffcff + 800351c: 4bb3 ldr r3, [pc, #716] ; (80037ec ) + 800351e: 689b ldr r3, [r3, #8] + 8003520: 4ab2 ldr r2, [pc, #712] ; (80037ec ) + 8003522: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000 + 8003526: 6093 str r3, [r2, #8] + 8003528: 4bb0 ldr r3, [pc, #704] ; (80037ec ) + 800352a: 6f1a ldr r2, [r3, #112] ; 0x70 + 800352c: 687b ldr r3, [r7, #4] + 800352e: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003530: f3c3 030b ubfx r3, r3, #0, #12 + 8003534: 49ad ldr r1, [pc, #692] ; (80037ec ) + 8003536: 4313 orrs r3, r2 + 8003538: 670b str r3, [r1, #112] ; 0x70 } /*------------------------------------ TIM configuration --------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) - 800288e: 687b ldr r3, [r7, #4] - 8002890: 681b ldr r3, [r3, #0] - 8002892: f003 0310 and.w r3, r3, #16 - 8002896: 2b00 cmp r3, #0 - 8002898: d010 beq.n 80028bc + 800353a: 687b ldr r3, [r7, #4] + 800353c: 681b ldr r3, [r3, #0] + 800353e: f003 0310 and.w r3, r3, #16 + 8003542: 2b00 cmp r3, #0 + 8003544: d010 beq.n 8003568 { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); /* Configure Timer Prescaler */ __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); - 800289a: 4ba9 ldr r3, [pc, #676] ; (8002b40 ) - 800289c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c - 80028a0: 4aa7 ldr r2, [pc, #668] ; (8002b40 ) - 80028a2: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 - 80028a6: f8c2 308c str.w r3, [r2, #140] ; 0x8c - 80028aa: 4ba5 ldr r3, [pc, #660] ; (8002b40 ) - 80028ac: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c - 80028b0: 687b ldr r3, [r7, #4] - 80028b2: 6b9b ldr r3, [r3, #56] ; 0x38 - 80028b4: 49a2 ldr r1, [pc, #648] ; (8002b40 ) - 80028b6: 4313 orrs r3, r2 - 80028b8: f8c1 308c str.w r3, [r1, #140] ; 0x8c + 8003546: 4ba9 ldr r3, [pc, #676] ; (80037ec ) + 8003548: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 800354c: 4aa7 ldr r2, [pc, #668] ; (80037ec ) + 800354e: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 8003552: f8c2 308c str.w r3, [r2, #140] ; 0x8c + 8003556: 4ba5 ldr r3, [pc, #660] ; (80037ec ) + 8003558: f8d3 208c ldr.w r2, [r3, #140] ; 0x8c + 800355c: 687b ldr r3, [r7, #4] + 800355e: 6b9b ldr r3, [r3, #56] ; 0x38 + 8003560: 49a2 ldr r1, [pc, #648] ; (80037ec ) + 8003562: 4313 orrs r3, r2 + 8003564: f8c1 308c str.w r3, [r1, #140] ; 0x8c } /*-------------------------------------- I2C1 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) - 80028bc: 687b ldr r3, [r7, #4] - 80028be: 681b ldr r3, [r3, #0] - 80028c0: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 80028c4: 2b00 cmp r3, #0 - 80028c6: d00a beq.n 80028de + 8003568: 687b ldr r3, [r7, #4] + 800356a: 681b ldr r3, [r3, #0] + 800356c: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8003570: 2b00 cmp r3, #0 + 8003572: d00a beq.n 800358a { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); - 80028c8: 4b9d ldr r3, [pc, #628] ; (8002b40 ) - 80028ca: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 80028ce: f423 3240 bic.w r2, r3, #196608 ; 0x30000 - 80028d2: 687b ldr r3, [r7, #4] - 80028d4: 6e5b ldr r3, [r3, #100] ; 0x64 - 80028d6: 499a ldr r1, [pc, #616] ; (8002b40 ) - 80028d8: 4313 orrs r3, r2 - 80028da: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8003574: 4b9d ldr r3, [pc, #628] ; (80037ec ) + 8003576: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800357a: f423 3240 bic.w r2, r3, #196608 ; 0x30000 + 800357e: 687b ldr r3, [r7, #4] + 8003580: 6e5b ldr r3, [r3, #100] ; 0x64 + 8003582: 499a ldr r1, [pc, #616] ; (80037ec ) + 8003584: 4313 orrs r3, r2 + 8003586: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- I2C2 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) - 80028de: 687b ldr r3, [r7, #4] - 80028e0: 681b ldr r3, [r3, #0] - 80028e2: f403 4300 and.w r3, r3, #32768 ; 0x8000 - 80028e6: 2b00 cmp r3, #0 - 80028e8: d00a beq.n 8002900 + 800358a: 687b ldr r3, [r7, #4] + 800358c: 681b ldr r3, [r3, #0] + 800358e: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 8003592: 2b00 cmp r3, #0 + 8003594: d00a beq.n 80035ac { /* Check the parameters */ assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); /* Configure the I2C2 clock source */ __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); - 80028ea: 4b95 ldr r3, [pc, #596] ; (8002b40 ) - 80028ec: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 80028f0: f423 2240 bic.w r2, r3, #786432 ; 0xc0000 - 80028f4: 687b ldr r3, [r7, #4] - 80028f6: 6e9b ldr r3, [r3, #104] ; 0x68 - 80028f8: 4991 ldr r1, [pc, #580] ; (8002b40 ) - 80028fa: 4313 orrs r3, r2 - 80028fc: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8003596: 4b95 ldr r3, [pc, #596] ; (80037ec ) + 8003598: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800359c: f423 2240 bic.w r2, r3, #786432 ; 0xc0000 + 80035a0: 687b ldr r3, [r7, #4] + 80035a2: 6e9b ldr r3, [r3, #104] ; 0x68 + 80035a4: 4991 ldr r1, [pc, #580] ; (80037ec ) + 80035a6: 4313 orrs r3, r2 + 80035a8: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- I2C3 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) - 8002900: 687b ldr r3, [r7, #4] - 8002902: 681b ldr r3, [r3, #0] - 8002904: f403 3380 and.w r3, r3, #65536 ; 0x10000 - 8002908: 2b00 cmp r3, #0 - 800290a: d00a beq.n 8002922 + 80035ac: 687b ldr r3, [r7, #4] + 80035ae: 681b ldr r3, [r3, #0] + 80035b0: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 80035b4: 2b00 cmp r3, #0 + 80035b6: d00a beq.n 80035ce { /* Check the parameters */ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); - 800290c: 4b8c ldr r3, [pc, #560] ; (8002b40 ) - 800290e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8002912: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 - 8002916: 687b ldr r3, [r7, #4] - 8002918: 6edb ldr r3, [r3, #108] ; 0x6c - 800291a: 4989 ldr r1, [pc, #548] ; (8002b40 ) - 800291c: 4313 orrs r3, r2 - 800291e: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 80035b8: 4b8c ldr r3, [pc, #560] ; (80037ec ) + 80035ba: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80035be: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 + 80035c2: 687b ldr r3, [r7, #4] + 80035c4: 6edb ldr r3, [r3, #108] ; 0x6c + 80035c6: 4989 ldr r1, [pc, #548] ; (80037ec ) + 80035c8: 4313 orrs r3, r2 + 80035ca: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- I2C4 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) - 8002922: 687b ldr r3, [r7, #4] - 8002924: 681b ldr r3, [r3, #0] - 8002926: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 800292a: 2b00 cmp r3, #0 - 800292c: d00a beq.n 8002944 + 80035ce: 687b ldr r3, [r7, #4] + 80035d0: 681b ldr r3, [r3, #0] + 80035d2: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 80035d6: 2b00 cmp r3, #0 + 80035d8: d00a beq.n 80035f0 { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); /* Configure the I2C4 clock source */ __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); - 800292e: 4b84 ldr r3, [pc, #528] ; (8002b40 ) - 8002930: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8002934: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 - 8002938: 687b ldr r3, [r7, #4] - 800293a: 6f1b ldr r3, [r3, #112] ; 0x70 - 800293c: 4980 ldr r1, [pc, #512] ; (8002b40 ) - 800293e: 4313 orrs r3, r2 - 8002940: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 80035da: 4b84 ldr r3, [pc, #528] ; (80037ec ) + 80035dc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80035e0: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 + 80035e4: 687b ldr r3, [r7, #4] + 80035e6: 6f1b ldr r3, [r3, #112] ; 0x70 + 80035e8: 4980 ldr r1, [pc, #512] ; (80037ec ) + 80035ea: 4313 orrs r3, r2 + 80035ec: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- USART1 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) - 8002944: 687b ldr r3, [r7, #4] - 8002946: 681b ldr r3, [r3, #0] - 8002948: f003 0340 and.w r3, r3, #64 ; 0x40 - 800294c: 2b00 cmp r3, #0 - 800294e: d00a beq.n 8002966 + 80035f0: 687b ldr r3, [r7, #4] + 80035f2: 681b ldr r3, [r3, #0] + 80035f4: f003 0340 and.w r3, r3, #64 ; 0x40 + 80035f8: 2b00 cmp r3, #0 + 80035fa: d00a beq.n 8003612 { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); - 8002950: 4b7b ldr r3, [pc, #492] ; (8002b40 ) - 8002952: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8002956: f023 0203 bic.w r2, r3, #3 - 800295a: 687b ldr r3, [r7, #4] - 800295c: 6c5b ldr r3, [r3, #68] ; 0x44 - 800295e: 4978 ldr r1, [pc, #480] ; (8002b40 ) - 8002960: 4313 orrs r3, r2 - 8002962: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 80035fc: 4b7b ldr r3, [pc, #492] ; (80037ec ) + 80035fe: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003602: f023 0203 bic.w r2, r3, #3 + 8003606: 687b ldr r3, [r7, #4] + 8003608: 6c5b ldr r3, [r3, #68] ; 0x44 + 800360a: 4978 ldr r1, [pc, #480] ; (80037ec ) + 800360c: 4313 orrs r3, r2 + 800360e: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- USART2 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) - 8002966: 687b ldr r3, [r7, #4] - 8002968: 681b ldr r3, [r3, #0] - 800296a: f003 0380 and.w r3, r3, #128 ; 0x80 - 800296e: 2b00 cmp r3, #0 - 8002970: d00a beq.n 8002988 + 8003612: 687b ldr r3, [r7, #4] + 8003614: 681b ldr r3, [r3, #0] + 8003616: f003 0380 and.w r3, r3, #128 ; 0x80 + 800361a: 2b00 cmp r3, #0 + 800361c: d00a beq.n 8003634 { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); - 8002972: 4b73 ldr r3, [pc, #460] ; (8002b40 ) - 8002974: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8002978: f023 020c bic.w r2, r3, #12 - 800297c: 687b ldr r3, [r7, #4] - 800297e: 6c9b ldr r3, [r3, #72] ; 0x48 - 8002980: 496f ldr r1, [pc, #444] ; (8002b40 ) - 8002982: 4313 orrs r3, r2 - 8002984: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 800361e: 4b73 ldr r3, [pc, #460] ; (80037ec ) + 8003620: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003624: f023 020c bic.w r2, r3, #12 + 8003628: 687b ldr r3, [r7, #4] + 800362a: 6c9b ldr r3, [r3, #72] ; 0x48 + 800362c: 496f ldr r1, [pc, #444] ; (80037ec ) + 800362e: 4313 orrs r3, r2 + 8003630: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- USART3 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) - 8002988: 687b ldr r3, [r7, #4] - 800298a: 681b ldr r3, [r3, #0] - 800298c: f403 7380 and.w r3, r3, #256 ; 0x100 - 8002990: 2b00 cmp r3, #0 - 8002992: d00a beq.n 80029aa + 8003634: 687b ldr r3, [r7, #4] + 8003636: 681b ldr r3, [r3, #0] + 8003638: f403 7380 and.w r3, r3, #256 ; 0x100 + 800363c: 2b00 cmp r3, #0 + 800363e: d00a beq.n 8003656 { /* Check the parameters */ assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); /* Configure the USART3 clock source */ __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); - 8002994: 4b6a ldr r3, [pc, #424] ; (8002b40 ) - 8002996: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 800299a: f023 0230 bic.w r2, r3, #48 ; 0x30 - 800299e: 687b ldr r3, [r7, #4] - 80029a0: 6cdb ldr r3, [r3, #76] ; 0x4c - 80029a2: 4967 ldr r1, [pc, #412] ; (8002b40 ) - 80029a4: 4313 orrs r3, r2 - 80029a6: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8003640: 4b6a ldr r3, [pc, #424] ; (80037ec ) + 8003642: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003646: f023 0230 bic.w r2, r3, #48 ; 0x30 + 800364a: 687b ldr r3, [r7, #4] + 800364c: 6cdb ldr r3, [r3, #76] ; 0x4c + 800364e: 4967 ldr r1, [pc, #412] ; (80037ec ) + 8003650: 4313 orrs r3, r2 + 8003652: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- UART4 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) - 80029aa: 687b ldr r3, [r7, #4] - 80029ac: 681b ldr r3, [r3, #0] - 80029ae: f403 7300 and.w r3, r3, #512 ; 0x200 - 80029b2: 2b00 cmp r3, #0 - 80029b4: d00a beq.n 80029cc + 8003656: 687b ldr r3, [r7, #4] + 8003658: 681b ldr r3, [r3, #0] + 800365a: f403 7300 and.w r3, r3, #512 ; 0x200 + 800365e: 2b00 cmp r3, #0 + 8003660: d00a beq.n 8003678 { /* Check the parameters */ assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); /* Configure the UART4 clock source */ __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); - 80029b6: 4b62 ldr r3, [pc, #392] ; (8002b40 ) - 80029b8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 80029bc: f023 02c0 bic.w r2, r3, #192 ; 0xc0 - 80029c0: 687b ldr r3, [r7, #4] - 80029c2: 6d1b ldr r3, [r3, #80] ; 0x50 - 80029c4: 495e ldr r1, [pc, #376] ; (8002b40 ) - 80029c6: 4313 orrs r3, r2 - 80029c8: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8003662: 4b62 ldr r3, [pc, #392] ; (80037ec ) + 8003664: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003668: f023 02c0 bic.w r2, r3, #192 ; 0xc0 + 800366c: 687b ldr r3, [r7, #4] + 800366e: 6d1b ldr r3, [r3, #80] ; 0x50 + 8003670: 495e ldr r1, [pc, #376] ; (80037ec ) + 8003672: 4313 orrs r3, r2 + 8003674: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- UART5 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) - 80029cc: 687b ldr r3, [r7, #4] - 80029ce: 681b ldr r3, [r3, #0] - 80029d0: f403 6380 and.w r3, r3, #1024 ; 0x400 - 80029d4: 2b00 cmp r3, #0 - 80029d6: d00a beq.n 80029ee + 8003678: 687b ldr r3, [r7, #4] + 800367a: 681b ldr r3, [r3, #0] + 800367c: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8003680: 2b00 cmp r3, #0 + 8003682: d00a beq.n 800369a { /* Check the parameters */ assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); /* Configure the UART5 clock source */ __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); - 80029d8: 4b59 ldr r3, [pc, #356] ; (8002b40 ) - 80029da: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 80029de: f423 7240 bic.w r2, r3, #768 ; 0x300 - 80029e2: 687b ldr r3, [r7, #4] - 80029e4: 6d5b ldr r3, [r3, #84] ; 0x54 - 80029e6: 4956 ldr r1, [pc, #344] ; (8002b40 ) - 80029e8: 4313 orrs r3, r2 - 80029ea: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8003684: 4b59 ldr r3, [pc, #356] ; (80037ec ) + 8003686: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800368a: f423 7240 bic.w r2, r3, #768 ; 0x300 + 800368e: 687b ldr r3, [r7, #4] + 8003690: 6d5b ldr r3, [r3, #84] ; 0x54 + 8003692: 4956 ldr r1, [pc, #344] ; (80037ec ) + 8003694: 4313 orrs r3, r2 + 8003696: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- USART6 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) - 80029ee: 687b ldr r3, [r7, #4] - 80029f0: 681b ldr r3, [r3, #0] - 80029f2: f403 6300 and.w r3, r3, #2048 ; 0x800 - 80029f6: 2b00 cmp r3, #0 - 80029f8: d00a beq.n 8002a10 + 800369a: 687b ldr r3, [r7, #4] + 800369c: 681b ldr r3, [r3, #0] + 800369e: f403 6300 and.w r3, r3, #2048 ; 0x800 + 80036a2: 2b00 cmp r3, #0 + 80036a4: d00a beq.n 80036bc { /* Check the parameters */ assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); /* Configure the USART6 clock source */ __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); - 80029fa: 4b51 ldr r3, [pc, #324] ; (8002b40 ) - 80029fc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8002a00: f423 6240 bic.w r2, r3, #3072 ; 0xc00 - 8002a04: 687b ldr r3, [r7, #4] - 8002a06: 6d9b ldr r3, [r3, #88] ; 0x58 - 8002a08: 494d ldr r1, [pc, #308] ; (8002b40 ) - 8002a0a: 4313 orrs r3, r2 - 8002a0c: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 80036a6: 4b51 ldr r3, [pc, #324] ; (80037ec ) + 80036a8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80036ac: f423 6240 bic.w r2, r3, #3072 ; 0xc00 + 80036b0: 687b ldr r3, [r7, #4] + 80036b2: 6d9b ldr r3, [r3, #88] ; 0x58 + 80036b4: 494d ldr r1, [pc, #308] ; (80037ec ) + 80036b6: 4313 orrs r3, r2 + 80036b8: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- UART7 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) - 8002a10: 687b ldr r3, [r7, #4] - 8002a12: 681b ldr r3, [r3, #0] - 8002a14: f403 5380 and.w r3, r3, #4096 ; 0x1000 - 8002a18: 2b00 cmp r3, #0 - 8002a1a: d00a beq.n 8002a32 + 80036bc: 687b ldr r3, [r7, #4] + 80036be: 681b ldr r3, [r3, #0] + 80036c0: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 80036c4: 2b00 cmp r3, #0 + 80036c6: d00a beq.n 80036de { /* Check the parameters */ assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); /* Configure the UART7 clock source */ __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); - 8002a1c: 4b48 ldr r3, [pc, #288] ; (8002b40 ) - 8002a1e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8002a22: f423 5240 bic.w r2, r3, #12288 ; 0x3000 - 8002a26: 687b ldr r3, [r7, #4] - 8002a28: 6ddb ldr r3, [r3, #92] ; 0x5c - 8002a2a: 4945 ldr r1, [pc, #276] ; (8002b40 ) - 8002a2c: 4313 orrs r3, r2 - 8002a2e: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 80036c8: 4b48 ldr r3, [pc, #288] ; (80037ec ) + 80036ca: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80036ce: f423 5240 bic.w r2, r3, #12288 ; 0x3000 + 80036d2: 687b ldr r3, [r7, #4] + 80036d4: 6ddb ldr r3, [r3, #92] ; 0x5c + 80036d6: 4945 ldr r1, [pc, #276] ; (80037ec ) + 80036d8: 4313 orrs r3, r2 + 80036da: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- UART8 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) - 8002a32: 687b ldr r3, [r7, #4] - 8002a34: 681b ldr r3, [r3, #0] - 8002a36: f403 5300 and.w r3, r3, #8192 ; 0x2000 - 8002a3a: 2b00 cmp r3, #0 - 8002a3c: d00a beq.n 8002a54 + 80036de: 687b ldr r3, [r7, #4] + 80036e0: 681b ldr r3, [r3, #0] + 80036e2: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 80036e6: 2b00 cmp r3, #0 + 80036e8: d00a beq.n 8003700 { /* Check the parameters */ assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); /* Configure the UART8 clock source */ __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); - 8002a3e: 4b40 ldr r3, [pc, #256] ; (8002b40 ) - 8002a40: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8002a44: f423 4240 bic.w r2, r3, #49152 ; 0xc000 - 8002a48: 687b ldr r3, [r7, #4] - 8002a4a: 6e1b ldr r3, [r3, #96] ; 0x60 - 8002a4c: 493c ldr r1, [pc, #240] ; (8002b40 ) - 8002a4e: 4313 orrs r3, r2 - 8002a50: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 80036ea: 4b40 ldr r3, [pc, #256] ; (80037ec ) + 80036ec: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80036f0: f423 4240 bic.w r2, r3, #49152 ; 0xc000 + 80036f4: 687b ldr r3, [r7, #4] + 80036f6: 6e1b ldr r3, [r3, #96] ; 0x60 + 80036f8: 493c ldr r1, [pc, #240] ; (80037ec ) + 80036fa: 4313 orrs r3, r2 + 80036fc: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*--------------------------------------- CEC Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) - 8002a54: 687b ldr r3, [r7, #4] - 8002a56: 681b ldr r3, [r3, #0] - 8002a58: f403 0380 and.w r3, r3, #4194304 ; 0x400000 - 8002a5c: 2b00 cmp r3, #0 - 8002a5e: d00a beq.n 8002a76 + 8003700: 687b ldr r3, [r7, #4] + 8003702: 681b ldr r3, [r3, #0] + 8003704: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8003708: 2b00 cmp r3, #0 + 800370a: d00a beq.n 8003722 { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); /* Configure the CEC clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); - 8002a60: 4b37 ldr r3, [pc, #220] ; (8002b40 ) - 8002a62: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8002a66: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000 - 8002a6a: 687b ldr r3, [r7, #4] - 8002a6c: 6f9b ldr r3, [r3, #120] ; 0x78 - 8002a6e: 4934 ldr r1, [pc, #208] ; (8002b40 ) - 8002a70: 4313 orrs r3, r2 - 8002a72: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 800370c: 4b37 ldr r3, [pc, #220] ; (80037ec ) + 800370e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003712: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000 + 8003716: 687b ldr r3, [r7, #4] + 8003718: 6f9b ldr r3, [r3, #120] ; 0x78 + 800371a: 4934 ldr r1, [pc, #208] ; (80037ec ) + 800371c: 4313 orrs r3, r2 + 800371e: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*-------------------------------------- CK48 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) - 8002a76: 687b ldr r3, [r7, #4] - 8002a78: 681b ldr r3, [r3, #0] - 8002a7a: f403 1300 and.w r3, r3, #2097152 ; 0x200000 - 8002a7e: 2b00 cmp r3, #0 - 8002a80: d011 beq.n 8002aa6 + 8003722: 687b ldr r3, [r7, #4] + 8003724: 681b ldr r3, [r3, #0] + 8003726: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 800372a: 2b00 cmp r3, #0 + 800372c: d011 beq.n 8003752 { /* Check the parameters */ assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); /* Configure the CLK48 source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); - 8002a82: 4b2f ldr r3, [pc, #188] ; (8002b40 ) - 8002a84: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8002a88: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000 - 8002a8c: 687b ldr r3, [r7, #4] - 8002a8e: 6fdb ldr r3, [r3, #124] ; 0x7c - 8002a90: 492b ldr r1, [pc, #172] ; (8002b40 ) - 8002a92: 4313 orrs r3, r2 - 8002a94: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 800372e: 4b2f ldr r3, [pc, #188] ; (80037ec ) + 8003730: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003734: f023 6200 bic.w r2, r3, #134217728 ; 0x8000000 + 8003738: 687b ldr r3, [r7, #4] + 800373a: 6fdb ldr r3, [r3, #124] ; 0x7c + 800373c: 492b ldr r1, [pc, #172] ; (80037ec ) + 800373e: 4313 orrs r3, r2 + 8003740: f8c1 3090 str.w r3, [r1, #144] ; 0x90 /* Enable the PLLSAI when it's used as clock source for CK48 */ if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) - 8002a98: 687b ldr r3, [r7, #4] - 8002a9a: 6fdb ldr r3, [r3, #124] ; 0x7c - 8002a9c: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 - 8002aa0: d101 bne.n 8002aa6 + 8003744: 687b ldr r3, [r7, #4] + 8003746: 6fdb ldr r3, [r3, #124] ; 0x7c + 8003748: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 + 800374c: d101 bne.n 8003752 { pllsaiused = 1; - 8002aa2: 2301 movs r3, #1 - 8002aa4: 61bb str r3, [r7, #24] + 800374e: 2301 movs r3, #1 + 8003750: 61bb str r3, [r7, #24] } } /*-------------------------------------- LTDC Configuration -----------------------------------*/ #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) - 8002aa6: 687b ldr r3, [r7, #4] - 8002aa8: 681b ldr r3, [r3, #0] - 8002aaa: f003 0308 and.w r3, r3, #8 - 8002aae: 2b00 cmp r3, #0 - 8002ab0: d001 beq.n 8002ab6 + 8003752: 687b ldr r3, [r7, #4] + 8003754: 681b ldr r3, [r3, #0] + 8003756: f003 0308 and.w r3, r3, #8 + 800375a: 2b00 cmp r3, #0 + 800375c: d001 beq.n 8003762 { pllsaiused = 1; - 8002ab2: 2301 movs r3, #1 - 8002ab4: 61bb str r3, [r7, #24] + 800375e: 2301 movs r3, #1 + 8003760: 61bb str r3, [r7, #24] } #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) - 8002ab6: 687b ldr r3, [r7, #4] - 8002ab8: 681b ldr r3, [r3, #0] - 8002aba: f403 2380 and.w r3, r3, #262144 ; 0x40000 - 8002abe: 2b00 cmp r3, #0 - 8002ac0: d00a beq.n 8002ad8 + 8003762: 687b ldr r3, [r7, #4] + 8003764: 681b ldr r3, [r3, #0] + 8003766: f403 2380 and.w r3, r3, #262144 ; 0x40000 + 800376a: 2b00 cmp r3, #0 + 800376c: d00a beq.n 8003784 { /* Check the parameters */ assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); /* Configure the LTPIM1 clock source */ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); - 8002ac2: 4b1f ldr r3, [pc, #124] ; (8002b40 ) - 8002ac4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8002ac8: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000 - 8002acc: 687b ldr r3, [r7, #4] - 8002ace: 6f5b ldr r3, [r3, #116] ; 0x74 - 8002ad0: 491b ldr r1, [pc, #108] ; (8002b40 ) - 8002ad2: 4313 orrs r3, r2 - 8002ad4: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 800376e: 4b1f ldr r3, [pc, #124] ; (80037ec ) + 8003770: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003774: f023 7240 bic.w r2, r3, #50331648 ; 0x3000000 + 8003778: 687b ldr r3, [r7, #4] + 800377a: 6f5b ldr r3, [r3, #116] ; 0x74 + 800377c: 491b ldr r1, [pc, #108] ; (80037ec ) + 800377e: 4313 orrs r3, r2 + 8003780: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) - 8002ad8: 687b ldr r3, [r7, #4] - 8002ada: 681b ldr r3, [r3, #0] - 8002adc: f403 0300 and.w r3, r3, #8388608 ; 0x800000 - 8002ae0: 2b00 cmp r3, #0 - 8002ae2: d00b beq.n 8002afc + 8003784: 687b ldr r3, [r7, #4] + 8003786: 681b ldr r3, [r3, #0] + 8003788: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 800378c: 2b00 cmp r3, #0 + 800378e: d00b beq.n 80037a8 { /* Check the parameters */ assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); /* Configure the SDMMC1 clock source */ __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); - 8002ae4: 4b16 ldr r3, [pc, #88] ; (8002b40 ) - 8002ae6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8002aea: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000 - 8002aee: 687b ldr r3, [r7, #4] - 8002af0: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 - 8002af4: 4912 ldr r1, [pc, #72] ; (8002b40 ) - 8002af6: 4313 orrs r3, r2 - 8002af8: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 8003790: 4b16 ldr r3, [pc, #88] ; (80037ec ) + 8003792: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003796: f023 5280 bic.w r2, r3, #268435456 ; 0x10000000 + 800379a: 687b ldr r3, [r7, #4] + 800379c: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 80037a0: 4912 ldr r1, [pc, #72] ; (80037ec ) + 80037a2: 4313 orrs r3, r2 + 80037a4: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) - 8002afc: 687b ldr r3, [r7, #4] - 8002afe: 681b ldr r3, [r3, #0] - 8002b00: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 - 8002b04: 2b00 cmp r3, #0 - 8002b06: d00b beq.n 8002b20 + 80037a8: 687b ldr r3, [r7, #4] + 80037aa: 681b ldr r3, [r3, #0] + 80037ac: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 + 80037b0: 2b00 cmp r3, #0 + 80037b2: d00b beq.n 80037cc { /* Check the parameters */ assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); /* Configure the SDMMC2 clock source */ __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); - 8002b08: 4b0d ldr r3, [pc, #52] ; (8002b40 ) - 8002b0a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8002b0e: f023 5200 bic.w r2, r3, #536870912 ; 0x20000000 - 8002b12: 687b ldr r3, [r7, #4] - 8002b14: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 8002b18: 4909 ldr r1, [pc, #36] ; (8002b40 ) - 8002b1a: 4313 orrs r3, r2 - 8002b1c: f8c1 3090 str.w r3, [r1, #144] ; 0x90 + 80037b4: 4b0d ldr r3, [pc, #52] ; (80037ec ) + 80037b6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80037ba: f023 5200 bic.w r2, r3, #536870912 ; 0x20000000 + 80037be: 687b ldr r3, [r7, #4] + 80037c0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 80037c4: 4909 ldr r1, [pc, #36] ; (80037ec ) + 80037c6: 4313 orrs r3, r2 + 80037c8: f8c1 3090 str.w r3, [r1, #144] ; 0x90 } /*------------------------------------- DFSDM1 Configuration -------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) - 8002b20: 687b ldr r3, [r7, #4] - 8002b22: 681b ldr r3, [r3, #0] - 8002b24: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 - 8002b28: 2b00 cmp r3, #0 - 8002b2a: d00f beq.n 8002b4c + 80037cc: 687b ldr r3, [r7, #4] + 80037ce: 681b ldr r3, [r3, #0] + 80037d0: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 80037d4: 2b00 cmp r3, #0 + 80037d6: d00f beq.n 80037f8 { /* Check the parameters */ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); /* Configure the DFSDM1 interface clock source */ __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); - 8002b2c: 4b04 ldr r3, [pc, #16] ; (8002b40 ) - 8002b2e: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c - 8002b32: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000 - 8002b36: 687b ldr r3, [r7, #4] - 8002b38: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8002b3c: e002 b.n 8002b44 - 8002b3e: bf00 nop - 8002b40: 40023800 .word 0x40023800 - 8002b44: 4986 ldr r1, [pc, #536] ; (8002d60 ) - 8002b46: 4313 orrs r3, r2 - 8002b48: f8c1 308c str.w r3, [r1, #140] ; 0x8c + 80037d8: 4b04 ldr r3, [pc, #16] ; (80037ec ) + 80037da: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 80037de: f023 7200 bic.w r2, r3, #33554432 ; 0x2000000 + 80037e2: 687b ldr r3, [r7, #4] + 80037e4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 80037e8: e002 b.n 80037f0 + 80037ea: bf00 nop + 80037ec: 40023800 .word 0x40023800 + 80037f0: 4986 ldr r1, [pc, #536] ; (8003a0c ) + 80037f2: 4313 orrs r3, r2 + 80037f4: f8c1 308c str.w r3, [r1, #140] ; 0x8c } /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) - 8002b4c: 687b ldr r3, [r7, #4] - 8002b4e: 681b ldr r3, [r3, #0] - 8002b50: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8002b54: 2b00 cmp r3, #0 - 8002b56: d00b beq.n 8002b70 + 80037f8: 687b ldr r3, [r7, #4] + 80037fa: 681b ldr r3, [r3, #0] + 80037fc: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8003800: 2b00 cmp r3, #0 + 8003802: d00b beq.n 800381c { /* Check the parameters */ assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); /* Configure the DFSDM interface clock source */ __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); - 8002b58: 4b81 ldr r3, [pc, #516] ; (8002d60 ) - 8002b5a: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c - 8002b5e: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000 - 8002b62: 687b ldr r3, [r7, #4] - 8002b64: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c - 8002b68: 497d ldr r1, [pc, #500] ; (8002d60 ) - 8002b6a: 4313 orrs r3, r2 - 8002b6c: f8c1 308c str.w r3, [r1, #140] ; 0x8c + 8003804: 4b81 ldr r3, [pc, #516] ; (8003a0c ) + 8003806: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 800380a: f023 6280 bic.w r2, r3, #67108864 ; 0x4000000 + 800380e: 687b ldr r3, [r7, #4] + 8003810: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8003814: 497d ldr r1, [pc, #500] ; (8003a0c ) + 8003816: 4313 orrs r3, r2 + 8003818: f8c1 308c str.w r3, [r1, #140] ; 0x8c } #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */ if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) - 8002b70: 69fb ldr r3, [r7, #28] - 8002b72: 2b01 cmp r3, #1 - 8002b74: d006 beq.n 8002b84 - 8002b76: 687b ldr r3, [r7, #4] - 8002b78: 681b ldr r3, [r3, #0] - 8002b7a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 8002b7e: 2b00 cmp r3, #0 - 8002b80: f000 80d6 beq.w 8002d30 + 800381c: 69fb ldr r3, [r7, #28] + 800381e: 2b01 cmp r3, #1 + 8003820: d006 beq.n 8003830 + 8003822: 687b ldr r3, [r7, #4] + 8003824: 681b ldr r3, [r3, #0] + 8003826: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 800382a: 2b00 cmp r3, #0 + 800382c: f000 80d6 beq.w 80039dc { /* Disable the PLLI2S */ __HAL_RCC_PLLI2S_DISABLE(); - 8002b84: 4b76 ldr r3, [pc, #472] ; (8002d60 ) - 8002b86: 681b ldr r3, [r3, #0] - 8002b88: 4a75 ldr r2, [pc, #468] ; (8002d60 ) - 8002b8a: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 - 8002b8e: 6013 str r3, [r2, #0] + 8003830: 4b76 ldr r3, [pc, #472] ; (8003a0c ) + 8003832: 681b ldr r3, [r3, #0] + 8003834: 4a75 ldr r2, [pc, #468] ; (8003a0c ) + 8003836: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 + 800383a: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8002b90: f7fe fb56 bl 8001240 - 8002b94: 6178 str r0, [r7, #20] + 800383c: f7fe f958 bl 8001af0 + 8003840: 6178 str r0, [r7, #20] /* Wait till PLLI2S is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) - 8002b96: e008 b.n 8002baa + 8003842: e008 b.n 8003856 { if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) - 8002b98: f7fe fb52 bl 8001240 - 8002b9c: 4602 mov r2, r0 - 8002b9e: 697b ldr r3, [r7, #20] - 8002ba0: 1ad3 subs r3, r2, r3 - 8002ba2: 2b64 cmp r3, #100 ; 0x64 - 8002ba4: d901 bls.n 8002baa + 8003844: f7fe f954 bl 8001af0 + 8003848: 4602 mov r2, r0 + 800384a: 697b ldr r3, [r7, #20] + 800384c: 1ad3 subs r3, r2, r3 + 800384e: 2b64 cmp r3, #100 ; 0x64 + 8003850: d901 bls.n 8003856 { /* return in case of Timeout detected */ return HAL_TIMEOUT; - 8002ba6: 2303 movs r3, #3 - 8002ba8: e195 b.n 8002ed6 + 8003852: 2303 movs r3, #3 + 8003854: e195 b.n 8003b82 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) - 8002baa: 4b6d ldr r3, [pc, #436] ; (8002d60 ) - 8002bac: 681b ldr r3, [r3, #0] - 8002bae: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 - 8002bb2: 2b00 cmp r3, #0 - 8002bb4: d1f0 bne.n 8002b98 + 8003856: 4b6d ldr r3, [pc, #436] ; (8003a0c ) + 8003858: 681b ldr r3, [r3, #0] + 800385a: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 800385e: 2b00 cmp r3, #0 + 8003860: d1f0 bne.n 8003844 /* check for common PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) - 8002bb6: 687b ldr r3, [r7, #4] - 8002bb8: 681b ldr r3, [r3, #0] - 8002bba: f003 0301 and.w r3, r3, #1 - 8002bbe: 2b00 cmp r3, #0 - 8002bc0: d021 beq.n 8002c06 - 8002bc2: 687b ldr r3, [r7, #4] - 8002bc4: 6b5b ldr r3, [r3, #52] ; 0x34 - 8002bc6: 2b00 cmp r3, #0 - 8002bc8: d11d bne.n 8002c06 + 8003862: 687b ldr r3, [r7, #4] + 8003864: 681b ldr r3, [r3, #0] + 8003866: f003 0301 and.w r3, r3, #1 + 800386a: 2b00 cmp r3, #0 + 800386c: d021 beq.n 80038b2 + 800386e: 687b ldr r3, [r7, #4] + 8003870: 6b5b ldr r3, [r3, #52] ; 0x34 + 8003872: 2b00 cmp r3, #0 + 8003874: d11d bne.n 80038b2 { /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); - 8002bca: 4b65 ldr r3, [pc, #404] ; (8002d60 ) - 8002bcc: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 8002bd0: 0c1b lsrs r3, r3, #16 - 8002bd2: f003 0303 and.w r3, r3, #3 - 8002bd6: 613b str r3, [r7, #16] + 8003876: 4b65 ldr r3, [pc, #404] ; (8003a0c ) + 8003878: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800387c: 0c1b lsrs r3, r3, #16 + 800387e: f003 0303 and.w r3, r3, #3 + 8003882: 613b str r3, [r7, #16] tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); - 8002bd8: 4b61 ldr r3, [pc, #388] ; (8002d60 ) - 8002bda: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 8002bde: 0e1b lsrs r3, r3, #24 - 8002be0: f003 030f and.w r3, r3, #15 - 8002be4: 60fb str r3, [r7, #12] + 8003884: 4b61 ldr r3, [pc, #388] ; (8003a0c ) + 8003886: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 800388a: 0e1b lsrs r3, r3, #24 + 800388c: f003 030f and.w r3, r3, #15 + 8003890: 60fb str r3, [r7, #12] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR); - 8002be6: 687b ldr r3, [r7, #4] - 8002be8: 685b ldr r3, [r3, #4] - 8002bea: 019a lsls r2, r3, #6 - 8002bec: 693b ldr r3, [r7, #16] - 8002bee: 041b lsls r3, r3, #16 - 8002bf0: 431a orrs r2, r3 - 8002bf2: 68fb ldr r3, [r7, #12] - 8002bf4: 061b lsls r3, r3, #24 - 8002bf6: 431a orrs r2, r3 - 8002bf8: 687b ldr r3, [r7, #4] - 8002bfa: 689b ldr r3, [r3, #8] - 8002bfc: 071b lsls r3, r3, #28 - 8002bfe: 4958 ldr r1, [pc, #352] ; (8002d60 ) - 8002c00: 4313 orrs r3, r2 - 8002c02: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + 8003892: 687b ldr r3, [r7, #4] + 8003894: 685b ldr r3, [r3, #4] + 8003896: 019a lsls r2, r3, #6 + 8003898: 693b ldr r3, [r7, #16] + 800389a: 041b lsls r3, r3, #16 + 800389c: 431a orrs r2, r3 + 800389e: 68fb ldr r3, [r7, #12] + 80038a0: 061b lsls r3, r3, #24 + 80038a2: 431a orrs r2, r3 + 80038a4: 687b ldr r3, [r7, #4] + 80038a6: 689b ldr r3, [r3, #8] + 80038a8: 071b lsls r3, r3, #28 + 80038aa: 4958 ldr r1, [pc, #352] ; (8003a0c ) + 80038ac: 4313 orrs r3, r2 + 80038ae: f8c1 3084 str.w r3, [r1, #132] ; 0x84 } /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || - 8002c06: 687b ldr r3, [r7, #4] - 8002c08: 681b ldr r3, [r3, #0] - 8002c0a: f403 2300 and.w r3, r3, #524288 ; 0x80000 - 8002c0e: 2b00 cmp r3, #0 - 8002c10: d004 beq.n 8002c1c - 8002c12: 687b ldr r3, [r7, #4] - 8002c14: 6bdb ldr r3, [r3, #60] ; 0x3c - 8002c16: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 - 8002c1a: d00a beq.n 8002c32 + 80038b2: 687b ldr r3, [r7, #4] + 80038b4: 681b ldr r3, [r3, #0] + 80038b6: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 80038ba: 2b00 cmp r3, #0 + 80038bc: d004 beq.n 80038c8 + 80038be: 687b ldr r3, [r7, #4] + 80038c0: 6bdb ldr r3, [r3, #60] ; 0x3c + 80038c2: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 80038c6: d00a beq.n 80038de ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) - 8002c1c: 687b ldr r3, [r7, #4] - 8002c1e: 681b ldr r3, [r3, #0] - 8002c20: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 80038c8: 687b ldr r3, [r7, #4] + 80038ca: 681b ldr r3, [r3, #0] + 80038cc: f403 1380 and.w r3, r3, #1048576 ; 0x100000 if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || - 8002c24: 2b00 cmp r3, #0 - 8002c26: d02e beq.n 8002c86 + 80038d0: 2b00 cmp r3, #0 + 80038d2: d02e beq.n 8003932 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) - 8002c28: 687b ldr r3, [r7, #4] - 8002c2a: 6c1b ldr r3, [r3, #64] ; 0x40 - 8002c2c: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 - 8002c30: d129 bne.n 8002c86 + 80038d4: 687b ldr r3, [r7, #4] + 80038d6: 6c1b ldr r3, [r3, #64] ; 0x40 + 80038d8: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 80038dc: d129 bne.n 8003932 assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Check for PLLI2S/DIVQ parameters */ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); - 8002c32: 4b4b ldr r3, [pc, #300] ; (8002d60 ) - 8002c34: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 8002c38: 0c1b lsrs r3, r3, #16 - 8002c3a: f003 0303 and.w r3, r3, #3 - 8002c3e: 613b str r3, [r7, #16] + 80038de: 4b4b ldr r3, [pc, #300] ; (8003a0c ) + 80038e0: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 80038e4: 0c1b lsrs r3, r3, #16 + 80038e6: f003 0303 and.w r3, r3, #3 + 80038ea: 613b str r3, [r7, #16] tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - 8002c40: 4b47 ldr r3, [pc, #284] ; (8002d60 ) - 8002c42: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 8002c46: 0f1b lsrs r3, r3, #28 - 8002c48: f003 0307 and.w r3, r3, #7 - 8002c4c: 60fb str r3, [r7, #12] + 80038ec: 4b47 ldr r3, [pc, #284] ; (8003a0c ) + 80038ee: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 80038f2: 0f1b lsrs r3, r3, #28 + 80038f4: f003 0307 and.w r3, r3, #7 + 80038f8: 60fb str r3, [r7, #12] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); - 8002c4e: 687b ldr r3, [r7, #4] - 8002c50: 685b ldr r3, [r3, #4] - 8002c52: 019a lsls r2, r3, #6 - 8002c54: 693b ldr r3, [r7, #16] - 8002c56: 041b lsls r3, r3, #16 - 8002c58: 431a orrs r2, r3 - 8002c5a: 687b ldr r3, [r7, #4] - 8002c5c: 68db ldr r3, [r3, #12] - 8002c5e: 061b lsls r3, r3, #24 - 8002c60: 431a orrs r2, r3 - 8002c62: 68fb ldr r3, [r7, #12] - 8002c64: 071b lsls r3, r3, #28 - 8002c66: 493e ldr r1, [pc, #248] ; (8002d60 ) - 8002c68: 4313 orrs r3, r2 - 8002c6a: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + 80038fa: 687b ldr r3, [r7, #4] + 80038fc: 685b ldr r3, [r3, #4] + 80038fe: 019a lsls r2, r3, #6 + 8003900: 693b ldr r3, [r7, #16] + 8003902: 041b lsls r3, r3, #16 + 8003904: 431a orrs r2, r3 + 8003906: 687b ldr r3, [r7, #4] + 8003908: 68db ldr r3, [r3, #12] + 800390a: 061b lsls r3, r3, #24 + 800390c: 431a orrs r2, r3 + 800390e: 68fb ldr r3, [r7, #12] + 8003910: 071b lsls r3, r3, #28 + 8003912: 493e ldr r1, [pc, #248] ; (8003a0c ) + 8003914: 4313 orrs r3, r2 + 8003916: f8c1 3084 str.w r3, [r1, #132] ; 0x84 /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); - 8002c6e: 4b3c ldr r3, [pc, #240] ; (8002d60 ) - 8002c70: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c - 8002c74: f023 021f bic.w r2, r3, #31 - 8002c78: 687b ldr r3, [r7, #4] - 8002c7a: 6a5b ldr r3, [r3, #36] ; 0x24 - 8002c7c: 3b01 subs r3, #1 - 8002c7e: 4938 ldr r1, [pc, #224] ; (8002d60 ) - 8002c80: 4313 orrs r3, r2 - 8002c82: f8c1 308c str.w r3, [r1, #140] ; 0x8c + 800391a: 4b3c ldr r3, [pc, #240] ; (8003a0c ) + 800391c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8003920: f023 021f bic.w r2, r3, #31 + 8003924: 687b ldr r3, [r7, #4] + 8003926: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003928: 3b01 subs r3, #1 + 800392a: 4938 ldr r1, [pc, #224] ; (8003a0c ) + 800392c: 4313 orrs r3, r2 + 800392e: f8c1 308c str.w r3, [r1, #140] ; 0x8c } /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) - 8002c86: 687b ldr r3, [r7, #4] - 8002c88: 681b ldr r3, [r3, #0] - 8002c8a: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 - 8002c8e: 2b00 cmp r3, #0 - 8002c90: d01d beq.n 8002cce + 8003932: 687b ldr r3, [r7, #4] + 8003934: 681b ldr r3, [r3, #0] + 8003936: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 800393a: 2b00 cmp r3, #0 + 800393c: d01d beq.n 800397a { /* check for Parameters */ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); - 8002c92: 4b33 ldr r3, [pc, #204] ; (8002d60 ) - 8002c94: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 8002c98: 0e1b lsrs r3, r3, #24 - 8002c9a: f003 030f and.w r3, r3, #15 - 8002c9e: 613b str r3, [r7, #16] + 800393e: 4b33 ldr r3, [pc, #204] ; (8003a0c ) + 8003940: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8003944: 0e1b lsrs r3, r3, #24 + 8003946: f003 030f and.w r3, r3, #15 + 800394a: 613b str r3, [r7, #16] tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - 8002ca0: 4b2f ldr r3, [pc, #188] ; (8002d60 ) - 8002ca2: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 - 8002ca6: 0f1b lsrs r3, r3, #28 - 8002ca8: f003 0307 and.w r3, r3, #7 - 8002cac: 60fb str r3, [r7, #12] + 800394c: 4b2f ldr r3, [pc, #188] ; (8003a0c ) + 800394e: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8003952: 0f1b lsrs r3, r3, #28 + 8003954: f003 0307 and.w r3, r3, #7 + 8003958: 60fb str r3, [r7, #12] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1); - 8002cae: 687b ldr r3, [r7, #4] - 8002cb0: 685b ldr r3, [r3, #4] - 8002cb2: 019a lsls r2, r3, #6 - 8002cb4: 687b ldr r3, [r7, #4] - 8002cb6: 691b ldr r3, [r3, #16] - 8002cb8: 041b lsls r3, r3, #16 - 8002cba: 431a orrs r2, r3 - 8002cbc: 693b ldr r3, [r7, #16] - 8002cbe: 061b lsls r3, r3, #24 - 8002cc0: 431a orrs r2, r3 - 8002cc2: 68fb ldr r3, [r7, #12] - 8002cc4: 071b lsls r3, r3, #28 - 8002cc6: 4926 ldr r1, [pc, #152] ; (8002d60 ) - 8002cc8: 4313 orrs r3, r2 - 8002cca: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + 800395a: 687b ldr r3, [r7, #4] + 800395c: 685b ldr r3, [r3, #4] + 800395e: 019a lsls r2, r3, #6 + 8003960: 687b ldr r3, [r7, #4] + 8003962: 691b ldr r3, [r3, #16] + 8003964: 041b lsls r3, r3, #16 + 8003966: 431a orrs r2, r3 + 8003968: 693b ldr r3, [r7, #16] + 800396a: 061b lsls r3, r3, #24 + 800396c: 431a orrs r2, r3 + 800396e: 68fb ldr r3, [r7, #12] + 8003970: 071b lsls r3, r3, #28 + 8003972: 4926 ldr r1, [pc, #152] ; (8003a0c ) + 8003974: 4313 orrs r3, r2 + 8003976: f8c1 3084 str.w r3, [r1, #132] ; 0x84 } /*----------------- In Case of PLLI2S is just selected -----------------*/ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) - 8002cce: 687b ldr r3, [r7, #4] - 8002cd0: 681b ldr r3, [r3, #0] - 8002cd2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 8002cd6: 2b00 cmp r3, #0 - 8002cd8: d011 beq.n 8002cfe + 800397a: 687b ldr r3, [r7, #4] + 800397c: 681b ldr r3, [r3, #0] + 800397e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8003982: 2b00 cmp r3, #0 + 8003984: d011 beq.n 80039aa assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); - 8002cda: 687b ldr r3, [r7, #4] - 8002cdc: 685b ldr r3, [r3, #4] - 8002cde: 019a lsls r2, r3, #6 - 8002ce0: 687b ldr r3, [r7, #4] - 8002ce2: 691b ldr r3, [r3, #16] - 8002ce4: 041b lsls r3, r3, #16 - 8002ce6: 431a orrs r2, r3 - 8002ce8: 687b ldr r3, [r7, #4] - 8002cea: 68db ldr r3, [r3, #12] - 8002cec: 061b lsls r3, r3, #24 - 8002cee: 431a orrs r2, r3 - 8002cf0: 687b ldr r3, [r7, #4] - 8002cf2: 689b ldr r3, [r3, #8] - 8002cf4: 071b lsls r3, r3, #28 - 8002cf6: 491a ldr r1, [pc, #104] ; (8002d60 ) - 8002cf8: 4313 orrs r3, r2 - 8002cfa: f8c1 3084 str.w r3, [r1, #132] ; 0x84 + 8003986: 687b ldr r3, [r7, #4] + 8003988: 685b ldr r3, [r3, #4] + 800398a: 019a lsls r2, r3, #6 + 800398c: 687b ldr r3, [r7, #4] + 800398e: 691b ldr r3, [r3, #16] + 8003990: 041b lsls r3, r3, #16 + 8003992: 431a orrs r2, r3 + 8003994: 687b ldr r3, [r7, #4] + 8003996: 68db ldr r3, [r3, #12] + 8003998: 061b lsls r3, r3, #24 + 800399a: 431a orrs r2, r3 + 800399c: 687b ldr r3, [r7, #4] + 800399e: 689b ldr r3, [r3, #8] + 80039a0: 071b lsls r3, r3, #28 + 80039a2: 491a ldr r1, [pc, #104] ; (8003a0c ) + 80039a4: 4313 orrs r3, r2 + 80039a6: f8c1 3084 str.w r3, [r1, #132] ; 0x84 } /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); - 8002cfe: 4b18 ldr r3, [pc, #96] ; (8002d60 ) - 8002d00: 681b ldr r3, [r3, #0] - 8002d02: 4a17 ldr r2, [pc, #92] ; (8002d60 ) - 8002d04: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 - 8002d08: 6013 str r3, [r2, #0] + 80039aa: 4b18 ldr r3, [pc, #96] ; (8003a0c ) + 80039ac: 681b ldr r3, [r3, #0] + 80039ae: 4a17 ldr r2, [pc, #92] ; (8003a0c ) + 80039b0: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 + 80039b4: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8002d0a: f7fe fa99 bl 8001240 - 8002d0e: 6178 str r0, [r7, #20] + 80039b6: f7fe f89b bl 8001af0 + 80039ba: 6178 str r0, [r7, #20] /* Wait till PLLI2S is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) - 8002d10: e008 b.n 8002d24 + 80039bc: e008 b.n 80039d0 { if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) - 8002d12: f7fe fa95 bl 8001240 - 8002d16: 4602 mov r2, r0 - 8002d18: 697b ldr r3, [r7, #20] - 8002d1a: 1ad3 subs r3, r2, r3 - 8002d1c: 2b64 cmp r3, #100 ; 0x64 - 8002d1e: d901 bls.n 8002d24 + 80039be: f7fe f897 bl 8001af0 + 80039c2: 4602 mov r2, r0 + 80039c4: 697b ldr r3, [r7, #20] + 80039c6: 1ad3 subs r3, r2, r3 + 80039c8: 2b64 cmp r3, #100 ; 0x64 + 80039ca: d901 bls.n 80039d0 { /* return in case of Timeout detected */ return HAL_TIMEOUT; - 8002d20: 2303 movs r3, #3 - 8002d22: e0d8 b.n 8002ed6 + 80039cc: 2303 movs r3, #3 + 80039ce: e0d8 b.n 8003b82 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) - 8002d24: 4b0e ldr r3, [pc, #56] ; (8002d60 ) - 8002d26: 681b ldr r3, [r3, #0] - 8002d28: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 - 8002d2c: 2b00 cmp r3, #0 - 8002d2e: d0f0 beq.n 8002d12 + 80039d0: 4b0e ldr r3, [pc, #56] ; (8003a0c ) + 80039d2: 681b ldr r3, [r3, #0] + 80039d4: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 80039d8: 2b00 cmp r3, #0 + 80039da: d0f0 beq.n 80039be } } /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ if(pllsaiused == 1) - 8002d30: 69bb ldr r3, [r7, #24] - 8002d32: 2b01 cmp r3, #1 - 8002d34: f040 80ce bne.w 8002ed4 + 80039dc: 69bb ldr r3, [r7, #24] + 80039de: 2b01 cmp r3, #1 + 80039e0: f040 80ce bne.w 8003b80 { /* Disable PLLSAI Clock */ __HAL_RCC_PLLSAI_DISABLE(); - 8002d38: 4b09 ldr r3, [pc, #36] ; (8002d60 ) - 8002d3a: 681b ldr r3, [r3, #0] - 8002d3c: 4a08 ldr r2, [pc, #32] ; (8002d60 ) - 8002d3e: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 - 8002d42: 6013 str r3, [r2, #0] + 80039e4: 4b09 ldr r3, [pc, #36] ; (8003a0c ) + 80039e6: 681b ldr r3, [r3, #0] + 80039e8: 4a08 ldr r2, [pc, #32] ; (8003a0c ) + 80039ea: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 80039ee: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8002d44: f7fe fa7c bl 8001240 - 8002d48: 6178 str r0, [r7, #20] + 80039f0: f7fe f87e bl 8001af0 + 80039f4: 6178 str r0, [r7, #20] /* Wait till PLLSAI is disabled */ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) - 8002d4a: e00b b.n 8002d64 + 80039f6: e00b b.n 8003a10 { if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) - 8002d4c: f7fe fa78 bl 8001240 - 8002d50: 4602 mov r2, r0 - 8002d52: 697b ldr r3, [r7, #20] - 8002d54: 1ad3 subs r3, r2, r3 - 8002d56: 2b64 cmp r3, #100 ; 0x64 - 8002d58: d904 bls.n 8002d64 + 80039f8: f7fe f87a bl 8001af0 + 80039fc: 4602 mov r2, r0 + 80039fe: 697b ldr r3, [r7, #20] + 8003a00: 1ad3 subs r3, r2, r3 + 8003a02: 2b64 cmp r3, #100 ; 0x64 + 8003a04: d904 bls.n 8003a10 { /* return in case of Timeout detected */ return HAL_TIMEOUT; - 8002d5a: 2303 movs r3, #3 - 8002d5c: e0bb b.n 8002ed6 - 8002d5e: bf00 nop - 8002d60: 40023800 .word 0x40023800 + 8003a06: 2303 movs r3, #3 + 8003a08: e0bb b.n 8003b82 + 8003a0a: bf00 nop + 8003a0c: 40023800 .word 0x40023800 while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) - 8002d64: 4b5e ldr r3, [pc, #376] ; (8002ee0 ) - 8002d66: 681b ldr r3, [r3, #0] - 8002d68: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 - 8002d6c: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 - 8002d70: d0ec beq.n 8002d4c + 8003a10: 4b5e ldr r3, [pc, #376] ; (8003b8c ) + 8003a12: 681b ldr r3, [r3, #0] + 8003a14: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 + 8003a18: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 + 8003a1c: d0ec beq.n 80039f8 /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ - 8002d72: 687b ldr r3, [r7, #4] - 8002d74: 681b ldr r3, [r3, #0] - 8002d76: f403 2300 and.w r3, r3, #524288 ; 0x80000 - 8002d7a: 2b00 cmp r3, #0 - 8002d7c: d003 beq.n 8002d86 - 8002d7e: 687b ldr r3, [r7, #4] - 8002d80: 6bdb ldr r3, [r3, #60] ; 0x3c - 8002d82: 2b00 cmp r3, #0 - 8002d84: d009 beq.n 8002d9a + 8003a1e: 687b ldr r3, [r7, #4] + 8003a20: 681b ldr r3, [r3, #0] + 8003a22: f403 2300 and.w r3, r3, #524288 ; 0x80000 + 8003a26: 2b00 cmp r3, #0 + 8003a28: d003 beq.n 8003a32 + 8003a2a: 687b ldr r3, [r7, #4] + 8003a2c: 6bdb ldr r3, [r3, #60] ; 0x3c + 8003a2e: 2b00 cmp r3, #0 + 8003a30: d009 beq.n 8003a46 ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) - 8002d86: 687b ldr r3, [r7, #4] - 8002d88: 681b ldr r3, [r3, #0] - 8002d8a: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 8003a32: 687b ldr r3, [r7, #4] + 8003a34: 681b ldr r3, [r3, #0] + 8003a36: f403 1380 and.w r3, r3, #1048576 ; 0x100000 if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ - 8002d8e: 2b00 cmp r3, #0 - 8002d90: d02e beq.n 8002df0 + 8003a3a: 2b00 cmp r3, #0 + 8003a3c: d02e beq.n 8003a9c ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) - 8002d92: 687b ldr r3, [r7, #4] - 8002d94: 6c1b ldr r3, [r3, #64] ; 0x40 - 8002d96: 2b00 cmp r3, #0 - 8002d98: d12a bne.n 8002df0 + 8003a3e: 687b ldr r3, [r7, #4] + 8003a40: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003a42: 2b00 cmp r3, #0 + 8003a44: d12a bne.n 8003a9c assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); /* check for PLLSAI/DIVQ Parameter */ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); - 8002d9a: 4b51 ldr r3, [pc, #324] ; (8002ee0 ) - 8002d9c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8002da0: 0c1b lsrs r3, r3, #16 - 8002da2: f003 0303 and.w r3, r3, #3 - 8002da6: 613b str r3, [r7, #16] + 8003a46: 4b51 ldr r3, [pc, #324] ; (8003b8c ) + 8003a48: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8003a4c: 0c1b lsrs r3, r3, #16 + 8003a4e: f003 0303 and.w r3, r3, #3 + 8003a52: 613b str r3, [r7, #16] tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); - 8002da8: 4b4d ldr r3, [pc, #308] ; (8002ee0 ) - 8002daa: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8002dae: 0f1b lsrs r3, r3, #28 - 8002db0: f003 0307 and.w r3, r3, #7 - 8002db4: 60fb str r3, [r7, #12] + 8003a54: 4b4d ldr r3, [pc, #308] ; (8003b8c ) + 8003a56: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8003a5a: 0f1b lsrs r3, r3, #28 + 8003a5c: f003 0307 and.w r3, r3, #7 + 8003a60: 60fb str r3, [r7, #12] /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); - 8002db6: 687b ldr r3, [r7, #4] - 8002db8: 695b ldr r3, [r3, #20] - 8002dba: 019a lsls r2, r3, #6 - 8002dbc: 693b ldr r3, [r7, #16] - 8002dbe: 041b lsls r3, r3, #16 - 8002dc0: 431a orrs r2, r3 - 8002dc2: 687b ldr r3, [r7, #4] - 8002dc4: 699b ldr r3, [r3, #24] - 8002dc6: 061b lsls r3, r3, #24 - 8002dc8: 431a orrs r2, r3 - 8002dca: 68fb ldr r3, [r7, #12] - 8002dcc: 071b lsls r3, r3, #28 - 8002dce: 4944 ldr r1, [pc, #272] ; (8002ee0 ) - 8002dd0: 4313 orrs r3, r2 - 8002dd2: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + 8003a62: 687b ldr r3, [r7, #4] + 8003a64: 695b ldr r3, [r3, #20] + 8003a66: 019a lsls r2, r3, #6 + 8003a68: 693b ldr r3, [r7, #16] + 8003a6a: 041b lsls r3, r3, #16 + 8003a6c: 431a orrs r2, r3 + 8003a6e: 687b ldr r3, [r7, #4] + 8003a70: 699b ldr r3, [r3, #24] + 8003a72: 061b lsls r3, r3, #24 + 8003a74: 431a orrs r2, r3 + 8003a76: 68fb ldr r3, [r7, #12] + 8003a78: 071b lsls r3, r3, #28 + 8003a7a: 4944 ldr r1, [pc, #272] ; (8003b8c ) + 8003a7c: 4313 orrs r3, r2 + 8003a7e: f8c1 3088 str.w r3, [r1, #136] ; 0x88 /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); - 8002dd6: 4b42 ldr r3, [pc, #264] ; (8002ee0 ) - 8002dd8: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c - 8002ddc: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00 - 8002de0: 687b ldr r3, [r7, #4] - 8002de2: 6a9b ldr r3, [r3, #40] ; 0x28 - 8002de4: 3b01 subs r3, #1 - 8002de6: 021b lsls r3, r3, #8 - 8002de8: 493d ldr r1, [pc, #244] ; (8002ee0 ) - 8002dea: 4313 orrs r3, r2 - 8002dec: f8c1 308c str.w r3, [r1, #140] ; 0x8c + 8003a82: 4b42 ldr r3, [pc, #264] ; (8003b8c ) + 8003a84: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8003a88: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00 + 8003a8c: 687b ldr r3, [r7, #4] + 8003a8e: 6a9b ldr r3, [r3, #40] ; 0x28 + 8003a90: 3b01 subs r3, #1 + 8003a92: 021b lsls r3, r3, #8 + 8003a94: 493d ldr r1, [pc, #244] ; (8003b8c ) + 8003a96: 4313 orrs r3, r2 + 8003a98: f8c1 308c str.w r3, [r1, #140] ; 0x8c } /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ /* In Case of PLLI2S is selected as source clock for CK48 */ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) - 8002df0: 687b ldr r3, [r7, #4] - 8002df2: 681b ldr r3, [r3, #0] - 8002df4: f403 1300 and.w r3, r3, #2097152 ; 0x200000 - 8002df8: 2b00 cmp r3, #0 - 8002dfa: d022 beq.n 8002e42 - 8002dfc: 687b ldr r3, [r7, #4] - 8002dfe: 6fdb ldr r3, [r3, #124] ; 0x7c - 8002e00: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 - 8002e04: d11d bne.n 8002e42 + 8003a9c: 687b ldr r3, [r7, #4] + 8003a9e: 681b ldr r3, [r3, #0] + 8003aa0: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8003aa4: 2b00 cmp r3, #0 + 8003aa6: d022 beq.n 8003aee + 8003aa8: 687b ldr r3, [r7, #4] + 8003aaa: 6fdb ldr r3, [r3, #124] ; 0x7c + 8003aac: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 + 8003ab0: d11d bne.n 8003aee { /* check for Parameters */ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); - 8002e06: 4b36 ldr r3, [pc, #216] ; (8002ee0 ) - 8002e08: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8002e0c: 0e1b lsrs r3, r3, #24 - 8002e0e: f003 030f and.w r3, r3, #15 - 8002e12: 613b str r3, [r7, #16] + 8003ab2: 4b36 ldr r3, [pc, #216] ; (8003b8c ) + 8003ab4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8003ab8: 0e1b lsrs r3, r3, #24 + 8003aba: f003 030f and.w r3, r3, #15 + 8003abe: 613b str r3, [r7, #16] tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); - 8002e14: 4b32 ldr r3, [pc, #200] ; (8002ee0 ) - 8002e16: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8002e1a: 0f1b lsrs r3, r3, #28 - 8002e1c: f003 0307 and.w r3, r3, #7 - 8002e20: 60fb str r3, [r7, #12] + 8003ac0: 4b32 ldr r3, [pc, #200] ; (8003b8c ) + 8003ac2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8003ac6: 0f1b lsrs r3, r3, #28 + 8003ac8: f003 0307 and.w r3, r3, #7 + 8003acc: 60fb str r3, [r7, #12] /* Configure the PLLSAI division factors */ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1); - 8002e22: 687b ldr r3, [r7, #4] - 8002e24: 695b ldr r3, [r3, #20] - 8002e26: 019a lsls r2, r3, #6 - 8002e28: 687b ldr r3, [r7, #4] - 8002e2a: 6a1b ldr r3, [r3, #32] - 8002e2c: 041b lsls r3, r3, #16 - 8002e2e: 431a orrs r2, r3 - 8002e30: 693b ldr r3, [r7, #16] - 8002e32: 061b lsls r3, r3, #24 - 8002e34: 431a orrs r2, r3 - 8002e36: 68fb ldr r3, [r7, #12] - 8002e38: 071b lsls r3, r3, #28 - 8002e3a: 4929 ldr r1, [pc, #164] ; (8002ee0 ) - 8002e3c: 4313 orrs r3, r2 - 8002e3e: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + 8003ace: 687b ldr r3, [r7, #4] + 8003ad0: 695b ldr r3, [r3, #20] + 8003ad2: 019a lsls r2, r3, #6 + 8003ad4: 687b ldr r3, [r7, #4] + 8003ad6: 6a1b ldr r3, [r3, #32] + 8003ad8: 041b lsls r3, r3, #16 + 8003ada: 431a orrs r2, r3 + 8003adc: 693b ldr r3, [r7, #16] + 8003ade: 061b lsls r3, r3, #24 + 8003ae0: 431a orrs r2, r3 + 8003ae2: 68fb ldr r3, [r7, #12] + 8003ae4: 071b lsls r3, r3, #28 + 8003ae6: 4929 ldr r1, [pc, #164] ; (8003b8c ) + 8003ae8: 4313 orrs r3, r2 + 8003aea: f8c1 3088 str.w r3, [r1, #136] ; 0x88 } #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) /*---------------------------- LTDC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) - 8002e42: 687b ldr r3, [r7, #4] - 8002e44: 681b ldr r3, [r3, #0] - 8002e46: f003 0308 and.w r3, r3, #8 - 8002e4a: 2b00 cmp r3, #0 - 8002e4c: d028 beq.n 8002ea0 + 8003aee: 687b ldr r3, [r7, #4] + 8003af0: 681b ldr r3, [r3, #0] + 8003af2: f003 0308 and.w r3, r3, #8 + 8003af6: 2b00 cmp r3, #0 + 8003af8: d028 beq.n 8003b4c { assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); - 8002e4e: 4b24 ldr r3, [pc, #144] ; (8002ee0 ) - 8002e50: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8002e54: 0e1b lsrs r3, r3, #24 - 8002e56: f003 030f and.w r3, r3, #15 - 8002e5a: 613b str r3, [r7, #16] + 8003afa: 4b24 ldr r3, [pc, #144] ; (8003b8c ) + 8003afc: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8003b00: 0e1b lsrs r3, r3, #24 + 8003b02: f003 030f and.w r3, r3, #15 + 8003b06: 613b str r3, [r7, #16] tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); - 8002e5c: 4b20 ldr r3, [pc, #128] ; (8002ee0 ) - 8002e5e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8002e62: 0c1b lsrs r3, r3, #16 - 8002e64: f003 0303 and.w r3, r3, #3 - 8002e68: 60fb str r3, [r7, #12] + 8003b08: 4b20 ldr r3, [pc, #128] ; (8003b8c ) + 8003b0a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8003b0e: 0c1b lsrs r3, r3, #16 + 8003b10: f003 0303 and.w r3, r3, #3 + 8003b14: 60fb str r3, [r7, #12] /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR); - 8002e6a: 687b ldr r3, [r7, #4] - 8002e6c: 695b ldr r3, [r3, #20] - 8002e6e: 019a lsls r2, r3, #6 - 8002e70: 68fb ldr r3, [r7, #12] - 8002e72: 041b lsls r3, r3, #16 - 8002e74: 431a orrs r2, r3 - 8002e76: 693b ldr r3, [r7, #16] - 8002e78: 061b lsls r3, r3, #24 - 8002e7a: 431a orrs r2, r3 - 8002e7c: 687b ldr r3, [r7, #4] - 8002e7e: 69db ldr r3, [r3, #28] - 8002e80: 071b lsls r3, r3, #28 - 8002e82: 4917 ldr r1, [pc, #92] ; (8002ee0 ) - 8002e84: 4313 orrs r3, r2 - 8002e86: f8c1 3088 str.w r3, [r1, #136] ; 0x88 + 8003b16: 687b ldr r3, [r7, #4] + 8003b18: 695b ldr r3, [r3, #20] + 8003b1a: 019a lsls r2, r3, #6 + 8003b1c: 68fb ldr r3, [r7, #12] + 8003b1e: 041b lsls r3, r3, #16 + 8003b20: 431a orrs r2, r3 + 8003b22: 693b ldr r3, [r7, #16] + 8003b24: 061b lsls r3, r3, #24 + 8003b26: 431a orrs r2, r3 + 8003b28: 687b ldr r3, [r7, #4] + 8003b2a: 69db ldr r3, [r3, #28] + 8003b2c: 071b lsls r3, r3, #28 + 8003b2e: 4917 ldr r1, [pc, #92] ; (8003b8c ) + 8003b30: 4313 orrs r3, r2 + 8003b32: f8c1 3088 str.w r3, [r1, #136] ; 0x88 /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); - 8002e8a: 4b15 ldr r3, [pc, #84] ; (8002ee0 ) - 8002e8c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c - 8002e90: f423 3240 bic.w r2, r3, #196608 ; 0x30000 - 8002e94: 687b ldr r3, [r7, #4] - 8002e96: 6adb ldr r3, [r3, #44] ; 0x2c - 8002e98: 4911 ldr r1, [pc, #68] ; (8002ee0 ) - 8002e9a: 4313 orrs r3, r2 - 8002e9c: f8c1 308c str.w r3, [r1, #140] ; 0x8c + 8003b36: 4b15 ldr r3, [pc, #84] ; (8003b8c ) + 8003b38: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8003b3c: f423 3240 bic.w r2, r3, #196608 ; 0x30000 + 8003b40: 687b ldr r3, [r7, #4] + 8003b42: 6adb ldr r3, [r3, #44] ; 0x2c + 8003b44: 4911 ldr r1, [pc, #68] ; (8003b8c ) + 8003b46: 4313 orrs r3, r2 + 8003b48: f8c1 308c str.w r3, [r1, #140] ; 0x8c } #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); - 8002ea0: 4b0f ldr r3, [pc, #60] ; (8002ee0 ) - 8002ea2: 681b ldr r3, [r3, #0] - 8002ea4: 4a0e ldr r2, [pc, #56] ; (8002ee0 ) - 8002ea6: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 8002eaa: 6013 str r3, [r2, #0] + 8003b4c: 4b0f ldr r3, [pc, #60] ; (8003b8c ) + 8003b4e: 681b ldr r3, [r3, #0] + 8003b50: 4a0e ldr r2, [pc, #56] ; (8003b8c ) + 8003b52: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8003b56: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8002eac: f7fe f9c8 bl 8001240 - 8002eb0: 6178 str r0, [r7, #20] + 8003b58: f7fd ffca bl 8001af0 + 8003b5c: 6178 str r0, [r7, #20] /* Wait till PLLSAI is ready */ while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) - 8002eb2: e008 b.n 8002ec6 + 8003b5e: e008 b.n 8003b72 { if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) - 8002eb4: f7fe f9c4 bl 8001240 - 8002eb8: 4602 mov r2, r0 - 8002eba: 697b ldr r3, [r7, #20] - 8002ebc: 1ad3 subs r3, r2, r3 - 8002ebe: 2b64 cmp r3, #100 ; 0x64 - 8002ec0: d901 bls.n 8002ec6 + 8003b60: f7fd ffc6 bl 8001af0 + 8003b64: 4602 mov r2, r0 + 8003b66: 697b ldr r3, [r7, #20] + 8003b68: 1ad3 subs r3, r2, r3 + 8003b6a: 2b64 cmp r3, #100 ; 0x64 + 8003b6c: d901 bls.n 8003b72 { /* return in case of Timeout detected */ return HAL_TIMEOUT; - 8002ec2: 2303 movs r3, #3 - 8002ec4: e007 b.n 8002ed6 + 8003b6e: 2303 movs r3, #3 + 8003b70: e007 b.n 8003b82 while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) - 8002ec6: 4b06 ldr r3, [pc, #24] ; (8002ee0 ) - 8002ec8: 681b ldr r3, [r3, #0] - 8002eca: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 - 8002ece: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 - 8002ed2: d1ef bne.n 8002eb4 + 8003b72: 4b06 ldr r3, [pc, #24] ; (8003b8c ) + 8003b74: 681b ldr r3, [r3, #0] + 8003b76: f003 5300 and.w r3, r3, #536870912 ; 0x20000000 + 8003b7a: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 + 8003b7e: d1ef bne.n 8003b60 } } } return HAL_OK; - 8002ed4: 2300 movs r3, #0 + 8003b80: 2300 movs r3, #0 } - 8002ed6: 4618 mov r0, r3 - 8002ed8: 3720 adds r7, #32 - 8002eda: 46bd mov sp, r7 - 8002edc: bd80 pop {r7, pc} - 8002ede: bf00 nop - 8002ee0: 40023800 .word 0x40023800 - -08002ee4 : + 8003b82: 4618 mov r0, r3 + 8003b84: 3720 adds r7, #32 + 8003b86: 46bd mov sp, r7 + 8003b88: bd80 pop {r7, pc} + 8003b8a: bf00 nop + 8003b8c: 40023800 .word 0x40023800 + +08003b90 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { - 8002ee4: b580 push {r7, lr} - 8002ee6: b082 sub sp, #8 - 8002ee8: af00 add r7, sp, #0 - 8002eea: 6078 str r0, [r7, #4] + 8003b90: b580 push {r7, lr} + 8003b92: b082 sub sp, #8 + 8003b94: af00 add r7, sp, #0 + 8003b96: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) - 8002eec: 687b ldr r3, [r7, #4] - 8002eee: 2b00 cmp r3, #0 - 8002ef0: d101 bne.n 8002ef6 + 8003b98: 687b ldr r3, [r7, #4] + 8003b9a: 2b00 cmp r3, #0 + 8003b9c: d101 bne.n 8003ba2 { return HAL_ERROR; - 8002ef2: 2301 movs r3, #1 - 8002ef4: e040 b.n 8002f78 + 8003b9e: 2301 movs r3, #1 + 8003ba0: e040 b.n 8003c24 { /* Check the parameters */ assert_param(IS_UART_INSTANCE(huart->Instance)); } if (huart->gState == HAL_UART_STATE_RESET) - 8002ef6: 687b ldr r3, [r7, #4] - 8002ef8: 6f9b ldr r3, [r3, #120] ; 0x78 - 8002efa: 2b00 cmp r3, #0 - 8002efc: d106 bne.n 8002f0c + 8003ba2: 687b ldr r3, [r7, #4] + 8003ba4: 6f9b ldr r3, [r3, #120] ; 0x78 + 8003ba6: 2b00 cmp r3, #0 + 8003ba8: d106 bne.n 8003bb8 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - 8002efe: 687b ldr r3, [r7, #4] - 8002f00: 2200 movs r2, #0 - 8002f02: f883 2074 strb.w r2, [r3, #116] ; 0x74 + 8003baa: 687b ldr r3, [r7, #4] + 8003bac: 2200 movs r2, #0 + 8003bae: f883 2074 strb.w r2, [r3, #116] ; 0x74 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); - 8002f06: 6878 ldr r0, [r7, #4] - 8002f08: f7fd ffcc bl 8000ea4 + 8003bb2: 6878 ldr r0, [r7, #4] + 8003bb4: f7fd fdce bl 8001754 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; - 8002f0c: 687b ldr r3, [r7, #4] - 8002f0e: 2224 movs r2, #36 ; 0x24 - 8002f10: 679a str r2, [r3, #120] ; 0x78 + 8003bb8: 687b ldr r3, [r7, #4] + 8003bba: 2224 movs r2, #36 ; 0x24 + 8003bbc: 679a str r2, [r3, #120] ; 0x78 __HAL_UART_DISABLE(huart); - 8002f12: 687b ldr r3, [r7, #4] - 8002f14: 681b ldr r3, [r3, #0] - 8002f16: 681a ldr r2, [r3, #0] - 8002f18: 687b ldr r3, [r7, #4] - 8002f1a: 681b ldr r3, [r3, #0] - 8002f1c: f022 0201 bic.w r2, r2, #1 - 8002f20: 601a str r2, [r3, #0] + 8003bbe: 687b ldr r3, [r7, #4] + 8003bc0: 681b ldr r3, [r3, #0] + 8003bc2: 681a ldr r2, [r3, #0] + 8003bc4: 687b ldr r3, [r7, #4] + 8003bc6: 681b ldr r3, [r3, #0] + 8003bc8: f022 0201 bic.w r2, r2, #1 + 8003bcc: 601a str r2, [r3, #0] /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) - 8002f22: 6878 ldr r0, [r7, #4] - 8002f24: f000 f990 bl 8003248 - 8002f28: 4603 mov r3, r0 - 8002f2a: 2b01 cmp r3, #1 - 8002f2c: d101 bne.n 8002f32 + 8003bce: 6878 ldr r0, [r7, #4] + 8003bd0: f000 f990 bl 8003ef4 + 8003bd4: 4603 mov r3, r0 + 8003bd6: 2b01 cmp r3, #1 + 8003bd8: d101 bne.n 8003bde { return HAL_ERROR; - 8002f2e: 2301 movs r3, #1 - 8002f30: e022 b.n 8002f78 + 8003bda: 2301 movs r3, #1 + 8003bdc: e022 b.n 8003c24 } if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - 8002f32: 687b ldr r3, [r7, #4] - 8002f34: 6a5b ldr r3, [r3, #36] ; 0x24 - 8002f36: 2b00 cmp r3, #0 - 8002f38: d002 beq.n 8002f40 + 8003bde: 687b ldr r3, [r7, #4] + 8003be0: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003be2: 2b00 cmp r3, #0 + 8003be4: d002 beq.n 8003bec { UART_AdvFeatureConfig(huart); - 8002f3a: 6878 ldr r0, [r7, #4] - 8002f3c: f000 fbe6 bl 800370c + 8003be6: 6878 ldr r0, [r7, #4] + 8003be8: f000 fbe6 bl 80043b8 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - 8002f40: 687b ldr r3, [r7, #4] - 8002f42: 681b ldr r3, [r3, #0] - 8002f44: 685a ldr r2, [r3, #4] - 8002f46: 687b ldr r3, [r7, #4] - 8002f48: 681b ldr r3, [r3, #0] - 8002f4a: f422 4290 bic.w r2, r2, #18432 ; 0x4800 - 8002f4e: 605a str r2, [r3, #4] + 8003bec: 687b ldr r3, [r7, #4] + 8003bee: 681b ldr r3, [r3, #0] + 8003bf0: 685a ldr r2, [r3, #4] + 8003bf2: 687b ldr r3, [r7, #4] + 8003bf4: 681b ldr r3, [r3, #0] + 8003bf6: f422 4290 bic.w r2, r2, #18432 ; 0x4800 + 8003bfa: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - 8002f50: 687b ldr r3, [r7, #4] - 8002f52: 681b ldr r3, [r3, #0] - 8002f54: 689a ldr r2, [r3, #8] - 8002f56: 687b ldr r3, [r7, #4] - 8002f58: 681b ldr r3, [r3, #0] - 8002f5a: f022 022a bic.w r2, r2, #42 ; 0x2a - 8002f5e: 609a str r2, [r3, #8] + 8003bfc: 687b ldr r3, [r7, #4] + 8003bfe: 681b ldr r3, [r3, #0] + 8003c00: 689a ldr r2, [r3, #8] + 8003c02: 687b ldr r3, [r7, #4] + 8003c04: 681b ldr r3, [r3, #0] + 8003c06: f022 022a bic.w r2, r2, #42 ; 0x2a + 8003c0a: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); - 8002f60: 687b ldr r3, [r7, #4] - 8002f62: 681b ldr r3, [r3, #0] - 8002f64: 681a ldr r2, [r3, #0] - 8002f66: 687b ldr r3, [r7, #4] - 8002f68: 681b ldr r3, [r3, #0] - 8002f6a: f042 0201 orr.w r2, r2, #1 - 8002f6e: 601a str r2, [r3, #0] + 8003c0c: 687b ldr r3, [r7, #4] + 8003c0e: 681b ldr r3, [r3, #0] + 8003c10: 681a ldr r2, [r3, #0] + 8003c12: 687b ldr r3, [r7, #4] + 8003c14: 681b ldr r3, [r3, #0] + 8003c16: f042 0201 orr.w r2, r2, #1 + 8003c1a: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); - 8002f70: 6878 ldr r0, [r7, #4] - 8002f72: f000 fc6d bl 8003850 - 8002f76: 4603 mov r3, r0 + 8003c1c: 6878 ldr r0, [r7, #4] + 8003c1e: f000 fc6d bl 80044fc + 8003c22: 4603 mov r3, r0 } - 8002f78: 4618 mov r0, r3 - 8002f7a: 3708 adds r7, #8 - 8002f7c: 46bd mov sp, r7 - 8002f7e: bd80 pop {r7, pc} + 8003c24: 4618 mov r0, r3 + 8003c26: 3708 adds r7, #8 + 8003c28: 46bd mov sp, r7 + 8003c2a: bd80 pop {r7, pc} -08002f80 : +08003c2c : * @param Size Amount of data elements (u8 or u16) to be sent. * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - 8002f80: b580 push {r7, lr} - 8002f82: b08a sub sp, #40 ; 0x28 - 8002f84: af02 add r7, sp, #8 - 8002f86: 60f8 str r0, [r7, #12] - 8002f88: 60b9 str r1, [r7, #8] - 8002f8a: 603b str r3, [r7, #0] - 8002f8c: 4613 mov r3, r2 - 8002f8e: 80fb strh r3, [r7, #6] + 8003c2c: b580 push {r7, lr} + 8003c2e: b08a sub sp, #40 ; 0x28 + 8003c30: af02 add r7, sp, #8 + 8003c32: 60f8 str r0, [r7, #12] + 8003c34: 60b9 str r1, [r7, #8] + 8003c36: 603b str r3, [r7, #0] + 8003c38: 4613 mov r3, r2 + 8003c3a: 80fb strh r3, [r7, #6] uint8_t *pdata8bits; uint16_t *pdata16bits; uint32_t tickstart; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) - 8002f90: 68fb ldr r3, [r7, #12] - 8002f92: 6f9b ldr r3, [r3, #120] ; 0x78 - 8002f94: 2b20 cmp r3, #32 - 8002f96: f040 8081 bne.w 800309c + 8003c3c: 68fb ldr r3, [r7, #12] + 8003c3e: 6f9b ldr r3, [r3, #120] ; 0x78 + 8003c40: 2b20 cmp r3, #32 + 8003c42: f040 8081 bne.w 8003d48 { if ((pData == NULL) || (Size == 0U)) - 8002f9a: 68bb ldr r3, [r7, #8] - 8002f9c: 2b00 cmp r3, #0 - 8002f9e: d002 beq.n 8002fa6 - 8002fa0: 88fb ldrh r3, [r7, #6] - 8002fa2: 2b00 cmp r3, #0 - 8002fa4: d101 bne.n 8002faa + 8003c46: 68bb ldr r3, [r7, #8] + 8003c48: 2b00 cmp r3, #0 + 8003c4a: d002 beq.n 8003c52 + 8003c4c: 88fb ldrh r3, [r7, #6] + 8003c4e: 2b00 cmp r3, #0 + 8003c50: d101 bne.n 8003c56 { return HAL_ERROR; - 8002fa6: 2301 movs r3, #1 - 8002fa8: e079 b.n 800309e + 8003c52: 2301 movs r3, #1 + 8003c54: e079 b.n 8003d4a } __HAL_LOCK(huart); - 8002faa: 68fb ldr r3, [r7, #12] - 8002fac: f893 3074 ldrb.w r3, [r3, #116] ; 0x74 - 8002fb0: 2b01 cmp r3, #1 - 8002fb2: d101 bne.n 8002fb8 - 8002fb4: 2302 movs r3, #2 - 8002fb6: e072 b.n 800309e - 8002fb8: 68fb ldr r3, [r7, #12] - 8002fba: 2201 movs r2, #1 - 8002fbc: f883 2074 strb.w r2, [r3, #116] ; 0x74 + 8003c56: 68fb ldr r3, [r7, #12] + 8003c58: f893 3074 ldrb.w r3, [r3, #116] ; 0x74 + 8003c5c: 2b01 cmp r3, #1 + 8003c5e: d101 bne.n 8003c64 + 8003c60: 2302 movs r3, #2 + 8003c62: e072 b.n 8003d4a + 8003c64: 68fb ldr r3, [r7, #12] + 8003c66: 2201 movs r2, #1 + 8003c68: f883 2074 strb.w r2, [r3, #116] ; 0x74 huart->ErrorCode = HAL_UART_ERROR_NONE; - 8002fc0: 68fb ldr r3, [r7, #12] - 8002fc2: 2200 movs r2, #0 - 8002fc4: f8c3 2080 str.w r2, [r3, #128] ; 0x80 + 8003c6c: 68fb ldr r3, [r7, #12] + 8003c6e: 2200 movs r2, #0 + 8003c70: f8c3 2080 str.w r2, [r3, #128] ; 0x80 huart->gState = HAL_UART_STATE_BUSY_TX; - 8002fc8: 68fb ldr r3, [r7, #12] - 8002fca: 2221 movs r2, #33 ; 0x21 - 8002fcc: 679a str r2, [r3, #120] ; 0x78 + 8003c74: 68fb ldr r3, [r7, #12] + 8003c76: 2221 movs r2, #33 ; 0x21 + 8003c78: 679a str r2, [r3, #120] ; 0x78 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - 8002fce: f7fe f937 bl 8001240 - 8002fd2: 6178 str r0, [r7, #20] + 8003c7a: f7fd ff39 bl 8001af0 + 8003c7e: 6178 str r0, [r7, #20] huart->TxXferSize = Size; - 8002fd4: 68fb ldr r3, [r7, #12] - 8002fd6: 88fa ldrh r2, [r7, #6] - 8002fd8: f8a3 2050 strh.w r2, [r3, #80] ; 0x50 + 8003c80: 68fb ldr r3, [r7, #12] + 8003c82: 88fa ldrh r2, [r7, #6] + 8003c84: f8a3 2050 strh.w r2, [r3, #80] ; 0x50 huart->TxXferCount = Size; - 8002fdc: 68fb ldr r3, [r7, #12] - 8002fde: 88fa ldrh r2, [r7, #6] - 8002fe0: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 + 8003c88: 68fb ldr r3, [r7, #12] + 8003c8a: 88fa ldrh r2, [r7, #6] + 8003c8c: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - 8002fe4: 68fb ldr r3, [r7, #12] - 8002fe6: 689b ldr r3, [r3, #8] - 8002fe8: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 - 8002fec: d108 bne.n 8003000 - 8002fee: 68fb ldr r3, [r7, #12] - 8002ff0: 691b ldr r3, [r3, #16] - 8002ff2: 2b00 cmp r3, #0 - 8002ff4: d104 bne.n 8003000 + 8003c90: 68fb ldr r3, [r7, #12] + 8003c92: 689b ldr r3, [r3, #8] + 8003c94: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8003c98: d108 bne.n 8003cac + 8003c9a: 68fb ldr r3, [r7, #12] + 8003c9c: 691b ldr r3, [r3, #16] + 8003c9e: 2b00 cmp r3, #0 + 8003ca0: d104 bne.n 8003cac { pdata8bits = NULL; - 8002ff6: 2300 movs r3, #0 - 8002ff8: 61fb str r3, [r7, #28] + 8003ca2: 2300 movs r3, #0 + 8003ca4: 61fb str r3, [r7, #28] pdata16bits = (uint16_t *) pData; - 8002ffa: 68bb ldr r3, [r7, #8] - 8002ffc: 61bb str r3, [r7, #24] - 8002ffe: e003 b.n 8003008 + 8003ca6: 68bb ldr r3, [r7, #8] + 8003ca8: 61bb str r3, [r7, #24] + 8003caa: e003 b.n 8003cb4 } else { pdata8bits = pData; - 8003000: 68bb ldr r3, [r7, #8] - 8003002: 61fb str r3, [r7, #28] + 8003cac: 68bb ldr r3, [r7, #8] + 8003cae: 61fb str r3, [r7, #28] pdata16bits = NULL; - 8003004: 2300 movs r3, #0 - 8003006: 61bb str r3, [r7, #24] + 8003cb0: 2300 movs r3, #0 + 8003cb2: 61bb str r3, [r7, #24] } __HAL_UNLOCK(huart); - 8003008: 68fb ldr r3, [r7, #12] - 800300a: 2200 movs r2, #0 - 800300c: f883 2074 strb.w r2, [r3, #116] ; 0x74 + 8003cb4: 68fb ldr r3, [r7, #12] + 8003cb6: 2200 movs r2, #0 + 8003cb8: f883 2074 strb.w r2, [r3, #116] ; 0x74 while (huart->TxXferCount > 0U) - 8003010: e02c b.n 800306c + 8003cbc: e02c b.n 8003d18 { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - 8003012: 683b ldr r3, [r7, #0] - 8003014: 9300 str r3, [sp, #0] - 8003016: 697b ldr r3, [r7, #20] - 8003018: 2200 movs r2, #0 - 800301a: 2180 movs r1, #128 ; 0x80 - 800301c: 68f8 ldr r0, [r7, #12] - 800301e: f000 fc60 bl 80038e2 - 8003022: 4603 mov r3, r0 - 8003024: 2b00 cmp r3, #0 - 8003026: d001 beq.n 800302c + 8003cbe: 683b ldr r3, [r7, #0] + 8003cc0: 9300 str r3, [sp, #0] + 8003cc2: 697b ldr r3, [r7, #20] + 8003cc4: 2200 movs r2, #0 + 8003cc6: 2180 movs r1, #128 ; 0x80 + 8003cc8: 68f8 ldr r0, [r7, #12] + 8003cca: f000 fc60 bl 800458e + 8003cce: 4603 mov r3, r0 + 8003cd0: 2b00 cmp r3, #0 + 8003cd2: d001 beq.n 8003cd8 { return HAL_TIMEOUT; - 8003028: 2303 movs r3, #3 - 800302a: e038 b.n 800309e + 8003cd4: 2303 movs r3, #3 + 8003cd6: e038 b.n 8003d4a } if (pdata8bits == NULL) - 800302c: 69fb ldr r3, [r7, #28] - 800302e: 2b00 cmp r3, #0 - 8003030: d10b bne.n 800304a + 8003cd8: 69fb ldr r3, [r7, #28] + 8003cda: 2b00 cmp r3, #0 + 8003cdc: d10b bne.n 8003cf6 { huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); - 8003032: 69bb ldr r3, [r7, #24] - 8003034: 881b ldrh r3, [r3, #0] - 8003036: 461a mov r2, r3 - 8003038: 68fb ldr r3, [r7, #12] - 800303a: 681b ldr r3, [r3, #0] - 800303c: f3c2 0208 ubfx r2, r2, #0, #9 - 8003040: 629a str r2, [r3, #40] ; 0x28 + 8003cde: 69bb ldr r3, [r7, #24] + 8003ce0: 881b ldrh r3, [r3, #0] + 8003ce2: 461a mov r2, r3 + 8003ce4: 68fb ldr r3, [r7, #12] + 8003ce6: 681b ldr r3, [r3, #0] + 8003ce8: f3c2 0208 ubfx r2, r2, #0, #9 + 8003cec: 629a str r2, [r3, #40] ; 0x28 pdata16bits++; - 8003042: 69bb ldr r3, [r7, #24] - 8003044: 3302 adds r3, #2 - 8003046: 61bb str r3, [r7, #24] - 8003048: e007 b.n 800305a + 8003cee: 69bb ldr r3, [r7, #24] + 8003cf0: 3302 adds r3, #2 + 8003cf2: 61bb str r3, [r7, #24] + 8003cf4: e007 b.n 8003d06 } else { huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); - 800304a: 69fb ldr r3, [r7, #28] - 800304c: 781a ldrb r2, [r3, #0] - 800304e: 68fb ldr r3, [r7, #12] - 8003050: 681b ldr r3, [r3, #0] - 8003052: 629a str r2, [r3, #40] ; 0x28 + 8003cf6: 69fb ldr r3, [r7, #28] + 8003cf8: 781a ldrb r2, [r3, #0] + 8003cfa: 68fb ldr r3, [r7, #12] + 8003cfc: 681b ldr r3, [r3, #0] + 8003cfe: 629a str r2, [r3, #40] ; 0x28 pdata8bits++; - 8003054: 69fb ldr r3, [r7, #28] - 8003056: 3301 adds r3, #1 - 8003058: 61fb str r3, [r7, #28] + 8003d00: 69fb ldr r3, [r7, #28] + 8003d02: 3301 adds r3, #1 + 8003d04: 61fb str r3, [r7, #28] } huart->TxXferCount--; - 800305a: 68fb ldr r3, [r7, #12] - 800305c: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52 - 8003060: b29b uxth r3, r3 - 8003062: 3b01 subs r3, #1 - 8003064: b29a uxth r2, r3 - 8003066: 68fb ldr r3, [r7, #12] - 8003068: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 + 8003d06: 68fb ldr r3, [r7, #12] + 8003d08: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52 + 8003d0c: b29b uxth r3, r3 + 8003d0e: 3b01 subs r3, #1 + 8003d10: b29a uxth r2, r3 + 8003d12: 68fb ldr r3, [r7, #12] + 8003d14: f8a3 2052 strh.w r2, [r3, #82] ; 0x52 while (huart->TxXferCount > 0U) - 800306c: 68fb ldr r3, [r7, #12] - 800306e: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52 - 8003072: b29b uxth r3, r3 - 8003074: 2b00 cmp r3, #0 - 8003076: d1cc bne.n 8003012 + 8003d18: 68fb ldr r3, [r7, #12] + 8003d1a: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52 + 8003d1e: b29b uxth r3, r3 + 8003d20: 2b00 cmp r3, #0 + 8003d22: d1cc bne.n 8003cbe } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) - 8003078: 683b ldr r3, [r7, #0] - 800307a: 9300 str r3, [sp, #0] - 800307c: 697b ldr r3, [r7, #20] - 800307e: 2200 movs r2, #0 - 8003080: 2140 movs r1, #64 ; 0x40 - 8003082: 68f8 ldr r0, [r7, #12] - 8003084: f000 fc2d bl 80038e2 - 8003088: 4603 mov r3, r0 - 800308a: 2b00 cmp r3, #0 - 800308c: d001 beq.n 8003092 + 8003d24: 683b ldr r3, [r7, #0] + 8003d26: 9300 str r3, [sp, #0] + 8003d28: 697b ldr r3, [r7, #20] + 8003d2a: 2200 movs r2, #0 + 8003d2c: 2140 movs r1, #64 ; 0x40 + 8003d2e: 68f8 ldr r0, [r7, #12] + 8003d30: f000 fc2d bl 800458e + 8003d34: 4603 mov r3, r0 + 8003d36: 2b00 cmp r3, #0 + 8003d38: d001 beq.n 8003d3e { return HAL_TIMEOUT; - 800308e: 2303 movs r3, #3 - 8003090: e005 b.n 800309e + 8003d3a: 2303 movs r3, #3 + 8003d3c: e005 b.n 8003d4a } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - 8003092: 68fb ldr r3, [r7, #12] - 8003094: 2220 movs r2, #32 - 8003096: 679a str r2, [r3, #120] ; 0x78 + 8003d3e: 68fb ldr r3, [r7, #12] + 8003d40: 2220 movs r2, #32 + 8003d42: 679a str r2, [r3, #120] ; 0x78 return HAL_OK; - 8003098: 2300 movs r3, #0 - 800309a: e000 b.n 800309e + 8003d44: 2300 movs r3, #0 + 8003d46: e000 b.n 8003d4a } else { return HAL_BUSY; - 800309c: 2302 movs r3, #2 + 8003d48: 2302 movs r3, #2 } } - 800309e: 4618 mov r0, r3 - 80030a0: 3720 adds r7, #32 - 80030a2: 46bd mov sp, r7 - 80030a4: bd80 pop {r7, pc} + 8003d4a: 4618 mov r0, r3 + 8003d4c: 3720 adds r7, #32 + 8003d4e: 46bd mov sp, r7 + 8003d50: bd80 pop {r7, pc} -080030a6 : +08003d52 : * @param Size Amount of data elements (u8 or u16) to be received. * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - 80030a6: b580 push {r7, lr} - 80030a8: b08a sub sp, #40 ; 0x28 - 80030aa: af02 add r7, sp, #8 - 80030ac: 60f8 str r0, [r7, #12] - 80030ae: 60b9 str r1, [r7, #8] - 80030b0: 603b str r3, [r7, #0] - 80030b2: 4613 mov r3, r2 - 80030b4: 80fb strh r3, [r7, #6] + 8003d52: b580 push {r7, lr} + 8003d54: b08a sub sp, #40 ; 0x28 + 8003d56: af02 add r7, sp, #8 + 8003d58: 60f8 str r0, [r7, #12] + 8003d5a: 60b9 str r1, [r7, #8] + 8003d5c: 603b str r3, [r7, #0] + 8003d5e: 4613 mov r3, r2 + 8003d60: 80fb strh r3, [r7, #6] uint16_t *pdata16bits; uint16_t uhMask; uint32_t tickstart; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) - 80030b6: 68fb ldr r3, [r7, #12] - 80030b8: 6fdb ldr r3, [r3, #124] ; 0x7c - 80030ba: 2b20 cmp r3, #32 - 80030bc: f040 80be bne.w 800323c + 8003d62: 68fb ldr r3, [r7, #12] + 8003d64: 6fdb ldr r3, [r3, #124] ; 0x7c + 8003d66: 2b20 cmp r3, #32 + 8003d68: f040 80be bne.w 8003ee8 { if ((pData == NULL) || (Size == 0U)) - 80030c0: 68bb ldr r3, [r7, #8] - 80030c2: 2b00 cmp r3, #0 - 80030c4: d002 beq.n 80030cc - 80030c6: 88fb ldrh r3, [r7, #6] - 80030c8: 2b00 cmp r3, #0 - 80030ca: d101 bne.n 80030d0 + 8003d6c: 68bb ldr r3, [r7, #8] + 8003d6e: 2b00 cmp r3, #0 + 8003d70: d002 beq.n 8003d78 + 8003d72: 88fb ldrh r3, [r7, #6] + 8003d74: 2b00 cmp r3, #0 + 8003d76: d101 bne.n 8003d7c { return HAL_ERROR; - 80030cc: 2301 movs r3, #1 - 80030ce: e0b6 b.n 800323e + 8003d78: 2301 movs r3, #1 + 8003d7a: e0b6 b.n 8003eea } __HAL_LOCK(huart); - 80030d0: 68fb ldr r3, [r7, #12] - 80030d2: f893 3074 ldrb.w r3, [r3, #116] ; 0x74 - 80030d6: 2b01 cmp r3, #1 - 80030d8: d101 bne.n 80030de - 80030da: 2302 movs r3, #2 - 80030dc: e0af b.n 800323e - 80030de: 68fb ldr r3, [r7, #12] - 80030e0: 2201 movs r2, #1 - 80030e2: f883 2074 strb.w r2, [r3, #116] ; 0x74 + 8003d7c: 68fb ldr r3, [r7, #12] + 8003d7e: f893 3074 ldrb.w r3, [r3, #116] ; 0x74 + 8003d82: 2b01 cmp r3, #1 + 8003d84: d101 bne.n 8003d8a + 8003d86: 2302 movs r3, #2 + 8003d88: e0af b.n 8003eea + 8003d8a: 68fb ldr r3, [r7, #12] + 8003d8c: 2201 movs r2, #1 + 8003d8e: f883 2074 strb.w r2, [r3, #116] ; 0x74 huart->ErrorCode = HAL_UART_ERROR_NONE; - 80030e6: 68fb ldr r3, [r7, #12] - 80030e8: 2200 movs r2, #0 - 80030ea: f8c3 2080 str.w r2, [r3, #128] ; 0x80 + 8003d92: 68fb ldr r3, [r7, #12] + 8003d94: 2200 movs r2, #0 + 8003d96: f8c3 2080 str.w r2, [r3, #128] ; 0x80 huart->RxState = HAL_UART_STATE_BUSY_RX; - 80030ee: 68fb ldr r3, [r7, #12] - 80030f0: 2222 movs r2, #34 ; 0x22 - 80030f2: 67da str r2, [r3, #124] ; 0x7c + 8003d9a: 68fb ldr r3, [r7, #12] + 8003d9c: 2222 movs r2, #34 ; 0x22 + 8003d9e: 67da str r2, [r3, #124] ; 0x7c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 80030f4: 68fb ldr r3, [r7, #12] - 80030f6: 2200 movs r2, #0 - 80030f8: 661a str r2, [r3, #96] ; 0x60 + 8003da0: 68fb ldr r3, [r7, #12] + 8003da2: 2200 movs r2, #0 + 8003da4: 661a str r2, [r3, #96] ; 0x60 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - 80030fa: f7fe f8a1 bl 8001240 - 80030fe: 6178 str r0, [r7, #20] + 8003da6: f7fd fea3 bl 8001af0 + 8003daa: 6178 str r0, [r7, #20] huart->RxXferSize = Size; - 8003100: 68fb ldr r3, [r7, #12] - 8003102: 88fa ldrh r2, [r7, #6] - 8003104: f8a3 2058 strh.w r2, [r3, #88] ; 0x58 + 8003dac: 68fb ldr r3, [r7, #12] + 8003dae: 88fa ldrh r2, [r7, #6] + 8003db0: f8a3 2058 strh.w r2, [r3, #88] ; 0x58 huart->RxXferCount = Size; - 8003108: 68fb ldr r3, [r7, #12] - 800310a: 88fa ldrh r2, [r7, #6] - 800310c: f8a3 205a strh.w r2, [r3, #90] ; 0x5a + 8003db4: 68fb ldr r3, [r7, #12] + 8003db6: 88fa ldrh r2, [r7, #6] + 8003db8: f8a3 205a strh.w r2, [r3, #90] ; 0x5a /* Computation of UART mask to apply to RDR register */ UART_MASK_COMPUTATION(huart); - 8003110: 68fb ldr r3, [r7, #12] - 8003112: 689b ldr r3, [r3, #8] - 8003114: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 - 8003118: d10e bne.n 8003138 - 800311a: 68fb ldr r3, [r7, #12] - 800311c: 691b ldr r3, [r3, #16] - 800311e: 2b00 cmp r3, #0 - 8003120: d105 bne.n 800312e - 8003122: 68fb ldr r3, [r7, #12] - 8003124: f240 12ff movw r2, #511 ; 0x1ff - 8003128: f8a3 205c strh.w r2, [r3, #92] ; 0x5c - 800312c: e02d b.n 800318a - 800312e: 68fb ldr r3, [r7, #12] - 8003130: 22ff movs r2, #255 ; 0xff - 8003132: f8a3 205c strh.w r2, [r3, #92] ; 0x5c - 8003136: e028 b.n 800318a - 8003138: 68fb ldr r3, [r7, #12] - 800313a: 689b ldr r3, [r3, #8] - 800313c: 2b00 cmp r3, #0 - 800313e: d10d bne.n 800315c - 8003140: 68fb ldr r3, [r7, #12] - 8003142: 691b ldr r3, [r3, #16] - 8003144: 2b00 cmp r3, #0 - 8003146: d104 bne.n 8003152 - 8003148: 68fb ldr r3, [r7, #12] - 800314a: 22ff movs r2, #255 ; 0xff - 800314c: f8a3 205c strh.w r2, [r3, #92] ; 0x5c - 8003150: e01b b.n 800318a - 8003152: 68fb ldr r3, [r7, #12] - 8003154: 227f movs r2, #127 ; 0x7f - 8003156: f8a3 205c strh.w r2, [r3, #92] ; 0x5c - 800315a: e016 b.n 800318a - 800315c: 68fb ldr r3, [r7, #12] - 800315e: 689b ldr r3, [r3, #8] - 8003160: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 - 8003164: d10d bne.n 8003182 - 8003166: 68fb ldr r3, [r7, #12] - 8003168: 691b ldr r3, [r3, #16] - 800316a: 2b00 cmp r3, #0 - 800316c: d104 bne.n 8003178 - 800316e: 68fb ldr r3, [r7, #12] - 8003170: 227f movs r2, #127 ; 0x7f - 8003172: f8a3 205c strh.w r2, [r3, #92] ; 0x5c - 8003176: e008 b.n 800318a - 8003178: 68fb ldr r3, [r7, #12] - 800317a: 223f movs r2, #63 ; 0x3f - 800317c: f8a3 205c strh.w r2, [r3, #92] ; 0x5c - 8003180: e003 b.n 800318a - 8003182: 68fb ldr r3, [r7, #12] - 8003184: 2200 movs r2, #0 - 8003186: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 8003dbc: 68fb ldr r3, [r7, #12] + 8003dbe: 689b ldr r3, [r3, #8] + 8003dc0: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8003dc4: d10e bne.n 8003de4 + 8003dc6: 68fb ldr r3, [r7, #12] + 8003dc8: 691b ldr r3, [r3, #16] + 8003dca: 2b00 cmp r3, #0 + 8003dcc: d105 bne.n 8003dda + 8003dce: 68fb ldr r3, [r7, #12] + 8003dd0: f240 12ff movw r2, #511 ; 0x1ff + 8003dd4: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 8003dd8: e02d b.n 8003e36 + 8003dda: 68fb ldr r3, [r7, #12] + 8003ddc: 22ff movs r2, #255 ; 0xff + 8003dde: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 8003de2: e028 b.n 8003e36 + 8003de4: 68fb ldr r3, [r7, #12] + 8003de6: 689b ldr r3, [r3, #8] + 8003de8: 2b00 cmp r3, #0 + 8003dea: d10d bne.n 8003e08 + 8003dec: 68fb ldr r3, [r7, #12] + 8003dee: 691b ldr r3, [r3, #16] + 8003df0: 2b00 cmp r3, #0 + 8003df2: d104 bne.n 8003dfe + 8003df4: 68fb ldr r3, [r7, #12] + 8003df6: 22ff movs r2, #255 ; 0xff + 8003df8: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 8003dfc: e01b b.n 8003e36 + 8003dfe: 68fb ldr r3, [r7, #12] + 8003e00: 227f movs r2, #127 ; 0x7f + 8003e02: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 8003e06: e016 b.n 8003e36 + 8003e08: 68fb ldr r3, [r7, #12] + 8003e0a: 689b ldr r3, [r3, #8] + 8003e0c: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 + 8003e10: d10d bne.n 8003e2e + 8003e12: 68fb ldr r3, [r7, #12] + 8003e14: 691b ldr r3, [r3, #16] + 8003e16: 2b00 cmp r3, #0 + 8003e18: d104 bne.n 8003e24 + 8003e1a: 68fb ldr r3, [r7, #12] + 8003e1c: 227f movs r2, #127 ; 0x7f + 8003e1e: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 8003e22: e008 b.n 8003e36 + 8003e24: 68fb ldr r3, [r7, #12] + 8003e26: 223f movs r2, #63 ; 0x3f + 8003e28: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + 8003e2c: e003 b.n 8003e36 + 8003e2e: 68fb ldr r3, [r7, #12] + 8003e30: 2200 movs r2, #0 + 8003e32: f8a3 205c strh.w r2, [r3, #92] ; 0x5c uhMask = huart->Mask; - 800318a: 68fb ldr r3, [r7, #12] - 800318c: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c - 8003190: 827b strh r3, [r7, #18] + 8003e36: 68fb ldr r3, [r7, #12] + 8003e38: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c + 8003e3c: 827b strh r3, [r7, #18] /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - 8003192: 68fb ldr r3, [r7, #12] - 8003194: 689b ldr r3, [r3, #8] - 8003196: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 - 800319a: d108 bne.n 80031ae - 800319c: 68fb ldr r3, [r7, #12] - 800319e: 691b ldr r3, [r3, #16] - 80031a0: 2b00 cmp r3, #0 - 80031a2: d104 bne.n 80031ae + 8003e3e: 68fb ldr r3, [r7, #12] + 8003e40: 689b ldr r3, [r3, #8] + 8003e42: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8003e46: d108 bne.n 8003e5a + 8003e48: 68fb ldr r3, [r7, #12] + 8003e4a: 691b ldr r3, [r3, #16] + 8003e4c: 2b00 cmp r3, #0 + 8003e4e: d104 bne.n 8003e5a { pdata8bits = NULL; - 80031a4: 2300 movs r3, #0 - 80031a6: 61fb str r3, [r7, #28] + 8003e50: 2300 movs r3, #0 + 8003e52: 61fb str r3, [r7, #28] pdata16bits = (uint16_t *) pData; - 80031a8: 68bb ldr r3, [r7, #8] - 80031aa: 61bb str r3, [r7, #24] - 80031ac: e003 b.n 80031b6 + 8003e54: 68bb ldr r3, [r7, #8] + 8003e56: 61bb str r3, [r7, #24] + 8003e58: e003 b.n 8003e62 } else { pdata8bits = pData; - 80031ae: 68bb ldr r3, [r7, #8] - 80031b0: 61fb str r3, [r7, #28] + 8003e5a: 68bb ldr r3, [r7, #8] + 8003e5c: 61fb str r3, [r7, #28] pdata16bits = NULL; - 80031b2: 2300 movs r3, #0 - 80031b4: 61bb str r3, [r7, #24] + 8003e5e: 2300 movs r3, #0 + 8003e60: 61bb str r3, [r7, #24] } __HAL_UNLOCK(huart); - 80031b6: 68fb ldr r3, [r7, #12] - 80031b8: 2200 movs r2, #0 - 80031ba: f883 2074 strb.w r2, [r3, #116] ; 0x74 + 8003e62: 68fb ldr r3, [r7, #12] + 8003e64: 2200 movs r2, #0 + 8003e66: f883 2074 strb.w r2, [r3, #116] ; 0x74 /* as long as data have to be received */ while (huart->RxXferCount > 0U) - 80031be: e032 b.n 8003226 + 8003e6a: e032 b.n 8003ed2 { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) - 80031c0: 683b ldr r3, [r7, #0] - 80031c2: 9300 str r3, [sp, #0] - 80031c4: 697b ldr r3, [r7, #20] - 80031c6: 2200 movs r2, #0 - 80031c8: 2120 movs r1, #32 - 80031ca: 68f8 ldr r0, [r7, #12] - 80031cc: f000 fb89 bl 80038e2 - 80031d0: 4603 mov r3, r0 - 80031d2: 2b00 cmp r3, #0 - 80031d4: d001 beq.n 80031da + 8003e6c: 683b ldr r3, [r7, #0] + 8003e6e: 9300 str r3, [sp, #0] + 8003e70: 697b ldr r3, [r7, #20] + 8003e72: 2200 movs r2, #0 + 8003e74: 2120 movs r1, #32 + 8003e76: 68f8 ldr r0, [r7, #12] + 8003e78: f000 fb89 bl 800458e + 8003e7c: 4603 mov r3, r0 + 8003e7e: 2b00 cmp r3, #0 + 8003e80: d001 beq.n 8003e86 { return HAL_TIMEOUT; - 80031d6: 2303 movs r3, #3 - 80031d8: e031 b.n 800323e + 8003e82: 2303 movs r3, #3 + 8003e84: e031 b.n 8003eea } if (pdata8bits == NULL) - 80031da: 69fb ldr r3, [r7, #28] - 80031dc: 2b00 cmp r3, #0 - 80031de: d10c bne.n 80031fa + 8003e86: 69fb ldr r3, [r7, #28] + 8003e88: 2b00 cmp r3, #0 + 8003e8a: d10c bne.n 8003ea6 { *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); - 80031e0: 68fb ldr r3, [r7, #12] - 80031e2: 681b ldr r3, [r3, #0] - 80031e4: 6a5b ldr r3, [r3, #36] ; 0x24 - 80031e6: b29a uxth r2, r3 - 80031e8: 8a7b ldrh r3, [r7, #18] - 80031ea: 4013 ands r3, r2 - 80031ec: b29a uxth r2, r3 - 80031ee: 69bb ldr r3, [r7, #24] - 80031f0: 801a strh r2, [r3, #0] + 8003e8c: 68fb ldr r3, [r7, #12] + 8003e8e: 681b ldr r3, [r3, #0] + 8003e90: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003e92: b29a uxth r2, r3 + 8003e94: 8a7b ldrh r3, [r7, #18] + 8003e96: 4013 ands r3, r2 + 8003e98: b29a uxth r2, r3 + 8003e9a: 69bb ldr r3, [r7, #24] + 8003e9c: 801a strh r2, [r3, #0] pdata16bits++; - 80031f2: 69bb ldr r3, [r7, #24] - 80031f4: 3302 adds r3, #2 - 80031f6: 61bb str r3, [r7, #24] - 80031f8: e00c b.n 8003214 + 8003e9e: 69bb ldr r3, [r7, #24] + 8003ea0: 3302 adds r3, #2 + 8003ea2: 61bb str r3, [r7, #24] + 8003ea4: e00c b.n 8003ec0 } else { *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); - 80031fa: 68fb ldr r3, [r7, #12] - 80031fc: 681b ldr r3, [r3, #0] - 80031fe: 6a5b ldr r3, [r3, #36] ; 0x24 - 8003200: b2da uxtb r2, r3 - 8003202: 8a7b ldrh r3, [r7, #18] - 8003204: b2db uxtb r3, r3 - 8003206: 4013 ands r3, r2 - 8003208: b2da uxtb r2, r3 - 800320a: 69fb ldr r3, [r7, #28] - 800320c: 701a strb r2, [r3, #0] + 8003ea6: 68fb ldr r3, [r7, #12] + 8003ea8: 681b ldr r3, [r3, #0] + 8003eaa: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003eac: b2da uxtb r2, r3 + 8003eae: 8a7b ldrh r3, [r7, #18] + 8003eb0: b2db uxtb r3, r3 + 8003eb2: 4013 ands r3, r2 + 8003eb4: b2da uxtb r2, r3 + 8003eb6: 69fb ldr r3, [r7, #28] + 8003eb8: 701a strb r2, [r3, #0] pdata8bits++; - 800320e: 69fb ldr r3, [r7, #28] - 8003210: 3301 adds r3, #1 - 8003212: 61fb str r3, [r7, #28] + 8003eba: 69fb ldr r3, [r7, #28] + 8003ebc: 3301 adds r3, #1 + 8003ebe: 61fb str r3, [r7, #28] } huart->RxXferCount--; - 8003214: 68fb ldr r3, [r7, #12] - 8003216: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a - 800321a: b29b uxth r3, r3 - 800321c: 3b01 subs r3, #1 - 800321e: b29a uxth r2, r3 - 8003220: 68fb ldr r3, [r7, #12] - 8003222: f8a3 205a strh.w r2, [r3, #90] ; 0x5a + 8003ec0: 68fb ldr r3, [r7, #12] + 8003ec2: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a + 8003ec6: b29b uxth r3, r3 + 8003ec8: 3b01 subs r3, #1 + 8003eca: b29a uxth r2, r3 + 8003ecc: 68fb ldr r3, [r7, #12] + 8003ece: f8a3 205a strh.w r2, [r3, #90] ; 0x5a while (huart->RxXferCount > 0U) - 8003226: 68fb ldr r3, [r7, #12] - 8003228: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a - 800322c: b29b uxth r3, r3 - 800322e: 2b00 cmp r3, #0 - 8003230: d1c6 bne.n 80031c0 + 8003ed2: 68fb ldr r3, [r7, #12] + 8003ed4: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a + 8003ed8: b29b uxth r3, r3 + 8003eda: 2b00 cmp r3, #0 + 8003edc: d1c6 bne.n 8003e6c } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - 8003232: 68fb ldr r3, [r7, #12] - 8003234: 2220 movs r2, #32 - 8003236: 67da str r2, [r3, #124] ; 0x7c + 8003ede: 68fb ldr r3, [r7, #12] + 8003ee0: 2220 movs r2, #32 + 8003ee2: 67da str r2, [r3, #124] ; 0x7c return HAL_OK; - 8003238: 2300 movs r3, #0 - 800323a: e000 b.n 800323e + 8003ee4: 2300 movs r3, #0 + 8003ee6: e000 b.n 8003eea } else { return HAL_BUSY; - 800323c: 2302 movs r3, #2 + 8003ee8: 2302 movs r3, #2 } } - 800323e: 4618 mov r0, r3 - 8003240: 3720 adds r7, #32 - 8003242: 46bd mov sp, r7 - 8003244: bd80 pop {r7, pc} + 8003eea: 4618 mov r0, r3 + 8003eec: 3720 adds r7, #32 + 8003eee: 46bd mov sp, r7 + 8003ef0: bd80 pop {r7, pc} ... -08003248 : +08003ef4 : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { - 8003248: b580 push {r7, lr} - 800324a: b088 sub sp, #32 - 800324c: af00 add r7, sp, #0 - 800324e: 6078 str r0, [r7, #4] + 8003ef4: b580 push {r7, lr} + 8003ef6: b088 sub sp, #32 + 8003ef8: af00 add r7, sp, #0 + 8003efa: 6078 str r0, [r7, #4] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; - 8003250: 2300 movs r3, #0 - 8003252: 77bb strb r3, [r7, #30] + 8003efc: 2300 movs r3, #0 + 8003efe: 77bb strb r3, [r7, #30] * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; - 8003254: 687b ldr r3, [r7, #4] - 8003256: 689a ldr r2, [r3, #8] - 8003258: 687b ldr r3, [r7, #4] - 800325a: 691b ldr r3, [r3, #16] - 800325c: 431a orrs r2, r3 - 800325e: 687b ldr r3, [r7, #4] - 8003260: 695b ldr r3, [r3, #20] - 8003262: 431a orrs r2, r3 - 8003264: 687b ldr r3, [r7, #4] - 8003266: 69db ldr r3, [r3, #28] - 8003268: 4313 orrs r3, r2 - 800326a: 617b str r3, [r7, #20] + 8003f00: 687b ldr r3, [r7, #4] + 8003f02: 689a ldr r2, [r3, #8] + 8003f04: 687b ldr r3, [r7, #4] + 8003f06: 691b ldr r3, [r3, #16] + 8003f08: 431a orrs r2, r3 + 8003f0a: 687b ldr r3, [r7, #4] + 8003f0c: 695b ldr r3, [r3, #20] + 8003f0e: 431a orrs r2, r3 + 8003f10: 687b ldr r3, [r7, #4] + 8003f12: 69db ldr r3, [r3, #28] + 8003f14: 4313 orrs r3, r2 + 8003f16: 617b str r3, [r7, #20] MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); - 800326c: 687b ldr r3, [r7, #4] - 800326e: 681b ldr r3, [r3, #0] - 8003270: 681a ldr r2, [r3, #0] - 8003272: 4ba7 ldr r3, [pc, #668] ; (8003510 ) - 8003274: 4013 ands r3, r2 - 8003276: 687a ldr r2, [r7, #4] - 8003278: 6812 ldr r2, [r2, #0] - 800327a: 6979 ldr r1, [r7, #20] - 800327c: 430b orrs r3, r1 - 800327e: 6013 str r3, [r2, #0] + 8003f18: 687b ldr r3, [r7, #4] + 8003f1a: 681b ldr r3, [r3, #0] + 8003f1c: 681a ldr r2, [r3, #0] + 8003f1e: 4ba7 ldr r3, [pc, #668] ; (80041bc ) + 8003f20: 4013 ands r3, r2 + 8003f22: 687a ldr r2, [r7, #4] + 8003f24: 6812 ldr r2, [r2, #0] + 8003f26: 6979 ldr r1, [r7, #20] + 8003f28: 430b orrs r3, r1 + 8003f2a: 6013 str r3, [r2, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - 8003280: 687b ldr r3, [r7, #4] - 8003282: 681b ldr r3, [r3, #0] - 8003284: 685b ldr r3, [r3, #4] - 8003286: f423 5140 bic.w r1, r3, #12288 ; 0x3000 - 800328a: 687b ldr r3, [r7, #4] - 800328c: 68da ldr r2, [r3, #12] - 800328e: 687b ldr r3, [r7, #4] - 8003290: 681b ldr r3, [r3, #0] - 8003292: 430a orrs r2, r1 - 8003294: 605a str r2, [r3, #4] + 8003f2c: 687b ldr r3, [r7, #4] + 8003f2e: 681b ldr r3, [r3, #0] + 8003f30: 685b ldr r3, [r3, #4] + 8003f32: f423 5140 bic.w r1, r3, #12288 ; 0x3000 + 8003f36: 687b ldr r3, [r7, #4] + 8003f38: 68da ldr r2, [r3, #12] + 8003f3a: 687b ldr r3, [r7, #4] + 8003f3c: 681b ldr r3, [r3, #0] + 8003f3e: 430a orrs r2, r1 + 8003f40: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; - 8003296: 687b ldr r3, [r7, #4] - 8003298: 699b ldr r3, [r3, #24] - 800329a: 617b str r3, [r7, #20] + 8003f42: 687b ldr r3, [r7, #4] + 8003f44: 699b ldr r3, [r3, #24] + 8003f46: 617b str r3, [r7, #20] tmpreg |= huart->Init.OneBitSampling; - 800329c: 687b ldr r3, [r7, #4] - 800329e: 6a1b ldr r3, [r3, #32] - 80032a0: 697a ldr r2, [r7, #20] - 80032a2: 4313 orrs r3, r2 - 80032a4: 617b str r3, [r7, #20] + 8003f48: 687b ldr r3, [r7, #4] + 8003f4a: 6a1b ldr r3, [r3, #32] + 8003f4c: 697a ldr r2, [r7, #20] + 8003f4e: 4313 orrs r3, r2 + 8003f50: 617b str r3, [r7, #20] MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); - 80032a6: 687b ldr r3, [r7, #4] - 80032a8: 681b ldr r3, [r3, #0] - 80032aa: 689b ldr r3, [r3, #8] - 80032ac: f423 6130 bic.w r1, r3, #2816 ; 0xb00 - 80032b0: 687b ldr r3, [r7, #4] - 80032b2: 681b ldr r3, [r3, #0] - 80032b4: 697a ldr r2, [r7, #20] - 80032b6: 430a orrs r2, r1 - 80032b8: 609a str r2, [r3, #8] + 8003f52: 687b ldr r3, [r7, #4] + 8003f54: 681b ldr r3, [r3, #0] + 8003f56: 689b ldr r3, [r3, #8] + 8003f58: f423 6130 bic.w r1, r3, #2816 ; 0xb00 + 8003f5c: 687b ldr r3, [r7, #4] + 8003f5e: 681b ldr r3, [r3, #0] + 8003f60: 697a ldr r2, [r7, #20] + 8003f62: 430a orrs r2, r1 + 8003f64: 609a str r2, [r3, #8] /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); - 80032ba: 687b ldr r3, [r7, #4] - 80032bc: 681b ldr r3, [r3, #0] - 80032be: 4a95 ldr r2, [pc, #596] ; (8003514 ) - 80032c0: 4293 cmp r3, r2 - 80032c2: d120 bne.n 8003306 - 80032c4: 4b94 ldr r3, [pc, #592] ; (8003518 ) - 80032c6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 80032ca: f003 0303 and.w r3, r3, #3 - 80032ce: 2b03 cmp r3, #3 - 80032d0: d816 bhi.n 8003300 - 80032d2: a201 add r2, pc, #4 ; (adr r2, 80032d8 ) - 80032d4: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 80032d8: 080032e9 .word 0x080032e9 - 80032dc: 080032f5 .word 0x080032f5 - 80032e0: 080032ef .word 0x080032ef - 80032e4: 080032fb .word 0x080032fb - 80032e8: 2301 movs r3, #1 - 80032ea: 77fb strb r3, [r7, #31] - 80032ec: e14f b.n 800358e - 80032ee: 2302 movs r3, #2 - 80032f0: 77fb strb r3, [r7, #31] - 80032f2: e14c b.n 800358e - 80032f4: 2304 movs r3, #4 - 80032f6: 77fb strb r3, [r7, #31] - 80032f8: e149 b.n 800358e - 80032fa: 2308 movs r3, #8 - 80032fc: 77fb strb r3, [r7, #31] - 80032fe: e146 b.n 800358e - 8003300: 2310 movs r3, #16 - 8003302: 77fb strb r3, [r7, #31] - 8003304: e143 b.n 800358e - 8003306: 687b ldr r3, [r7, #4] - 8003308: 681b ldr r3, [r3, #0] - 800330a: 4a84 ldr r2, [pc, #528] ; (800351c ) - 800330c: 4293 cmp r3, r2 - 800330e: d132 bne.n 8003376 - 8003310: 4b81 ldr r3, [pc, #516] ; (8003518 ) - 8003312: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8003316: f003 030c and.w r3, r3, #12 - 800331a: 2b0c cmp r3, #12 - 800331c: d828 bhi.n 8003370 - 800331e: a201 add r2, pc, #4 ; (adr r2, 8003324 ) - 8003320: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 8003324: 08003359 .word 0x08003359 - 8003328: 08003371 .word 0x08003371 - 800332c: 08003371 .word 0x08003371 - 8003330: 08003371 .word 0x08003371 - 8003334: 08003365 .word 0x08003365 - 8003338: 08003371 .word 0x08003371 - 800333c: 08003371 .word 0x08003371 - 8003340: 08003371 .word 0x08003371 - 8003344: 0800335f .word 0x0800335f - 8003348: 08003371 .word 0x08003371 - 800334c: 08003371 .word 0x08003371 - 8003350: 08003371 .word 0x08003371 - 8003354: 0800336b .word 0x0800336b - 8003358: 2300 movs r3, #0 - 800335a: 77fb strb r3, [r7, #31] - 800335c: e117 b.n 800358e - 800335e: 2302 movs r3, #2 - 8003360: 77fb strb r3, [r7, #31] - 8003362: e114 b.n 800358e - 8003364: 2304 movs r3, #4 - 8003366: 77fb strb r3, [r7, #31] - 8003368: e111 b.n 800358e - 800336a: 2308 movs r3, #8 - 800336c: 77fb strb r3, [r7, #31] - 800336e: e10e b.n 800358e - 8003370: 2310 movs r3, #16 - 8003372: 77fb strb r3, [r7, #31] - 8003374: e10b b.n 800358e - 8003376: 687b ldr r3, [r7, #4] - 8003378: 681b ldr r3, [r3, #0] - 800337a: 4a69 ldr r2, [pc, #420] ; (8003520 ) - 800337c: 4293 cmp r3, r2 - 800337e: d120 bne.n 80033c2 - 8003380: 4b65 ldr r3, [pc, #404] ; (8003518 ) - 8003382: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8003386: f003 0330 and.w r3, r3, #48 ; 0x30 - 800338a: 2b30 cmp r3, #48 ; 0x30 - 800338c: d013 beq.n 80033b6 - 800338e: 2b30 cmp r3, #48 ; 0x30 - 8003390: d814 bhi.n 80033bc - 8003392: 2b20 cmp r3, #32 - 8003394: d009 beq.n 80033aa - 8003396: 2b20 cmp r3, #32 - 8003398: d810 bhi.n 80033bc - 800339a: 2b00 cmp r3, #0 - 800339c: d002 beq.n 80033a4 - 800339e: 2b10 cmp r3, #16 - 80033a0: d006 beq.n 80033b0 - 80033a2: e00b b.n 80033bc - 80033a4: 2300 movs r3, #0 - 80033a6: 77fb strb r3, [r7, #31] - 80033a8: e0f1 b.n 800358e - 80033aa: 2302 movs r3, #2 - 80033ac: 77fb strb r3, [r7, #31] - 80033ae: e0ee b.n 800358e - 80033b0: 2304 movs r3, #4 - 80033b2: 77fb strb r3, [r7, #31] - 80033b4: e0eb b.n 800358e - 80033b6: 2308 movs r3, #8 - 80033b8: 77fb strb r3, [r7, #31] - 80033ba: e0e8 b.n 800358e - 80033bc: 2310 movs r3, #16 - 80033be: 77fb strb r3, [r7, #31] - 80033c0: e0e5 b.n 800358e - 80033c2: 687b ldr r3, [r7, #4] - 80033c4: 681b ldr r3, [r3, #0] - 80033c6: 4a57 ldr r2, [pc, #348] ; (8003524 ) - 80033c8: 4293 cmp r3, r2 - 80033ca: d120 bne.n 800340e - 80033cc: 4b52 ldr r3, [pc, #328] ; (8003518 ) - 80033ce: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 80033d2: f003 03c0 and.w r3, r3, #192 ; 0xc0 - 80033d6: 2bc0 cmp r3, #192 ; 0xc0 - 80033d8: d013 beq.n 8003402 - 80033da: 2bc0 cmp r3, #192 ; 0xc0 - 80033dc: d814 bhi.n 8003408 - 80033de: 2b80 cmp r3, #128 ; 0x80 - 80033e0: d009 beq.n 80033f6 - 80033e2: 2b80 cmp r3, #128 ; 0x80 - 80033e4: d810 bhi.n 8003408 - 80033e6: 2b00 cmp r3, #0 - 80033e8: d002 beq.n 80033f0 - 80033ea: 2b40 cmp r3, #64 ; 0x40 - 80033ec: d006 beq.n 80033fc - 80033ee: e00b b.n 8003408 - 80033f0: 2300 movs r3, #0 - 80033f2: 77fb strb r3, [r7, #31] - 80033f4: e0cb b.n 800358e - 80033f6: 2302 movs r3, #2 - 80033f8: 77fb strb r3, [r7, #31] - 80033fa: e0c8 b.n 800358e - 80033fc: 2304 movs r3, #4 - 80033fe: 77fb strb r3, [r7, #31] - 8003400: e0c5 b.n 800358e - 8003402: 2308 movs r3, #8 - 8003404: 77fb strb r3, [r7, #31] - 8003406: e0c2 b.n 800358e - 8003408: 2310 movs r3, #16 - 800340a: 77fb strb r3, [r7, #31] - 800340c: e0bf b.n 800358e - 800340e: 687b ldr r3, [r7, #4] - 8003410: 681b ldr r3, [r3, #0] - 8003412: 4a45 ldr r2, [pc, #276] ; (8003528 ) - 8003414: 4293 cmp r3, r2 - 8003416: d125 bne.n 8003464 - 8003418: 4b3f ldr r3, [pc, #252] ; (8003518 ) - 800341a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 800341e: f403 7340 and.w r3, r3, #768 ; 0x300 - 8003422: f5b3 7f40 cmp.w r3, #768 ; 0x300 - 8003426: d017 beq.n 8003458 - 8003428: f5b3 7f40 cmp.w r3, #768 ; 0x300 - 800342c: d817 bhi.n 800345e - 800342e: f5b3 7f00 cmp.w r3, #512 ; 0x200 - 8003432: d00b beq.n 800344c - 8003434: f5b3 7f00 cmp.w r3, #512 ; 0x200 - 8003438: d811 bhi.n 800345e - 800343a: 2b00 cmp r3, #0 - 800343c: d003 beq.n 8003446 - 800343e: f5b3 7f80 cmp.w r3, #256 ; 0x100 - 8003442: d006 beq.n 8003452 - 8003444: e00b b.n 800345e - 8003446: 2300 movs r3, #0 - 8003448: 77fb strb r3, [r7, #31] - 800344a: e0a0 b.n 800358e - 800344c: 2302 movs r3, #2 - 800344e: 77fb strb r3, [r7, #31] - 8003450: e09d b.n 800358e - 8003452: 2304 movs r3, #4 - 8003454: 77fb strb r3, [r7, #31] - 8003456: e09a b.n 800358e - 8003458: 2308 movs r3, #8 - 800345a: 77fb strb r3, [r7, #31] - 800345c: e097 b.n 800358e - 800345e: 2310 movs r3, #16 - 8003460: 77fb strb r3, [r7, #31] - 8003462: e094 b.n 800358e - 8003464: 687b ldr r3, [r7, #4] - 8003466: 681b ldr r3, [r3, #0] - 8003468: 4a30 ldr r2, [pc, #192] ; (800352c ) - 800346a: 4293 cmp r3, r2 - 800346c: d125 bne.n 80034ba - 800346e: 4b2a ldr r3, [pc, #168] ; (8003518 ) - 8003470: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8003474: f403 6340 and.w r3, r3, #3072 ; 0xc00 - 8003478: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 - 800347c: d017 beq.n 80034ae - 800347e: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 - 8003482: d817 bhi.n 80034b4 - 8003484: f5b3 6f00 cmp.w r3, #2048 ; 0x800 - 8003488: d00b beq.n 80034a2 - 800348a: f5b3 6f00 cmp.w r3, #2048 ; 0x800 - 800348e: d811 bhi.n 80034b4 - 8003490: 2b00 cmp r3, #0 - 8003492: d003 beq.n 800349c - 8003494: f5b3 6f80 cmp.w r3, #1024 ; 0x400 - 8003498: d006 beq.n 80034a8 - 800349a: e00b b.n 80034b4 - 800349c: 2301 movs r3, #1 - 800349e: 77fb strb r3, [r7, #31] - 80034a0: e075 b.n 800358e - 80034a2: 2302 movs r3, #2 - 80034a4: 77fb strb r3, [r7, #31] - 80034a6: e072 b.n 800358e - 80034a8: 2304 movs r3, #4 - 80034aa: 77fb strb r3, [r7, #31] - 80034ac: e06f b.n 800358e - 80034ae: 2308 movs r3, #8 - 80034b0: 77fb strb r3, [r7, #31] - 80034b2: e06c b.n 800358e - 80034b4: 2310 movs r3, #16 - 80034b6: 77fb strb r3, [r7, #31] - 80034b8: e069 b.n 800358e - 80034ba: 687b ldr r3, [r7, #4] - 80034bc: 681b ldr r3, [r3, #0] - 80034be: 4a1c ldr r2, [pc, #112] ; (8003530 ) - 80034c0: 4293 cmp r3, r2 - 80034c2: d137 bne.n 8003534 - 80034c4: 4b14 ldr r3, [pc, #80] ; (8003518 ) - 80034c6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 80034ca: f403 5340 and.w r3, r3, #12288 ; 0x3000 - 80034ce: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 - 80034d2: d017 beq.n 8003504 - 80034d4: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 - 80034d8: d817 bhi.n 800350a - 80034da: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 - 80034de: d00b beq.n 80034f8 - 80034e0: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 - 80034e4: d811 bhi.n 800350a - 80034e6: 2b00 cmp r3, #0 - 80034e8: d003 beq.n 80034f2 - 80034ea: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 - 80034ee: d006 beq.n 80034fe - 80034f0: e00b b.n 800350a - 80034f2: 2300 movs r3, #0 - 80034f4: 77fb strb r3, [r7, #31] - 80034f6: e04a b.n 800358e - 80034f8: 2302 movs r3, #2 - 80034fa: 77fb strb r3, [r7, #31] - 80034fc: e047 b.n 800358e - 80034fe: 2304 movs r3, #4 - 8003500: 77fb strb r3, [r7, #31] - 8003502: e044 b.n 800358e - 8003504: 2308 movs r3, #8 - 8003506: 77fb strb r3, [r7, #31] - 8003508: e041 b.n 800358e - 800350a: 2310 movs r3, #16 - 800350c: 77fb strb r3, [r7, #31] - 800350e: e03e b.n 800358e - 8003510: efff69f3 .word 0xefff69f3 - 8003514: 40011000 .word 0x40011000 - 8003518: 40023800 .word 0x40023800 - 800351c: 40004400 .word 0x40004400 - 8003520: 40004800 .word 0x40004800 - 8003524: 40004c00 .word 0x40004c00 - 8003528: 40005000 .word 0x40005000 - 800352c: 40011400 .word 0x40011400 - 8003530: 40007800 .word 0x40007800 - 8003534: 687b ldr r3, [r7, #4] - 8003536: 681b ldr r3, [r3, #0] - 8003538: 4a71 ldr r2, [pc, #452] ; (8003700 ) - 800353a: 4293 cmp r3, r2 - 800353c: d125 bne.n 800358a - 800353e: 4b71 ldr r3, [pc, #452] ; (8003704 ) - 8003540: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 - 8003544: f403 4340 and.w r3, r3, #49152 ; 0xc000 - 8003548: f5b3 4f40 cmp.w r3, #49152 ; 0xc000 - 800354c: d017 beq.n 800357e - 800354e: f5b3 4f40 cmp.w r3, #49152 ; 0xc000 - 8003552: d817 bhi.n 8003584 - 8003554: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 - 8003558: d00b beq.n 8003572 - 800355a: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 - 800355e: d811 bhi.n 8003584 - 8003560: 2b00 cmp r3, #0 - 8003562: d003 beq.n 800356c - 8003564: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 - 8003568: d006 beq.n 8003578 - 800356a: e00b b.n 8003584 - 800356c: 2300 movs r3, #0 - 800356e: 77fb strb r3, [r7, #31] - 8003570: e00d b.n 800358e - 8003572: 2302 movs r3, #2 - 8003574: 77fb strb r3, [r7, #31] - 8003576: e00a b.n 800358e - 8003578: 2304 movs r3, #4 - 800357a: 77fb strb r3, [r7, #31] - 800357c: e007 b.n 800358e - 800357e: 2308 movs r3, #8 - 8003580: 77fb strb r3, [r7, #31] - 8003582: e004 b.n 800358e - 8003584: 2310 movs r3, #16 - 8003586: 77fb strb r3, [r7, #31] - 8003588: e001 b.n 800358e - 800358a: 2310 movs r3, #16 - 800358c: 77fb strb r3, [r7, #31] + 8003f66: 687b ldr r3, [r7, #4] + 8003f68: 681b ldr r3, [r3, #0] + 8003f6a: 4a95 ldr r2, [pc, #596] ; (80041c0 ) + 8003f6c: 4293 cmp r3, r2 + 8003f6e: d120 bne.n 8003fb2 + 8003f70: 4b94 ldr r3, [pc, #592] ; (80041c4 ) + 8003f72: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003f76: f003 0303 and.w r3, r3, #3 + 8003f7a: 2b03 cmp r3, #3 + 8003f7c: d816 bhi.n 8003fac + 8003f7e: a201 add r2, pc, #4 ; (adr r2, 8003f84 ) + 8003f80: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8003f84: 08003f95 .word 0x08003f95 + 8003f88: 08003fa1 .word 0x08003fa1 + 8003f8c: 08003f9b .word 0x08003f9b + 8003f90: 08003fa7 .word 0x08003fa7 + 8003f94: 2301 movs r3, #1 + 8003f96: 77fb strb r3, [r7, #31] + 8003f98: e14f b.n 800423a + 8003f9a: 2302 movs r3, #2 + 8003f9c: 77fb strb r3, [r7, #31] + 8003f9e: e14c b.n 800423a + 8003fa0: 2304 movs r3, #4 + 8003fa2: 77fb strb r3, [r7, #31] + 8003fa4: e149 b.n 800423a + 8003fa6: 2308 movs r3, #8 + 8003fa8: 77fb strb r3, [r7, #31] + 8003faa: e146 b.n 800423a + 8003fac: 2310 movs r3, #16 + 8003fae: 77fb strb r3, [r7, #31] + 8003fb0: e143 b.n 800423a + 8003fb2: 687b ldr r3, [r7, #4] + 8003fb4: 681b ldr r3, [r3, #0] + 8003fb6: 4a84 ldr r2, [pc, #528] ; (80041c8 ) + 8003fb8: 4293 cmp r3, r2 + 8003fba: d132 bne.n 8004022 + 8003fbc: 4b81 ldr r3, [pc, #516] ; (80041c4 ) + 8003fbe: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003fc2: f003 030c and.w r3, r3, #12 + 8003fc6: 2b0c cmp r3, #12 + 8003fc8: d828 bhi.n 800401c + 8003fca: a201 add r2, pc, #4 ; (adr r2, 8003fd0 ) + 8003fcc: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8003fd0: 08004005 .word 0x08004005 + 8003fd4: 0800401d .word 0x0800401d + 8003fd8: 0800401d .word 0x0800401d + 8003fdc: 0800401d .word 0x0800401d + 8003fe0: 08004011 .word 0x08004011 + 8003fe4: 0800401d .word 0x0800401d + 8003fe8: 0800401d .word 0x0800401d + 8003fec: 0800401d .word 0x0800401d + 8003ff0: 0800400b .word 0x0800400b + 8003ff4: 0800401d .word 0x0800401d + 8003ff8: 0800401d .word 0x0800401d + 8003ffc: 0800401d .word 0x0800401d + 8004000: 08004017 .word 0x08004017 + 8004004: 2300 movs r3, #0 + 8004006: 77fb strb r3, [r7, #31] + 8004008: e117 b.n 800423a + 800400a: 2302 movs r3, #2 + 800400c: 77fb strb r3, [r7, #31] + 800400e: e114 b.n 800423a + 8004010: 2304 movs r3, #4 + 8004012: 77fb strb r3, [r7, #31] + 8004014: e111 b.n 800423a + 8004016: 2308 movs r3, #8 + 8004018: 77fb strb r3, [r7, #31] + 800401a: e10e b.n 800423a + 800401c: 2310 movs r3, #16 + 800401e: 77fb strb r3, [r7, #31] + 8004020: e10b b.n 800423a + 8004022: 687b ldr r3, [r7, #4] + 8004024: 681b ldr r3, [r3, #0] + 8004026: 4a69 ldr r2, [pc, #420] ; (80041cc ) + 8004028: 4293 cmp r3, r2 + 800402a: d120 bne.n 800406e + 800402c: 4b65 ldr r3, [pc, #404] ; (80041c4 ) + 800402e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8004032: f003 0330 and.w r3, r3, #48 ; 0x30 + 8004036: 2b30 cmp r3, #48 ; 0x30 + 8004038: d013 beq.n 8004062 + 800403a: 2b30 cmp r3, #48 ; 0x30 + 800403c: d814 bhi.n 8004068 + 800403e: 2b20 cmp r3, #32 + 8004040: d009 beq.n 8004056 + 8004042: 2b20 cmp r3, #32 + 8004044: d810 bhi.n 8004068 + 8004046: 2b00 cmp r3, #0 + 8004048: d002 beq.n 8004050 + 800404a: 2b10 cmp r3, #16 + 800404c: d006 beq.n 800405c + 800404e: e00b b.n 8004068 + 8004050: 2300 movs r3, #0 + 8004052: 77fb strb r3, [r7, #31] + 8004054: e0f1 b.n 800423a + 8004056: 2302 movs r3, #2 + 8004058: 77fb strb r3, [r7, #31] + 800405a: e0ee b.n 800423a + 800405c: 2304 movs r3, #4 + 800405e: 77fb strb r3, [r7, #31] + 8004060: e0eb b.n 800423a + 8004062: 2308 movs r3, #8 + 8004064: 77fb strb r3, [r7, #31] + 8004066: e0e8 b.n 800423a + 8004068: 2310 movs r3, #16 + 800406a: 77fb strb r3, [r7, #31] + 800406c: e0e5 b.n 800423a + 800406e: 687b ldr r3, [r7, #4] + 8004070: 681b ldr r3, [r3, #0] + 8004072: 4a57 ldr r2, [pc, #348] ; (80041d0 ) + 8004074: 4293 cmp r3, r2 + 8004076: d120 bne.n 80040ba + 8004078: 4b52 ldr r3, [pc, #328] ; (80041c4 ) + 800407a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800407e: f003 03c0 and.w r3, r3, #192 ; 0xc0 + 8004082: 2bc0 cmp r3, #192 ; 0xc0 + 8004084: d013 beq.n 80040ae + 8004086: 2bc0 cmp r3, #192 ; 0xc0 + 8004088: d814 bhi.n 80040b4 + 800408a: 2b80 cmp r3, #128 ; 0x80 + 800408c: d009 beq.n 80040a2 + 800408e: 2b80 cmp r3, #128 ; 0x80 + 8004090: d810 bhi.n 80040b4 + 8004092: 2b00 cmp r3, #0 + 8004094: d002 beq.n 800409c + 8004096: 2b40 cmp r3, #64 ; 0x40 + 8004098: d006 beq.n 80040a8 + 800409a: e00b b.n 80040b4 + 800409c: 2300 movs r3, #0 + 800409e: 77fb strb r3, [r7, #31] + 80040a0: e0cb b.n 800423a + 80040a2: 2302 movs r3, #2 + 80040a4: 77fb strb r3, [r7, #31] + 80040a6: e0c8 b.n 800423a + 80040a8: 2304 movs r3, #4 + 80040aa: 77fb strb r3, [r7, #31] + 80040ac: e0c5 b.n 800423a + 80040ae: 2308 movs r3, #8 + 80040b0: 77fb strb r3, [r7, #31] + 80040b2: e0c2 b.n 800423a + 80040b4: 2310 movs r3, #16 + 80040b6: 77fb strb r3, [r7, #31] + 80040b8: e0bf b.n 800423a + 80040ba: 687b ldr r3, [r7, #4] + 80040bc: 681b ldr r3, [r3, #0] + 80040be: 4a45 ldr r2, [pc, #276] ; (80041d4 ) + 80040c0: 4293 cmp r3, r2 + 80040c2: d125 bne.n 8004110 + 80040c4: 4b3f ldr r3, [pc, #252] ; (80041c4 ) + 80040c6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80040ca: f403 7340 and.w r3, r3, #768 ; 0x300 + 80040ce: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 80040d2: d017 beq.n 8004104 + 80040d4: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 80040d8: d817 bhi.n 800410a + 80040da: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 80040de: d00b beq.n 80040f8 + 80040e0: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 80040e4: d811 bhi.n 800410a + 80040e6: 2b00 cmp r3, #0 + 80040e8: d003 beq.n 80040f2 + 80040ea: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 80040ee: d006 beq.n 80040fe + 80040f0: e00b b.n 800410a + 80040f2: 2300 movs r3, #0 + 80040f4: 77fb strb r3, [r7, #31] + 80040f6: e0a0 b.n 800423a + 80040f8: 2302 movs r3, #2 + 80040fa: 77fb strb r3, [r7, #31] + 80040fc: e09d b.n 800423a + 80040fe: 2304 movs r3, #4 + 8004100: 77fb strb r3, [r7, #31] + 8004102: e09a b.n 800423a + 8004104: 2308 movs r3, #8 + 8004106: 77fb strb r3, [r7, #31] + 8004108: e097 b.n 800423a + 800410a: 2310 movs r3, #16 + 800410c: 77fb strb r3, [r7, #31] + 800410e: e094 b.n 800423a + 8004110: 687b ldr r3, [r7, #4] + 8004112: 681b ldr r3, [r3, #0] + 8004114: 4a30 ldr r2, [pc, #192] ; (80041d8 ) + 8004116: 4293 cmp r3, r2 + 8004118: d125 bne.n 8004166 + 800411a: 4b2a ldr r3, [pc, #168] ; (80041c4 ) + 800411c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8004120: f403 6340 and.w r3, r3, #3072 ; 0xc00 + 8004124: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 + 8004128: d017 beq.n 800415a + 800412a: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 + 800412e: d817 bhi.n 8004160 + 8004130: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 8004134: d00b beq.n 800414e + 8004136: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 800413a: d811 bhi.n 8004160 + 800413c: 2b00 cmp r3, #0 + 800413e: d003 beq.n 8004148 + 8004140: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 8004144: d006 beq.n 8004154 + 8004146: e00b b.n 8004160 + 8004148: 2301 movs r3, #1 + 800414a: 77fb strb r3, [r7, #31] + 800414c: e075 b.n 800423a + 800414e: 2302 movs r3, #2 + 8004150: 77fb strb r3, [r7, #31] + 8004152: e072 b.n 800423a + 8004154: 2304 movs r3, #4 + 8004156: 77fb strb r3, [r7, #31] + 8004158: e06f b.n 800423a + 800415a: 2308 movs r3, #8 + 800415c: 77fb strb r3, [r7, #31] + 800415e: e06c b.n 800423a + 8004160: 2310 movs r3, #16 + 8004162: 77fb strb r3, [r7, #31] + 8004164: e069 b.n 800423a + 8004166: 687b ldr r3, [r7, #4] + 8004168: 681b ldr r3, [r3, #0] + 800416a: 4a1c ldr r2, [pc, #112] ; (80041dc ) + 800416c: 4293 cmp r3, r2 + 800416e: d137 bne.n 80041e0 + 8004170: 4b14 ldr r3, [pc, #80] ; (80041c4 ) + 8004172: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8004176: f403 5340 and.w r3, r3, #12288 ; 0x3000 + 800417a: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 + 800417e: d017 beq.n 80041b0 + 8004180: f5b3 5f40 cmp.w r3, #12288 ; 0x3000 + 8004184: d817 bhi.n 80041b6 + 8004186: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 800418a: d00b beq.n 80041a4 + 800418c: f5b3 5f00 cmp.w r3, #8192 ; 0x2000 + 8004190: d811 bhi.n 80041b6 + 8004192: 2b00 cmp r3, #0 + 8004194: d003 beq.n 800419e + 8004196: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 800419a: d006 beq.n 80041aa + 800419c: e00b b.n 80041b6 + 800419e: 2300 movs r3, #0 + 80041a0: 77fb strb r3, [r7, #31] + 80041a2: e04a b.n 800423a + 80041a4: 2302 movs r3, #2 + 80041a6: 77fb strb r3, [r7, #31] + 80041a8: e047 b.n 800423a + 80041aa: 2304 movs r3, #4 + 80041ac: 77fb strb r3, [r7, #31] + 80041ae: e044 b.n 800423a + 80041b0: 2308 movs r3, #8 + 80041b2: 77fb strb r3, [r7, #31] + 80041b4: e041 b.n 800423a + 80041b6: 2310 movs r3, #16 + 80041b8: 77fb strb r3, [r7, #31] + 80041ba: e03e b.n 800423a + 80041bc: efff69f3 .word 0xefff69f3 + 80041c0: 40011000 .word 0x40011000 + 80041c4: 40023800 .word 0x40023800 + 80041c8: 40004400 .word 0x40004400 + 80041cc: 40004800 .word 0x40004800 + 80041d0: 40004c00 .word 0x40004c00 + 80041d4: 40005000 .word 0x40005000 + 80041d8: 40011400 .word 0x40011400 + 80041dc: 40007800 .word 0x40007800 + 80041e0: 687b ldr r3, [r7, #4] + 80041e2: 681b ldr r3, [r3, #0] + 80041e4: 4a71 ldr r2, [pc, #452] ; (80043ac ) + 80041e6: 4293 cmp r3, r2 + 80041e8: d125 bne.n 8004236 + 80041ea: 4b71 ldr r3, [pc, #452] ; (80043b0 ) + 80041ec: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80041f0: f403 4340 and.w r3, r3, #49152 ; 0xc000 + 80041f4: f5b3 4f40 cmp.w r3, #49152 ; 0xc000 + 80041f8: d017 beq.n 800422a + 80041fa: f5b3 4f40 cmp.w r3, #49152 ; 0xc000 + 80041fe: d817 bhi.n 8004230 + 8004200: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8004204: d00b beq.n 800421e + 8004206: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 800420a: d811 bhi.n 8004230 + 800420c: 2b00 cmp r3, #0 + 800420e: d003 beq.n 8004218 + 8004210: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 8004214: d006 beq.n 8004224 + 8004216: e00b b.n 8004230 + 8004218: 2300 movs r3, #0 + 800421a: 77fb strb r3, [r7, #31] + 800421c: e00d b.n 800423a + 800421e: 2302 movs r3, #2 + 8004220: 77fb strb r3, [r7, #31] + 8004222: e00a b.n 800423a + 8004224: 2304 movs r3, #4 + 8004226: 77fb strb r3, [r7, #31] + 8004228: e007 b.n 800423a + 800422a: 2308 movs r3, #8 + 800422c: 77fb strb r3, [r7, #31] + 800422e: e004 b.n 800423a + 8004230: 2310 movs r3, #16 + 8004232: 77fb strb r3, [r7, #31] + 8004234: e001 b.n 800423a + 8004236: 2310 movs r3, #16 + 8004238: 77fb strb r3, [r7, #31] if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - 800358e: 687b ldr r3, [r7, #4] - 8003590: 69db ldr r3, [r3, #28] - 8003592: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 - 8003596: d15b bne.n 8003650 + 800423a: 687b ldr r3, [r7, #4] + 800423c: 69db ldr r3, [r3, #28] + 800423e: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8004242: d15b bne.n 80042fc { switch (clocksource) - 8003598: 7ffb ldrb r3, [r7, #31] - 800359a: 2b08 cmp r3, #8 - 800359c: d827 bhi.n 80035ee - 800359e: a201 add r2, pc, #4 ; (adr r2, 80035a4 ) - 80035a0: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 80035a4: 080035c9 .word 0x080035c9 - 80035a8: 080035d1 .word 0x080035d1 - 80035ac: 080035d9 .word 0x080035d9 - 80035b0: 080035ef .word 0x080035ef - 80035b4: 080035df .word 0x080035df - 80035b8: 080035ef .word 0x080035ef - 80035bc: 080035ef .word 0x080035ef - 80035c0: 080035ef .word 0x080035ef - 80035c4: 080035e7 .word 0x080035e7 + 8004244: 7ffb ldrb r3, [r7, #31] + 8004246: 2b08 cmp r3, #8 + 8004248: d827 bhi.n 800429a + 800424a: a201 add r2, pc, #4 ; (adr r2, 8004250 ) + 800424c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8004250: 08004275 .word 0x08004275 + 8004254: 0800427d .word 0x0800427d + 8004258: 08004285 .word 0x08004285 + 800425c: 0800429b .word 0x0800429b + 8004260: 0800428b .word 0x0800428b + 8004264: 0800429b .word 0x0800429b + 8004268: 0800429b .word 0x0800429b + 800426c: 0800429b .word 0x0800429b + 8004270: 08004293 .word 0x08004293 { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - 80035c8: f7ff f83c bl 8002644 - 80035cc: 61b8 str r0, [r7, #24] + 8004274: f7ff f83c bl 80032f0 + 8004278: 61b8 str r0, [r7, #24] break; - 80035ce: e013 b.n 80035f8 + 800427a: e013 b.n 80042a4 case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - 80035d0: f7ff f84c bl 800266c - 80035d4: 61b8 str r0, [r7, #24] + 800427c: f7ff f84c bl 8003318 + 8004280: 61b8 str r0, [r7, #24] break; - 80035d6: e00f b.n 80035f8 + 8004282: e00f b.n 80042a4 case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; - 80035d8: 4b4b ldr r3, [pc, #300] ; (8003708 ) - 80035da: 61bb str r3, [r7, #24] + 8004284: 4b4b ldr r3, [pc, #300] ; (80043b4 ) + 8004286: 61bb str r3, [r7, #24] break; - 80035dc: e00c b.n 80035f8 + 8004288: e00c b.n 80042a4 case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - 80035de: f7fe ff6f bl 80024c0 - 80035e2: 61b8 str r0, [r7, #24] + 800428a: f7fe ff6f bl 800316c + 800428e: 61b8 str r0, [r7, #24] break; - 80035e4: e008 b.n 80035f8 + 8004290: e008 b.n 80042a4 case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; - 80035e6: f44f 4300 mov.w r3, #32768 ; 0x8000 - 80035ea: 61bb str r3, [r7, #24] + 8004292: f44f 4300 mov.w r3, #32768 ; 0x8000 + 8004296: 61bb str r3, [r7, #24] break; - 80035ec: e004 b.n 80035f8 + 8004298: e004 b.n 80042a4 default: pclk = 0U; - 80035ee: 2300 movs r3, #0 - 80035f0: 61bb str r3, [r7, #24] + 800429a: 2300 movs r3, #0 + 800429c: 61bb str r3, [r7, #24] ret = HAL_ERROR; - 80035f2: 2301 movs r3, #1 - 80035f4: 77bb strb r3, [r7, #30] + 800429e: 2301 movs r3, #1 + 80042a0: 77bb strb r3, [r7, #30] break; - 80035f6: bf00 nop + 80042a2: bf00 nop } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) - 80035f8: 69bb ldr r3, [r7, #24] - 80035fa: 2b00 cmp r3, #0 - 80035fc: d074 beq.n 80036e8 + 80042a4: 69bb ldr r3, [r7, #24] + 80042a6: 2b00 cmp r3, #0 + 80042a8: d074 beq.n 8004394 { usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); - 80035fe: 69bb ldr r3, [r7, #24] - 8003600: 005a lsls r2, r3, #1 - 8003602: 687b ldr r3, [r7, #4] - 8003604: 685b ldr r3, [r3, #4] - 8003606: 085b lsrs r3, r3, #1 - 8003608: 441a add r2, r3 - 800360a: 687b ldr r3, [r7, #4] - 800360c: 685b ldr r3, [r3, #4] - 800360e: fbb2 f3f3 udiv r3, r2, r3 - 8003612: b29b uxth r3, r3 - 8003614: 613b str r3, [r7, #16] + 80042aa: 69bb ldr r3, [r7, #24] + 80042ac: 005a lsls r2, r3, #1 + 80042ae: 687b ldr r3, [r7, #4] + 80042b0: 685b ldr r3, [r3, #4] + 80042b2: 085b lsrs r3, r3, #1 + 80042b4: 441a add r2, r3 + 80042b6: 687b ldr r3, [r7, #4] + 80042b8: 685b ldr r3, [r3, #4] + 80042ba: fbb2 f3f3 udiv r3, r2, r3 + 80042be: b29b uxth r3, r3 + 80042c0: 613b str r3, [r7, #16] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - 8003616: 693b ldr r3, [r7, #16] - 8003618: 2b0f cmp r3, #15 - 800361a: d916 bls.n 800364a - 800361c: 693b ldr r3, [r7, #16] - 800361e: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 - 8003622: d212 bcs.n 800364a + 80042c2: 693b ldr r3, [r7, #16] + 80042c4: 2b0f cmp r3, #15 + 80042c6: d916 bls.n 80042f6 + 80042c8: 693b ldr r3, [r7, #16] + 80042ca: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 80042ce: d212 bcs.n 80042f6 { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); - 8003624: 693b ldr r3, [r7, #16] - 8003626: b29b uxth r3, r3 - 8003628: f023 030f bic.w r3, r3, #15 - 800362c: 81fb strh r3, [r7, #14] + 80042d0: 693b ldr r3, [r7, #16] + 80042d2: b29b uxth r3, r3 + 80042d4: f023 030f bic.w r3, r3, #15 + 80042d8: 81fb strh r3, [r7, #14] brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - 800362e: 693b ldr r3, [r7, #16] - 8003630: 085b lsrs r3, r3, #1 - 8003632: b29b uxth r3, r3 - 8003634: f003 0307 and.w r3, r3, #7 - 8003638: b29a uxth r2, r3 - 800363a: 89fb ldrh r3, [r7, #14] - 800363c: 4313 orrs r3, r2 - 800363e: 81fb strh r3, [r7, #14] + 80042da: 693b ldr r3, [r7, #16] + 80042dc: 085b lsrs r3, r3, #1 + 80042de: b29b uxth r3, r3 + 80042e0: f003 0307 and.w r3, r3, #7 + 80042e4: b29a uxth r2, r3 + 80042e6: 89fb ldrh r3, [r7, #14] + 80042e8: 4313 orrs r3, r2 + 80042ea: 81fb strh r3, [r7, #14] huart->Instance->BRR = brrtemp; - 8003640: 687b ldr r3, [r7, #4] - 8003642: 681b ldr r3, [r3, #0] - 8003644: 89fa ldrh r2, [r7, #14] - 8003646: 60da str r2, [r3, #12] - 8003648: e04e b.n 80036e8 + 80042ec: 687b ldr r3, [r7, #4] + 80042ee: 681b ldr r3, [r3, #0] + 80042f0: 89fa ldrh r2, [r7, #14] + 80042f2: 60da str r2, [r3, #12] + 80042f4: e04e b.n 8004394 } else { ret = HAL_ERROR; - 800364a: 2301 movs r3, #1 - 800364c: 77bb strb r3, [r7, #30] - 800364e: e04b b.n 80036e8 + 80042f6: 2301 movs r3, #1 + 80042f8: 77bb strb r3, [r7, #30] + 80042fa: e04b b.n 8004394 } } } else { switch (clocksource) - 8003650: 7ffb ldrb r3, [r7, #31] - 8003652: 2b08 cmp r3, #8 - 8003654: d827 bhi.n 80036a6 - 8003656: a201 add r2, pc, #4 ; (adr r2, 800365c ) - 8003658: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 800365c: 08003681 .word 0x08003681 - 8003660: 08003689 .word 0x08003689 - 8003664: 08003691 .word 0x08003691 - 8003668: 080036a7 .word 0x080036a7 - 800366c: 08003697 .word 0x08003697 - 8003670: 080036a7 .word 0x080036a7 - 8003674: 080036a7 .word 0x080036a7 - 8003678: 080036a7 .word 0x080036a7 - 800367c: 0800369f .word 0x0800369f + 80042fc: 7ffb ldrb r3, [r7, #31] + 80042fe: 2b08 cmp r3, #8 + 8004300: d827 bhi.n 8004352 + 8004302: a201 add r2, pc, #4 ; (adr r2, 8004308 ) + 8004304: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8004308: 0800432d .word 0x0800432d + 800430c: 08004335 .word 0x08004335 + 8004310: 0800433d .word 0x0800433d + 8004314: 08004353 .word 0x08004353 + 8004318: 08004343 .word 0x08004343 + 800431c: 08004353 .word 0x08004353 + 8004320: 08004353 .word 0x08004353 + 8004324: 08004353 .word 0x08004353 + 8004328: 0800434b .word 0x0800434b { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - 8003680: f7fe ffe0 bl 8002644 - 8003684: 61b8 str r0, [r7, #24] + 800432c: f7fe ffe0 bl 80032f0 + 8004330: 61b8 str r0, [r7, #24] break; - 8003686: e013 b.n 80036b0 + 8004332: e013 b.n 800435c case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - 8003688: f7fe fff0 bl 800266c - 800368c: 61b8 str r0, [r7, #24] + 8004334: f7fe fff0 bl 8003318 + 8004338: 61b8 str r0, [r7, #24] break; - 800368e: e00f b.n 80036b0 + 800433a: e00f b.n 800435c case UART_CLOCKSOURCE_HSI: pclk = (uint32_t) HSI_VALUE; - 8003690: 4b1d ldr r3, [pc, #116] ; (8003708 ) - 8003692: 61bb str r3, [r7, #24] + 800433c: 4b1d ldr r3, [pc, #116] ; (80043b4 ) + 800433e: 61bb str r3, [r7, #24] break; - 8003694: e00c b.n 80036b0 + 8004340: e00c b.n 800435c case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - 8003696: f7fe ff13 bl 80024c0 - 800369a: 61b8 str r0, [r7, #24] + 8004342: f7fe ff13 bl 800316c + 8004346: 61b8 str r0, [r7, #24] break; - 800369c: e008 b.n 80036b0 + 8004348: e008 b.n 800435c case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; - 800369e: f44f 4300 mov.w r3, #32768 ; 0x8000 - 80036a2: 61bb str r3, [r7, #24] + 800434a: f44f 4300 mov.w r3, #32768 ; 0x8000 + 800434e: 61bb str r3, [r7, #24] break; - 80036a4: e004 b.n 80036b0 + 8004350: e004 b.n 800435c default: pclk = 0U; - 80036a6: 2300 movs r3, #0 - 80036a8: 61bb str r3, [r7, #24] + 8004352: 2300 movs r3, #0 + 8004354: 61bb str r3, [r7, #24] ret = HAL_ERROR; - 80036aa: 2301 movs r3, #1 - 80036ac: 77bb strb r3, [r7, #30] + 8004356: 2301 movs r3, #1 + 8004358: 77bb strb r3, [r7, #30] break; - 80036ae: bf00 nop + 800435a: bf00 nop } if (pclk != 0U) - 80036b0: 69bb ldr r3, [r7, #24] - 80036b2: 2b00 cmp r3, #0 - 80036b4: d018 beq.n 80036e8 + 800435c: 69bb ldr r3, [r7, #24] + 800435e: 2b00 cmp r3, #0 + 8004360: d018 beq.n 8004394 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); - 80036b6: 687b ldr r3, [r7, #4] - 80036b8: 685b ldr r3, [r3, #4] - 80036ba: 085a lsrs r2, r3, #1 - 80036bc: 69bb ldr r3, [r7, #24] - 80036be: 441a add r2, r3 - 80036c0: 687b ldr r3, [r7, #4] - 80036c2: 685b ldr r3, [r3, #4] - 80036c4: fbb2 f3f3 udiv r3, r2, r3 - 80036c8: b29b uxth r3, r3 - 80036ca: 613b str r3, [r7, #16] + 8004362: 687b ldr r3, [r7, #4] + 8004364: 685b ldr r3, [r3, #4] + 8004366: 085a lsrs r2, r3, #1 + 8004368: 69bb ldr r3, [r7, #24] + 800436a: 441a add r2, r3 + 800436c: 687b ldr r3, [r7, #4] + 800436e: 685b ldr r3, [r3, #4] + 8004370: fbb2 f3f3 udiv r3, r2, r3 + 8004374: b29b uxth r3, r3 + 8004376: 613b str r3, [r7, #16] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - 80036cc: 693b ldr r3, [r7, #16] - 80036ce: 2b0f cmp r3, #15 - 80036d0: d908 bls.n 80036e4 - 80036d2: 693b ldr r3, [r7, #16] - 80036d4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 - 80036d8: d204 bcs.n 80036e4 + 8004378: 693b ldr r3, [r7, #16] + 800437a: 2b0f cmp r3, #15 + 800437c: d908 bls.n 8004390 + 800437e: 693b ldr r3, [r7, #16] + 8004380: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8004384: d204 bcs.n 8004390 { huart->Instance->BRR = usartdiv; - 80036da: 687b ldr r3, [r7, #4] - 80036dc: 681b ldr r3, [r3, #0] - 80036de: 693a ldr r2, [r7, #16] - 80036e0: 60da str r2, [r3, #12] - 80036e2: e001 b.n 80036e8 + 8004386: 687b ldr r3, [r7, #4] + 8004388: 681b ldr r3, [r3, #0] + 800438a: 693a ldr r2, [r7, #16] + 800438c: 60da str r2, [r3, #12] + 800438e: e001 b.n 8004394 } else { ret = HAL_ERROR; - 80036e4: 2301 movs r3, #1 - 80036e6: 77bb strb r3, [r7, #30] + 8004390: 2301 movs r3, #1 + 8004392: 77bb strb r3, [r7, #30] } } /* Clear ISR function pointers */ huart->RxISR = NULL; - 80036e8: 687b ldr r3, [r7, #4] - 80036ea: 2200 movs r2, #0 - 80036ec: 665a str r2, [r3, #100] ; 0x64 + 8004394: 687b ldr r3, [r7, #4] + 8004396: 2200 movs r2, #0 + 8004398: 665a str r2, [r3, #100] ; 0x64 huart->TxISR = NULL; - 80036ee: 687b ldr r3, [r7, #4] - 80036f0: 2200 movs r2, #0 - 80036f2: 669a str r2, [r3, #104] ; 0x68 + 800439a: 687b ldr r3, [r7, #4] + 800439c: 2200 movs r2, #0 + 800439e: 669a str r2, [r3, #104] ; 0x68 return ret; - 80036f4: 7fbb ldrb r3, [r7, #30] + 80043a0: 7fbb ldrb r3, [r7, #30] } - 80036f6: 4618 mov r0, r3 - 80036f8: 3720 adds r7, #32 - 80036fa: 46bd mov sp, r7 - 80036fc: bd80 pop {r7, pc} - 80036fe: bf00 nop - 8003700: 40007c00 .word 0x40007c00 - 8003704: 40023800 .word 0x40023800 - 8003708: 00f42400 .word 0x00f42400 - -0800370c : + 80043a2: 4618 mov r0, r3 + 80043a4: 3720 adds r7, #32 + 80043a6: 46bd mov sp, r7 + 80043a8: bd80 pop {r7, pc} + 80043aa: bf00 nop + 80043ac: 40007c00 .word 0x40007c00 + 80043b0: 40023800 .word 0x40023800 + 80043b4: 00f42400 .word 0x00f42400 + +080043b8 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { - 800370c: b480 push {r7} - 800370e: b083 sub sp, #12 - 8003710: af00 add r7, sp, #0 - 8003712: 6078 str r0, [r7, #4] + 80043b8: b480 push {r7} + 80043ba: b083 sub sp, #12 + 80043bc: af00 add r7, sp, #0 + 80043be: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) - 8003714: 687b ldr r3, [r7, #4] - 8003716: 6a5b ldr r3, [r3, #36] ; 0x24 - 8003718: f003 0301 and.w r3, r3, #1 - 800371c: 2b00 cmp r3, #0 - 800371e: d00a beq.n 8003736 + 80043c0: 687b ldr r3, [r7, #4] + 80043c2: 6a5b ldr r3, [r3, #36] ; 0x24 + 80043c4: f003 0301 and.w r3, r3, #1 + 80043c8: 2b00 cmp r3, #0 + 80043ca: d00a beq.n 80043e2 { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); - 8003720: 687b ldr r3, [r7, #4] - 8003722: 681b ldr r3, [r3, #0] - 8003724: 685b ldr r3, [r3, #4] - 8003726: f423 3100 bic.w r1, r3, #131072 ; 0x20000 - 800372a: 687b ldr r3, [r7, #4] - 800372c: 6a9a ldr r2, [r3, #40] ; 0x28 - 800372e: 687b ldr r3, [r7, #4] - 8003730: 681b ldr r3, [r3, #0] - 8003732: 430a orrs r2, r1 - 8003734: 605a str r2, [r3, #4] + 80043cc: 687b ldr r3, [r7, #4] + 80043ce: 681b ldr r3, [r3, #0] + 80043d0: 685b ldr r3, [r3, #4] + 80043d2: f423 3100 bic.w r1, r3, #131072 ; 0x20000 + 80043d6: 687b ldr r3, [r7, #4] + 80043d8: 6a9a ldr r2, [r3, #40] ; 0x28 + 80043da: 687b ldr r3, [r7, #4] + 80043dc: 681b ldr r3, [r3, #0] + 80043de: 430a orrs r2, r1 + 80043e0: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) - 8003736: 687b ldr r3, [r7, #4] - 8003738: 6a5b ldr r3, [r3, #36] ; 0x24 - 800373a: f003 0302 and.w r3, r3, #2 - 800373e: 2b00 cmp r3, #0 - 8003740: d00a beq.n 8003758 + 80043e2: 687b ldr r3, [r7, #4] + 80043e4: 6a5b ldr r3, [r3, #36] ; 0x24 + 80043e6: f003 0302 and.w r3, r3, #2 + 80043ea: 2b00 cmp r3, #0 + 80043ec: d00a beq.n 8004404 { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); - 8003742: 687b ldr r3, [r7, #4] - 8003744: 681b ldr r3, [r3, #0] - 8003746: 685b ldr r3, [r3, #4] - 8003748: f423 3180 bic.w r1, r3, #65536 ; 0x10000 - 800374c: 687b ldr r3, [r7, #4] - 800374e: 6ada ldr r2, [r3, #44] ; 0x2c - 8003750: 687b ldr r3, [r7, #4] - 8003752: 681b ldr r3, [r3, #0] - 8003754: 430a orrs r2, r1 - 8003756: 605a str r2, [r3, #4] + 80043ee: 687b ldr r3, [r7, #4] + 80043f0: 681b ldr r3, [r3, #0] + 80043f2: 685b ldr r3, [r3, #4] + 80043f4: f423 3180 bic.w r1, r3, #65536 ; 0x10000 + 80043f8: 687b ldr r3, [r7, #4] + 80043fa: 6ada ldr r2, [r3, #44] ; 0x2c + 80043fc: 687b ldr r3, [r7, #4] + 80043fe: 681b ldr r3, [r3, #0] + 8004400: 430a orrs r2, r1 + 8004402: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) - 8003758: 687b ldr r3, [r7, #4] - 800375a: 6a5b ldr r3, [r3, #36] ; 0x24 - 800375c: f003 0304 and.w r3, r3, #4 - 8003760: 2b00 cmp r3, #0 - 8003762: d00a beq.n 800377a + 8004404: 687b ldr r3, [r7, #4] + 8004406: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004408: f003 0304 and.w r3, r3, #4 + 800440c: 2b00 cmp r3, #0 + 800440e: d00a beq.n 8004426 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); - 8003764: 687b ldr r3, [r7, #4] - 8003766: 681b ldr r3, [r3, #0] - 8003768: 685b ldr r3, [r3, #4] - 800376a: f423 2180 bic.w r1, r3, #262144 ; 0x40000 - 800376e: 687b ldr r3, [r7, #4] - 8003770: 6b1a ldr r2, [r3, #48] ; 0x30 - 8003772: 687b ldr r3, [r7, #4] - 8003774: 681b ldr r3, [r3, #0] - 8003776: 430a orrs r2, r1 - 8003778: 605a str r2, [r3, #4] + 8004410: 687b ldr r3, [r7, #4] + 8004412: 681b ldr r3, [r3, #0] + 8004414: 685b ldr r3, [r3, #4] + 8004416: f423 2180 bic.w r1, r3, #262144 ; 0x40000 + 800441a: 687b ldr r3, [r7, #4] + 800441c: 6b1a ldr r2, [r3, #48] ; 0x30 + 800441e: 687b ldr r3, [r7, #4] + 8004420: 681b ldr r3, [r3, #0] + 8004422: 430a orrs r2, r1 + 8004424: 605a str r2, [r3, #4] } /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) - 800377a: 687b ldr r3, [r7, #4] - 800377c: 6a5b ldr r3, [r3, #36] ; 0x24 - 800377e: f003 0308 and.w r3, r3, #8 - 8003782: 2b00 cmp r3, #0 - 8003784: d00a beq.n 800379c + 8004426: 687b ldr r3, [r7, #4] + 8004428: 6a5b ldr r3, [r3, #36] ; 0x24 + 800442a: f003 0308 and.w r3, r3, #8 + 800442e: 2b00 cmp r3, #0 + 8004430: d00a beq.n 8004448 { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); - 8003786: 687b ldr r3, [r7, #4] - 8003788: 681b ldr r3, [r3, #0] - 800378a: 685b ldr r3, [r3, #4] - 800378c: f423 4100 bic.w r1, r3, #32768 ; 0x8000 - 8003790: 687b ldr r3, [r7, #4] - 8003792: 6b5a ldr r2, [r3, #52] ; 0x34 - 8003794: 687b ldr r3, [r7, #4] - 8003796: 681b ldr r3, [r3, #0] - 8003798: 430a orrs r2, r1 - 800379a: 605a str r2, [r3, #4] + 8004432: 687b ldr r3, [r7, #4] + 8004434: 681b ldr r3, [r3, #0] + 8004436: 685b ldr r3, [r3, #4] + 8004438: f423 4100 bic.w r1, r3, #32768 ; 0x8000 + 800443c: 687b ldr r3, [r7, #4] + 800443e: 6b5a ldr r2, [r3, #52] ; 0x34 + 8004440: 687b ldr r3, [r7, #4] + 8004442: 681b ldr r3, [r3, #0] + 8004444: 430a orrs r2, r1 + 8004446: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) - 800379c: 687b ldr r3, [r7, #4] - 800379e: 6a5b ldr r3, [r3, #36] ; 0x24 - 80037a0: f003 0310 and.w r3, r3, #16 - 80037a4: 2b00 cmp r3, #0 - 80037a6: d00a beq.n 80037be + 8004448: 687b ldr r3, [r7, #4] + 800444a: 6a5b ldr r3, [r3, #36] ; 0x24 + 800444c: f003 0310 and.w r3, r3, #16 + 8004450: 2b00 cmp r3, #0 + 8004452: d00a beq.n 800446a { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); - 80037a8: 687b ldr r3, [r7, #4] - 80037aa: 681b ldr r3, [r3, #0] - 80037ac: 689b ldr r3, [r3, #8] - 80037ae: f423 5180 bic.w r1, r3, #4096 ; 0x1000 - 80037b2: 687b ldr r3, [r7, #4] - 80037b4: 6b9a ldr r2, [r3, #56] ; 0x38 - 80037b6: 687b ldr r3, [r7, #4] - 80037b8: 681b ldr r3, [r3, #0] - 80037ba: 430a orrs r2, r1 - 80037bc: 609a str r2, [r3, #8] + 8004454: 687b ldr r3, [r7, #4] + 8004456: 681b ldr r3, [r3, #0] + 8004458: 689b ldr r3, [r3, #8] + 800445a: f423 5180 bic.w r1, r3, #4096 ; 0x1000 + 800445e: 687b ldr r3, [r7, #4] + 8004460: 6b9a ldr r2, [r3, #56] ; 0x38 + 8004462: 687b ldr r3, [r7, #4] + 8004464: 681b ldr r3, [r3, #0] + 8004466: 430a orrs r2, r1 + 8004468: 609a str r2, [r3, #8] } /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) - 80037be: 687b ldr r3, [r7, #4] - 80037c0: 6a5b ldr r3, [r3, #36] ; 0x24 - 80037c2: f003 0320 and.w r3, r3, #32 - 80037c6: 2b00 cmp r3, #0 - 80037c8: d00a beq.n 80037e0 + 800446a: 687b ldr r3, [r7, #4] + 800446c: 6a5b ldr r3, [r3, #36] ; 0x24 + 800446e: f003 0320 and.w r3, r3, #32 + 8004472: 2b00 cmp r3, #0 + 8004474: d00a beq.n 800448c { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); - 80037ca: 687b ldr r3, [r7, #4] - 80037cc: 681b ldr r3, [r3, #0] - 80037ce: 689b ldr r3, [r3, #8] - 80037d0: f423 5100 bic.w r1, r3, #8192 ; 0x2000 - 80037d4: 687b ldr r3, [r7, #4] - 80037d6: 6bda ldr r2, [r3, #60] ; 0x3c - 80037d8: 687b ldr r3, [r7, #4] - 80037da: 681b ldr r3, [r3, #0] - 80037dc: 430a orrs r2, r1 - 80037de: 609a str r2, [r3, #8] + 8004476: 687b ldr r3, [r7, #4] + 8004478: 681b ldr r3, [r3, #0] + 800447a: 689b ldr r3, [r3, #8] + 800447c: f423 5100 bic.w r1, r3, #8192 ; 0x2000 + 8004480: 687b ldr r3, [r7, #4] + 8004482: 6bda ldr r2, [r3, #60] ; 0x3c + 8004484: 687b ldr r3, [r7, #4] + 8004486: 681b ldr r3, [r3, #0] + 8004488: 430a orrs r2, r1 + 800448a: 609a str r2, [r3, #8] } /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) - 80037e0: 687b ldr r3, [r7, #4] - 80037e2: 6a5b ldr r3, [r3, #36] ; 0x24 - 80037e4: f003 0340 and.w r3, r3, #64 ; 0x40 - 80037e8: 2b00 cmp r3, #0 - 80037ea: d01a beq.n 8003822 + 800448c: 687b ldr r3, [r7, #4] + 800448e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004490: f003 0340 and.w r3, r3, #64 ; 0x40 + 8004494: 2b00 cmp r3, #0 + 8004496: d01a beq.n 80044ce { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); - 80037ec: 687b ldr r3, [r7, #4] - 80037ee: 681b ldr r3, [r3, #0] - 80037f0: 685b ldr r3, [r3, #4] - 80037f2: f423 1180 bic.w r1, r3, #1048576 ; 0x100000 - 80037f6: 687b ldr r3, [r7, #4] - 80037f8: 6c1a ldr r2, [r3, #64] ; 0x40 - 80037fa: 687b ldr r3, [r7, #4] - 80037fc: 681b ldr r3, [r3, #0] - 80037fe: 430a orrs r2, r1 - 8003800: 605a str r2, [r3, #4] + 8004498: 687b ldr r3, [r7, #4] + 800449a: 681b ldr r3, [r3, #0] + 800449c: 685b ldr r3, [r3, #4] + 800449e: f423 1180 bic.w r1, r3, #1048576 ; 0x100000 + 80044a2: 687b ldr r3, [r7, #4] + 80044a4: 6c1a ldr r2, [r3, #64] ; 0x40 + 80044a6: 687b ldr r3, [r7, #4] + 80044a8: 681b ldr r3, [r3, #0] + 80044aa: 430a orrs r2, r1 + 80044ac: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) - 8003802: 687b ldr r3, [r7, #4] - 8003804: 6c1b ldr r3, [r3, #64] ; 0x40 - 8003806: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 - 800380a: d10a bne.n 8003822 + 80044ae: 687b ldr r3, [r7, #4] + 80044b0: 6c1b ldr r3, [r3, #64] ; 0x40 + 80044b2: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 80044b6: d10a bne.n 80044ce { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); - 800380c: 687b ldr r3, [r7, #4] - 800380e: 681b ldr r3, [r3, #0] - 8003810: 685b ldr r3, [r3, #4] - 8003812: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000 - 8003816: 687b ldr r3, [r7, #4] - 8003818: 6c5a ldr r2, [r3, #68] ; 0x44 - 800381a: 687b ldr r3, [r7, #4] - 800381c: 681b ldr r3, [r3, #0] - 800381e: 430a orrs r2, r1 - 8003820: 605a str r2, [r3, #4] + 80044b8: 687b ldr r3, [r7, #4] + 80044ba: 681b ldr r3, [r3, #0] + 80044bc: 685b ldr r3, [r3, #4] + 80044be: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000 + 80044c2: 687b ldr r3, [r7, #4] + 80044c4: 6c5a ldr r2, [r3, #68] ; 0x44 + 80044c6: 687b ldr r3, [r7, #4] + 80044c8: 681b ldr r3, [r3, #0] + 80044ca: 430a orrs r2, r1 + 80044cc: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) - 8003822: 687b ldr r3, [r7, #4] - 8003824: 6a5b ldr r3, [r3, #36] ; 0x24 - 8003826: f003 0380 and.w r3, r3, #128 ; 0x80 - 800382a: 2b00 cmp r3, #0 - 800382c: d00a beq.n 8003844 + 80044ce: 687b ldr r3, [r7, #4] + 80044d0: 6a5b ldr r3, [r3, #36] ; 0x24 + 80044d2: f003 0380 and.w r3, r3, #128 ; 0x80 + 80044d6: 2b00 cmp r3, #0 + 80044d8: d00a beq.n 80044f0 { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); - 800382e: 687b ldr r3, [r7, #4] - 8003830: 681b ldr r3, [r3, #0] - 8003832: 685b ldr r3, [r3, #4] - 8003834: f423 2100 bic.w r1, r3, #524288 ; 0x80000 - 8003838: 687b ldr r3, [r7, #4] - 800383a: 6c9a ldr r2, [r3, #72] ; 0x48 - 800383c: 687b ldr r3, [r7, #4] - 800383e: 681b ldr r3, [r3, #0] - 8003840: 430a orrs r2, r1 - 8003842: 605a str r2, [r3, #4] + 80044da: 687b ldr r3, [r7, #4] + 80044dc: 681b ldr r3, [r3, #0] + 80044de: 685b ldr r3, [r3, #4] + 80044e0: f423 2100 bic.w r1, r3, #524288 ; 0x80000 + 80044e4: 687b ldr r3, [r7, #4] + 80044e6: 6c9a ldr r2, [r3, #72] ; 0x48 + 80044e8: 687b ldr r3, [r7, #4] + 80044ea: 681b ldr r3, [r3, #0] + 80044ec: 430a orrs r2, r1 + 80044ee: 605a str r2, [r3, #4] } } - 8003844: bf00 nop - 8003846: 370c adds r7, #12 - 8003848: 46bd mov sp, r7 - 800384a: f85d 7b04 ldr.w r7, [sp], #4 - 800384e: 4770 bx lr + 80044f0: bf00 nop + 80044f2: 370c adds r7, #12 + 80044f4: 46bd mov sp, r7 + 80044f6: f85d 7b04 ldr.w r7, [sp], #4 + 80044fa: 4770 bx lr -08003850 : +080044fc : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { - 8003850: b580 push {r7, lr} - 8003852: b086 sub sp, #24 - 8003854: af02 add r7, sp, #8 - 8003856: 6078 str r0, [r7, #4] + 80044fc: b580 push {r7, lr} + 80044fe: b086 sub sp, #24 + 8004500: af02 add r7, sp, #8 + 8004502: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - 8003858: 687b ldr r3, [r7, #4] - 800385a: 2200 movs r2, #0 - 800385c: f8c3 2080 str.w r2, [r3, #128] ; 0x80 + 8004504: 687b ldr r3, [r7, #4] + 8004506: 2200 movs r2, #0 + 8004508: f8c3 2080 str.w r2, [r3, #128] ; 0x80 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - 8003860: f7fd fcee bl 8001240 - 8003864: 60f8 str r0, [r7, #12] + 800450c: f7fd faf0 bl 8001af0 + 8004510: 60f8 str r0, [r7, #12] /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - 8003866: 687b ldr r3, [r7, #4] - 8003868: 681b ldr r3, [r3, #0] - 800386a: 681b ldr r3, [r3, #0] - 800386c: f003 0308 and.w r3, r3, #8 - 8003870: 2b08 cmp r3, #8 - 8003872: d10e bne.n 8003892 + 8004512: 687b ldr r3, [r7, #4] + 8004514: 681b ldr r3, [r3, #0] + 8004516: 681b ldr r3, [r3, #0] + 8004518: f003 0308 and.w r3, r3, #8 + 800451c: 2b08 cmp r3, #8 + 800451e: d10e bne.n 800453e { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - 8003874: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 - 8003878: 9300 str r3, [sp, #0] - 800387a: 68fb ldr r3, [r7, #12] - 800387c: 2200 movs r2, #0 - 800387e: f44f 1100 mov.w r1, #2097152 ; 0x200000 - 8003882: 6878 ldr r0, [r7, #4] - 8003884: f000 f82d bl 80038e2 - 8003888: 4603 mov r3, r0 - 800388a: 2b00 cmp r3, #0 - 800388c: d001 beq.n 8003892 + 8004520: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 + 8004524: 9300 str r3, [sp, #0] + 8004526: 68fb ldr r3, [r7, #12] + 8004528: 2200 movs r2, #0 + 800452a: f44f 1100 mov.w r1, #2097152 ; 0x200000 + 800452e: 6878 ldr r0, [r7, #4] + 8004530: f000 f82d bl 800458e + 8004534: 4603 mov r3, r0 + 8004536: 2b00 cmp r3, #0 + 8004538: d001 beq.n 800453e { /* Timeout occurred */ return HAL_TIMEOUT; - 800388e: 2303 movs r3, #3 - 8003890: e023 b.n 80038da + 800453a: 2303 movs r3, #3 + 800453c: e023 b.n 8004586 } } #if defined(USART_ISR_REACK) /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - 8003892: 687b ldr r3, [r7, #4] - 8003894: 681b ldr r3, [r3, #0] - 8003896: 681b ldr r3, [r3, #0] - 8003898: f003 0304 and.w r3, r3, #4 - 800389c: 2b04 cmp r3, #4 - 800389e: d10e bne.n 80038be + 800453e: 687b ldr r3, [r7, #4] + 8004540: 681b ldr r3, [r3, #0] + 8004542: 681b ldr r3, [r3, #0] + 8004544: f003 0304 and.w r3, r3, #4 + 8004548: 2b04 cmp r3, #4 + 800454a: d10e bne.n 800456a { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - 80038a0: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 - 80038a4: 9300 str r3, [sp, #0] - 80038a6: 68fb ldr r3, [r7, #12] - 80038a8: 2200 movs r2, #0 - 80038aa: f44f 0180 mov.w r1, #4194304 ; 0x400000 - 80038ae: 6878 ldr r0, [r7, #4] - 80038b0: f000 f817 bl 80038e2 - 80038b4: 4603 mov r3, r0 - 80038b6: 2b00 cmp r3, #0 - 80038b8: d001 beq.n 80038be + 800454c: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 + 8004550: 9300 str r3, [sp, #0] + 8004552: 68fb ldr r3, [r7, #12] + 8004554: 2200 movs r2, #0 + 8004556: f44f 0180 mov.w r1, #4194304 ; 0x400000 + 800455a: 6878 ldr r0, [r7, #4] + 800455c: f000 f817 bl 800458e + 8004560: 4603 mov r3, r0 + 8004562: 2b00 cmp r3, #0 + 8004564: d001 beq.n 800456a { /* Timeout occurred */ return HAL_TIMEOUT; - 80038ba: 2303 movs r3, #3 - 80038bc: e00d b.n 80038da + 8004566: 2303 movs r3, #3 + 8004568: e00d b.n 8004586 } } #endif /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; - 80038be: 687b ldr r3, [r7, #4] - 80038c0: 2220 movs r2, #32 - 80038c2: 679a str r2, [r3, #120] ; 0x78 + 800456a: 687b ldr r3, [r7, #4] + 800456c: 2220 movs r2, #32 + 800456e: 679a str r2, [r3, #120] ; 0x78 huart->RxState = HAL_UART_STATE_READY; - 80038c4: 687b ldr r3, [r7, #4] - 80038c6: 2220 movs r2, #32 - 80038c8: 67da str r2, [r3, #124] ; 0x7c + 8004570: 687b ldr r3, [r7, #4] + 8004572: 2220 movs r2, #32 + 8004574: 67da str r2, [r3, #124] ; 0x7c huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 80038ca: 687b ldr r3, [r7, #4] - 80038cc: 2200 movs r2, #0 - 80038ce: 661a str r2, [r3, #96] ; 0x60 + 8004576: 687b ldr r3, [r7, #4] + 8004578: 2200 movs r2, #0 + 800457a: 661a str r2, [r3, #96] ; 0x60 __HAL_UNLOCK(huart); - 80038d0: 687b ldr r3, [r7, #4] - 80038d2: 2200 movs r2, #0 - 80038d4: f883 2074 strb.w r2, [r3, #116] ; 0x74 + 800457c: 687b ldr r3, [r7, #4] + 800457e: 2200 movs r2, #0 + 8004580: f883 2074 strb.w r2, [r3, #116] ; 0x74 return HAL_OK; - 80038d8: 2300 movs r3, #0 + 8004584: 2300 movs r3, #0 } - 80038da: 4618 mov r0, r3 - 80038dc: 3710 adds r7, #16 - 80038de: 46bd mov sp, r7 - 80038e0: bd80 pop {r7, pc} + 8004586: 4618 mov r0, r3 + 8004588: 3710 adds r7, #16 + 800458a: 46bd mov sp, r7 + 800458c: bd80 pop {r7, pc} -080038e2 : +0800458e : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { - 80038e2: b580 push {r7, lr} - 80038e4: b084 sub sp, #16 - 80038e6: af00 add r7, sp, #0 - 80038e8: 60f8 str r0, [r7, #12] - 80038ea: 60b9 str r1, [r7, #8] - 80038ec: 603b str r3, [r7, #0] - 80038ee: 4613 mov r3, r2 - 80038f0: 71fb strb r3, [r7, #7] + 800458e: b580 push {r7, lr} + 8004590: b084 sub sp, #16 + 8004592: af00 add r7, sp, #0 + 8004594: 60f8 str r0, [r7, #12] + 8004596: 60b9 str r1, [r7, #8] + 8004598: 603b str r3, [r7, #0] + 800459a: 4613 mov r3, r2 + 800459c: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - 80038f2: e05e b.n 80039b2 + 800459e: e05e b.n 800465e { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) - 80038f4: 69bb ldr r3, [r7, #24] - 80038f6: f1b3 3fff cmp.w r3, #4294967295 - 80038fa: d05a beq.n 80039b2 + 80045a0: 69bb ldr r3, [r7, #24] + 80045a2: f1b3 3fff cmp.w r3, #4294967295 + 80045a6: d05a beq.n 800465e { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - 80038fc: f7fd fca0 bl 8001240 - 8003900: 4602 mov r2, r0 - 8003902: 683b ldr r3, [r7, #0] - 8003904: 1ad3 subs r3, r2, r3 - 8003906: 69ba ldr r2, [r7, #24] - 8003908: 429a cmp r2, r3 - 800390a: d302 bcc.n 8003912 - 800390c: 69bb ldr r3, [r7, #24] - 800390e: 2b00 cmp r3, #0 - 8003910: d11b bne.n 800394a + 80045a8: f7fd faa2 bl 8001af0 + 80045ac: 4602 mov r2, r0 + 80045ae: 683b ldr r3, [r7, #0] + 80045b0: 1ad3 subs r3, r2, r3 + 80045b2: 69ba ldr r2, [r7, #24] + 80045b4: 429a cmp r2, r3 + 80045b6: d302 bcc.n 80045be + 80045b8: 69bb ldr r3, [r7, #24] + 80045ba: 2b00 cmp r3, #0 + 80045bc: d11b bne.n 80045f6 { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); - 8003912: 68fb ldr r3, [r7, #12] - 8003914: 681b ldr r3, [r3, #0] - 8003916: 681a ldr r2, [r3, #0] - 8003918: 68fb ldr r3, [r7, #12] - 800391a: 681b ldr r3, [r3, #0] - 800391c: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 - 8003920: 601a str r2, [r3, #0] + 80045be: 68fb ldr r3, [r7, #12] + 80045c0: 681b ldr r3, [r3, #0] + 80045c2: 681a ldr r2, [r3, #0] + 80045c4: 68fb ldr r3, [r7, #12] + 80045c6: 681b ldr r3, [r3, #0] + 80045c8: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 + 80045cc: 601a str r2, [r3, #0] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 8003922: 68fb ldr r3, [r7, #12] - 8003924: 681b ldr r3, [r3, #0] - 8003926: 689a ldr r2, [r3, #8] - 8003928: 68fb ldr r3, [r7, #12] - 800392a: 681b ldr r3, [r3, #0] - 800392c: f022 0201 bic.w r2, r2, #1 - 8003930: 609a str r2, [r3, #8] + 80045ce: 68fb ldr r3, [r7, #12] + 80045d0: 681b ldr r3, [r3, #0] + 80045d2: 689a ldr r2, [r3, #8] + 80045d4: 68fb ldr r3, [r7, #12] + 80045d6: 681b ldr r3, [r3, #0] + 80045d8: f022 0201 bic.w r2, r2, #1 + 80045dc: 609a str r2, [r3, #8] huart->gState = HAL_UART_STATE_READY; - 8003932: 68fb ldr r3, [r7, #12] - 8003934: 2220 movs r2, #32 - 8003936: 679a str r2, [r3, #120] ; 0x78 + 80045de: 68fb ldr r3, [r7, #12] + 80045e0: 2220 movs r2, #32 + 80045e2: 679a str r2, [r3, #120] ; 0x78 huart->RxState = HAL_UART_STATE_READY; - 8003938: 68fb ldr r3, [r7, #12] - 800393a: 2220 movs r2, #32 - 800393c: 67da str r2, [r3, #124] ; 0x7c + 80045e4: 68fb ldr r3, [r7, #12] + 80045e6: 2220 movs r2, #32 + 80045e8: 67da str r2, [r3, #124] ; 0x7c __HAL_UNLOCK(huart); - 800393e: 68fb ldr r3, [r7, #12] - 8003940: 2200 movs r2, #0 - 8003942: f883 2074 strb.w r2, [r3, #116] ; 0x74 + 80045ea: 68fb ldr r3, [r7, #12] + 80045ec: 2200 movs r2, #0 + 80045ee: f883 2074 strb.w r2, [r3, #116] ; 0x74 return HAL_TIMEOUT; - 8003946: 2303 movs r3, #3 - 8003948: e043 b.n 80039d2 + 80045f2: 2303 movs r3, #3 + 80045f4: e043 b.n 800467e } if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) - 800394a: 68fb ldr r3, [r7, #12] - 800394c: 681b ldr r3, [r3, #0] - 800394e: 681b ldr r3, [r3, #0] - 8003950: f003 0304 and.w r3, r3, #4 - 8003954: 2b00 cmp r3, #0 - 8003956: d02c beq.n 80039b2 + 80045f6: 68fb ldr r3, [r7, #12] + 80045f8: 681b ldr r3, [r3, #0] + 80045fa: 681b ldr r3, [r3, #0] + 80045fc: f003 0304 and.w r3, r3, #4 + 8004600: 2b00 cmp r3, #0 + 8004602: d02c beq.n 800465e { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) - 8003958: 68fb ldr r3, [r7, #12] - 800395a: 681b ldr r3, [r3, #0] - 800395c: 69db ldr r3, [r3, #28] - 800395e: f403 6300 and.w r3, r3, #2048 ; 0x800 - 8003962: f5b3 6f00 cmp.w r3, #2048 ; 0x800 - 8003966: d124 bne.n 80039b2 + 8004604: 68fb ldr r3, [r7, #12] + 8004606: 681b ldr r3, [r3, #0] + 8004608: 69db ldr r3, [r3, #28] + 800460a: f403 6300 and.w r3, r3, #2048 ; 0x800 + 800460e: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 8004612: d124 bne.n 800465e { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - 8003968: 68fb ldr r3, [r7, #12] - 800396a: 681b ldr r3, [r3, #0] - 800396c: f44f 6200 mov.w r2, #2048 ; 0x800 - 8003970: 621a str r2, [r3, #32] + 8004614: 68fb ldr r3, [r7, #12] + 8004616: 681b ldr r3, [r3, #0] + 8004618: f44f 6200 mov.w r2, #2048 ; 0x800 + 800461c: 621a str r2, [r3, #32] /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); - 8003972: 68fb ldr r3, [r7, #12] - 8003974: 681b ldr r3, [r3, #0] - 8003976: 681a ldr r2, [r3, #0] - 8003978: 68fb ldr r3, [r7, #12] - 800397a: 681b ldr r3, [r3, #0] - 800397c: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 - 8003980: 601a str r2, [r3, #0] + 800461e: 68fb ldr r3, [r7, #12] + 8004620: 681b ldr r3, [r3, #0] + 8004622: 681a ldr r2, [r3, #0] + 8004624: 68fb ldr r3, [r7, #12] + 8004626: 681b ldr r3, [r3, #0] + 8004628: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 + 800462c: 601a str r2, [r3, #0] CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 8003982: 68fb ldr r3, [r7, #12] - 8003984: 681b ldr r3, [r3, #0] - 8003986: 689a ldr r2, [r3, #8] - 8003988: 68fb ldr r3, [r7, #12] - 800398a: 681b ldr r3, [r3, #0] - 800398c: f022 0201 bic.w r2, r2, #1 - 8003990: 609a str r2, [r3, #8] + 800462e: 68fb ldr r3, [r7, #12] + 8004630: 681b ldr r3, [r3, #0] + 8004632: 689a ldr r2, [r3, #8] + 8004634: 68fb ldr r3, [r7, #12] + 8004636: 681b ldr r3, [r3, #0] + 8004638: f022 0201 bic.w r2, r2, #1 + 800463c: 609a str r2, [r3, #8] huart->gState = HAL_UART_STATE_READY; - 8003992: 68fb ldr r3, [r7, #12] - 8003994: 2220 movs r2, #32 - 8003996: 679a str r2, [r3, #120] ; 0x78 + 800463e: 68fb ldr r3, [r7, #12] + 8004640: 2220 movs r2, #32 + 8004642: 679a str r2, [r3, #120] ; 0x78 huart->RxState = HAL_UART_STATE_READY; - 8003998: 68fb ldr r3, [r7, #12] - 800399a: 2220 movs r2, #32 - 800399c: 67da str r2, [r3, #124] ; 0x7c + 8004644: 68fb ldr r3, [r7, #12] + 8004646: 2220 movs r2, #32 + 8004648: 67da str r2, [r3, #124] ; 0x7c huart->ErrorCode = HAL_UART_ERROR_RTO; - 800399e: 68fb ldr r3, [r7, #12] - 80039a0: 2220 movs r2, #32 - 80039a2: f8c3 2080 str.w r2, [r3, #128] ; 0x80 + 800464a: 68fb ldr r3, [r7, #12] + 800464c: 2220 movs r2, #32 + 800464e: f8c3 2080 str.w r2, [r3, #128] ; 0x80 /* Process Unlocked */ __HAL_UNLOCK(huart); - 80039a6: 68fb ldr r3, [r7, #12] - 80039a8: 2200 movs r2, #0 - 80039aa: f883 2074 strb.w r2, [r3, #116] ; 0x74 + 8004652: 68fb ldr r3, [r7, #12] + 8004654: 2200 movs r2, #0 + 8004656: f883 2074 strb.w r2, [r3, #116] ; 0x74 return HAL_TIMEOUT; - 80039ae: 2303 movs r3, #3 - 80039b0: e00f b.n 80039d2 + 800465a: 2303 movs r3, #3 + 800465c: e00f b.n 800467e while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - 80039b2: 68fb ldr r3, [r7, #12] - 80039b4: 681b ldr r3, [r3, #0] - 80039b6: 69da ldr r2, [r3, #28] - 80039b8: 68bb ldr r3, [r7, #8] - 80039ba: 4013 ands r3, r2 - 80039bc: 68ba ldr r2, [r7, #8] - 80039be: 429a cmp r2, r3 - 80039c0: bf0c ite eq - 80039c2: 2301 moveq r3, #1 - 80039c4: 2300 movne r3, #0 - 80039c6: b2db uxtb r3, r3 - 80039c8: 461a mov r2, r3 - 80039ca: 79fb ldrb r3, [r7, #7] - 80039cc: 429a cmp r2, r3 - 80039ce: d091 beq.n 80038f4 + 800465e: 68fb ldr r3, [r7, #12] + 8004660: 681b ldr r3, [r3, #0] + 8004662: 69da ldr r2, [r3, #28] + 8004664: 68bb ldr r3, [r7, #8] + 8004666: 4013 ands r3, r2 + 8004668: 68ba ldr r2, [r7, #8] + 800466a: 429a cmp r2, r3 + 800466c: bf0c ite eq + 800466e: 2301 moveq r3, #1 + 8004670: 2300 movne r3, #0 + 8004672: b2db uxtb r3, r3 + 8004674: 461a mov r2, r3 + 8004676: 79fb ldrb r3, [r7, #7] + 8004678: 429a cmp r2, r3 + 800467a: d091 beq.n 80045a0 } } } } return HAL_OK; - 80039d0: 2300 movs r3, #0 + 800467c: 2300 movs r3, #0 } - 80039d2: 4618 mov r0, r3 - 80039d4: 3710 adds r7, #16 - 80039d6: 46bd mov sp, r7 - 80039d8: bd80 pop {r7, pc} + 800467e: 4618 mov r0, r3 + 8004680: 3710 adds r7, #16 + 8004682: 46bd mov sp, r7 + 8004684: bd80 pop {r7, pc} ... -080039dc <__errno>: - 80039dc: 4b01 ldr r3, [pc, #4] ; (80039e4 <__errno+0x8>) - 80039de: 6818 ldr r0, [r3, #0] - 80039e0: 4770 bx lr - 80039e2: bf00 nop - 80039e4: 2000000c .word 0x2000000c - -080039e8 <__libc_init_array>: - 80039e8: b570 push {r4, r5, r6, lr} - 80039ea: 4d0d ldr r5, [pc, #52] ; (8003a20 <__libc_init_array+0x38>) - 80039ec: 4c0d ldr r4, [pc, #52] ; (8003a24 <__libc_init_array+0x3c>) - 80039ee: 1b64 subs r4, r4, r5 - 80039f0: 10a4 asrs r4, r4, #2 - 80039f2: 2600 movs r6, #0 - 80039f4: 42a6 cmp r6, r4 - 80039f6: d109 bne.n 8003a0c <__libc_init_array+0x24> - 80039f8: 4d0b ldr r5, [pc, #44] ; (8003a28 <__libc_init_array+0x40>) - 80039fa: 4c0c ldr r4, [pc, #48] ; (8003a2c <__libc_init_array+0x44>) - 80039fc: f000 ffec bl 80049d8 <_init> - 8003a00: 1b64 subs r4, r4, r5 - 8003a02: 10a4 asrs r4, r4, #2 - 8003a04: 2600 movs r6, #0 - 8003a06: 42a6 cmp r6, r4 - 8003a08: d105 bne.n 8003a16 <__libc_init_array+0x2e> - 8003a0a: bd70 pop {r4, r5, r6, pc} - 8003a0c: f855 3b04 ldr.w r3, [r5], #4 - 8003a10: 4798 blx r3 - 8003a12: 3601 adds r6, #1 - 8003a14: e7ee b.n 80039f4 <__libc_init_array+0xc> - 8003a16: f855 3b04 ldr.w r3, [r5], #4 - 8003a1a: 4798 blx r3 - 8003a1c: 3601 adds r6, #1 - 8003a1e: e7f2 b.n 8003a06 <__libc_init_array+0x1e> - 8003a20: 08004cb4 .word 0x08004cb4 - 8003a24: 08004cb4 .word 0x08004cb4 - 8003a28: 08004cb4 .word 0x08004cb4 - 8003a2c: 08004cb8 .word 0x08004cb8 - -08003a30 : - 8003a30: 4402 add r2, r0 - 8003a32: 4603 mov r3, r0 - 8003a34: 4293 cmp r3, r2 - 8003a36: d100 bne.n 8003a3a - 8003a38: 4770 bx lr - 8003a3a: f803 1b01 strb.w r1, [r3], #1 - 8003a3e: e7f9 b.n 8003a34 - -08003a40 : - 8003a40: b40f push {r0, r1, r2, r3} - 8003a42: 4b0a ldr r3, [pc, #40] ; (8003a6c ) - 8003a44: b513 push {r0, r1, r4, lr} - 8003a46: 681c ldr r4, [r3, #0] - 8003a48: b124 cbz r4, 8003a54 - 8003a4a: 69a3 ldr r3, [r4, #24] - 8003a4c: b913 cbnz r3, 8003a54 - 8003a4e: 4620 mov r0, r4 - 8003a50: f000 fa5e bl 8003f10 <__sinit> - 8003a54: ab05 add r3, sp, #20 - 8003a56: 9a04 ldr r2, [sp, #16] - 8003a58: 68a1 ldr r1, [r4, #8] - 8003a5a: 9301 str r3, [sp, #4] - 8003a5c: 4620 mov r0, r4 - 8003a5e: f000 fc2f bl 80042c0 <_vfiprintf_r> - 8003a62: b002 add sp, #8 - 8003a64: e8bd 4010 ldmia.w sp!, {r4, lr} - 8003a68: b004 add sp, #16 - 8003a6a: 4770 bx lr - 8003a6c: 2000000c .word 0x2000000c - -08003a70 <_puts_r>: - 8003a70: b570 push {r4, r5, r6, lr} - 8003a72: 460e mov r6, r1 - 8003a74: 4605 mov r5, r0 - 8003a76: b118 cbz r0, 8003a80 <_puts_r+0x10> - 8003a78: 6983 ldr r3, [r0, #24] - 8003a7a: b90b cbnz r3, 8003a80 <_puts_r+0x10> - 8003a7c: f000 fa48 bl 8003f10 <__sinit> - 8003a80: 69ab ldr r3, [r5, #24] - 8003a82: 68ac ldr r4, [r5, #8] - 8003a84: b913 cbnz r3, 8003a8c <_puts_r+0x1c> - 8003a86: 4628 mov r0, r5 - 8003a88: f000 fa42 bl 8003f10 <__sinit> - 8003a8c: 4b2c ldr r3, [pc, #176] ; (8003b40 <_puts_r+0xd0>) - 8003a8e: 429c cmp r4, r3 - 8003a90: d120 bne.n 8003ad4 <_puts_r+0x64> - 8003a92: 686c ldr r4, [r5, #4] - 8003a94: 6e63 ldr r3, [r4, #100] ; 0x64 - 8003a96: 07db lsls r3, r3, #31 - 8003a98: d405 bmi.n 8003aa6 <_puts_r+0x36> - 8003a9a: 89a3 ldrh r3, [r4, #12] - 8003a9c: 0598 lsls r0, r3, #22 - 8003a9e: d402 bmi.n 8003aa6 <_puts_r+0x36> - 8003aa0: 6da0 ldr r0, [r4, #88] ; 0x58 - 8003aa2: f000 fad3 bl 800404c <__retarget_lock_acquire_recursive> - 8003aa6: 89a3 ldrh r3, [r4, #12] - 8003aa8: 0719 lsls r1, r3, #28 - 8003aaa: d51d bpl.n 8003ae8 <_puts_r+0x78> - 8003aac: 6923 ldr r3, [r4, #16] - 8003aae: b1db cbz r3, 8003ae8 <_puts_r+0x78> - 8003ab0: 3e01 subs r6, #1 - 8003ab2: 68a3 ldr r3, [r4, #8] - 8003ab4: f816 1f01 ldrb.w r1, [r6, #1]! - 8003ab8: 3b01 subs r3, #1 - 8003aba: 60a3 str r3, [r4, #8] - 8003abc: bb39 cbnz r1, 8003b0e <_puts_r+0x9e> - 8003abe: 2b00 cmp r3, #0 - 8003ac0: da38 bge.n 8003b34 <_puts_r+0xc4> - 8003ac2: 4622 mov r2, r4 - 8003ac4: 210a movs r1, #10 - 8003ac6: 4628 mov r0, r5 - 8003ac8: f000 f848 bl 8003b5c <__swbuf_r> - 8003acc: 3001 adds r0, #1 - 8003ace: d011 beq.n 8003af4 <_puts_r+0x84> - 8003ad0: 250a movs r5, #10 - 8003ad2: e011 b.n 8003af8 <_puts_r+0x88> - 8003ad4: 4b1b ldr r3, [pc, #108] ; (8003b44 <_puts_r+0xd4>) - 8003ad6: 429c cmp r4, r3 - 8003ad8: d101 bne.n 8003ade <_puts_r+0x6e> - 8003ada: 68ac ldr r4, [r5, #8] - 8003adc: e7da b.n 8003a94 <_puts_r+0x24> - 8003ade: 4b1a ldr r3, [pc, #104] ; (8003b48 <_puts_r+0xd8>) - 8003ae0: 429c cmp r4, r3 - 8003ae2: bf08 it eq - 8003ae4: 68ec ldreq r4, [r5, #12] - 8003ae6: e7d5 b.n 8003a94 <_puts_r+0x24> - 8003ae8: 4621 mov r1, r4 - 8003aea: 4628 mov r0, r5 - 8003aec: f000 f888 bl 8003c00 <__swsetup_r> - 8003af0: 2800 cmp r0, #0 - 8003af2: d0dd beq.n 8003ab0 <_puts_r+0x40> - 8003af4: f04f 35ff mov.w r5, #4294967295 - 8003af8: 6e63 ldr r3, [r4, #100] ; 0x64 - 8003afa: 07da lsls r2, r3, #31 - 8003afc: d405 bmi.n 8003b0a <_puts_r+0x9a> - 8003afe: 89a3 ldrh r3, [r4, #12] - 8003b00: 059b lsls r3, r3, #22 - 8003b02: d402 bmi.n 8003b0a <_puts_r+0x9a> - 8003b04: 6da0 ldr r0, [r4, #88] ; 0x58 - 8003b06: f000 faa2 bl 800404e <__retarget_lock_release_recursive> - 8003b0a: 4628 mov r0, r5 - 8003b0c: bd70 pop {r4, r5, r6, pc} - 8003b0e: 2b00 cmp r3, #0 - 8003b10: da04 bge.n 8003b1c <_puts_r+0xac> - 8003b12: 69a2 ldr r2, [r4, #24] - 8003b14: 429a cmp r2, r3 - 8003b16: dc06 bgt.n 8003b26 <_puts_r+0xb6> - 8003b18: 290a cmp r1, #10 - 8003b1a: d004 beq.n 8003b26 <_puts_r+0xb6> - 8003b1c: 6823 ldr r3, [r4, #0] - 8003b1e: 1c5a adds r2, r3, #1 - 8003b20: 6022 str r2, [r4, #0] - 8003b22: 7019 strb r1, [r3, #0] - 8003b24: e7c5 b.n 8003ab2 <_puts_r+0x42> - 8003b26: 4622 mov r2, r4 - 8003b28: 4628 mov r0, r5 - 8003b2a: f000 f817 bl 8003b5c <__swbuf_r> - 8003b2e: 3001 adds r0, #1 - 8003b30: d1bf bne.n 8003ab2 <_puts_r+0x42> - 8003b32: e7df b.n 8003af4 <_puts_r+0x84> - 8003b34: 6823 ldr r3, [r4, #0] - 8003b36: 250a movs r5, #10 - 8003b38: 1c5a adds r2, r3, #1 - 8003b3a: 6022 str r2, [r4, #0] - 8003b3c: 701d strb r5, [r3, #0] - 8003b3e: e7db b.n 8003af8 <_puts_r+0x88> - 8003b40: 08004c38 .word 0x08004c38 - 8003b44: 08004c58 .word 0x08004c58 - 8003b48: 08004c18 .word 0x08004c18 - -08003b4c : - 8003b4c: 4b02 ldr r3, [pc, #8] ; (8003b58 ) - 8003b4e: 4601 mov r1, r0 - 8003b50: 6818 ldr r0, [r3, #0] - 8003b52: f7ff bf8d b.w 8003a70 <_puts_r> - 8003b56: bf00 nop - 8003b58: 2000000c .word 0x2000000c - -08003b5c <__swbuf_r>: - 8003b5c: b5f8 push {r3, r4, r5, r6, r7, lr} - 8003b5e: 460e mov r6, r1 - 8003b60: 4614 mov r4, r2 - 8003b62: 4605 mov r5, r0 - 8003b64: b118 cbz r0, 8003b6e <__swbuf_r+0x12> - 8003b66: 6983 ldr r3, [r0, #24] - 8003b68: b90b cbnz r3, 8003b6e <__swbuf_r+0x12> - 8003b6a: f000 f9d1 bl 8003f10 <__sinit> - 8003b6e: 4b21 ldr r3, [pc, #132] ; (8003bf4 <__swbuf_r+0x98>) - 8003b70: 429c cmp r4, r3 - 8003b72: d12b bne.n 8003bcc <__swbuf_r+0x70> - 8003b74: 686c ldr r4, [r5, #4] - 8003b76: 69a3 ldr r3, [r4, #24] - 8003b78: 60a3 str r3, [r4, #8] - 8003b7a: 89a3 ldrh r3, [r4, #12] - 8003b7c: 071a lsls r2, r3, #28 - 8003b7e: d52f bpl.n 8003be0 <__swbuf_r+0x84> - 8003b80: 6923 ldr r3, [r4, #16] - 8003b82: b36b cbz r3, 8003be0 <__swbuf_r+0x84> - 8003b84: 6923 ldr r3, [r4, #16] - 8003b86: 6820 ldr r0, [r4, #0] - 8003b88: 1ac0 subs r0, r0, r3 - 8003b8a: 6963 ldr r3, [r4, #20] - 8003b8c: b2f6 uxtb r6, r6 - 8003b8e: 4283 cmp r3, r0 - 8003b90: 4637 mov r7, r6 - 8003b92: dc04 bgt.n 8003b9e <__swbuf_r+0x42> - 8003b94: 4621 mov r1, r4 - 8003b96: 4628 mov r0, r5 - 8003b98: f000 f926 bl 8003de8 <_fflush_r> - 8003b9c: bb30 cbnz r0, 8003bec <__swbuf_r+0x90> - 8003b9e: 68a3 ldr r3, [r4, #8] - 8003ba0: 3b01 subs r3, #1 - 8003ba2: 60a3 str r3, [r4, #8] - 8003ba4: 6823 ldr r3, [r4, #0] - 8003ba6: 1c5a adds r2, r3, #1 - 8003ba8: 6022 str r2, [r4, #0] - 8003baa: 701e strb r6, [r3, #0] - 8003bac: 6963 ldr r3, [r4, #20] - 8003bae: 3001 adds r0, #1 - 8003bb0: 4283 cmp r3, r0 - 8003bb2: d004 beq.n 8003bbe <__swbuf_r+0x62> - 8003bb4: 89a3 ldrh r3, [r4, #12] - 8003bb6: 07db lsls r3, r3, #31 - 8003bb8: d506 bpl.n 8003bc8 <__swbuf_r+0x6c> - 8003bba: 2e0a cmp r6, #10 - 8003bbc: d104 bne.n 8003bc8 <__swbuf_r+0x6c> - 8003bbe: 4621 mov r1, r4 - 8003bc0: 4628 mov r0, r5 - 8003bc2: f000 f911 bl 8003de8 <_fflush_r> - 8003bc6: b988 cbnz r0, 8003bec <__swbuf_r+0x90> - 8003bc8: 4638 mov r0, r7 - 8003bca: bdf8 pop {r3, r4, r5, r6, r7, pc} - 8003bcc: 4b0a ldr r3, [pc, #40] ; (8003bf8 <__swbuf_r+0x9c>) - 8003bce: 429c cmp r4, r3 - 8003bd0: d101 bne.n 8003bd6 <__swbuf_r+0x7a> - 8003bd2: 68ac ldr r4, [r5, #8] - 8003bd4: e7cf b.n 8003b76 <__swbuf_r+0x1a> - 8003bd6: 4b09 ldr r3, [pc, #36] ; (8003bfc <__swbuf_r+0xa0>) - 8003bd8: 429c cmp r4, r3 - 8003bda: bf08 it eq - 8003bdc: 68ec ldreq r4, [r5, #12] - 8003bde: e7ca b.n 8003b76 <__swbuf_r+0x1a> - 8003be0: 4621 mov r1, r4 - 8003be2: 4628 mov r0, r5 - 8003be4: f000 f80c bl 8003c00 <__swsetup_r> - 8003be8: 2800 cmp r0, #0 - 8003bea: d0cb beq.n 8003b84 <__swbuf_r+0x28> - 8003bec: f04f 37ff mov.w r7, #4294967295 - 8003bf0: e7ea b.n 8003bc8 <__swbuf_r+0x6c> - 8003bf2: bf00 nop - 8003bf4: 08004c38 .word 0x08004c38 - 8003bf8: 08004c58 .word 0x08004c58 - 8003bfc: 08004c18 .word 0x08004c18 - -08003c00 <__swsetup_r>: - 8003c00: 4b32 ldr r3, [pc, #200] ; (8003ccc <__swsetup_r+0xcc>) - 8003c02: b570 push {r4, r5, r6, lr} - 8003c04: 681d ldr r5, [r3, #0] - 8003c06: 4606 mov r6, r0 - 8003c08: 460c mov r4, r1 - 8003c0a: b125 cbz r5, 8003c16 <__swsetup_r+0x16> - 8003c0c: 69ab ldr r3, [r5, #24] - 8003c0e: b913 cbnz r3, 8003c16 <__swsetup_r+0x16> - 8003c10: 4628 mov r0, r5 - 8003c12: f000 f97d bl 8003f10 <__sinit> - 8003c16: 4b2e ldr r3, [pc, #184] ; (8003cd0 <__swsetup_r+0xd0>) - 8003c18: 429c cmp r4, r3 - 8003c1a: d10f bne.n 8003c3c <__swsetup_r+0x3c> - 8003c1c: 686c ldr r4, [r5, #4] - 8003c1e: 89a3 ldrh r3, [r4, #12] - 8003c20: f9b4 200c ldrsh.w r2, [r4, #12] - 8003c24: 0719 lsls r1, r3, #28 - 8003c26: d42c bmi.n 8003c82 <__swsetup_r+0x82> - 8003c28: 06dd lsls r5, r3, #27 - 8003c2a: d411 bmi.n 8003c50 <__swsetup_r+0x50> - 8003c2c: 2309 movs r3, #9 - 8003c2e: 6033 str r3, [r6, #0] - 8003c30: f042 0340 orr.w r3, r2, #64 ; 0x40 - 8003c34: 81a3 strh r3, [r4, #12] - 8003c36: f04f 30ff mov.w r0, #4294967295 - 8003c3a: e03e b.n 8003cba <__swsetup_r+0xba> - 8003c3c: 4b25 ldr r3, [pc, #148] ; (8003cd4 <__swsetup_r+0xd4>) - 8003c3e: 429c cmp r4, r3 - 8003c40: d101 bne.n 8003c46 <__swsetup_r+0x46> - 8003c42: 68ac ldr r4, [r5, #8] - 8003c44: e7eb b.n 8003c1e <__swsetup_r+0x1e> - 8003c46: 4b24 ldr r3, [pc, #144] ; (8003cd8 <__swsetup_r+0xd8>) - 8003c48: 429c cmp r4, r3 - 8003c4a: bf08 it eq - 8003c4c: 68ec ldreq r4, [r5, #12] - 8003c4e: e7e6 b.n 8003c1e <__swsetup_r+0x1e> - 8003c50: 0758 lsls r0, r3, #29 - 8003c52: d512 bpl.n 8003c7a <__swsetup_r+0x7a> - 8003c54: 6b61 ldr r1, [r4, #52] ; 0x34 - 8003c56: b141 cbz r1, 8003c6a <__swsetup_r+0x6a> - 8003c58: f104 0344 add.w r3, r4, #68 ; 0x44 - 8003c5c: 4299 cmp r1, r3 - 8003c5e: d002 beq.n 8003c66 <__swsetup_r+0x66> - 8003c60: 4630 mov r0, r6 - 8003c62: f000 fa59 bl 8004118 <_free_r> - 8003c66: 2300 movs r3, #0 - 8003c68: 6363 str r3, [r4, #52] ; 0x34 - 8003c6a: 89a3 ldrh r3, [r4, #12] - 8003c6c: f023 0324 bic.w r3, r3, #36 ; 0x24 - 8003c70: 81a3 strh r3, [r4, #12] - 8003c72: 2300 movs r3, #0 - 8003c74: 6063 str r3, [r4, #4] - 8003c76: 6923 ldr r3, [r4, #16] - 8003c78: 6023 str r3, [r4, #0] - 8003c7a: 89a3 ldrh r3, [r4, #12] - 8003c7c: f043 0308 orr.w r3, r3, #8 - 8003c80: 81a3 strh r3, [r4, #12] - 8003c82: 6923 ldr r3, [r4, #16] - 8003c84: b94b cbnz r3, 8003c9a <__swsetup_r+0x9a> - 8003c86: 89a3 ldrh r3, [r4, #12] - 8003c88: f403 7320 and.w r3, r3, #640 ; 0x280 - 8003c8c: f5b3 7f00 cmp.w r3, #512 ; 0x200 - 8003c90: d003 beq.n 8003c9a <__swsetup_r+0x9a> - 8003c92: 4621 mov r1, r4 - 8003c94: 4630 mov r0, r6 - 8003c96: f000 f9ff bl 8004098 <__smakebuf_r> - 8003c9a: 89a0 ldrh r0, [r4, #12] - 8003c9c: f9b4 200c ldrsh.w r2, [r4, #12] - 8003ca0: f010 0301 ands.w r3, r0, #1 - 8003ca4: d00a beq.n 8003cbc <__swsetup_r+0xbc> - 8003ca6: 2300 movs r3, #0 - 8003ca8: 60a3 str r3, [r4, #8] - 8003caa: 6963 ldr r3, [r4, #20] - 8003cac: 425b negs r3, r3 - 8003cae: 61a3 str r3, [r4, #24] - 8003cb0: 6923 ldr r3, [r4, #16] - 8003cb2: b943 cbnz r3, 8003cc6 <__swsetup_r+0xc6> - 8003cb4: f010 0080 ands.w r0, r0, #128 ; 0x80 - 8003cb8: d1ba bne.n 8003c30 <__swsetup_r+0x30> - 8003cba: bd70 pop {r4, r5, r6, pc} - 8003cbc: 0781 lsls r1, r0, #30 - 8003cbe: bf58 it pl - 8003cc0: 6963 ldrpl r3, [r4, #20] - 8003cc2: 60a3 str r3, [r4, #8] - 8003cc4: e7f4 b.n 8003cb0 <__swsetup_r+0xb0> - 8003cc6: 2000 movs r0, #0 - 8003cc8: e7f7 b.n 8003cba <__swsetup_r+0xba> - 8003cca: bf00 nop - 8003ccc: 2000000c .word 0x2000000c - 8003cd0: 08004c38 .word 0x08004c38 - 8003cd4: 08004c58 .word 0x08004c58 - 8003cd8: 08004c18 .word 0x08004c18 - -08003cdc <__sflush_r>: - 8003cdc: 898a ldrh r2, [r1, #12] - 8003cde: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} - 8003ce2: 4605 mov r5, r0 - 8003ce4: 0710 lsls r0, r2, #28 - 8003ce6: 460c mov r4, r1 - 8003ce8: d458 bmi.n 8003d9c <__sflush_r+0xc0> - 8003cea: 684b ldr r3, [r1, #4] - 8003cec: 2b00 cmp r3, #0 - 8003cee: dc05 bgt.n 8003cfc <__sflush_r+0x20> - 8003cf0: 6c0b ldr r3, [r1, #64] ; 0x40 - 8003cf2: 2b00 cmp r3, #0 - 8003cf4: dc02 bgt.n 8003cfc <__sflush_r+0x20> - 8003cf6: 2000 movs r0, #0 - 8003cf8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} - 8003cfc: 6ae6 ldr r6, [r4, #44] ; 0x2c - 8003cfe: 2e00 cmp r6, #0 - 8003d00: d0f9 beq.n 8003cf6 <__sflush_r+0x1a> - 8003d02: 2300 movs r3, #0 - 8003d04: f412 5280 ands.w r2, r2, #4096 ; 0x1000 - 8003d08: 682f ldr r7, [r5, #0] - 8003d0a: 602b str r3, [r5, #0] - 8003d0c: d032 beq.n 8003d74 <__sflush_r+0x98> - 8003d0e: 6d60 ldr r0, [r4, #84] ; 0x54 - 8003d10: 89a3 ldrh r3, [r4, #12] - 8003d12: 075a lsls r2, r3, #29 - 8003d14: d505 bpl.n 8003d22 <__sflush_r+0x46> - 8003d16: 6863 ldr r3, [r4, #4] - 8003d18: 1ac0 subs r0, r0, r3 - 8003d1a: 6b63 ldr r3, [r4, #52] ; 0x34 - 8003d1c: b10b cbz r3, 8003d22 <__sflush_r+0x46> - 8003d1e: 6c23 ldr r3, [r4, #64] ; 0x40 - 8003d20: 1ac0 subs r0, r0, r3 - 8003d22: 2300 movs r3, #0 - 8003d24: 4602 mov r2, r0 - 8003d26: 6ae6 ldr r6, [r4, #44] ; 0x2c - 8003d28: 6a21 ldr r1, [r4, #32] - 8003d2a: 4628 mov r0, r5 - 8003d2c: 47b0 blx r6 - 8003d2e: 1c43 adds r3, r0, #1 - 8003d30: 89a3 ldrh r3, [r4, #12] - 8003d32: d106 bne.n 8003d42 <__sflush_r+0x66> - 8003d34: 6829 ldr r1, [r5, #0] - 8003d36: 291d cmp r1, #29 - 8003d38: d82c bhi.n 8003d94 <__sflush_r+0xb8> - 8003d3a: 4a2a ldr r2, [pc, #168] ; (8003de4 <__sflush_r+0x108>) - 8003d3c: 40ca lsrs r2, r1 - 8003d3e: 07d6 lsls r6, r2, #31 - 8003d40: d528 bpl.n 8003d94 <__sflush_r+0xb8> - 8003d42: 2200 movs r2, #0 - 8003d44: 6062 str r2, [r4, #4] - 8003d46: 04d9 lsls r1, r3, #19 - 8003d48: 6922 ldr r2, [r4, #16] - 8003d4a: 6022 str r2, [r4, #0] - 8003d4c: d504 bpl.n 8003d58 <__sflush_r+0x7c> - 8003d4e: 1c42 adds r2, r0, #1 - 8003d50: d101 bne.n 8003d56 <__sflush_r+0x7a> - 8003d52: 682b ldr r3, [r5, #0] - 8003d54: b903 cbnz r3, 8003d58 <__sflush_r+0x7c> - 8003d56: 6560 str r0, [r4, #84] ; 0x54 - 8003d58: 6b61 ldr r1, [r4, #52] ; 0x34 - 8003d5a: 602f str r7, [r5, #0] - 8003d5c: 2900 cmp r1, #0 - 8003d5e: d0ca beq.n 8003cf6 <__sflush_r+0x1a> - 8003d60: f104 0344 add.w r3, r4, #68 ; 0x44 - 8003d64: 4299 cmp r1, r3 - 8003d66: d002 beq.n 8003d6e <__sflush_r+0x92> - 8003d68: 4628 mov r0, r5 - 8003d6a: f000 f9d5 bl 8004118 <_free_r> - 8003d6e: 2000 movs r0, #0 - 8003d70: 6360 str r0, [r4, #52] ; 0x34 - 8003d72: e7c1 b.n 8003cf8 <__sflush_r+0x1c> - 8003d74: 6a21 ldr r1, [r4, #32] - 8003d76: 2301 movs r3, #1 - 8003d78: 4628 mov r0, r5 - 8003d7a: 47b0 blx r6 - 8003d7c: 1c41 adds r1, r0, #1 - 8003d7e: d1c7 bne.n 8003d10 <__sflush_r+0x34> - 8003d80: 682b ldr r3, [r5, #0] - 8003d82: 2b00 cmp r3, #0 - 8003d84: d0c4 beq.n 8003d10 <__sflush_r+0x34> - 8003d86: 2b1d cmp r3, #29 - 8003d88: d001 beq.n 8003d8e <__sflush_r+0xb2> - 8003d8a: 2b16 cmp r3, #22 - 8003d8c: d101 bne.n 8003d92 <__sflush_r+0xb6> - 8003d8e: 602f str r7, [r5, #0] - 8003d90: e7b1 b.n 8003cf6 <__sflush_r+0x1a> - 8003d92: 89a3 ldrh r3, [r4, #12] - 8003d94: f043 0340 orr.w r3, r3, #64 ; 0x40 - 8003d98: 81a3 strh r3, [r4, #12] - 8003d9a: e7ad b.n 8003cf8 <__sflush_r+0x1c> - 8003d9c: 690f ldr r7, [r1, #16] - 8003d9e: 2f00 cmp r7, #0 - 8003da0: d0a9 beq.n 8003cf6 <__sflush_r+0x1a> - 8003da2: 0793 lsls r3, r2, #30 - 8003da4: 680e ldr r6, [r1, #0] - 8003da6: bf08 it eq - 8003da8: 694b ldreq r3, [r1, #20] - 8003daa: 600f str r7, [r1, #0] - 8003dac: bf18 it ne - 8003dae: 2300 movne r3, #0 - 8003db0: eba6 0807 sub.w r8, r6, r7 - 8003db4: 608b str r3, [r1, #8] - 8003db6: f1b8 0f00 cmp.w r8, #0 - 8003dba: dd9c ble.n 8003cf6 <__sflush_r+0x1a> - 8003dbc: 6a21 ldr r1, [r4, #32] - 8003dbe: 6aa6 ldr r6, [r4, #40] ; 0x28 - 8003dc0: 4643 mov r3, r8 - 8003dc2: 463a mov r2, r7 - 8003dc4: 4628 mov r0, r5 - 8003dc6: 47b0 blx r6 - 8003dc8: 2800 cmp r0, #0 - 8003dca: dc06 bgt.n 8003dda <__sflush_r+0xfe> - 8003dcc: 89a3 ldrh r3, [r4, #12] - 8003dce: f043 0340 orr.w r3, r3, #64 ; 0x40 - 8003dd2: 81a3 strh r3, [r4, #12] - 8003dd4: f04f 30ff mov.w r0, #4294967295 - 8003dd8: e78e b.n 8003cf8 <__sflush_r+0x1c> - 8003dda: 4407 add r7, r0 - 8003ddc: eba8 0800 sub.w r8, r8, r0 - 8003de0: e7e9 b.n 8003db6 <__sflush_r+0xda> - 8003de2: bf00 nop - 8003de4: 20400001 .word 0x20400001 - -08003de8 <_fflush_r>: - 8003de8: b538 push {r3, r4, r5, lr} - 8003dea: 690b ldr r3, [r1, #16] - 8003dec: 4605 mov r5, r0 - 8003dee: 460c mov r4, r1 - 8003df0: b913 cbnz r3, 8003df8 <_fflush_r+0x10> - 8003df2: 2500 movs r5, #0 - 8003df4: 4628 mov r0, r5 - 8003df6: bd38 pop {r3, r4, r5, pc} - 8003df8: b118 cbz r0, 8003e02 <_fflush_r+0x1a> - 8003dfa: 6983 ldr r3, [r0, #24] - 8003dfc: b90b cbnz r3, 8003e02 <_fflush_r+0x1a> - 8003dfe: f000 f887 bl 8003f10 <__sinit> - 8003e02: 4b14 ldr r3, [pc, #80] ; (8003e54 <_fflush_r+0x6c>) - 8003e04: 429c cmp r4, r3 - 8003e06: d11b bne.n 8003e40 <_fflush_r+0x58> - 8003e08: 686c ldr r4, [r5, #4] - 8003e0a: f9b4 300c ldrsh.w r3, [r4, #12] - 8003e0e: 2b00 cmp r3, #0 - 8003e10: d0ef beq.n 8003df2 <_fflush_r+0xa> - 8003e12: 6e62 ldr r2, [r4, #100] ; 0x64 - 8003e14: 07d0 lsls r0, r2, #31 - 8003e16: d404 bmi.n 8003e22 <_fflush_r+0x3a> - 8003e18: 0599 lsls r1, r3, #22 - 8003e1a: d402 bmi.n 8003e22 <_fflush_r+0x3a> - 8003e1c: 6da0 ldr r0, [r4, #88] ; 0x58 - 8003e1e: f000 f915 bl 800404c <__retarget_lock_acquire_recursive> - 8003e22: 4628 mov r0, r5 - 8003e24: 4621 mov r1, r4 - 8003e26: f7ff ff59 bl 8003cdc <__sflush_r> - 8003e2a: 6e63 ldr r3, [r4, #100] ; 0x64 - 8003e2c: 07da lsls r2, r3, #31 - 8003e2e: 4605 mov r5, r0 - 8003e30: d4e0 bmi.n 8003df4 <_fflush_r+0xc> - 8003e32: 89a3 ldrh r3, [r4, #12] - 8003e34: 059b lsls r3, r3, #22 - 8003e36: d4dd bmi.n 8003df4 <_fflush_r+0xc> - 8003e38: 6da0 ldr r0, [r4, #88] ; 0x58 - 8003e3a: f000 f908 bl 800404e <__retarget_lock_release_recursive> - 8003e3e: e7d9 b.n 8003df4 <_fflush_r+0xc> - 8003e40: 4b05 ldr r3, [pc, #20] ; (8003e58 <_fflush_r+0x70>) - 8003e42: 429c cmp r4, r3 - 8003e44: d101 bne.n 8003e4a <_fflush_r+0x62> - 8003e46: 68ac ldr r4, [r5, #8] - 8003e48: e7df b.n 8003e0a <_fflush_r+0x22> - 8003e4a: 4b04 ldr r3, [pc, #16] ; (8003e5c <_fflush_r+0x74>) - 8003e4c: 429c cmp r4, r3 - 8003e4e: bf08 it eq - 8003e50: 68ec ldreq r4, [r5, #12] - 8003e52: e7da b.n 8003e0a <_fflush_r+0x22> - 8003e54: 08004c38 .word 0x08004c38 - 8003e58: 08004c58 .word 0x08004c58 - 8003e5c: 08004c18 .word 0x08004c18 - -08003e60 : - 8003e60: 2300 movs r3, #0 - 8003e62: b510 push {r4, lr} - 8003e64: 4604 mov r4, r0 - 8003e66: e9c0 3300 strd r3, r3, [r0] - 8003e6a: e9c0 3304 strd r3, r3, [r0, #16] - 8003e6e: 6083 str r3, [r0, #8] - 8003e70: 8181 strh r1, [r0, #12] - 8003e72: 6643 str r3, [r0, #100] ; 0x64 - 8003e74: 81c2 strh r2, [r0, #14] - 8003e76: 6183 str r3, [r0, #24] - 8003e78: 4619 mov r1, r3 - 8003e7a: 2208 movs r2, #8 - 8003e7c: 305c adds r0, #92 ; 0x5c - 8003e7e: f7ff fdd7 bl 8003a30 - 8003e82: 4b05 ldr r3, [pc, #20] ; (8003e98 ) - 8003e84: 6263 str r3, [r4, #36] ; 0x24 - 8003e86: 4b05 ldr r3, [pc, #20] ; (8003e9c ) - 8003e88: 62a3 str r3, [r4, #40] ; 0x28 - 8003e8a: 4b05 ldr r3, [pc, #20] ; (8003ea0 ) - 8003e8c: 62e3 str r3, [r4, #44] ; 0x2c - 8003e8e: 4b05 ldr r3, [pc, #20] ; (8003ea4 ) - 8003e90: 6224 str r4, [r4, #32] - 8003e92: 6323 str r3, [r4, #48] ; 0x30 - 8003e94: bd10 pop {r4, pc} - 8003e96: bf00 nop - 8003e98: 08004869 .word 0x08004869 - 8003e9c: 0800488b .word 0x0800488b - 8003ea0: 080048c3 .word 0x080048c3 - 8003ea4: 080048e7 .word 0x080048e7 - -08003ea8 <_cleanup_r>: - 8003ea8: 4901 ldr r1, [pc, #4] ; (8003eb0 <_cleanup_r+0x8>) - 8003eaa: f000 b8af b.w 800400c <_fwalk_reent> - 8003eae: bf00 nop - 8003eb0: 08003de9 .word 0x08003de9 - -08003eb4 <__sfmoreglue>: - 8003eb4: b570 push {r4, r5, r6, lr} - 8003eb6: 1e4a subs r2, r1, #1 - 8003eb8: 2568 movs r5, #104 ; 0x68 - 8003eba: 4355 muls r5, r2 - 8003ebc: 460e mov r6, r1 - 8003ebe: f105 0174 add.w r1, r5, #116 ; 0x74 - 8003ec2: f000 f979 bl 80041b8 <_malloc_r> - 8003ec6: 4604 mov r4, r0 - 8003ec8: b140 cbz r0, 8003edc <__sfmoreglue+0x28> - 8003eca: 2100 movs r1, #0 - 8003ecc: e9c0 1600 strd r1, r6, [r0] - 8003ed0: 300c adds r0, #12 - 8003ed2: 60a0 str r0, [r4, #8] - 8003ed4: f105 0268 add.w r2, r5, #104 ; 0x68 - 8003ed8: f7ff fdaa bl 8003a30 - 8003edc: 4620 mov r0, r4 - 8003ede: bd70 pop {r4, r5, r6, pc} - -08003ee0 <__sfp_lock_acquire>: - 8003ee0: 4801 ldr r0, [pc, #4] ; (8003ee8 <__sfp_lock_acquire+0x8>) - 8003ee2: f000 b8b3 b.w 800404c <__retarget_lock_acquire_recursive> - 8003ee6: bf00 nop - 8003ee8: 200005e0 .word 0x200005e0 - -08003eec <__sfp_lock_release>: - 8003eec: 4801 ldr r0, [pc, #4] ; (8003ef4 <__sfp_lock_release+0x8>) - 8003eee: f000 b8ae b.w 800404e <__retarget_lock_release_recursive> - 8003ef2: bf00 nop - 8003ef4: 200005e0 .word 0x200005e0 - -08003ef8 <__sinit_lock_acquire>: - 8003ef8: 4801 ldr r0, [pc, #4] ; (8003f00 <__sinit_lock_acquire+0x8>) - 8003efa: f000 b8a7 b.w 800404c <__retarget_lock_acquire_recursive> - 8003efe: bf00 nop - 8003f00: 200005db .word 0x200005db - -08003f04 <__sinit_lock_release>: - 8003f04: 4801 ldr r0, [pc, #4] ; (8003f0c <__sinit_lock_release+0x8>) - 8003f06: f000 b8a2 b.w 800404e <__retarget_lock_release_recursive> - 8003f0a: bf00 nop - 8003f0c: 200005db .word 0x200005db - -08003f10 <__sinit>: - 8003f10: b510 push {r4, lr} - 8003f12: 4604 mov r4, r0 - 8003f14: f7ff fff0 bl 8003ef8 <__sinit_lock_acquire> - 8003f18: 69a3 ldr r3, [r4, #24] - 8003f1a: b11b cbz r3, 8003f24 <__sinit+0x14> - 8003f1c: e8bd 4010 ldmia.w sp!, {r4, lr} - 8003f20: f7ff bff0 b.w 8003f04 <__sinit_lock_release> - 8003f24: e9c4 3312 strd r3, r3, [r4, #72] ; 0x48 - 8003f28: 6523 str r3, [r4, #80] ; 0x50 - 8003f2a: 4b13 ldr r3, [pc, #76] ; (8003f78 <__sinit+0x68>) - 8003f2c: 4a13 ldr r2, [pc, #76] ; (8003f7c <__sinit+0x6c>) - 8003f2e: 681b ldr r3, [r3, #0] - 8003f30: 62a2 str r2, [r4, #40] ; 0x28 - 8003f32: 42a3 cmp r3, r4 - 8003f34: bf04 itt eq - 8003f36: 2301 moveq r3, #1 - 8003f38: 61a3 streq r3, [r4, #24] - 8003f3a: 4620 mov r0, r4 - 8003f3c: f000 f820 bl 8003f80 <__sfp> - 8003f40: 6060 str r0, [r4, #4] - 8003f42: 4620 mov r0, r4 - 8003f44: f000 f81c bl 8003f80 <__sfp> - 8003f48: 60a0 str r0, [r4, #8] - 8003f4a: 4620 mov r0, r4 - 8003f4c: f000 f818 bl 8003f80 <__sfp> - 8003f50: 2200 movs r2, #0 - 8003f52: 60e0 str r0, [r4, #12] - 8003f54: 2104 movs r1, #4 - 8003f56: 6860 ldr r0, [r4, #4] - 8003f58: f7ff ff82 bl 8003e60 - 8003f5c: 68a0 ldr r0, [r4, #8] - 8003f5e: 2201 movs r2, #1 - 8003f60: 2109 movs r1, #9 - 8003f62: f7ff ff7d bl 8003e60 - 8003f66: 68e0 ldr r0, [r4, #12] - 8003f68: 2202 movs r2, #2 - 8003f6a: 2112 movs r1, #18 - 8003f6c: f7ff ff78 bl 8003e60 - 8003f70: 2301 movs r3, #1 - 8003f72: 61a3 str r3, [r4, #24] - 8003f74: e7d2 b.n 8003f1c <__sinit+0xc> - 8003f76: bf00 nop - 8003f78: 08004c14 .word 0x08004c14 - 8003f7c: 08003ea9 .word 0x08003ea9 - -08003f80 <__sfp>: - 8003f80: b5f8 push {r3, r4, r5, r6, r7, lr} - 8003f82: 4607 mov r7, r0 - 8003f84: f7ff ffac bl 8003ee0 <__sfp_lock_acquire> - 8003f88: 4b1e ldr r3, [pc, #120] ; (8004004 <__sfp+0x84>) - 8003f8a: 681e ldr r6, [r3, #0] - 8003f8c: 69b3 ldr r3, [r6, #24] - 8003f8e: b913 cbnz r3, 8003f96 <__sfp+0x16> - 8003f90: 4630 mov r0, r6 - 8003f92: f7ff ffbd bl 8003f10 <__sinit> - 8003f96: 3648 adds r6, #72 ; 0x48 - 8003f98: e9d6 3401 ldrd r3, r4, [r6, #4] - 8003f9c: 3b01 subs r3, #1 - 8003f9e: d503 bpl.n 8003fa8 <__sfp+0x28> - 8003fa0: 6833 ldr r3, [r6, #0] - 8003fa2: b30b cbz r3, 8003fe8 <__sfp+0x68> - 8003fa4: 6836 ldr r6, [r6, #0] - 8003fa6: e7f7 b.n 8003f98 <__sfp+0x18> - 8003fa8: f9b4 500c ldrsh.w r5, [r4, #12] - 8003fac: b9d5 cbnz r5, 8003fe4 <__sfp+0x64> - 8003fae: 4b16 ldr r3, [pc, #88] ; (8004008 <__sfp+0x88>) - 8003fb0: 60e3 str r3, [r4, #12] - 8003fb2: f104 0058 add.w r0, r4, #88 ; 0x58 - 8003fb6: 6665 str r5, [r4, #100] ; 0x64 - 8003fb8: f000 f847 bl 800404a <__retarget_lock_init_recursive> - 8003fbc: f7ff ff96 bl 8003eec <__sfp_lock_release> - 8003fc0: e9c4 5501 strd r5, r5, [r4, #4] - 8003fc4: e9c4 5504 strd r5, r5, [r4, #16] - 8003fc8: 6025 str r5, [r4, #0] - 8003fca: 61a5 str r5, [r4, #24] - 8003fcc: 2208 movs r2, #8 - 8003fce: 4629 mov r1, r5 - 8003fd0: f104 005c add.w r0, r4, #92 ; 0x5c - 8003fd4: f7ff fd2c bl 8003a30 - 8003fd8: e9c4 550d strd r5, r5, [r4, #52] ; 0x34 - 8003fdc: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48 - 8003fe0: 4620 mov r0, r4 - 8003fe2: bdf8 pop {r3, r4, r5, r6, r7, pc} - 8003fe4: 3468 adds r4, #104 ; 0x68 - 8003fe6: e7d9 b.n 8003f9c <__sfp+0x1c> - 8003fe8: 2104 movs r1, #4 - 8003fea: 4638 mov r0, r7 - 8003fec: f7ff ff62 bl 8003eb4 <__sfmoreglue> - 8003ff0: 4604 mov r4, r0 - 8003ff2: 6030 str r0, [r6, #0] - 8003ff4: 2800 cmp r0, #0 - 8003ff6: d1d5 bne.n 8003fa4 <__sfp+0x24> - 8003ff8: f7ff ff78 bl 8003eec <__sfp_lock_release> - 8003ffc: 230c movs r3, #12 - 8003ffe: 603b str r3, [r7, #0] - 8004000: e7ee b.n 8003fe0 <__sfp+0x60> - 8004002: bf00 nop - 8004004: 08004c14 .word 0x08004c14 - 8004008: ffff0001 .word 0xffff0001 - -0800400c <_fwalk_reent>: - 800400c: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} - 8004010: 4606 mov r6, r0 - 8004012: 4688 mov r8, r1 - 8004014: f100 0448 add.w r4, r0, #72 ; 0x48 - 8004018: 2700 movs r7, #0 - 800401a: e9d4 9501 ldrd r9, r5, [r4, #4] - 800401e: f1b9 0901 subs.w r9, r9, #1 - 8004022: d505 bpl.n 8004030 <_fwalk_reent+0x24> - 8004024: 6824 ldr r4, [r4, #0] - 8004026: 2c00 cmp r4, #0 - 8004028: d1f7 bne.n 800401a <_fwalk_reent+0xe> - 800402a: 4638 mov r0, r7 - 800402c: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} - 8004030: 89ab ldrh r3, [r5, #12] - 8004032: 2b01 cmp r3, #1 - 8004034: d907 bls.n 8004046 <_fwalk_reent+0x3a> - 8004036: f9b5 300e ldrsh.w r3, [r5, #14] - 800403a: 3301 adds r3, #1 - 800403c: d003 beq.n 8004046 <_fwalk_reent+0x3a> - 800403e: 4629 mov r1, r5 - 8004040: 4630 mov r0, r6 - 8004042: 47c0 blx r8 - 8004044: 4307 orrs r7, r0 - 8004046: 3568 adds r5, #104 ; 0x68 - 8004048: e7e9 b.n 800401e <_fwalk_reent+0x12> - -0800404a <__retarget_lock_init_recursive>: - 800404a: 4770 bx lr - -0800404c <__retarget_lock_acquire_recursive>: - 800404c: 4770 bx lr - -0800404e <__retarget_lock_release_recursive>: - 800404e: 4770 bx lr - -08004050 <__swhatbuf_r>: - 8004050: b570 push {r4, r5, r6, lr} - 8004052: 460e mov r6, r1 - 8004054: f9b1 100e ldrsh.w r1, [r1, #14] - 8004058: 2900 cmp r1, #0 - 800405a: b096 sub sp, #88 ; 0x58 - 800405c: 4614 mov r4, r2 - 800405e: 461d mov r5, r3 - 8004060: da07 bge.n 8004072 <__swhatbuf_r+0x22> - 8004062: 2300 movs r3, #0 - 8004064: 602b str r3, [r5, #0] - 8004066: 89b3 ldrh r3, [r6, #12] - 8004068: 061a lsls r2, r3, #24 - 800406a: d410 bmi.n 800408e <__swhatbuf_r+0x3e> - 800406c: f44f 6380 mov.w r3, #1024 ; 0x400 - 8004070: e00e b.n 8004090 <__swhatbuf_r+0x40> - 8004072: 466a mov r2, sp - 8004074: f000 fc5e bl 8004934 <_fstat_r> - 8004078: 2800 cmp r0, #0 - 800407a: dbf2 blt.n 8004062 <__swhatbuf_r+0x12> - 800407c: 9a01 ldr r2, [sp, #4] - 800407e: f402 4270 and.w r2, r2, #61440 ; 0xf000 - 8004082: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000 - 8004086: 425a negs r2, r3 - 8004088: 415a adcs r2, r3 - 800408a: 602a str r2, [r5, #0] - 800408c: e7ee b.n 800406c <__swhatbuf_r+0x1c> - 800408e: 2340 movs r3, #64 ; 0x40 - 8004090: 2000 movs r0, #0 - 8004092: 6023 str r3, [r4, #0] - 8004094: b016 add sp, #88 ; 0x58 - 8004096: bd70 pop {r4, r5, r6, pc} - -08004098 <__smakebuf_r>: - 8004098: 898b ldrh r3, [r1, #12] - 800409a: b573 push {r0, r1, r4, r5, r6, lr} - 800409c: 079d lsls r5, r3, #30 - 800409e: 4606 mov r6, r0 - 80040a0: 460c mov r4, r1 - 80040a2: d507 bpl.n 80040b4 <__smakebuf_r+0x1c> - 80040a4: f104 0347 add.w r3, r4, #71 ; 0x47 - 80040a8: 6023 str r3, [r4, #0] - 80040aa: 6123 str r3, [r4, #16] - 80040ac: 2301 movs r3, #1 - 80040ae: 6163 str r3, [r4, #20] - 80040b0: b002 add sp, #8 - 80040b2: bd70 pop {r4, r5, r6, pc} - 80040b4: ab01 add r3, sp, #4 - 80040b6: 466a mov r2, sp - 80040b8: f7ff ffca bl 8004050 <__swhatbuf_r> - 80040bc: 9900 ldr r1, [sp, #0] - 80040be: 4605 mov r5, r0 - 80040c0: 4630 mov r0, r6 - 80040c2: f000 f879 bl 80041b8 <_malloc_r> - 80040c6: b948 cbnz r0, 80040dc <__smakebuf_r+0x44> - 80040c8: f9b4 300c ldrsh.w r3, [r4, #12] - 80040cc: 059a lsls r2, r3, #22 - 80040ce: d4ef bmi.n 80040b0 <__smakebuf_r+0x18> - 80040d0: f023 0303 bic.w r3, r3, #3 - 80040d4: f043 0302 orr.w r3, r3, #2 - 80040d8: 81a3 strh r3, [r4, #12] - 80040da: e7e3 b.n 80040a4 <__smakebuf_r+0xc> - 80040dc: 4b0d ldr r3, [pc, #52] ; (8004114 <__smakebuf_r+0x7c>) - 80040de: 62b3 str r3, [r6, #40] ; 0x28 - 80040e0: 89a3 ldrh r3, [r4, #12] - 80040e2: 6020 str r0, [r4, #0] - 80040e4: f043 0380 orr.w r3, r3, #128 ; 0x80 - 80040e8: 81a3 strh r3, [r4, #12] - 80040ea: 9b00 ldr r3, [sp, #0] - 80040ec: 6163 str r3, [r4, #20] - 80040ee: 9b01 ldr r3, [sp, #4] - 80040f0: 6120 str r0, [r4, #16] - 80040f2: b15b cbz r3, 800410c <__smakebuf_r+0x74> - 80040f4: f9b4 100e ldrsh.w r1, [r4, #14] - 80040f8: 4630 mov r0, r6 - 80040fa: f000 fc2d bl 8004958 <_isatty_r> - 80040fe: b128 cbz r0, 800410c <__smakebuf_r+0x74> - 8004100: 89a3 ldrh r3, [r4, #12] - 8004102: f023 0303 bic.w r3, r3, #3 - 8004106: f043 0301 orr.w r3, r3, #1 - 800410a: 81a3 strh r3, [r4, #12] - 800410c: 89a0 ldrh r0, [r4, #12] - 800410e: 4305 orrs r5, r0 - 8004110: 81a5 strh r5, [r4, #12] - 8004112: e7cd b.n 80040b0 <__smakebuf_r+0x18> - 8004114: 08003ea9 .word 0x08003ea9 - -08004118 <_free_r>: - 8004118: b537 push {r0, r1, r2, r4, r5, lr} - 800411a: 2900 cmp r1, #0 - 800411c: d048 beq.n 80041b0 <_free_r+0x98> - 800411e: f851 3c04 ldr.w r3, [r1, #-4] - 8004122: 9001 str r0, [sp, #4] - 8004124: 2b00 cmp r3, #0 - 8004126: f1a1 0404 sub.w r4, r1, #4 - 800412a: bfb8 it lt - 800412c: 18e4 addlt r4, r4, r3 - 800412e: f000 fc35 bl 800499c <__malloc_lock> - 8004132: 4a20 ldr r2, [pc, #128] ; (80041b4 <_free_r+0x9c>) - 8004134: 9801 ldr r0, [sp, #4] - 8004136: 6813 ldr r3, [r2, #0] - 8004138: 4615 mov r5, r2 - 800413a: b933 cbnz r3, 800414a <_free_r+0x32> - 800413c: 6063 str r3, [r4, #4] - 800413e: 6014 str r4, [r2, #0] - 8004140: b003 add sp, #12 - 8004142: e8bd 4030 ldmia.w sp!, {r4, r5, lr} - 8004146: f000 bc2f b.w 80049a8 <__malloc_unlock> - 800414a: 42a3 cmp r3, r4 - 800414c: d90b bls.n 8004166 <_free_r+0x4e> - 800414e: 6821 ldr r1, [r4, #0] - 8004150: 1862 adds r2, r4, r1 - 8004152: 4293 cmp r3, r2 - 8004154: bf04 itt eq - 8004156: 681a ldreq r2, [r3, #0] - 8004158: 685b ldreq r3, [r3, #4] - 800415a: 6063 str r3, [r4, #4] - 800415c: bf04 itt eq - 800415e: 1852 addeq r2, r2, r1 - 8004160: 6022 streq r2, [r4, #0] - 8004162: 602c str r4, [r5, #0] - 8004164: e7ec b.n 8004140 <_free_r+0x28> - 8004166: 461a mov r2, r3 - 8004168: 685b ldr r3, [r3, #4] - 800416a: b10b cbz r3, 8004170 <_free_r+0x58> - 800416c: 42a3 cmp r3, r4 - 800416e: d9fa bls.n 8004166 <_free_r+0x4e> - 8004170: 6811 ldr r1, [r2, #0] - 8004172: 1855 adds r5, r2, r1 - 8004174: 42a5 cmp r5, r4 - 8004176: d10b bne.n 8004190 <_free_r+0x78> - 8004178: 6824 ldr r4, [r4, #0] - 800417a: 4421 add r1, r4 - 800417c: 1854 adds r4, r2, r1 - 800417e: 42a3 cmp r3, r4 - 8004180: 6011 str r1, [r2, #0] - 8004182: d1dd bne.n 8004140 <_free_r+0x28> - 8004184: 681c ldr r4, [r3, #0] - 8004186: 685b ldr r3, [r3, #4] - 8004188: 6053 str r3, [r2, #4] - 800418a: 4421 add r1, r4 - 800418c: 6011 str r1, [r2, #0] - 800418e: e7d7 b.n 8004140 <_free_r+0x28> - 8004190: d902 bls.n 8004198 <_free_r+0x80> - 8004192: 230c movs r3, #12 - 8004194: 6003 str r3, [r0, #0] - 8004196: e7d3 b.n 8004140 <_free_r+0x28> - 8004198: 6825 ldr r5, [r4, #0] - 800419a: 1961 adds r1, r4, r5 - 800419c: 428b cmp r3, r1 - 800419e: bf04 itt eq - 80041a0: 6819 ldreq r1, [r3, #0] - 80041a2: 685b ldreq r3, [r3, #4] - 80041a4: 6063 str r3, [r4, #4] - 80041a6: bf04 itt eq - 80041a8: 1949 addeq r1, r1, r5 - 80041aa: 6021 streq r1, [r4, #0] - 80041ac: 6054 str r4, [r2, #4] - 80041ae: e7c7 b.n 8004140 <_free_r+0x28> - 80041b0: b003 add sp, #12 - 80041b2: bd30 pop {r4, r5, pc} - 80041b4: 200004a8 .word 0x200004a8 - -080041b8 <_malloc_r>: - 80041b8: b5f8 push {r3, r4, r5, r6, r7, lr} - 80041ba: 1ccd adds r5, r1, #3 - 80041bc: f025 0503 bic.w r5, r5, #3 - 80041c0: 3508 adds r5, #8 - 80041c2: 2d0c cmp r5, #12 - 80041c4: bf38 it cc - 80041c6: 250c movcc r5, #12 - 80041c8: 2d00 cmp r5, #0 - 80041ca: 4606 mov r6, r0 - 80041cc: db01 blt.n 80041d2 <_malloc_r+0x1a> - 80041ce: 42a9 cmp r1, r5 - 80041d0: d903 bls.n 80041da <_malloc_r+0x22> - 80041d2: 230c movs r3, #12 - 80041d4: 6033 str r3, [r6, #0] - 80041d6: 2000 movs r0, #0 - 80041d8: bdf8 pop {r3, r4, r5, r6, r7, pc} - 80041da: f000 fbdf bl 800499c <__malloc_lock> - 80041de: 4921 ldr r1, [pc, #132] ; (8004264 <_malloc_r+0xac>) - 80041e0: 680a ldr r2, [r1, #0] - 80041e2: 4614 mov r4, r2 - 80041e4: b99c cbnz r4, 800420e <_malloc_r+0x56> - 80041e6: 4f20 ldr r7, [pc, #128] ; (8004268 <_malloc_r+0xb0>) - 80041e8: 683b ldr r3, [r7, #0] - 80041ea: b923 cbnz r3, 80041f6 <_malloc_r+0x3e> - 80041ec: 4621 mov r1, r4 - 80041ee: 4630 mov r0, r6 - 80041f0: f000 fb2a bl 8004848 <_sbrk_r> - 80041f4: 6038 str r0, [r7, #0] - 80041f6: 4629 mov r1, r5 - 80041f8: 4630 mov r0, r6 - 80041fa: f000 fb25 bl 8004848 <_sbrk_r> - 80041fe: 1c43 adds r3, r0, #1 - 8004200: d123 bne.n 800424a <_malloc_r+0x92> - 8004202: 230c movs r3, #12 - 8004204: 6033 str r3, [r6, #0] - 8004206: 4630 mov r0, r6 - 8004208: f000 fbce bl 80049a8 <__malloc_unlock> - 800420c: e7e3 b.n 80041d6 <_malloc_r+0x1e> - 800420e: 6823 ldr r3, [r4, #0] - 8004210: 1b5b subs r3, r3, r5 - 8004212: d417 bmi.n 8004244 <_malloc_r+0x8c> - 8004214: 2b0b cmp r3, #11 - 8004216: d903 bls.n 8004220 <_malloc_r+0x68> - 8004218: 6023 str r3, [r4, #0] - 800421a: 441c add r4, r3 - 800421c: 6025 str r5, [r4, #0] - 800421e: e004 b.n 800422a <_malloc_r+0x72> - 8004220: 6863 ldr r3, [r4, #4] - 8004222: 42a2 cmp r2, r4 - 8004224: bf0c ite eq - 8004226: 600b streq r3, [r1, #0] - 8004228: 6053 strne r3, [r2, #4] - 800422a: 4630 mov r0, r6 - 800422c: f000 fbbc bl 80049a8 <__malloc_unlock> - 8004230: f104 000b add.w r0, r4, #11 - 8004234: 1d23 adds r3, r4, #4 - 8004236: f020 0007 bic.w r0, r0, #7 - 800423a: 1ac2 subs r2, r0, r3 - 800423c: d0cc beq.n 80041d8 <_malloc_r+0x20> - 800423e: 1a1b subs r3, r3, r0 - 8004240: 50a3 str r3, [r4, r2] - 8004242: e7c9 b.n 80041d8 <_malloc_r+0x20> - 8004244: 4622 mov r2, r4 - 8004246: 6864 ldr r4, [r4, #4] - 8004248: e7cc b.n 80041e4 <_malloc_r+0x2c> - 800424a: 1cc4 adds r4, r0, #3 - 800424c: f024 0403 bic.w r4, r4, #3 - 8004250: 42a0 cmp r0, r4 - 8004252: d0e3 beq.n 800421c <_malloc_r+0x64> - 8004254: 1a21 subs r1, r4, r0 - 8004256: 4630 mov r0, r6 - 8004258: f000 faf6 bl 8004848 <_sbrk_r> - 800425c: 3001 adds r0, #1 - 800425e: d1dd bne.n 800421c <_malloc_r+0x64> - 8004260: e7cf b.n 8004202 <_malloc_r+0x4a> - 8004262: bf00 nop - 8004264: 200004a8 .word 0x200004a8 - 8004268: 200004ac .word 0x200004ac - -0800426c <__sfputc_r>: - 800426c: 6893 ldr r3, [r2, #8] - 800426e: 3b01 subs r3, #1 - 8004270: 2b00 cmp r3, #0 - 8004272: b410 push {r4} - 8004274: 6093 str r3, [r2, #8] - 8004276: da08 bge.n 800428a <__sfputc_r+0x1e> - 8004278: 6994 ldr r4, [r2, #24] - 800427a: 42a3 cmp r3, r4 - 800427c: db01 blt.n 8004282 <__sfputc_r+0x16> - 800427e: 290a cmp r1, #10 - 8004280: d103 bne.n 800428a <__sfputc_r+0x1e> - 8004282: f85d 4b04 ldr.w r4, [sp], #4 - 8004286: f7ff bc69 b.w 8003b5c <__swbuf_r> - 800428a: 6813 ldr r3, [r2, #0] - 800428c: 1c58 adds r0, r3, #1 - 800428e: 6010 str r0, [r2, #0] - 8004290: 7019 strb r1, [r3, #0] - 8004292: 4608 mov r0, r1 - 8004294: f85d 4b04 ldr.w r4, [sp], #4 - 8004298: 4770 bx lr - -0800429a <__sfputs_r>: - 800429a: b5f8 push {r3, r4, r5, r6, r7, lr} - 800429c: 4606 mov r6, r0 - 800429e: 460f mov r7, r1 - 80042a0: 4614 mov r4, r2 - 80042a2: 18d5 adds r5, r2, r3 - 80042a4: 42ac cmp r4, r5 - 80042a6: d101 bne.n 80042ac <__sfputs_r+0x12> - 80042a8: 2000 movs r0, #0 - 80042aa: e007 b.n 80042bc <__sfputs_r+0x22> - 80042ac: f814 1b01 ldrb.w r1, [r4], #1 - 80042b0: 463a mov r2, r7 - 80042b2: 4630 mov r0, r6 - 80042b4: f7ff ffda bl 800426c <__sfputc_r> - 80042b8: 1c43 adds r3, r0, #1 - 80042ba: d1f3 bne.n 80042a4 <__sfputs_r+0xa> - 80042bc: bdf8 pop {r3, r4, r5, r6, r7, pc} +08004688 <__errno>: + 8004688: 4b01 ldr r3, [pc, #4] ; (8004690 <__errno+0x8>) + 800468a: 6818 ldr r0, [r3, #0] + 800468c: 4770 bx lr + 800468e: bf00 nop + 8004690: 20000010 .word 0x20000010 + +08004694 <__libc_init_array>: + 8004694: b570 push {r4, r5, r6, lr} + 8004696: 4d0d ldr r5, [pc, #52] ; (80046cc <__libc_init_array+0x38>) + 8004698: 4c0d ldr r4, [pc, #52] ; (80046d0 <__libc_init_array+0x3c>) + 800469a: 1b64 subs r4, r4, r5 + 800469c: 10a4 asrs r4, r4, #2 + 800469e: 2600 movs r6, #0 + 80046a0: 42a6 cmp r6, r4 + 80046a2: d109 bne.n 80046b8 <__libc_init_array+0x24> + 80046a4: 4d0b ldr r5, [pc, #44] ; (80046d4 <__libc_init_array+0x40>) + 80046a6: 4c0c ldr r4, [pc, #48] ; (80046d8 <__libc_init_array+0x44>) + 80046a8: f000 ffec bl 8005684 <_init> + 80046ac: 1b64 subs r4, r4, r5 + 80046ae: 10a4 asrs r4, r4, #2 + 80046b0: 2600 movs r6, #0 + 80046b2: 42a6 cmp r6, r4 + 80046b4: d105 bne.n 80046c2 <__libc_init_array+0x2e> + 80046b6: bd70 pop {r4, r5, r6, pc} + 80046b8: f855 3b04 ldr.w r3, [r5], #4 + 80046bc: 4798 blx r3 + 80046be: 3601 adds r6, #1 + 80046c0: e7ee b.n 80046a0 <__libc_init_array+0xc> + 80046c2: f855 3b04 ldr.w r3, [r5], #4 + 80046c6: 4798 blx r3 + 80046c8: 3601 adds r6, #1 + 80046ca: e7f2 b.n 80046b2 <__libc_init_array+0x1e> + 80046cc: 08005bbc .word 0x08005bbc + 80046d0: 08005bbc .word 0x08005bbc + 80046d4: 08005bbc .word 0x08005bbc + 80046d8: 08005bc0 .word 0x08005bc0 + +080046dc : + 80046dc: 4402 add r2, r0 + 80046de: 4603 mov r3, r0 + 80046e0: 4293 cmp r3, r2 + 80046e2: d100 bne.n 80046e6 + 80046e4: 4770 bx lr + 80046e6: f803 1b01 strb.w r1, [r3], #1 + 80046ea: e7f9 b.n 80046e0 + +080046ec : + 80046ec: b40f push {r0, r1, r2, r3} + 80046ee: 4b0a ldr r3, [pc, #40] ; (8004718 ) + 80046f0: b513 push {r0, r1, r4, lr} + 80046f2: 681c ldr r4, [r3, #0] + 80046f4: b124 cbz r4, 8004700 + 80046f6: 69a3 ldr r3, [r4, #24] + 80046f8: b913 cbnz r3, 8004700 + 80046fa: 4620 mov r0, r4 + 80046fc: f000 fa5e bl 8004bbc <__sinit> + 8004700: ab05 add r3, sp, #20 + 8004702: 9a04 ldr r2, [sp, #16] + 8004704: 68a1 ldr r1, [r4, #8] + 8004706: 9301 str r3, [sp, #4] + 8004708: 4620 mov r0, r4 + 800470a: f000 fc2f bl 8004f6c <_vfiprintf_r> + 800470e: b002 add sp, #8 + 8004710: e8bd 4010 ldmia.w sp!, {r4, lr} + 8004714: b004 add sp, #16 + 8004716: 4770 bx lr + 8004718: 20000010 .word 0x20000010 + +0800471c <_puts_r>: + 800471c: b570 push {r4, r5, r6, lr} + 800471e: 460e mov r6, r1 + 8004720: 4605 mov r5, r0 + 8004722: b118 cbz r0, 800472c <_puts_r+0x10> + 8004724: 6983 ldr r3, [r0, #24] + 8004726: b90b cbnz r3, 800472c <_puts_r+0x10> + 8004728: f000 fa48 bl 8004bbc <__sinit> + 800472c: 69ab ldr r3, [r5, #24] + 800472e: 68ac ldr r4, [r5, #8] + 8004730: b913 cbnz r3, 8004738 <_puts_r+0x1c> + 8004732: 4628 mov r0, r5 + 8004734: f000 fa42 bl 8004bbc <__sinit> + 8004738: 4b2c ldr r3, [pc, #176] ; (80047ec <_puts_r+0xd0>) + 800473a: 429c cmp r4, r3 + 800473c: d120 bne.n 8004780 <_puts_r+0x64> + 800473e: 686c ldr r4, [r5, #4] + 8004740: 6e63 ldr r3, [r4, #100] ; 0x64 + 8004742: 07db lsls r3, r3, #31 + 8004744: d405 bmi.n 8004752 <_puts_r+0x36> + 8004746: 89a3 ldrh r3, [r4, #12] + 8004748: 0598 lsls r0, r3, #22 + 800474a: d402 bmi.n 8004752 <_puts_r+0x36> + 800474c: 6da0 ldr r0, [r4, #88] ; 0x58 + 800474e: f000 fad3 bl 8004cf8 <__retarget_lock_acquire_recursive> + 8004752: 89a3 ldrh r3, [r4, #12] + 8004754: 0719 lsls r1, r3, #28 + 8004756: d51d bpl.n 8004794 <_puts_r+0x78> + 8004758: 6923 ldr r3, [r4, #16] + 800475a: b1db cbz r3, 8004794 <_puts_r+0x78> + 800475c: 3e01 subs r6, #1 + 800475e: 68a3 ldr r3, [r4, #8] + 8004760: f816 1f01 ldrb.w r1, [r6, #1]! + 8004764: 3b01 subs r3, #1 + 8004766: 60a3 str r3, [r4, #8] + 8004768: bb39 cbnz r1, 80047ba <_puts_r+0x9e> + 800476a: 2b00 cmp r3, #0 + 800476c: da38 bge.n 80047e0 <_puts_r+0xc4> + 800476e: 4622 mov r2, r4 + 8004770: 210a movs r1, #10 + 8004772: 4628 mov r0, r5 + 8004774: f000 f848 bl 8004808 <__swbuf_r> + 8004778: 3001 adds r0, #1 + 800477a: d011 beq.n 80047a0 <_puts_r+0x84> + 800477c: 250a movs r5, #10 + 800477e: e011 b.n 80047a4 <_puts_r+0x88> + 8004780: 4b1b ldr r3, [pc, #108] ; (80047f0 <_puts_r+0xd4>) + 8004782: 429c cmp r4, r3 + 8004784: d101 bne.n 800478a <_puts_r+0x6e> + 8004786: 68ac ldr r4, [r5, #8] + 8004788: e7da b.n 8004740 <_puts_r+0x24> + 800478a: 4b1a ldr r3, [pc, #104] ; (80047f4 <_puts_r+0xd8>) + 800478c: 429c cmp r4, r3 + 800478e: bf08 it eq + 8004790: 68ec ldreq r4, [r5, #12] + 8004792: e7d5 b.n 8004740 <_puts_r+0x24> + 8004794: 4621 mov r1, r4 + 8004796: 4628 mov r0, r5 + 8004798: f000 f888 bl 80048ac <__swsetup_r> + 800479c: 2800 cmp r0, #0 + 800479e: d0dd beq.n 800475c <_puts_r+0x40> + 80047a0: f04f 35ff mov.w r5, #4294967295 + 80047a4: 6e63 ldr r3, [r4, #100] ; 0x64 + 80047a6: 07da lsls r2, r3, #31 + 80047a8: d405 bmi.n 80047b6 <_puts_r+0x9a> + 80047aa: 89a3 ldrh r3, [r4, #12] + 80047ac: 059b lsls r3, r3, #22 + 80047ae: d402 bmi.n 80047b6 <_puts_r+0x9a> + 80047b0: 6da0 ldr r0, [r4, #88] ; 0x58 + 80047b2: f000 faa2 bl 8004cfa <__retarget_lock_release_recursive> + 80047b6: 4628 mov r0, r5 + 80047b8: bd70 pop {r4, r5, r6, pc} + 80047ba: 2b00 cmp r3, #0 + 80047bc: da04 bge.n 80047c8 <_puts_r+0xac> + 80047be: 69a2 ldr r2, [r4, #24] + 80047c0: 429a cmp r2, r3 + 80047c2: dc06 bgt.n 80047d2 <_puts_r+0xb6> + 80047c4: 290a cmp r1, #10 + 80047c6: d004 beq.n 80047d2 <_puts_r+0xb6> + 80047c8: 6823 ldr r3, [r4, #0] + 80047ca: 1c5a adds r2, r3, #1 + 80047cc: 6022 str r2, [r4, #0] + 80047ce: 7019 strb r1, [r3, #0] + 80047d0: e7c5 b.n 800475e <_puts_r+0x42> + 80047d2: 4622 mov r2, r4 + 80047d4: 4628 mov r0, r5 + 80047d6: f000 f817 bl 8004808 <__swbuf_r> + 80047da: 3001 adds r0, #1 + 80047dc: d1bf bne.n 800475e <_puts_r+0x42> + 80047de: e7df b.n 80047a0 <_puts_r+0x84> + 80047e0: 6823 ldr r3, [r4, #0] + 80047e2: 250a movs r5, #10 + 80047e4: 1c5a adds r2, r3, #1 + 80047e6: 6022 str r2, [r4, #0] + 80047e8: 701d strb r5, [r3, #0] + 80047ea: e7db b.n 80047a4 <_puts_r+0x88> + 80047ec: 08005b40 .word 0x08005b40 + 80047f0: 08005b60 .word 0x08005b60 + 80047f4: 08005b20 .word 0x08005b20 + +080047f8 : + 80047f8: 4b02 ldr r3, [pc, #8] ; (8004804 ) + 80047fa: 4601 mov r1, r0 + 80047fc: 6818 ldr r0, [r3, #0] + 80047fe: f7ff bf8d b.w 800471c <_puts_r> + 8004802: bf00 nop + 8004804: 20000010 .word 0x20000010 + +08004808 <__swbuf_r>: + 8004808: b5f8 push {r3, r4, r5, r6, r7, lr} + 800480a: 460e mov r6, r1 + 800480c: 4614 mov r4, r2 + 800480e: 4605 mov r5, r0 + 8004810: b118 cbz r0, 800481a <__swbuf_r+0x12> + 8004812: 6983 ldr r3, [r0, #24] + 8004814: b90b cbnz r3, 800481a <__swbuf_r+0x12> + 8004816: f000 f9d1 bl 8004bbc <__sinit> + 800481a: 4b21 ldr r3, [pc, #132] ; (80048a0 <__swbuf_r+0x98>) + 800481c: 429c cmp r4, r3 + 800481e: d12b bne.n 8004878 <__swbuf_r+0x70> + 8004820: 686c ldr r4, [r5, #4] + 8004822: 69a3 ldr r3, [r4, #24] + 8004824: 60a3 str r3, [r4, #8] + 8004826: 89a3 ldrh r3, [r4, #12] + 8004828: 071a lsls r2, r3, #28 + 800482a: d52f bpl.n 800488c <__swbuf_r+0x84> + 800482c: 6923 ldr r3, [r4, #16] + 800482e: b36b cbz r3, 800488c <__swbuf_r+0x84> + 8004830: 6923 ldr r3, [r4, #16] + 8004832: 6820 ldr r0, [r4, #0] + 8004834: 1ac0 subs r0, r0, r3 + 8004836: 6963 ldr r3, [r4, #20] + 8004838: b2f6 uxtb r6, r6 + 800483a: 4283 cmp r3, r0 + 800483c: 4637 mov r7, r6 + 800483e: dc04 bgt.n 800484a <__swbuf_r+0x42> + 8004840: 4621 mov r1, r4 + 8004842: 4628 mov r0, r5 + 8004844: f000 f926 bl 8004a94 <_fflush_r> + 8004848: bb30 cbnz r0, 8004898 <__swbuf_r+0x90> + 800484a: 68a3 ldr r3, [r4, #8] + 800484c: 3b01 subs r3, #1 + 800484e: 60a3 str r3, [r4, #8] + 8004850: 6823 ldr r3, [r4, #0] + 8004852: 1c5a adds r2, r3, #1 + 8004854: 6022 str r2, [r4, #0] + 8004856: 701e strb r6, [r3, #0] + 8004858: 6963 ldr r3, [r4, #20] + 800485a: 3001 adds r0, #1 + 800485c: 4283 cmp r3, r0 + 800485e: d004 beq.n 800486a <__swbuf_r+0x62> + 8004860: 89a3 ldrh r3, [r4, #12] + 8004862: 07db lsls r3, r3, #31 + 8004864: d506 bpl.n 8004874 <__swbuf_r+0x6c> + 8004866: 2e0a cmp r6, #10 + 8004868: d104 bne.n 8004874 <__swbuf_r+0x6c> + 800486a: 4621 mov r1, r4 + 800486c: 4628 mov r0, r5 + 800486e: f000 f911 bl 8004a94 <_fflush_r> + 8004872: b988 cbnz r0, 8004898 <__swbuf_r+0x90> + 8004874: 4638 mov r0, r7 + 8004876: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8004878: 4b0a ldr r3, [pc, #40] ; (80048a4 <__swbuf_r+0x9c>) + 800487a: 429c cmp r4, r3 + 800487c: d101 bne.n 8004882 <__swbuf_r+0x7a> + 800487e: 68ac ldr r4, [r5, #8] + 8004880: e7cf b.n 8004822 <__swbuf_r+0x1a> + 8004882: 4b09 ldr r3, [pc, #36] ; (80048a8 <__swbuf_r+0xa0>) + 8004884: 429c cmp r4, r3 + 8004886: bf08 it eq + 8004888: 68ec ldreq r4, [r5, #12] + 800488a: e7ca b.n 8004822 <__swbuf_r+0x1a> + 800488c: 4621 mov r1, r4 + 800488e: 4628 mov r0, r5 + 8004890: f000 f80c bl 80048ac <__swsetup_r> + 8004894: 2800 cmp r0, #0 + 8004896: d0cb beq.n 8004830 <__swbuf_r+0x28> + 8004898: f04f 37ff mov.w r7, #4294967295 + 800489c: e7ea b.n 8004874 <__swbuf_r+0x6c> + 800489e: bf00 nop + 80048a0: 08005b40 .word 0x08005b40 + 80048a4: 08005b60 .word 0x08005b60 + 80048a8: 08005b20 .word 0x08005b20 + +080048ac <__swsetup_r>: + 80048ac: 4b32 ldr r3, [pc, #200] ; (8004978 <__swsetup_r+0xcc>) + 80048ae: b570 push {r4, r5, r6, lr} + 80048b0: 681d ldr r5, [r3, #0] + 80048b2: 4606 mov r6, r0 + 80048b4: 460c mov r4, r1 + 80048b6: b125 cbz r5, 80048c2 <__swsetup_r+0x16> + 80048b8: 69ab ldr r3, [r5, #24] + 80048ba: b913 cbnz r3, 80048c2 <__swsetup_r+0x16> + 80048bc: 4628 mov r0, r5 + 80048be: f000 f97d bl 8004bbc <__sinit> + 80048c2: 4b2e ldr r3, [pc, #184] ; (800497c <__swsetup_r+0xd0>) + 80048c4: 429c cmp r4, r3 + 80048c6: d10f bne.n 80048e8 <__swsetup_r+0x3c> + 80048c8: 686c ldr r4, [r5, #4] + 80048ca: 89a3 ldrh r3, [r4, #12] + 80048cc: f9b4 200c ldrsh.w r2, [r4, #12] + 80048d0: 0719 lsls r1, r3, #28 + 80048d2: d42c bmi.n 800492e <__swsetup_r+0x82> + 80048d4: 06dd lsls r5, r3, #27 + 80048d6: d411 bmi.n 80048fc <__swsetup_r+0x50> + 80048d8: 2309 movs r3, #9 + 80048da: 6033 str r3, [r6, #0] + 80048dc: f042 0340 orr.w r3, r2, #64 ; 0x40 + 80048e0: 81a3 strh r3, [r4, #12] + 80048e2: f04f 30ff mov.w r0, #4294967295 + 80048e6: e03e b.n 8004966 <__swsetup_r+0xba> + 80048e8: 4b25 ldr r3, [pc, #148] ; (8004980 <__swsetup_r+0xd4>) + 80048ea: 429c cmp r4, r3 + 80048ec: d101 bne.n 80048f2 <__swsetup_r+0x46> + 80048ee: 68ac ldr r4, [r5, #8] + 80048f0: e7eb b.n 80048ca <__swsetup_r+0x1e> + 80048f2: 4b24 ldr r3, [pc, #144] ; (8004984 <__swsetup_r+0xd8>) + 80048f4: 429c cmp r4, r3 + 80048f6: bf08 it eq + 80048f8: 68ec ldreq r4, [r5, #12] + 80048fa: e7e6 b.n 80048ca <__swsetup_r+0x1e> + 80048fc: 0758 lsls r0, r3, #29 + 80048fe: d512 bpl.n 8004926 <__swsetup_r+0x7a> + 8004900: 6b61 ldr r1, [r4, #52] ; 0x34 + 8004902: b141 cbz r1, 8004916 <__swsetup_r+0x6a> + 8004904: f104 0344 add.w r3, r4, #68 ; 0x44 + 8004908: 4299 cmp r1, r3 + 800490a: d002 beq.n 8004912 <__swsetup_r+0x66> + 800490c: 4630 mov r0, r6 + 800490e: f000 fa59 bl 8004dc4 <_free_r> + 8004912: 2300 movs r3, #0 + 8004914: 6363 str r3, [r4, #52] ; 0x34 + 8004916: 89a3 ldrh r3, [r4, #12] + 8004918: f023 0324 bic.w r3, r3, #36 ; 0x24 + 800491c: 81a3 strh r3, [r4, #12] + 800491e: 2300 movs r3, #0 + 8004920: 6063 str r3, [r4, #4] + 8004922: 6923 ldr r3, [r4, #16] + 8004924: 6023 str r3, [r4, #0] + 8004926: 89a3 ldrh r3, [r4, #12] + 8004928: f043 0308 orr.w r3, r3, #8 + 800492c: 81a3 strh r3, [r4, #12] + 800492e: 6923 ldr r3, [r4, #16] + 8004930: b94b cbnz r3, 8004946 <__swsetup_r+0x9a> + 8004932: 89a3 ldrh r3, [r4, #12] + 8004934: f403 7320 and.w r3, r3, #640 ; 0x280 + 8004938: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 800493c: d003 beq.n 8004946 <__swsetup_r+0x9a> + 800493e: 4621 mov r1, r4 + 8004940: 4630 mov r0, r6 + 8004942: f000 f9ff bl 8004d44 <__smakebuf_r> + 8004946: 89a0 ldrh r0, [r4, #12] + 8004948: f9b4 200c ldrsh.w r2, [r4, #12] + 800494c: f010 0301 ands.w r3, r0, #1 + 8004950: d00a beq.n 8004968 <__swsetup_r+0xbc> + 8004952: 2300 movs r3, #0 + 8004954: 60a3 str r3, [r4, #8] + 8004956: 6963 ldr r3, [r4, #20] + 8004958: 425b negs r3, r3 + 800495a: 61a3 str r3, [r4, #24] + 800495c: 6923 ldr r3, [r4, #16] + 800495e: b943 cbnz r3, 8004972 <__swsetup_r+0xc6> + 8004960: f010 0080 ands.w r0, r0, #128 ; 0x80 + 8004964: d1ba bne.n 80048dc <__swsetup_r+0x30> + 8004966: bd70 pop {r4, r5, r6, pc} + 8004968: 0781 lsls r1, r0, #30 + 800496a: bf58 it pl + 800496c: 6963 ldrpl r3, [r4, #20] + 800496e: 60a3 str r3, [r4, #8] + 8004970: e7f4 b.n 800495c <__swsetup_r+0xb0> + 8004972: 2000 movs r0, #0 + 8004974: e7f7 b.n 8004966 <__swsetup_r+0xba> + 8004976: bf00 nop + 8004978: 20000010 .word 0x20000010 + 800497c: 08005b40 .word 0x08005b40 + 8004980: 08005b60 .word 0x08005b60 + 8004984: 08005b20 .word 0x08005b20 + +08004988 <__sflush_r>: + 8004988: 898a ldrh r2, [r1, #12] + 800498a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 800498e: 4605 mov r5, r0 + 8004990: 0710 lsls r0, r2, #28 + 8004992: 460c mov r4, r1 + 8004994: d458 bmi.n 8004a48 <__sflush_r+0xc0> + 8004996: 684b ldr r3, [r1, #4] + 8004998: 2b00 cmp r3, #0 + 800499a: dc05 bgt.n 80049a8 <__sflush_r+0x20> + 800499c: 6c0b ldr r3, [r1, #64] ; 0x40 + 800499e: 2b00 cmp r3, #0 + 80049a0: dc02 bgt.n 80049a8 <__sflush_r+0x20> + 80049a2: 2000 movs r0, #0 + 80049a4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 80049a8: 6ae6 ldr r6, [r4, #44] ; 0x2c + 80049aa: 2e00 cmp r6, #0 + 80049ac: d0f9 beq.n 80049a2 <__sflush_r+0x1a> + 80049ae: 2300 movs r3, #0 + 80049b0: f412 5280 ands.w r2, r2, #4096 ; 0x1000 + 80049b4: 682f ldr r7, [r5, #0] + 80049b6: 602b str r3, [r5, #0] + 80049b8: d032 beq.n 8004a20 <__sflush_r+0x98> + 80049ba: 6d60 ldr r0, [r4, #84] ; 0x54 + 80049bc: 89a3 ldrh r3, [r4, #12] + 80049be: 075a lsls r2, r3, #29 + 80049c0: d505 bpl.n 80049ce <__sflush_r+0x46> + 80049c2: 6863 ldr r3, [r4, #4] + 80049c4: 1ac0 subs r0, r0, r3 + 80049c6: 6b63 ldr r3, [r4, #52] ; 0x34 + 80049c8: b10b cbz r3, 80049ce <__sflush_r+0x46> + 80049ca: 6c23 ldr r3, [r4, #64] ; 0x40 + 80049cc: 1ac0 subs r0, r0, r3 + 80049ce: 2300 movs r3, #0 + 80049d0: 4602 mov r2, r0 + 80049d2: 6ae6 ldr r6, [r4, #44] ; 0x2c + 80049d4: 6a21 ldr r1, [r4, #32] + 80049d6: 4628 mov r0, r5 + 80049d8: 47b0 blx r6 + 80049da: 1c43 adds r3, r0, #1 + 80049dc: 89a3 ldrh r3, [r4, #12] + 80049de: d106 bne.n 80049ee <__sflush_r+0x66> + 80049e0: 6829 ldr r1, [r5, #0] + 80049e2: 291d cmp r1, #29 + 80049e4: d82c bhi.n 8004a40 <__sflush_r+0xb8> + 80049e6: 4a2a ldr r2, [pc, #168] ; (8004a90 <__sflush_r+0x108>) + 80049e8: 40ca lsrs r2, r1 + 80049ea: 07d6 lsls r6, r2, #31 + 80049ec: d528 bpl.n 8004a40 <__sflush_r+0xb8> + 80049ee: 2200 movs r2, #0 + 80049f0: 6062 str r2, [r4, #4] + 80049f2: 04d9 lsls r1, r3, #19 + 80049f4: 6922 ldr r2, [r4, #16] + 80049f6: 6022 str r2, [r4, #0] + 80049f8: d504 bpl.n 8004a04 <__sflush_r+0x7c> + 80049fa: 1c42 adds r2, r0, #1 + 80049fc: d101 bne.n 8004a02 <__sflush_r+0x7a> + 80049fe: 682b ldr r3, [r5, #0] + 8004a00: b903 cbnz r3, 8004a04 <__sflush_r+0x7c> + 8004a02: 6560 str r0, [r4, #84] ; 0x54 + 8004a04: 6b61 ldr r1, [r4, #52] ; 0x34 + 8004a06: 602f str r7, [r5, #0] + 8004a08: 2900 cmp r1, #0 + 8004a0a: d0ca beq.n 80049a2 <__sflush_r+0x1a> + 8004a0c: f104 0344 add.w r3, r4, #68 ; 0x44 + 8004a10: 4299 cmp r1, r3 + 8004a12: d002 beq.n 8004a1a <__sflush_r+0x92> + 8004a14: 4628 mov r0, r5 + 8004a16: f000 f9d5 bl 8004dc4 <_free_r> + 8004a1a: 2000 movs r0, #0 + 8004a1c: 6360 str r0, [r4, #52] ; 0x34 + 8004a1e: e7c1 b.n 80049a4 <__sflush_r+0x1c> + 8004a20: 6a21 ldr r1, [r4, #32] + 8004a22: 2301 movs r3, #1 + 8004a24: 4628 mov r0, r5 + 8004a26: 47b0 blx r6 + 8004a28: 1c41 adds r1, r0, #1 + 8004a2a: d1c7 bne.n 80049bc <__sflush_r+0x34> + 8004a2c: 682b ldr r3, [r5, #0] + 8004a2e: 2b00 cmp r3, #0 + 8004a30: d0c4 beq.n 80049bc <__sflush_r+0x34> + 8004a32: 2b1d cmp r3, #29 + 8004a34: d001 beq.n 8004a3a <__sflush_r+0xb2> + 8004a36: 2b16 cmp r3, #22 + 8004a38: d101 bne.n 8004a3e <__sflush_r+0xb6> + 8004a3a: 602f str r7, [r5, #0] + 8004a3c: e7b1 b.n 80049a2 <__sflush_r+0x1a> + 8004a3e: 89a3 ldrh r3, [r4, #12] + 8004a40: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8004a44: 81a3 strh r3, [r4, #12] + 8004a46: e7ad b.n 80049a4 <__sflush_r+0x1c> + 8004a48: 690f ldr r7, [r1, #16] + 8004a4a: 2f00 cmp r7, #0 + 8004a4c: d0a9 beq.n 80049a2 <__sflush_r+0x1a> + 8004a4e: 0793 lsls r3, r2, #30 + 8004a50: 680e ldr r6, [r1, #0] + 8004a52: bf08 it eq + 8004a54: 694b ldreq r3, [r1, #20] + 8004a56: 600f str r7, [r1, #0] + 8004a58: bf18 it ne + 8004a5a: 2300 movne r3, #0 + 8004a5c: eba6 0807 sub.w r8, r6, r7 + 8004a60: 608b str r3, [r1, #8] + 8004a62: f1b8 0f00 cmp.w r8, #0 + 8004a66: dd9c ble.n 80049a2 <__sflush_r+0x1a> + 8004a68: 6a21 ldr r1, [r4, #32] + 8004a6a: 6aa6 ldr r6, [r4, #40] ; 0x28 + 8004a6c: 4643 mov r3, r8 + 8004a6e: 463a mov r2, r7 + 8004a70: 4628 mov r0, r5 + 8004a72: 47b0 blx r6 + 8004a74: 2800 cmp r0, #0 + 8004a76: dc06 bgt.n 8004a86 <__sflush_r+0xfe> + 8004a78: 89a3 ldrh r3, [r4, #12] + 8004a7a: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8004a7e: 81a3 strh r3, [r4, #12] + 8004a80: f04f 30ff mov.w r0, #4294967295 + 8004a84: e78e b.n 80049a4 <__sflush_r+0x1c> + 8004a86: 4407 add r7, r0 + 8004a88: eba8 0800 sub.w r8, r8, r0 + 8004a8c: e7e9 b.n 8004a62 <__sflush_r+0xda> + 8004a8e: bf00 nop + 8004a90: 20400001 .word 0x20400001 + +08004a94 <_fflush_r>: + 8004a94: b538 push {r3, r4, r5, lr} + 8004a96: 690b ldr r3, [r1, #16] + 8004a98: 4605 mov r5, r0 + 8004a9a: 460c mov r4, r1 + 8004a9c: b913 cbnz r3, 8004aa4 <_fflush_r+0x10> + 8004a9e: 2500 movs r5, #0 + 8004aa0: 4628 mov r0, r5 + 8004aa2: bd38 pop {r3, r4, r5, pc} + 8004aa4: b118 cbz r0, 8004aae <_fflush_r+0x1a> + 8004aa6: 6983 ldr r3, [r0, #24] + 8004aa8: b90b cbnz r3, 8004aae <_fflush_r+0x1a> + 8004aaa: f000 f887 bl 8004bbc <__sinit> + 8004aae: 4b14 ldr r3, [pc, #80] ; (8004b00 <_fflush_r+0x6c>) + 8004ab0: 429c cmp r4, r3 + 8004ab2: d11b bne.n 8004aec <_fflush_r+0x58> + 8004ab4: 686c ldr r4, [r5, #4] + 8004ab6: f9b4 300c ldrsh.w r3, [r4, #12] + 8004aba: 2b00 cmp r3, #0 + 8004abc: d0ef beq.n 8004a9e <_fflush_r+0xa> + 8004abe: 6e62 ldr r2, [r4, #100] ; 0x64 + 8004ac0: 07d0 lsls r0, r2, #31 + 8004ac2: d404 bmi.n 8004ace <_fflush_r+0x3a> + 8004ac4: 0599 lsls r1, r3, #22 + 8004ac6: d402 bmi.n 8004ace <_fflush_r+0x3a> + 8004ac8: 6da0 ldr r0, [r4, #88] ; 0x58 + 8004aca: f000 f915 bl 8004cf8 <__retarget_lock_acquire_recursive> + 8004ace: 4628 mov r0, r5 + 8004ad0: 4621 mov r1, r4 + 8004ad2: f7ff ff59 bl 8004988 <__sflush_r> + 8004ad6: 6e63 ldr r3, [r4, #100] ; 0x64 + 8004ad8: 07da lsls r2, r3, #31 + 8004ada: 4605 mov r5, r0 + 8004adc: d4e0 bmi.n 8004aa0 <_fflush_r+0xc> + 8004ade: 89a3 ldrh r3, [r4, #12] + 8004ae0: 059b lsls r3, r3, #22 + 8004ae2: d4dd bmi.n 8004aa0 <_fflush_r+0xc> + 8004ae4: 6da0 ldr r0, [r4, #88] ; 0x58 + 8004ae6: f000 f908 bl 8004cfa <__retarget_lock_release_recursive> + 8004aea: e7d9 b.n 8004aa0 <_fflush_r+0xc> + 8004aec: 4b05 ldr r3, [pc, #20] ; (8004b04 <_fflush_r+0x70>) + 8004aee: 429c cmp r4, r3 + 8004af0: d101 bne.n 8004af6 <_fflush_r+0x62> + 8004af2: 68ac ldr r4, [r5, #8] + 8004af4: e7df b.n 8004ab6 <_fflush_r+0x22> + 8004af6: 4b04 ldr r3, [pc, #16] ; (8004b08 <_fflush_r+0x74>) + 8004af8: 429c cmp r4, r3 + 8004afa: bf08 it eq + 8004afc: 68ec ldreq r4, [r5, #12] + 8004afe: e7da b.n 8004ab6 <_fflush_r+0x22> + 8004b00: 08005b40 .word 0x08005b40 + 8004b04: 08005b60 .word 0x08005b60 + 8004b08: 08005b20 .word 0x08005b20 + +08004b0c : + 8004b0c: 2300 movs r3, #0 + 8004b0e: b510 push {r4, lr} + 8004b10: 4604 mov r4, r0 + 8004b12: e9c0 3300 strd r3, r3, [r0] + 8004b16: e9c0 3304 strd r3, r3, [r0, #16] + 8004b1a: 6083 str r3, [r0, #8] + 8004b1c: 8181 strh r1, [r0, #12] + 8004b1e: 6643 str r3, [r0, #100] ; 0x64 + 8004b20: 81c2 strh r2, [r0, #14] + 8004b22: 6183 str r3, [r0, #24] + 8004b24: 4619 mov r1, r3 + 8004b26: 2208 movs r2, #8 + 8004b28: 305c adds r0, #92 ; 0x5c + 8004b2a: f7ff fdd7 bl 80046dc + 8004b2e: 4b05 ldr r3, [pc, #20] ; (8004b44 ) + 8004b30: 6263 str r3, [r4, #36] ; 0x24 + 8004b32: 4b05 ldr r3, [pc, #20] ; (8004b48 ) + 8004b34: 62a3 str r3, [r4, #40] ; 0x28 + 8004b36: 4b05 ldr r3, [pc, #20] ; (8004b4c ) + 8004b38: 62e3 str r3, [r4, #44] ; 0x2c + 8004b3a: 4b05 ldr r3, [pc, #20] ; (8004b50 ) + 8004b3c: 6224 str r4, [r4, #32] + 8004b3e: 6323 str r3, [r4, #48] ; 0x30 + 8004b40: bd10 pop {r4, pc} + 8004b42: bf00 nop + 8004b44: 08005515 .word 0x08005515 + 8004b48: 08005537 .word 0x08005537 + 8004b4c: 0800556f .word 0x0800556f + 8004b50: 08005593 .word 0x08005593 + +08004b54 <_cleanup_r>: + 8004b54: 4901 ldr r1, [pc, #4] ; (8004b5c <_cleanup_r+0x8>) + 8004b56: f000 b8af b.w 8004cb8 <_fwalk_reent> + 8004b5a: bf00 nop + 8004b5c: 08004a95 .word 0x08004a95 + +08004b60 <__sfmoreglue>: + 8004b60: b570 push {r4, r5, r6, lr} + 8004b62: 1e4a subs r2, r1, #1 + 8004b64: 2568 movs r5, #104 ; 0x68 + 8004b66: 4355 muls r5, r2 + 8004b68: 460e mov r6, r1 + 8004b6a: f105 0174 add.w r1, r5, #116 ; 0x74 + 8004b6e: f000 f979 bl 8004e64 <_malloc_r> + 8004b72: 4604 mov r4, r0 + 8004b74: b140 cbz r0, 8004b88 <__sfmoreglue+0x28> + 8004b76: 2100 movs r1, #0 + 8004b78: e9c0 1600 strd r1, r6, [r0] + 8004b7c: 300c adds r0, #12 + 8004b7e: 60a0 str r0, [r4, #8] + 8004b80: f105 0268 add.w r2, r5, #104 ; 0x68 + 8004b84: f7ff fdaa bl 80046dc + 8004b88: 4620 mov r0, r4 + 8004b8a: bd70 pop {r4, r5, r6, pc} + +08004b8c <__sfp_lock_acquire>: + 8004b8c: 4801 ldr r0, [pc, #4] ; (8004b94 <__sfp_lock_acquire+0x8>) + 8004b8e: f000 b8b3 b.w 8004cf8 <__retarget_lock_acquire_recursive> + 8004b92: bf00 nop + 8004b94: 2000060c .word 0x2000060c + +08004b98 <__sfp_lock_release>: + 8004b98: 4801 ldr r0, [pc, #4] ; (8004ba0 <__sfp_lock_release+0x8>) + 8004b9a: f000 b8ae b.w 8004cfa <__retarget_lock_release_recursive> + 8004b9e: bf00 nop + 8004ba0: 2000060c .word 0x2000060c + +08004ba4 <__sinit_lock_acquire>: + 8004ba4: 4801 ldr r0, [pc, #4] ; (8004bac <__sinit_lock_acquire+0x8>) + 8004ba6: f000 b8a7 b.w 8004cf8 <__retarget_lock_acquire_recursive> + 8004baa: bf00 nop + 8004bac: 20000607 .word 0x20000607 + +08004bb0 <__sinit_lock_release>: + 8004bb0: 4801 ldr r0, [pc, #4] ; (8004bb8 <__sinit_lock_release+0x8>) + 8004bb2: f000 b8a2 b.w 8004cfa <__retarget_lock_release_recursive> + 8004bb6: bf00 nop + 8004bb8: 20000607 .word 0x20000607 + +08004bbc <__sinit>: + 8004bbc: b510 push {r4, lr} + 8004bbe: 4604 mov r4, r0 + 8004bc0: f7ff fff0 bl 8004ba4 <__sinit_lock_acquire> + 8004bc4: 69a3 ldr r3, [r4, #24] + 8004bc6: b11b cbz r3, 8004bd0 <__sinit+0x14> + 8004bc8: e8bd 4010 ldmia.w sp!, {r4, lr} + 8004bcc: f7ff bff0 b.w 8004bb0 <__sinit_lock_release> + 8004bd0: e9c4 3312 strd r3, r3, [r4, #72] ; 0x48 + 8004bd4: 6523 str r3, [r4, #80] ; 0x50 + 8004bd6: 4b13 ldr r3, [pc, #76] ; (8004c24 <__sinit+0x68>) + 8004bd8: 4a13 ldr r2, [pc, #76] ; (8004c28 <__sinit+0x6c>) + 8004bda: 681b ldr r3, [r3, #0] + 8004bdc: 62a2 str r2, [r4, #40] ; 0x28 + 8004bde: 42a3 cmp r3, r4 + 8004be0: bf04 itt eq + 8004be2: 2301 moveq r3, #1 + 8004be4: 61a3 streq r3, [r4, #24] + 8004be6: 4620 mov r0, r4 + 8004be8: f000 f820 bl 8004c2c <__sfp> + 8004bec: 6060 str r0, [r4, #4] + 8004bee: 4620 mov r0, r4 + 8004bf0: f000 f81c bl 8004c2c <__sfp> + 8004bf4: 60a0 str r0, [r4, #8] + 8004bf6: 4620 mov r0, r4 + 8004bf8: f000 f818 bl 8004c2c <__sfp> + 8004bfc: 2200 movs r2, #0 + 8004bfe: 60e0 str r0, [r4, #12] + 8004c00: 2104 movs r1, #4 + 8004c02: 6860 ldr r0, [r4, #4] + 8004c04: f7ff ff82 bl 8004b0c + 8004c08: 68a0 ldr r0, [r4, #8] + 8004c0a: 2201 movs r2, #1 + 8004c0c: 2109 movs r1, #9 + 8004c0e: f7ff ff7d bl 8004b0c + 8004c12: 68e0 ldr r0, [r4, #12] + 8004c14: 2202 movs r2, #2 + 8004c16: 2112 movs r1, #18 + 8004c18: f7ff ff78 bl 8004b0c + 8004c1c: 2301 movs r3, #1 + 8004c1e: 61a3 str r3, [r4, #24] + 8004c20: e7d2 b.n 8004bc8 <__sinit+0xc> + 8004c22: bf00 nop + 8004c24: 08005b1c .word 0x08005b1c + 8004c28: 08004b55 .word 0x08004b55 + +08004c2c <__sfp>: + 8004c2c: b5f8 push {r3, r4, r5, r6, r7, lr} + 8004c2e: 4607 mov r7, r0 + 8004c30: f7ff ffac bl 8004b8c <__sfp_lock_acquire> + 8004c34: 4b1e ldr r3, [pc, #120] ; (8004cb0 <__sfp+0x84>) + 8004c36: 681e ldr r6, [r3, #0] + 8004c38: 69b3 ldr r3, [r6, #24] + 8004c3a: b913 cbnz r3, 8004c42 <__sfp+0x16> + 8004c3c: 4630 mov r0, r6 + 8004c3e: f7ff ffbd bl 8004bbc <__sinit> + 8004c42: 3648 adds r6, #72 ; 0x48 + 8004c44: e9d6 3401 ldrd r3, r4, [r6, #4] + 8004c48: 3b01 subs r3, #1 + 8004c4a: d503 bpl.n 8004c54 <__sfp+0x28> + 8004c4c: 6833 ldr r3, [r6, #0] + 8004c4e: b30b cbz r3, 8004c94 <__sfp+0x68> + 8004c50: 6836 ldr r6, [r6, #0] + 8004c52: e7f7 b.n 8004c44 <__sfp+0x18> + 8004c54: f9b4 500c ldrsh.w r5, [r4, #12] + 8004c58: b9d5 cbnz r5, 8004c90 <__sfp+0x64> + 8004c5a: 4b16 ldr r3, [pc, #88] ; (8004cb4 <__sfp+0x88>) + 8004c5c: 60e3 str r3, [r4, #12] + 8004c5e: f104 0058 add.w r0, r4, #88 ; 0x58 + 8004c62: 6665 str r5, [r4, #100] ; 0x64 + 8004c64: f000 f847 bl 8004cf6 <__retarget_lock_init_recursive> + 8004c68: f7ff ff96 bl 8004b98 <__sfp_lock_release> + 8004c6c: e9c4 5501 strd r5, r5, [r4, #4] + 8004c70: e9c4 5504 strd r5, r5, [r4, #16] + 8004c74: 6025 str r5, [r4, #0] + 8004c76: 61a5 str r5, [r4, #24] + 8004c78: 2208 movs r2, #8 + 8004c7a: 4629 mov r1, r5 + 8004c7c: f104 005c add.w r0, r4, #92 ; 0x5c + 8004c80: f7ff fd2c bl 80046dc + 8004c84: e9c4 550d strd r5, r5, [r4, #52] ; 0x34 + 8004c88: e9c4 5512 strd r5, r5, [r4, #72] ; 0x48 + 8004c8c: 4620 mov r0, r4 + 8004c8e: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8004c90: 3468 adds r4, #104 ; 0x68 + 8004c92: e7d9 b.n 8004c48 <__sfp+0x1c> + 8004c94: 2104 movs r1, #4 + 8004c96: 4638 mov r0, r7 + 8004c98: f7ff ff62 bl 8004b60 <__sfmoreglue> + 8004c9c: 4604 mov r4, r0 + 8004c9e: 6030 str r0, [r6, #0] + 8004ca0: 2800 cmp r0, #0 + 8004ca2: d1d5 bne.n 8004c50 <__sfp+0x24> + 8004ca4: f7ff ff78 bl 8004b98 <__sfp_lock_release> + 8004ca8: 230c movs r3, #12 + 8004caa: 603b str r3, [r7, #0] + 8004cac: e7ee b.n 8004c8c <__sfp+0x60> + 8004cae: bf00 nop + 8004cb0: 08005b1c .word 0x08005b1c + 8004cb4: ffff0001 .word 0xffff0001 + +08004cb8 <_fwalk_reent>: + 8004cb8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 8004cbc: 4606 mov r6, r0 + 8004cbe: 4688 mov r8, r1 + 8004cc0: f100 0448 add.w r4, r0, #72 ; 0x48 + 8004cc4: 2700 movs r7, #0 + 8004cc6: e9d4 9501 ldrd r9, r5, [r4, #4] + 8004cca: f1b9 0901 subs.w r9, r9, #1 + 8004cce: d505 bpl.n 8004cdc <_fwalk_reent+0x24> + 8004cd0: 6824 ldr r4, [r4, #0] + 8004cd2: 2c00 cmp r4, #0 + 8004cd4: d1f7 bne.n 8004cc6 <_fwalk_reent+0xe> + 8004cd6: 4638 mov r0, r7 + 8004cd8: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 8004cdc: 89ab ldrh r3, [r5, #12] + 8004cde: 2b01 cmp r3, #1 + 8004ce0: d907 bls.n 8004cf2 <_fwalk_reent+0x3a> + 8004ce2: f9b5 300e ldrsh.w r3, [r5, #14] + 8004ce6: 3301 adds r3, #1 + 8004ce8: d003 beq.n 8004cf2 <_fwalk_reent+0x3a> + 8004cea: 4629 mov r1, r5 + 8004cec: 4630 mov r0, r6 + 8004cee: 47c0 blx r8 + 8004cf0: 4307 orrs r7, r0 + 8004cf2: 3568 adds r5, #104 ; 0x68 + 8004cf4: e7e9 b.n 8004cca <_fwalk_reent+0x12> + +08004cf6 <__retarget_lock_init_recursive>: + 8004cf6: 4770 bx lr + +08004cf8 <__retarget_lock_acquire_recursive>: + 8004cf8: 4770 bx lr + +08004cfa <__retarget_lock_release_recursive>: + 8004cfa: 4770 bx lr + +08004cfc <__swhatbuf_r>: + 8004cfc: b570 push {r4, r5, r6, lr} + 8004cfe: 460e mov r6, r1 + 8004d00: f9b1 100e ldrsh.w r1, [r1, #14] + 8004d04: 2900 cmp r1, #0 + 8004d06: b096 sub sp, #88 ; 0x58 + 8004d08: 4614 mov r4, r2 + 8004d0a: 461d mov r5, r3 + 8004d0c: da07 bge.n 8004d1e <__swhatbuf_r+0x22> + 8004d0e: 2300 movs r3, #0 + 8004d10: 602b str r3, [r5, #0] + 8004d12: 89b3 ldrh r3, [r6, #12] + 8004d14: 061a lsls r2, r3, #24 + 8004d16: d410 bmi.n 8004d3a <__swhatbuf_r+0x3e> + 8004d18: f44f 6380 mov.w r3, #1024 ; 0x400 + 8004d1c: e00e b.n 8004d3c <__swhatbuf_r+0x40> + 8004d1e: 466a mov r2, sp + 8004d20: f000 fc5e bl 80055e0 <_fstat_r> + 8004d24: 2800 cmp r0, #0 + 8004d26: dbf2 blt.n 8004d0e <__swhatbuf_r+0x12> + 8004d28: 9a01 ldr r2, [sp, #4] + 8004d2a: f402 4270 and.w r2, r2, #61440 ; 0xf000 + 8004d2e: f5a2 5300 sub.w r3, r2, #8192 ; 0x2000 + 8004d32: 425a negs r2, r3 + 8004d34: 415a adcs r2, r3 + 8004d36: 602a str r2, [r5, #0] + 8004d38: e7ee b.n 8004d18 <__swhatbuf_r+0x1c> + 8004d3a: 2340 movs r3, #64 ; 0x40 + 8004d3c: 2000 movs r0, #0 + 8004d3e: 6023 str r3, [r4, #0] + 8004d40: b016 add sp, #88 ; 0x58 + 8004d42: bd70 pop {r4, r5, r6, pc} + +08004d44 <__smakebuf_r>: + 8004d44: 898b ldrh r3, [r1, #12] + 8004d46: b573 push {r0, r1, r4, r5, r6, lr} + 8004d48: 079d lsls r5, r3, #30 + 8004d4a: 4606 mov r6, r0 + 8004d4c: 460c mov r4, r1 + 8004d4e: d507 bpl.n 8004d60 <__smakebuf_r+0x1c> + 8004d50: f104 0347 add.w r3, r4, #71 ; 0x47 + 8004d54: 6023 str r3, [r4, #0] + 8004d56: 6123 str r3, [r4, #16] + 8004d58: 2301 movs r3, #1 + 8004d5a: 6163 str r3, [r4, #20] + 8004d5c: b002 add sp, #8 + 8004d5e: bd70 pop {r4, r5, r6, pc} + 8004d60: ab01 add r3, sp, #4 + 8004d62: 466a mov r2, sp + 8004d64: f7ff ffca bl 8004cfc <__swhatbuf_r> + 8004d68: 9900 ldr r1, [sp, #0] + 8004d6a: 4605 mov r5, r0 + 8004d6c: 4630 mov r0, r6 + 8004d6e: f000 f879 bl 8004e64 <_malloc_r> + 8004d72: b948 cbnz r0, 8004d88 <__smakebuf_r+0x44> + 8004d74: f9b4 300c ldrsh.w r3, [r4, #12] + 8004d78: 059a lsls r2, r3, #22 + 8004d7a: d4ef bmi.n 8004d5c <__smakebuf_r+0x18> + 8004d7c: f023 0303 bic.w r3, r3, #3 + 8004d80: f043 0302 orr.w r3, r3, #2 + 8004d84: 81a3 strh r3, [r4, #12] + 8004d86: e7e3 b.n 8004d50 <__smakebuf_r+0xc> + 8004d88: 4b0d ldr r3, [pc, #52] ; (8004dc0 <__smakebuf_r+0x7c>) + 8004d8a: 62b3 str r3, [r6, #40] ; 0x28 + 8004d8c: 89a3 ldrh r3, [r4, #12] + 8004d8e: 6020 str r0, [r4, #0] + 8004d90: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8004d94: 81a3 strh r3, [r4, #12] + 8004d96: 9b00 ldr r3, [sp, #0] + 8004d98: 6163 str r3, [r4, #20] + 8004d9a: 9b01 ldr r3, [sp, #4] + 8004d9c: 6120 str r0, [r4, #16] + 8004d9e: b15b cbz r3, 8004db8 <__smakebuf_r+0x74> + 8004da0: f9b4 100e ldrsh.w r1, [r4, #14] + 8004da4: 4630 mov r0, r6 + 8004da6: f000 fc2d bl 8005604 <_isatty_r> + 8004daa: b128 cbz r0, 8004db8 <__smakebuf_r+0x74> + 8004dac: 89a3 ldrh r3, [r4, #12] + 8004dae: f023 0303 bic.w r3, r3, #3 + 8004db2: f043 0301 orr.w r3, r3, #1 + 8004db6: 81a3 strh r3, [r4, #12] + 8004db8: 89a0 ldrh r0, [r4, #12] + 8004dba: 4305 orrs r5, r0 + 8004dbc: 81a5 strh r5, [r4, #12] + 8004dbe: e7cd b.n 8004d5c <__smakebuf_r+0x18> + 8004dc0: 08004b55 .word 0x08004b55 + +08004dc4 <_free_r>: + 8004dc4: b537 push {r0, r1, r2, r4, r5, lr} + 8004dc6: 2900 cmp r1, #0 + 8004dc8: d048 beq.n 8004e5c <_free_r+0x98> + 8004dca: f851 3c04 ldr.w r3, [r1, #-4] + 8004dce: 9001 str r0, [sp, #4] + 8004dd0: 2b00 cmp r3, #0 + 8004dd2: f1a1 0404 sub.w r4, r1, #4 + 8004dd6: bfb8 it lt + 8004dd8: 18e4 addlt r4, r4, r3 + 8004dda: f000 fc35 bl 8005648 <__malloc_lock> + 8004dde: 4a20 ldr r2, [pc, #128] ; (8004e60 <_free_r+0x9c>) + 8004de0: 9801 ldr r0, [sp, #4] + 8004de2: 6813 ldr r3, [r2, #0] + 8004de4: 4615 mov r5, r2 + 8004de6: b933 cbnz r3, 8004df6 <_free_r+0x32> + 8004de8: 6063 str r3, [r4, #4] + 8004dea: 6014 str r4, [r2, #0] + 8004dec: b003 add sp, #12 + 8004dee: e8bd 4030 ldmia.w sp!, {r4, r5, lr} + 8004df2: f000 bc2f b.w 8005654 <__malloc_unlock> + 8004df6: 42a3 cmp r3, r4 + 8004df8: d90b bls.n 8004e12 <_free_r+0x4e> + 8004dfa: 6821 ldr r1, [r4, #0] + 8004dfc: 1862 adds r2, r4, r1 + 8004dfe: 4293 cmp r3, r2 + 8004e00: bf04 itt eq + 8004e02: 681a ldreq r2, [r3, #0] + 8004e04: 685b ldreq r3, [r3, #4] + 8004e06: 6063 str r3, [r4, #4] + 8004e08: bf04 itt eq + 8004e0a: 1852 addeq r2, r2, r1 + 8004e0c: 6022 streq r2, [r4, #0] + 8004e0e: 602c str r4, [r5, #0] + 8004e10: e7ec b.n 8004dec <_free_r+0x28> + 8004e12: 461a mov r2, r3 + 8004e14: 685b ldr r3, [r3, #4] + 8004e16: b10b cbz r3, 8004e1c <_free_r+0x58> + 8004e18: 42a3 cmp r3, r4 + 8004e1a: d9fa bls.n 8004e12 <_free_r+0x4e> + 8004e1c: 6811 ldr r1, [r2, #0] + 8004e1e: 1855 adds r5, r2, r1 + 8004e20: 42a5 cmp r5, r4 + 8004e22: d10b bne.n 8004e3c <_free_r+0x78> + 8004e24: 6824 ldr r4, [r4, #0] + 8004e26: 4421 add r1, r4 + 8004e28: 1854 adds r4, r2, r1 + 8004e2a: 42a3 cmp r3, r4 + 8004e2c: 6011 str r1, [r2, #0] + 8004e2e: d1dd bne.n 8004dec <_free_r+0x28> + 8004e30: 681c ldr r4, [r3, #0] + 8004e32: 685b ldr r3, [r3, #4] + 8004e34: 6053 str r3, [r2, #4] + 8004e36: 4421 add r1, r4 + 8004e38: 6011 str r1, [r2, #0] + 8004e3a: e7d7 b.n 8004dec <_free_r+0x28> + 8004e3c: d902 bls.n 8004e44 <_free_r+0x80> + 8004e3e: 230c movs r3, #12 + 8004e40: 6003 str r3, [r0, #0] + 8004e42: e7d3 b.n 8004dec <_free_r+0x28> + 8004e44: 6825 ldr r5, [r4, #0] + 8004e46: 1961 adds r1, r4, r5 + 8004e48: 428b cmp r3, r1 + 8004e4a: bf04 itt eq + 8004e4c: 6819 ldreq r1, [r3, #0] + 8004e4e: 685b ldreq r3, [r3, #4] + 8004e50: 6063 str r3, [r4, #4] + 8004e52: bf04 itt eq + 8004e54: 1949 addeq r1, r1, r5 + 8004e56: 6021 streq r1, [r4, #0] + 8004e58: 6054 str r4, [r2, #4] + 8004e5a: e7c7 b.n 8004dec <_free_r+0x28> + 8004e5c: b003 add sp, #12 + 8004e5e: bd30 pop {r4, r5, pc} + 8004e60: 200004b0 .word 0x200004b0 + +08004e64 <_malloc_r>: + 8004e64: b5f8 push {r3, r4, r5, r6, r7, lr} + 8004e66: 1ccd adds r5, r1, #3 + 8004e68: f025 0503 bic.w r5, r5, #3 + 8004e6c: 3508 adds r5, #8 + 8004e6e: 2d0c cmp r5, #12 + 8004e70: bf38 it cc + 8004e72: 250c movcc r5, #12 + 8004e74: 2d00 cmp r5, #0 + 8004e76: 4606 mov r6, r0 + 8004e78: db01 blt.n 8004e7e <_malloc_r+0x1a> + 8004e7a: 42a9 cmp r1, r5 + 8004e7c: d903 bls.n 8004e86 <_malloc_r+0x22> + 8004e7e: 230c movs r3, #12 + 8004e80: 6033 str r3, [r6, #0] + 8004e82: 2000 movs r0, #0 + 8004e84: bdf8 pop {r3, r4, r5, r6, r7, pc} + 8004e86: f000 fbdf bl 8005648 <__malloc_lock> + 8004e8a: 4921 ldr r1, [pc, #132] ; (8004f10 <_malloc_r+0xac>) + 8004e8c: 680a ldr r2, [r1, #0] + 8004e8e: 4614 mov r4, r2 + 8004e90: b99c cbnz r4, 8004eba <_malloc_r+0x56> + 8004e92: 4f20 ldr r7, [pc, #128] ; (8004f14 <_malloc_r+0xb0>) + 8004e94: 683b ldr r3, [r7, #0] + 8004e96: b923 cbnz r3, 8004ea2 <_malloc_r+0x3e> + 8004e98: 4621 mov r1, r4 + 8004e9a: 4630 mov r0, r6 + 8004e9c: f000 fb2a bl 80054f4 <_sbrk_r> + 8004ea0: 6038 str r0, [r7, #0] + 8004ea2: 4629 mov r1, r5 + 8004ea4: 4630 mov r0, r6 + 8004ea6: f000 fb25 bl 80054f4 <_sbrk_r> + 8004eaa: 1c43 adds r3, r0, #1 + 8004eac: d123 bne.n 8004ef6 <_malloc_r+0x92> + 8004eae: 230c movs r3, #12 + 8004eb0: 6033 str r3, [r6, #0] + 8004eb2: 4630 mov r0, r6 + 8004eb4: f000 fbce bl 8005654 <__malloc_unlock> + 8004eb8: e7e3 b.n 8004e82 <_malloc_r+0x1e> + 8004eba: 6823 ldr r3, [r4, #0] + 8004ebc: 1b5b subs r3, r3, r5 + 8004ebe: d417 bmi.n 8004ef0 <_malloc_r+0x8c> + 8004ec0: 2b0b cmp r3, #11 + 8004ec2: d903 bls.n 8004ecc <_malloc_r+0x68> + 8004ec4: 6023 str r3, [r4, #0] + 8004ec6: 441c add r4, r3 + 8004ec8: 6025 str r5, [r4, #0] + 8004eca: e004 b.n 8004ed6 <_malloc_r+0x72> + 8004ecc: 6863 ldr r3, [r4, #4] + 8004ece: 42a2 cmp r2, r4 + 8004ed0: bf0c ite eq + 8004ed2: 600b streq r3, [r1, #0] + 8004ed4: 6053 strne r3, [r2, #4] + 8004ed6: 4630 mov r0, r6 + 8004ed8: f000 fbbc bl 8005654 <__malloc_unlock> + 8004edc: f104 000b add.w r0, r4, #11 + 8004ee0: 1d23 adds r3, r4, #4 + 8004ee2: f020 0007 bic.w r0, r0, #7 + 8004ee6: 1ac2 subs r2, r0, r3 + 8004ee8: d0cc beq.n 8004e84 <_malloc_r+0x20> + 8004eea: 1a1b subs r3, r3, r0 + 8004eec: 50a3 str r3, [r4, r2] + 8004eee: e7c9 b.n 8004e84 <_malloc_r+0x20> + 8004ef0: 4622 mov r2, r4 + 8004ef2: 6864 ldr r4, [r4, #4] + 8004ef4: e7cc b.n 8004e90 <_malloc_r+0x2c> + 8004ef6: 1cc4 adds r4, r0, #3 + 8004ef8: f024 0403 bic.w r4, r4, #3 + 8004efc: 42a0 cmp r0, r4 + 8004efe: d0e3 beq.n 8004ec8 <_malloc_r+0x64> + 8004f00: 1a21 subs r1, r4, r0 + 8004f02: 4630 mov r0, r6 + 8004f04: f000 faf6 bl 80054f4 <_sbrk_r> + 8004f08: 3001 adds r0, #1 + 8004f0a: d1dd bne.n 8004ec8 <_malloc_r+0x64> + 8004f0c: e7cf b.n 8004eae <_malloc_r+0x4a> + 8004f0e: bf00 nop + 8004f10: 200004b0 .word 0x200004b0 + 8004f14: 200004b4 .word 0x200004b4 + +08004f18 <__sfputc_r>: + 8004f18: 6893 ldr r3, [r2, #8] + 8004f1a: 3b01 subs r3, #1 + 8004f1c: 2b00 cmp r3, #0 + 8004f1e: b410 push {r4} + 8004f20: 6093 str r3, [r2, #8] + 8004f22: da08 bge.n 8004f36 <__sfputc_r+0x1e> + 8004f24: 6994 ldr r4, [r2, #24] + 8004f26: 42a3 cmp r3, r4 + 8004f28: db01 blt.n 8004f2e <__sfputc_r+0x16> + 8004f2a: 290a cmp r1, #10 + 8004f2c: d103 bne.n 8004f36 <__sfputc_r+0x1e> + 8004f2e: f85d 4b04 ldr.w r4, [sp], #4 + 8004f32: f7ff bc69 b.w 8004808 <__swbuf_r> + 8004f36: 6813 ldr r3, [r2, #0] + 8004f38: 1c58 adds r0, r3, #1 + 8004f3a: 6010 str r0, [r2, #0] + 8004f3c: 7019 strb r1, [r3, #0] + 8004f3e: 4608 mov r0, r1 + 8004f40: f85d 4b04 ldr.w r4, [sp], #4 + 8004f44: 4770 bx lr + +08004f46 <__sfputs_r>: + 8004f46: b5f8 push {r3, r4, r5, r6, r7, lr} + 8004f48: 4606 mov r6, r0 + 8004f4a: 460f mov r7, r1 + 8004f4c: 4614 mov r4, r2 + 8004f4e: 18d5 adds r5, r2, r3 + 8004f50: 42ac cmp r4, r5 + 8004f52: d101 bne.n 8004f58 <__sfputs_r+0x12> + 8004f54: 2000 movs r0, #0 + 8004f56: e007 b.n 8004f68 <__sfputs_r+0x22> + 8004f58: f814 1b01 ldrb.w r1, [r4], #1 + 8004f5c: 463a mov r2, r7 + 8004f5e: 4630 mov r0, r6 + 8004f60: f7ff ffda bl 8004f18 <__sfputc_r> + 8004f64: 1c43 adds r3, r0, #1 + 8004f66: d1f3 bne.n 8004f50 <__sfputs_r+0xa> + 8004f68: bdf8 pop {r3, r4, r5, r6, r7, pc} ... -080042c0 <_vfiprintf_r>: - 80042c0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 80042c4: 460d mov r5, r1 - 80042c6: b09d sub sp, #116 ; 0x74 - 80042c8: 4614 mov r4, r2 - 80042ca: 4698 mov r8, r3 - 80042cc: 4606 mov r6, r0 - 80042ce: b118 cbz r0, 80042d8 <_vfiprintf_r+0x18> - 80042d0: 6983 ldr r3, [r0, #24] - 80042d2: b90b cbnz r3, 80042d8 <_vfiprintf_r+0x18> - 80042d4: f7ff fe1c bl 8003f10 <__sinit> - 80042d8: 4b89 ldr r3, [pc, #548] ; (8004500 <_vfiprintf_r+0x240>) - 80042da: 429d cmp r5, r3 - 80042dc: d11b bne.n 8004316 <_vfiprintf_r+0x56> - 80042de: 6875 ldr r5, [r6, #4] - 80042e0: 6e6b ldr r3, [r5, #100] ; 0x64 - 80042e2: 07d9 lsls r1, r3, #31 - 80042e4: d405 bmi.n 80042f2 <_vfiprintf_r+0x32> - 80042e6: 89ab ldrh r3, [r5, #12] - 80042e8: 059a lsls r2, r3, #22 - 80042ea: d402 bmi.n 80042f2 <_vfiprintf_r+0x32> - 80042ec: 6da8 ldr r0, [r5, #88] ; 0x58 - 80042ee: f7ff fead bl 800404c <__retarget_lock_acquire_recursive> - 80042f2: 89ab ldrh r3, [r5, #12] - 80042f4: 071b lsls r3, r3, #28 - 80042f6: d501 bpl.n 80042fc <_vfiprintf_r+0x3c> - 80042f8: 692b ldr r3, [r5, #16] - 80042fa: b9eb cbnz r3, 8004338 <_vfiprintf_r+0x78> - 80042fc: 4629 mov r1, r5 - 80042fe: 4630 mov r0, r6 - 8004300: f7ff fc7e bl 8003c00 <__swsetup_r> - 8004304: b1c0 cbz r0, 8004338 <_vfiprintf_r+0x78> - 8004306: 6e6b ldr r3, [r5, #100] ; 0x64 - 8004308: 07dc lsls r4, r3, #31 - 800430a: d50e bpl.n 800432a <_vfiprintf_r+0x6a> - 800430c: f04f 30ff mov.w r0, #4294967295 - 8004310: b01d add sp, #116 ; 0x74 - 8004312: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} - 8004316: 4b7b ldr r3, [pc, #492] ; (8004504 <_vfiprintf_r+0x244>) - 8004318: 429d cmp r5, r3 - 800431a: d101 bne.n 8004320 <_vfiprintf_r+0x60> - 800431c: 68b5 ldr r5, [r6, #8] - 800431e: e7df b.n 80042e0 <_vfiprintf_r+0x20> - 8004320: 4b79 ldr r3, [pc, #484] ; (8004508 <_vfiprintf_r+0x248>) - 8004322: 429d cmp r5, r3 - 8004324: bf08 it eq - 8004326: 68f5 ldreq r5, [r6, #12] - 8004328: e7da b.n 80042e0 <_vfiprintf_r+0x20> - 800432a: 89ab ldrh r3, [r5, #12] - 800432c: 0598 lsls r0, r3, #22 - 800432e: d4ed bmi.n 800430c <_vfiprintf_r+0x4c> - 8004330: 6da8 ldr r0, [r5, #88] ; 0x58 - 8004332: f7ff fe8c bl 800404e <__retarget_lock_release_recursive> - 8004336: e7e9 b.n 800430c <_vfiprintf_r+0x4c> - 8004338: 2300 movs r3, #0 - 800433a: 9309 str r3, [sp, #36] ; 0x24 - 800433c: 2320 movs r3, #32 - 800433e: f88d 3029 strb.w r3, [sp, #41] ; 0x29 - 8004342: f8cd 800c str.w r8, [sp, #12] - 8004346: 2330 movs r3, #48 ; 0x30 - 8004348: f8df 81c0 ldr.w r8, [pc, #448] ; 800450c <_vfiprintf_r+0x24c> - 800434c: f88d 302a strb.w r3, [sp, #42] ; 0x2a - 8004350: f04f 0901 mov.w r9, #1 - 8004354: 4623 mov r3, r4 - 8004356: 469a mov sl, r3 - 8004358: f813 2b01 ldrb.w r2, [r3], #1 - 800435c: b10a cbz r2, 8004362 <_vfiprintf_r+0xa2> - 800435e: 2a25 cmp r2, #37 ; 0x25 - 8004360: d1f9 bne.n 8004356 <_vfiprintf_r+0x96> - 8004362: ebba 0b04 subs.w fp, sl, r4 - 8004366: d00b beq.n 8004380 <_vfiprintf_r+0xc0> - 8004368: 465b mov r3, fp - 800436a: 4622 mov r2, r4 - 800436c: 4629 mov r1, r5 - 800436e: 4630 mov r0, r6 - 8004370: f7ff ff93 bl 800429a <__sfputs_r> - 8004374: 3001 adds r0, #1 - 8004376: f000 80aa beq.w 80044ce <_vfiprintf_r+0x20e> - 800437a: 9a09 ldr r2, [sp, #36] ; 0x24 - 800437c: 445a add r2, fp - 800437e: 9209 str r2, [sp, #36] ; 0x24 - 8004380: f89a 3000 ldrb.w r3, [sl] - 8004384: 2b00 cmp r3, #0 - 8004386: f000 80a2 beq.w 80044ce <_vfiprintf_r+0x20e> - 800438a: 2300 movs r3, #0 - 800438c: f04f 32ff mov.w r2, #4294967295 - 8004390: e9cd 2305 strd r2, r3, [sp, #20] - 8004394: f10a 0a01 add.w sl, sl, #1 - 8004398: 9304 str r3, [sp, #16] - 800439a: 9307 str r3, [sp, #28] - 800439c: f88d 3053 strb.w r3, [sp, #83] ; 0x53 - 80043a0: 931a str r3, [sp, #104] ; 0x68 - 80043a2: 4654 mov r4, sl - 80043a4: 2205 movs r2, #5 - 80043a6: f814 1b01 ldrb.w r1, [r4], #1 - 80043aa: 4858 ldr r0, [pc, #352] ; (800450c <_vfiprintf_r+0x24c>) - 80043ac: f7fb ff48 bl 8000240 - 80043b0: 9a04 ldr r2, [sp, #16] - 80043b2: b9d8 cbnz r0, 80043ec <_vfiprintf_r+0x12c> - 80043b4: 06d1 lsls r1, r2, #27 - 80043b6: bf44 itt mi - 80043b8: 2320 movmi r3, #32 - 80043ba: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 - 80043be: 0713 lsls r3, r2, #28 - 80043c0: bf44 itt mi - 80043c2: 232b movmi r3, #43 ; 0x2b - 80043c4: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 - 80043c8: f89a 3000 ldrb.w r3, [sl] - 80043cc: 2b2a cmp r3, #42 ; 0x2a - 80043ce: d015 beq.n 80043fc <_vfiprintf_r+0x13c> - 80043d0: 9a07 ldr r2, [sp, #28] - 80043d2: 4654 mov r4, sl - 80043d4: 2000 movs r0, #0 - 80043d6: f04f 0c0a mov.w ip, #10 - 80043da: 4621 mov r1, r4 - 80043dc: f811 3b01 ldrb.w r3, [r1], #1 - 80043e0: 3b30 subs r3, #48 ; 0x30 - 80043e2: 2b09 cmp r3, #9 - 80043e4: d94e bls.n 8004484 <_vfiprintf_r+0x1c4> - 80043e6: b1b0 cbz r0, 8004416 <_vfiprintf_r+0x156> - 80043e8: 9207 str r2, [sp, #28] - 80043ea: e014 b.n 8004416 <_vfiprintf_r+0x156> - 80043ec: eba0 0308 sub.w r3, r0, r8 - 80043f0: fa09 f303 lsl.w r3, r9, r3 - 80043f4: 4313 orrs r3, r2 - 80043f6: 9304 str r3, [sp, #16] - 80043f8: 46a2 mov sl, r4 - 80043fa: e7d2 b.n 80043a2 <_vfiprintf_r+0xe2> - 80043fc: 9b03 ldr r3, [sp, #12] - 80043fe: 1d19 adds r1, r3, #4 - 8004400: 681b ldr r3, [r3, #0] - 8004402: 9103 str r1, [sp, #12] - 8004404: 2b00 cmp r3, #0 - 8004406: bfbb ittet lt - 8004408: 425b neglt r3, r3 - 800440a: f042 0202 orrlt.w r2, r2, #2 - 800440e: 9307 strge r3, [sp, #28] - 8004410: 9307 strlt r3, [sp, #28] - 8004412: bfb8 it lt - 8004414: 9204 strlt r2, [sp, #16] - 8004416: 7823 ldrb r3, [r4, #0] - 8004418: 2b2e cmp r3, #46 ; 0x2e - 800441a: d10c bne.n 8004436 <_vfiprintf_r+0x176> - 800441c: 7863 ldrb r3, [r4, #1] - 800441e: 2b2a cmp r3, #42 ; 0x2a - 8004420: d135 bne.n 800448e <_vfiprintf_r+0x1ce> - 8004422: 9b03 ldr r3, [sp, #12] - 8004424: 1d1a adds r2, r3, #4 - 8004426: 681b ldr r3, [r3, #0] - 8004428: 9203 str r2, [sp, #12] - 800442a: 2b00 cmp r3, #0 - 800442c: bfb8 it lt - 800442e: f04f 33ff movlt.w r3, #4294967295 - 8004432: 3402 adds r4, #2 - 8004434: 9305 str r3, [sp, #20] - 8004436: f8df a0e4 ldr.w sl, [pc, #228] ; 800451c <_vfiprintf_r+0x25c> - 800443a: 7821 ldrb r1, [r4, #0] - 800443c: 2203 movs r2, #3 - 800443e: 4650 mov r0, sl - 8004440: f7fb fefe bl 8000240 - 8004444: b140 cbz r0, 8004458 <_vfiprintf_r+0x198> - 8004446: 2340 movs r3, #64 ; 0x40 - 8004448: eba0 000a sub.w r0, r0, sl - 800444c: fa03 f000 lsl.w r0, r3, r0 - 8004450: 9b04 ldr r3, [sp, #16] - 8004452: 4303 orrs r3, r0 - 8004454: 3401 adds r4, #1 - 8004456: 9304 str r3, [sp, #16] - 8004458: f814 1b01 ldrb.w r1, [r4], #1 - 800445c: 482c ldr r0, [pc, #176] ; (8004510 <_vfiprintf_r+0x250>) - 800445e: f88d 1028 strb.w r1, [sp, #40] ; 0x28 - 8004462: 2206 movs r2, #6 - 8004464: f7fb feec bl 8000240 - 8004468: 2800 cmp r0, #0 - 800446a: d03f beq.n 80044ec <_vfiprintf_r+0x22c> - 800446c: 4b29 ldr r3, [pc, #164] ; (8004514 <_vfiprintf_r+0x254>) - 800446e: bb1b cbnz r3, 80044b8 <_vfiprintf_r+0x1f8> - 8004470: 9b03 ldr r3, [sp, #12] - 8004472: 3307 adds r3, #7 - 8004474: f023 0307 bic.w r3, r3, #7 - 8004478: 3308 adds r3, #8 - 800447a: 9303 str r3, [sp, #12] - 800447c: 9b09 ldr r3, [sp, #36] ; 0x24 - 800447e: 443b add r3, r7 - 8004480: 9309 str r3, [sp, #36] ; 0x24 - 8004482: e767 b.n 8004354 <_vfiprintf_r+0x94> - 8004484: fb0c 3202 mla r2, ip, r2, r3 - 8004488: 460c mov r4, r1 - 800448a: 2001 movs r0, #1 - 800448c: e7a5 b.n 80043da <_vfiprintf_r+0x11a> - 800448e: 2300 movs r3, #0 - 8004490: 3401 adds r4, #1 - 8004492: 9305 str r3, [sp, #20] - 8004494: 4619 mov r1, r3 - 8004496: f04f 0c0a mov.w ip, #10 - 800449a: 4620 mov r0, r4 - 800449c: f810 2b01 ldrb.w r2, [r0], #1 - 80044a0: 3a30 subs r2, #48 ; 0x30 - 80044a2: 2a09 cmp r2, #9 - 80044a4: d903 bls.n 80044ae <_vfiprintf_r+0x1ee> - 80044a6: 2b00 cmp r3, #0 - 80044a8: d0c5 beq.n 8004436 <_vfiprintf_r+0x176> - 80044aa: 9105 str r1, [sp, #20] - 80044ac: e7c3 b.n 8004436 <_vfiprintf_r+0x176> - 80044ae: fb0c 2101 mla r1, ip, r1, r2 - 80044b2: 4604 mov r4, r0 - 80044b4: 2301 movs r3, #1 - 80044b6: e7f0 b.n 800449a <_vfiprintf_r+0x1da> - 80044b8: ab03 add r3, sp, #12 - 80044ba: 9300 str r3, [sp, #0] - 80044bc: 462a mov r2, r5 - 80044be: 4b16 ldr r3, [pc, #88] ; (8004518 <_vfiprintf_r+0x258>) - 80044c0: a904 add r1, sp, #16 - 80044c2: 4630 mov r0, r6 - 80044c4: f3af 8000 nop.w - 80044c8: 4607 mov r7, r0 - 80044ca: 1c78 adds r0, r7, #1 - 80044cc: d1d6 bne.n 800447c <_vfiprintf_r+0x1bc> - 80044ce: 6e6b ldr r3, [r5, #100] ; 0x64 - 80044d0: 07d9 lsls r1, r3, #31 - 80044d2: d405 bmi.n 80044e0 <_vfiprintf_r+0x220> - 80044d4: 89ab ldrh r3, [r5, #12] - 80044d6: 059a lsls r2, r3, #22 - 80044d8: d402 bmi.n 80044e0 <_vfiprintf_r+0x220> - 80044da: 6da8 ldr r0, [r5, #88] ; 0x58 - 80044dc: f7ff fdb7 bl 800404e <__retarget_lock_release_recursive> - 80044e0: 89ab ldrh r3, [r5, #12] - 80044e2: 065b lsls r3, r3, #25 - 80044e4: f53f af12 bmi.w 800430c <_vfiprintf_r+0x4c> - 80044e8: 9809 ldr r0, [sp, #36] ; 0x24 - 80044ea: e711 b.n 8004310 <_vfiprintf_r+0x50> - 80044ec: ab03 add r3, sp, #12 - 80044ee: 9300 str r3, [sp, #0] - 80044f0: 462a mov r2, r5 - 80044f2: 4b09 ldr r3, [pc, #36] ; (8004518 <_vfiprintf_r+0x258>) - 80044f4: a904 add r1, sp, #16 - 80044f6: 4630 mov r0, r6 - 80044f8: f000 f880 bl 80045fc <_printf_i> - 80044fc: e7e4 b.n 80044c8 <_vfiprintf_r+0x208> - 80044fe: bf00 nop - 8004500: 08004c38 .word 0x08004c38 - 8004504: 08004c58 .word 0x08004c58 - 8004508: 08004c18 .word 0x08004c18 - 800450c: 08004c78 .word 0x08004c78 - 8004510: 08004c82 .word 0x08004c82 - 8004514: 00000000 .word 0x00000000 - 8004518: 0800429b .word 0x0800429b - 800451c: 08004c7e .word 0x08004c7e - -08004520 <_printf_common>: - 8004520: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} - 8004524: 4616 mov r6, r2 - 8004526: 4699 mov r9, r3 - 8004528: 688a ldr r2, [r1, #8] - 800452a: 690b ldr r3, [r1, #16] - 800452c: f8dd 8020 ldr.w r8, [sp, #32] - 8004530: 4293 cmp r3, r2 - 8004532: bfb8 it lt - 8004534: 4613 movlt r3, r2 - 8004536: 6033 str r3, [r6, #0] - 8004538: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 - 800453c: 4607 mov r7, r0 - 800453e: 460c mov r4, r1 - 8004540: b10a cbz r2, 8004546 <_printf_common+0x26> - 8004542: 3301 adds r3, #1 - 8004544: 6033 str r3, [r6, #0] - 8004546: 6823 ldr r3, [r4, #0] - 8004548: 0699 lsls r1, r3, #26 - 800454a: bf42 ittt mi - 800454c: 6833 ldrmi r3, [r6, #0] - 800454e: 3302 addmi r3, #2 - 8004550: 6033 strmi r3, [r6, #0] - 8004552: 6825 ldr r5, [r4, #0] - 8004554: f015 0506 ands.w r5, r5, #6 - 8004558: d106 bne.n 8004568 <_printf_common+0x48> - 800455a: f104 0a19 add.w sl, r4, #25 - 800455e: 68e3 ldr r3, [r4, #12] - 8004560: 6832 ldr r2, [r6, #0] - 8004562: 1a9b subs r3, r3, r2 - 8004564: 42ab cmp r3, r5 - 8004566: dc26 bgt.n 80045b6 <_printf_common+0x96> - 8004568: f894 2043 ldrb.w r2, [r4, #67] ; 0x43 - 800456c: 1e13 subs r3, r2, #0 - 800456e: 6822 ldr r2, [r4, #0] - 8004570: bf18 it ne - 8004572: 2301 movne r3, #1 - 8004574: 0692 lsls r2, r2, #26 - 8004576: d42b bmi.n 80045d0 <_printf_common+0xb0> - 8004578: f104 0243 add.w r2, r4, #67 ; 0x43 - 800457c: 4649 mov r1, r9 - 800457e: 4638 mov r0, r7 - 8004580: 47c0 blx r8 - 8004582: 3001 adds r0, #1 - 8004584: d01e beq.n 80045c4 <_printf_common+0xa4> - 8004586: 6823 ldr r3, [r4, #0] - 8004588: 68e5 ldr r5, [r4, #12] - 800458a: 6832 ldr r2, [r6, #0] - 800458c: f003 0306 and.w r3, r3, #6 - 8004590: 2b04 cmp r3, #4 - 8004592: bf08 it eq - 8004594: 1aad subeq r5, r5, r2 - 8004596: 68a3 ldr r3, [r4, #8] - 8004598: 6922 ldr r2, [r4, #16] - 800459a: bf0c ite eq - 800459c: ea25 75e5 biceq.w r5, r5, r5, asr #31 - 80045a0: 2500 movne r5, #0 - 80045a2: 4293 cmp r3, r2 - 80045a4: bfc4 itt gt - 80045a6: 1a9b subgt r3, r3, r2 - 80045a8: 18ed addgt r5, r5, r3 - 80045aa: 2600 movs r6, #0 - 80045ac: 341a adds r4, #26 - 80045ae: 42b5 cmp r5, r6 - 80045b0: d11a bne.n 80045e8 <_printf_common+0xc8> - 80045b2: 2000 movs r0, #0 - 80045b4: e008 b.n 80045c8 <_printf_common+0xa8> - 80045b6: 2301 movs r3, #1 - 80045b8: 4652 mov r2, sl - 80045ba: 4649 mov r1, r9 - 80045bc: 4638 mov r0, r7 - 80045be: 47c0 blx r8 - 80045c0: 3001 adds r0, #1 - 80045c2: d103 bne.n 80045cc <_printf_common+0xac> - 80045c4: f04f 30ff mov.w r0, #4294967295 - 80045c8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 80045cc: 3501 adds r5, #1 - 80045ce: e7c6 b.n 800455e <_printf_common+0x3e> - 80045d0: 18e1 adds r1, r4, r3 - 80045d2: 1c5a adds r2, r3, #1 - 80045d4: 2030 movs r0, #48 ; 0x30 - 80045d6: f881 0043 strb.w r0, [r1, #67] ; 0x43 - 80045da: 4422 add r2, r4 - 80045dc: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 - 80045e0: f882 1043 strb.w r1, [r2, #67] ; 0x43 - 80045e4: 3302 adds r3, #2 - 80045e6: e7c7 b.n 8004578 <_printf_common+0x58> - 80045e8: 2301 movs r3, #1 - 80045ea: 4622 mov r2, r4 - 80045ec: 4649 mov r1, r9 - 80045ee: 4638 mov r0, r7 - 80045f0: 47c0 blx r8 - 80045f2: 3001 adds r0, #1 - 80045f4: d0e6 beq.n 80045c4 <_printf_common+0xa4> - 80045f6: 3601 adds r6, #1 - 80045f8: e7d9 b.n 80045ae <_printf_common+0x8e> +08004f6c <_vfiprintf_r>: + 8004f6c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8004f70: 460d mov r5, r1 + 8004f72: b09d sub sp, #116 ; 0x74 + 8004f74: 4614 mov r4, r2 + 8004f76: 4698 mov r8, r3 + 8004f78: 4606 mov r6, r0 + 8004f7a: b118 cbz r0, 8004f84 <_vfiprintf_r+0x18> + 8004f7c: 6983 ldr r3, [r0, #24] + 8004f7e: b90b cbnz r3, 8004f84 <_vfiprintf_r+0x18> + 8004f80: f7ff fe1c bl 8004bbc <__sinit> + 8004f84: 4b89 ldr r3, [pc, #548] ; (80051ac <_vfiprintf_r+0x240>) + 8004f86: 429d cmp r5, r3 + 8004f88: d11b bne.n 8004fc2 <_vfiprintf_r+0x56> + 8004f8a: 6875 ldr r5, [r6, #4] + 8004f8c: 6e6b ldr r3, [r5, #100] ; 0x64 + 8004f8e: 07d9 lsls r1, r3, #31 + 8004f90: d405 bmi.n 8004f9e <_vfiprintf_r+0x32> + 8004f92: 89ab ldrh r3, [r5, #12] + 8004f94: 059a lsls r2, r3, #22 + 8004f96: d402 bmi.n 8004f9e <_vfiprintf_r+0x32> + 8004f98: 6da8 ldr r0, [r5, #88] ; 0x58 + 8004f9a: f7ff fead bl 8004cf8 <__retarget_lock_acquire_recursive> + 8004f9e: 89ab ldrh r3, [r5, #12] + 8004fa0: 071b lsls r3, r3, #28 + 8004fa2: d501 bpl.n 8004fa8 <_vfiprintf_r+0x3c> + 8004fa4: 692b ldr r3, [r5, #16] + 8004fa6: b9eb cbnz r3, 8004fe4 <_vfiprintf_r+0x78> + 8004fa8: 4629 mov r1, r5 + 8004faa: 4630 mov r0, r6 + 8004fac: f7ff fc7e bl 80048ac <__swsetup_r> + 8004fb0: b1c0 cbz r0, 8004fe4 <_vfiprintf_r+0x78> + 8004fb2: 6e6b ldr r3, [r5, #100] ; 0x64 + 8004fb4: 07dc lsls r4, r3, #31 + 8004fb6: d50e bpl.n 8004fd6 <_vfiprintf_r+0x6a> + 8004fb8: f04f 30ff mov.w r0, #4294967295 + 8004fbc: b01d add sp, #116 ; 0x74 + 8004fbe: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8004fc2: 4b7b ldr r3, [pc, #492] ; (80051b0 <_vfiprintf_r+0x244>) + 8004fc4: 429d cmp r5, r3 + 8004fc6: d101 bne.n 8004fcc <_vfiprintf_r+0x60> + 8004fc8: 68b5 ldr r5, [r6, #8] + 8004fca: e7df b.n 8004f8c <_vfiprintf_r+0x20> + 8004fcc: 4b79 ldr r3, [pc, #484] ; (80051b4 <_vfiprintf_r+0x248>) + 8004fce: 429d cmp r5, r3 + 8004fd0: bf08 it eq + 8004fd2: 68f5 ldreq r5, [r6, #12] + 8004fd4: e7da b.n 8004f8c <_vfiprintf_r+0x20> + 8004fd6: 89ab ldrh r3, [r5, #12] + 8004fd8: 0598 lsls r0, r3, #22 + 8004fda: d4ed bmi.n 8004fb8 <_vfiprintf_r+0x4c> + 8004fdc: 6da8 ldr r0, [r5, #88] ; 0x58 + 8004fde: f7ff fe8c bl 8004cfa <__retarget_lock_release_recursive> + 8004fe2: e7e9 b.n 8004fb8 <_vfiprintf_r+0x4c> + 8004fe4: 2300 movs r3, #0 + 8004fe6: 9309 str r3, [sp, #36] ; 0x24 + 8004fe8: 2320 movs r3, #32 + 8004fea: f88d 3029 strb.w r3, [sp, #41] ; 0x29 + 8004fee: f8cd 800c str.w r8, [sp, #12] + 8004ff2: 2330 movs r3, #48 ; 0x30 + 8004ff4: f8df 81c0 ldr.w r8, [pc, #448] ; 80051b8 <_vfiprintf_r+0x24c> + 8004ff8: f88d 302a strb.w r3, [sp, #42] ; 0x2a + 8004ffc: f04f 0901 mov.w r9, #1 + 8005000: 4623 mov r3, r4 + 8005002: 469a mov sl, r3 + 8005004: f813 2b01 ldrb.w r2, [r3], #1 + 8005008: b10a cbz r2, 800500e <_vfiprintf_r+0xa2> + 800500a: 2a25 cmp r2, #37 ; 0x25 + 800500c: d1f9 bne.n 8005002 <_vfiprintf_r+0x96> + 800500e: ebba 0b04 subs.w fp, sl, r4 + 8005012: d00b beq.n 800502c <_vfiprintf_r+0xc0> + 8005014: 465b mov r3, fp + 8005016: 4622 mov r2, r4 + 8005018: 4629 mov r1, r5 + 800501a: 4630 mov r0, r6 + 800501c: f7ff ff93 bl 8004f46 <__sfputs_r> + 8005020: 3001 adds r0, #1 + 8005022: f000 80aa beq.w 800517a <_vfiprintf_r+0x20e> + 8005026: 9a09 ldr r2, [sp, #36] ; 0x24 + 8005028: 445a add r2, fp + 800502a: 9209 str r2, [sp, #36] ; 0x24 + 800502c: f89a 3000 ldrb.w r3, [sl] + 8005030: 2b00 cmp r3, #0 + 8005032: f000 80a2 beq.w 800517a <_vfiprintf_r+0x20e> + 8005036: 2300 movs r3, #0 + 8005038: f04f 32ff mov.w r2, #4294967295 + 800503c: e9cd 2305 strd r2, r3, [sp, #20] + 8005040: f10a 0a01 add.w sl, sl, #1 + 8005044: 9304 str r3, [sp, #16] + 8005046: 9307 str r3, [sp, #28] + 8005048: f88d 3053 strb.w r3, [sp, #83] ; 0x53 + 800504c: 931a str r3, [sp, #104] ; 0x68 + 800504e: 4654 mov r4, sl + 8005050: 2205 movs r2, #5 + 8005052: f814 1b01 ldrb.w r1, [r4], #1 + 8005056: 4858 ldr r0, [pc, #352] ; (80051b8 <_vfiprintf_r+0x24c>) + 8005058: f7fb f8f2 bl 8000240 + 800505c: 9a04 ldr r2, [sp, #16] + 800505e: b9d8 cbnz r0, 8005098 <_vfiprintf_r+0x12c> + 8005060: 06d1 lsls r1, r2, #27 + 8005062: bf44 itt mi + 8005064: 2320 movmi r3, #32 + 8005066: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 + 800506a: 0713 lsls r3, r2, #28 + 800506c: bf44 itt mi + 800506e: 232b movmi r3, #43 ; 0x2b + 8005070: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 + 8005074: f89a 3000 ldrb.w r3, [sl] + 8005078: 2b2a cmp r3, #42 ; 0x2a + 800507a: d015 beq.n 80050a8 <_vfiprintf_r+0x13c> + 800507c: 9a07 ldr r2, [sp, #28] + 800507e: 4654 mov r4, sl + 8005080: 2000 movs r0, #0 + 8005082: f04f 0c0a mov.w ip, #10 + 8005086: 4621 mov r1, r4 + 8005088: f811 3b01 ldrb.w r3, [r1], #1 + 800508c: 3b30 subs r3, #48 ; 0x30 + 800508e: 2b09 cmp r3, #9 + 8005090: d94e bls.n 8005130 <_vfiprintf_r+0x1c4> + 8005092: b1b0 cbz r0, 80050c2 <_vfiprintf_r+0x156> + 8005094: 9207 str r2, [sp, #28] + 8005096: e014 b.n 80050c2 <_vfiprintf_r+0x156> + 8005098: eba0 0308 sub.w r3, r0, r8 + 800509c: fa09 f303 lsl.w r3, r9, r3 + 80050a0: 4313 orrs r3, r2 + 80050a2: 9304 str r3, [sp, #16] + 80050a4: 46a2 mov sl, r4 + 80050a6: e7d2 b.n 800504e <_vfiprintf_r+0xe2> + 80050a8: 9b03 ldr r3, [sp, #12] + 80050aa: 1d19 adds r1, r3, #4 + 80050ac: 681b ldr r3, [r3, #0] + 80050ae: 9103 str r1, [sp, #12] + 80050b0: 2b00 cmp r3, #0 + 80050b2: bfbb ittet lt + 80050b4: 425b neglt r3, r3 + 80050b6: f042 0202 orrlt.w r2, r2, #2 + 80050ba: 9307 strge r3, [sp, #28] + 80050bc: 9307 strlt r3, [sp, #28] + 80050be: bfb8 it lt + 80050c0: 9204 strlt r2, [sp, #16] + 80050c2: 7823 ldrb r3, [r4, #0] + 80050c4: 2b2e cmp r3, #46 ; 0x2e + 80050c6: d10c bne.n 80050e2 <_vfiprintf_r+0x176> + 80050c8: 7863 ldrb r3, [r4, #1] + 80050ca: 2b2a cmp r3, #42 ; 0x2a + 80050cc: d135 bne.n 800513a <_vfiprintf_r+0x1ce> + 80050ce: 9b03 ldr r3, [sp, #12] + 80050d0: 1d1a adds r2, r3, #4 + 80050d2: 681b ldr r3, [r3, #0] + 80050d4: 9203 str r2, [sp, #12] + 80050d6: 2b00 cmp r3, #0 + 80050d8: bfb8 it lt + 80050da: f04f 33ff movlt.w r3, #4294967295 + 80050de: 3402 adds r4, #2 + 80050e0: 9305 str r3, [sp, #20] + 80050e2: f8df a0e4 ldr.w sl, [pc, #228] ; 80051c8 <_vfiprintf_r+0x25c> + 80050e6: 7821 ldrb r1, [r4, #0] + 80050e8: 2203 movs r2, #3 + 80050ea: 4650 mov r0, sl + 80050ec: f7fb f8a8 bl 8000240 + 80050f0: b140 cbz r0, 8005104 <_vfiprintf_r+0x198> + 80050f2: 2340 movs r3, #64 ; 0x40 + 80050f4: eba0 000a sub.w r0, r0, sl + 80050f8: fa03 f000 lsl.w r0, r3, r0 + 80050fc: 9b04 ldr r3, [sp, #16] + 80050fe: 4303 orrs r3, r0 + 8005100: 3401 adds r4, #1 + 8005102: 9304 str r3, [sp, #16] + 8005104: f814 1b01 ldrb.w r1, [r4], #1 + 8005108: 482c ldr r0, [pc, #176] ; (80051bc <_vfiprintf_r+0x250>) + 800510a: f88d 1028 strb.w r1, [sp, #40] ; 0x28 + 800510e: 2206 movs r2, #6 + 8005110: f7fb f896 bl 8000240 + 8005114: 2800 cmp r0, #0 + 8005116: d03f beq.n 8005198 <_vfiprintf_r+0x22c> + 8005118: 4b29 ldr r3, [pc, #164] ; (80051c0 <_vfiprintf_r+0x254>) + 800511a: bb1b cbnz r3, 8005164 <_vfiprintf_r+0x1f8> + 800511c: 9b03 ldr r3, [sp, #12] + 800511e: 3307 adds r3, #7 + 8005120: f023 0307 bic.w r3, r3, #7 + 8005124: 3308 adds r3, #8 + 8005126: 9303 str r3, [sp, #12] + 8005128: 9b09 ldr r3, [sp, #36] ; 0x24 + 800512a: 443b add r3, r7 + 800512c: 9309 str r3, [sp, #36] ; 0x24 + 800512e: e767 b.n 8005000 <_vfiprintf_r+0x94> + 8005130: fb0c 3202 mla r2, ip, r2, r3 + 8005134: 460c mov r4, r1 + 8005136: 2001 movs r0, #1 + 8005138: e7a5 b.n 8005086 <_vfiprintf_r+0x11a> + 800513a: 2300 movs r3, #0 + 800513c: 3401 adds r4, #1 + 800513e: 9305 str r3, [sp, #20] + 8005140: 4619 mov r1, r3 + 8005142: f04f 0c0a mov.w ip, #10 + 8005146: 4620 mov r0, r4 + 8005148: f810 2b01 ldrb.w r2, [r0], #1 + 800514c: 3a30 subs r2, #48 ; 0x30 + 800514e: 2a09 cmp r2, #9 + 8005150: d903 bls.n 800515a <_vfiprintf_r+0x1ee> + 8005152: 2b00 cmp r3, #0 + 8005154: d0c5 beq.n 80050e2 <_vfiprintf_r+0x176> + 8005156: 9105 str r1, [sp, #20] + 8005158: e7c3 b.n 80050e2 <_vfiprintf_r+0x176> + 800515a: fb0c 2101 mla r1, ip, r1, r2 + 800515e: 4604 mov r4, r0 + 8005160: 2301 movs r3, #1 + 8005162: e7f0 b.n 8005146 <_vfiprintf_r+0x1da> + 8005164: ab03 add r3, sp, #12 + 8005166: 9300 str r3, [sp, #0] + 8005168: 462a mov r2, r5 + 800516a: 4b16 ldr r3, [pc, #88] ; (80051c4 <_vfiprintf_r+0x258>) + 800516c: a904 add r1, sp, #16 + 800516e: 4630 mov r0, r6 + 8005170: f3af 8000 nop.w + 8005174: 4607 mov r7, r0 + 8005176: 1c78 adds r0, r7, #1 + 8005178: d1d6 bne.n 8005128 <_vfiprintf_r+0x1bc> + 800517a: 6e6b ldr r3, [r5, #100] ; 0x64 + 800517c: 07d9 lsls r1, r3, #31 + 800517e: d405 bmi.n 800518c <_vfiprintf_r+0x220> + 8005180: 89ab ldrh r3, [r5, #12] + 8005182: 059a lsls r2, r3, #22 + 8005184: d402 bmi.n 800518c <_vfiprintf_r+0x220> + 8005186: 6da8 ldr r0, [r5, #88] ; 0x58 + 8005188: f7ff fdb7 bl 8004cfa <__retarget_lock_release_recursive> + 800518c: 89ab ldrh r3, [r5, #12] + 800518e: 065b lsls r3, r3, #25 + 8005190: f53f af12 bmi.w 8004fb8 <_vfiprintf_r+0x4c> + 8005194: 9809 ldr r0, [sp, #36] ; 0x24 + 8005196: e711 b.n 8004fbc <_vfiprintf_r+0x50> + 8005198: ab03 add r3, sp, #12 + 800519a: 9300 str r3, [sp, #0] + 800519c: 462a mov r2, r5 + 800519e: 4b09 ldr r3, [pc, #36] ; (80051c4 <_vfiprintf_r+0x258>) + 80051a0: a904 add r1, sp, #16 + 80051a2: 4630 mov r0, r6 + 80051a4: f000 f880 bl 80052a8 <_printf_i> + 80051a8: e7e4 b.n 8005174 <_vfiprintf_r+0x208> + 80051aa: bf00 nop + 80051ac: 08005b40 .word 0x08005b40 + 80051b0: 08005b60 .word 0x08005b60 + 80051b4: 08005b20 .word 0x08005b20 + 80051b8: 08005b80 .word 0x08005b80 + 80051bc: 08005b8a .word 0x08005b8a + 80051c0: 00000000 .word 0x00000000 + 80051c4: 08004f47 .word 0x08004f47 + 80051c8: 08005b86 .word 0x08005b86 + +080051cc <_printf_common>: + 80051cc: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 80051d0: 4616 mov r6, r2 + 80051d2: 4699 mov r9, r3 + 80051d4: 688a ldr r2, [r1, #8] + 80051d6: 690b ldr r3, [r1, #16] + 80051d8: f8dd 8020 ldr.w r8, [sp, #32] + 80051dc: 4293 cmp r3, r2 + 80051de: bfb8 it lt + 80051e0: 4613 movlt r3, r2 + 80051e2: 6033 str r3, [r6, #0] + 80051e4: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 + 80051e8: 4607 mov r7, r0 + 80051ea: 460c mov r4, r1 + 80051ec: b10a cbz r2, 80051f2 <_printf_common+0x26> + 80051ee: 3301 adds r3, #1 + 80051f0: 6033 str r3, [r6, #0] + 80051f2: 6823 ldr r3, [r4, #0] + 80051f4: 0699 lsls r1, r3, #26 + 80051f6: bf42 ittt mi + 80051f8: 6833 ldrmi r3, [r6, #0] + 80051fa: 3302 addmi r3, #2 + 80051fc: 6033 strmi r3, [r6, #0] + 80051fe: 6825 ldr r5, [r4, #0] + 8005200: f015 0506 ands.w r5, r5, #6 + 8005204: d106 bne.n 8005214 <_printf_common+0x48> + 8005206: f104 0a19 add.w sl, r4, #25 + 800520a: 68e3 ldr r3, [r4, #12] + 800520c: 6832 ldr r2, [r6, #0] + 800520e: 1a9b subs r3, r3, r2 + 8005210: 42ab cmp r3, r5 + 8005212: dc26 bgt.n 8005262 <_printf_common+0x96> + 8005214: f894 2043 ldrb.w r2, [r4, #67] ; 0x43 + 8005218: 1e13 subs r3, r2, #0 + 800521a: 6822 ldr r2, [r4, #0] + 800521c: bf18 it ne + 800521e: 2301 movne r3, #1 + 8005220: 0692 lsls r2, r2, #26 + 8005222: d42b bmi.n 800527c <_printf_common+0xb0> + 8005224: f104 0243 add.w r2, r4, #67 ; 0x43 + 8005228: 4649 mov r1, r9 + 800522a: 4638 mov r0, r7 + 800522c: 47c0 blx r8 + 800522e: 3001 adds r0, #1 + 8005230: d01e beq.n 8005270 <_printf_common+0xa4> + 8005232: 6823 ldr r3, [r4, #0] + 8005234: 68e5 ldr r5, [r4, #12] + 8005236: 6832 ldr r2, [r6, #0] + 8005238: f003 0306 and.w r3, r3, #6 + 800523c: 2b04 cmp r3, #4 + 800523e: bf08 it eq + 8005240: 1aad subeq r5, r5, r2 + 8005242: 68a3 ldr r3, [r4, #8] + 8005244: 6922 ldr r2, [r4, #16] + 8005246: bf0c ite eq + 8005248: ea25 75e5 biceq.w r5, r5, r5, asr #31 + 800524c: 2500 movne r5, #0 + 800524e: 4293 cmp r3, r2 + 8005250: bfc4 itt gt + 8005252: 1a9b subgt r3, r3, r2 + 8005254: 18ed addgt r5, r5, r3 + 8005256: 2600 movs r6, #0 + 8005258: 341a adds r4, #26 + 800525a: 42b5 cmp r5, r6 + 800525c: d11a bne.n 8005294 <_printf_common+0xc8> + 800525e: 2000 movs r0, #0 + 8005260: e008 b.n 8005274 <_printf_common+0xa8> + 8005262: 2301 movs r3, #1 + 8005264: 4652 mov r2, sl + 8005266: 4649 mov r1, r9 + 8005268: 4638 mov r0, r7 + 800526a: 47c0 blx r8 + 800526c: 3001 adds r0, #1 + 800526e: d103 bne.n 8005278 <_printf_common+0xac> + 8005270: f04f 30ff mov.w r0, #4294967295 + 8005274: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8005278: 3501 adds r5, #1 + 800527a: e7c6 b.n 800520a <_printf_common+0x3e> + 800527c: 18e1 adds r1, r4, r3 + 800527e: 1c5a adds r2, r3, #1 + 8005280: 2030 movs r0, #48 ; 0x30 + 8005282: f881 0043 strb.w r0, [r1, #67] ; 0x43 + 8005286: 4422 add r2, r4 + 8005288: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 + 800528c: f882 1043 strb.w r1, [r2, #67] ; 0x43 + 8005290: 3302 adds r3, #2 + 8005292: e7c7 b.n 8005224 <_printf_common+0x58> + 8005294: 2301 movs r3, #1 + 8005296: 4622 mov r2, r4 + 8005298: 4649 mov r1, r9 + 800529a: 4638 mov r0, r7 + 800529c: 47c0 blx r8 + 800529e: 3001 adds r0, #1 + 80052a0: d0e6 beq.n 8005270 <_printf_common+0xa4> + 80052a2: 3601 adds r6, #1 + 80052a4: e7d9 b.n 800525a <_printf_common+0x8e> ... -080045fc <_printf_i>: - 80045fc: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} - 8004600: 460c mov r4, r1 - 8004602: 4691 mov r9, r2 - 8004604: 7e27 ldrb r7, [r4, #24] - 8004606: 990c ldr r1, [sp, #48] ; 0x30 - 8004608: 2f78 cmp r7, #120 ; 0x78 - 800460a: 4680 mov r8, r0 - 800460c: 469a mov sl, r3 - 800460e: f104 0243 add.w r2, r4, #67 ; 0x43 - 8004612: d807 bhi.n 8004624 <_printf_i+0x28> - 8004614: 2f62 cmp r7, #98 ; 0x62 - 8004616: d80a bhi.n 800462e <_printf_i+0x32> - 8004618: 2f00 cmp r7, #0 - 800461a: f000 80d8 beq.w 80047ce <_printf_i+0x1d2> - 800461e: 2f58 cmp r7, #88 ; 0x58 - 8004620: f000 80a3 beq.w 800476a <_printf_i+0x16e> - 8004624: f104 0642 add.w r6, r4, #66 ; 0x42 - 8004628: f884 7042 strb.w r7, [r4, #66] ; 0x42 - 800462c: e03a b.n 80046a4 <_printf_i+0xa8> - 800462e: f1a7 0363 sub.w r3, r7, #99 ; 0x63 - 8004632: 2b15 cmp r3, #21 - 8004634: d8f6 bhi.n 8004624 <_printf_i+0x28> - 8004636: a001 add r0, pc, #4 ; (adr r0, 800463c <_printf_i+0x40>) - 8004638: f850 f023 ldr.w pc, [r0, r3, lsl #2] - 800463c: 08004695 .word 0x08004695 - 8004640: 080046a9 .word 0x080046a9 - 8004644: 08004625 .word 0x08004625 - 8004648: 08004625 .word 0x08004625 - 800464c: 08004625 .word 0x08004625 - 8004650: 08004625 .word 0x08004625 - 8004654: 080046a9 .word 0x080046a9 - 8004658: 08004625 .word 0x08004625 - 800465c: 08004625 .word 0x08004625 - 8004660: 08004625 .word 0x08004625 - 8004664: 08004625 .word 0x08004625 - 8004668: 080047b5 .word 0x080047b5 - 800466c: 080046d9 .word 0x080046d9 - 8004670: 08004797 .word 0x08004797 - 8004674: 08004625 .word 0x08004625 - 8004678: 08004625 .word 0x08004625 - 800467c: 080047d7 .word 0x080047d7 - 8004680: 08004625 .word 0x08004625 - 8004684: 080046d9 .word 0x080046d9 - 8004688: 08004625 .word 0x08004625 - 800468c: 08004625 .word 0x08004625 - 8004690: 0800479f .word 0x0800479f - 8004694: 680b ldr r3, [r1, #0] - 8004696: 1d1a adds r2, r3, #4 - 8004698: 681b ldr r3, [r3, #0] - 800469a: 600a str r2, [r1, #0] - 800469c: f104 0642 add.w r6, r4, #66 ; 0x42 - 80046a0: f884 3042 strb.w r3, [r4, #66] ; 0x42 - 80046a4: 2301 movs r3, #1 - 80046a6: e0a3 b.n 80047f0 <_printf_i+0x1f4> - 80046a8: 6825 ldr r5, [r4, #0] - 80046aa: 6808 ldr r0, [r1, #0] - 80046ac: 062e lsls r6, r5, #24 - 80046ae: f100 0304 add.w r3, r0, #4 - 80046b2: d50a bpl.n 80046ca <_printf_i+0xce> - 80046b4: 6805 ldr r5, [r0, #0] - 80046b6: 600b str r3, [r1, #0] - 80046b8: 2d00 cmp r5, #0 - 80046ba: da03 bge.n 80046c4 <_printf_i+0xc8> - 80046bc: 232d movs r3, #45 ; 0x2d - 80046be: 426d negs r5, r5 - 80046c0: f884 3043 strb.w r3, [r4, #67] ; 0x43 - 80046c4: 485e ldr r0, [pc, #376] ; (8004840 <_printf_i+0x244>) - 80046c6: 230a movs r3, #10 - 80046c8: e019 b.n 80046fe <_printf_i+0x102> - 80046ca: f015 0f40 tst.w r5, #64 ; 0x40 - 80046ce: 6805 ldr r5, [r0, #0] - 80046d0: 600b str r3, [r1, #0] - 80046d2: bf18 it ne - 80046d4: b22d sxthne r5, r5 - 80046d6: e7ef b.n 80046b8 <_printf_i+0xbc> - 80046d8: 680b ldr r3, [r1, #0] - 80046da: 6825 ldr r5, [r4, #0] - 80046dc: 1d18 adds r0, r3, #4 - 80046de: 6008 str r0, [r1, #0] - 80046e0: 0628 lsls r0, r5, #24 - 80046e2: d501 bpl.n 80046e8 <_printf_i+0xec> - 80046e4: 681d ldr r5, [r3, #0] - 80046e6: e002 b.n 80046ee <_printf_i+0xf2> - 80046e8: 0669 lsls r1, r5, #25 - 80046ea: d5fb bpl.n 80046e4 <_printf_i+0xe8> - 80046ec: 881d ldrh r5, [r3, #0] - 80046ee: 4854 ldr r0, [pc, #336] ; (8004840 <_printf_i+0x244>) - 80046f0: 2f6f cmp r7, #111 ; 0x6f - 80046f2: bf0c ite eq - 80046f4: 2308 moveq r3, #8 - 80046f6: 230a movne r3, #10 - 80046f8: 2100 movs r1, #0 - 80046fa: f884 1043 strb.w r1, [r4, #67] ; 0x43 - 80046fe: 6866 ldr r6, [r4, #4] - 8004700: 60a6 str r6, [r4, #8] - 8004702: 2e00 cmp r6, #0 - 8004704: bfa2 ittt ge - 8004706: 6821 ldrge r1, [r4, #0] - 8004708: f021 0104 bicge.w r1, r1, #4 - 800470c: 6021 strge r1, [r4, #0] - 800470e: b90d cbnz r5, 8004714 <_printf_i+0x118> - 8004710: 2e00 cmp r6, #0 - 8004712: d04d beq.n 80047b0 <_printf_i+0x1b4> - 8004714: 4616 mov r6, r2 - 8004716: fbb5 f1f3 udiv r1, r5, r3 - 800471a: fb03 5711 mls r7, r3, r1, r5 - 800471e: 5dc7 ldrb r7, [r0, r7] - 8004720: f806 7d01 strb.w r7, [r6, #-1]! - 8004724: 462f mov r7, r5 - 8004726: 42bb cmp r3, r7 - 8004728: 460d mov r5, r1 - 800472a: d9f4 bls.n 8004716 <_printf_i+0x11a> - 800472c: 2b08 cmp r3, #8 - 800472e: d10b bne.n 8004748 <_printf_i+0x14c> - 8004730: 6823 ldr r3, [r4, #0] - 8004732: 07df lsls r7, r3, #31 - 8004734: d508 bpl.n 8004748 <_printf_i+0x14c> - 8004736: 6923 ldr r3, [r4, #16] - 8004738: 6861 ldr r1, [r4, #4] - 800473a: 4299 cmp r1, r3 - 800473c: bfde ittt le - 800473e: 2330 movle r3, #48 ; 0x30 - 8004740: f806 3c01 strble.w r3, [r6, #-1] - 8004744: f106 36ff addle.w r6, r6, #4294967295 - 8004748: 1b92 subs r2, r2, r6 - 800474a: 6122 str r2, [r4, #16] - 800474c: f8cd a000 str.w sl, [sp] - 8004750: 464b mov r3, r9 - 8004752: aa03 add r2, sp, #12 - 8004754: 4621 mov r1, r4 - 8004756: 4640 mov r0, r8 - 8004758: f7ff fee2 bl 8004520 <_printf_common> - 800475c: 3001 adds r0, #1 - 800475e: d14c bne.n 80047fa <_printf_i+0x1fe> - 8004760: f04f 30ff mov.w r0, #4294967295 - 8004764: b004 add sp, #16 - 8004766: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 800476a: 4835 ldr r0, [pc, #212] ; (8004840 <_printf_i+0x244>) - 800476c: f884 7045 strb.w r7, [r4, #69] ; 0x45 - 8004770: 6823 ldr r3, [r4, #0] - 8004772: 680e ldr r6, [r1, #0] - 8004774: 061f lsls r7, r3, #24 - 8004776: f856 5b04 ldr.w r5, [r6], #4 - 800477a: 600e str r6, [r1, #0] - 800477c: d514 bpl.n 80047a8 <_printf_i+0x1ac> - 800477e: 07d9 lsls r1, r3, #31 - 8004780: bf44 itt mi - 8004782: f043 0320 orrmi.w r3, r3, #32 - 8004786: 6023 strmi r3, [r4, #0] - 8004788: b91d cbnz r5, 8004792 <_printf_i+0x196> - 800478a: 6823 ldr r3, [r4, #0] - 800478c: f023 0320 bic.w r3, r3, #32 - 8004790: 6023 str r3, [r4, #0] - 8004792: 2310 movs r3, #16 - 8004794: e7b0 b.n 80046f8 <_printf_i+0xfc> - 8004796: 6823 ldr r3, [r4, #0] - 8004798: f043 0320 orr.w r3, r3, #32 - 800479c: 6023 str r3, [r4, #0] - 800479e: 2378 movs r3, #120 ; 0x78 - 80047a0: 4828 ldr r0, [pc, #160] ; (8004844 <_printf_i+0x248>) - 80047a2: f884 3045 strb.w r3, [r4, #69] ; 0x45 - 80047a6: e7e3 b.n 8004770 <_printf_i+0x174> - 80047a8: 065e lsls r6, r3, #25 - 80047aa: bf48 it mi - 80047ac: b2ad uxthmi r5, r5 - 80047ae: e7e6 b.n 800477e <_printf_i+0x182> - 80047b0: 4616 mov r6, r2 - 80047b2: e7bb b.n 800472c <_printf_i+0x130> - 80047b4: 680b ldr r3, [r1, #0] - 80047b6: 6826 ldr r6, [r4, #0] - 80047b8: 6960 ldr r0, [r4, #20] - 80047ba: 1d1d adds r5, r3, #4 - 80047bc: 600d str r5, [r1, #0] - 80047be: 0635 lsls r5, r6, #24 - 80047c0: 681b ldr r3, [r3, #0] - 80047c2: d501 bpl.n 80047c8 <_printf_i+0x1cc> - 80047c4: 6018 str r0, [r3, #0] - 80047c6: e002 b.n 80047ce <_printf_i+0x1d2> - 80047c8: 0671 lsls r1, r6, #25 - 80047ca: d5fb bpl.n 80047c4 <_printf_i+0x1c8> - 80047cc: 8018 strh r0, [r3, #0] - 80047ce: 2300 movs r3, #0 - 80047d0: 6123 str r3, [r4, #16] - 80047d2: 4616 mov r6, r2 - 80047d4: e7ba b.n 800474c <_printf_i+0x150> - 80047d6: 680b ldr r3, [r1, #0] - 80047d8: 1d1a adds r2, r3, #4 - 80047da: 600a str r2, [r1, #0] - 80047dc: 681e ldr r6, [r3, #0] - 80047de: 6862 ldr r2, [r4, #4] - 80047e0: 2100 movs r1, #0 - 80047e2: 4630 mov r0, r6 - 80047e4: f7fb fd2c bl 8000240 - 80047e8: b108 cbz r0, 80047ee <_printf_i+0x1f2> - 80047ea: 1b80 subs r0, r0, r6 - 80047ec: 6060 str r0, [r4, #4] - 80047ee: 6863 ldr r3, [r4, #4] - 80047f0: 6123 str r3, [r4, #16] - 80047f2: 2300 movs r3, #0 - 80047f4: f884 3043 strb.w r3, [r4, #67] ; 0x43 - 80047f8: e7a8 b.n 800474c <_printf_i+0x150> - 80047fa: 6923 ldr r3, [r4, #16] - 80047fc: 4632 mov r2, r6 - 80047fe: 4649 mov r1, r9 - 8004800: 4640 mov r0, r8 - 8004802: 47d0 blx sl - 8004804: 3001 adds r0, #1 - 8004806: d0ab beq.n 8004760 <_printf_i+0x164> - 8004808: 6823 ldr r3, [r4, #0] - 800480a: 079b lsls r3, r3, #30 - 800480c: d413 bmi.n 8004836 <_printf_i+0x23a> - 800480e: 68e0 ldr r0, [r4, #12] - 8004810: 9b03 ldr r3, [sp, #12] - 8004812: 4298 cmp r0, r3 - 8004814: bfb8 it lt - 8004816: 4618 movlt r0, r3 - 8004818: e7a4 b.n 8004764 <_printf_i+0x168> - 800481a: 2301 movs r3, #1 - 800481c: 4632 mov r2, r6 - 800481e: 4649 mov r1, r9 - 8004820: 4640 mov r0, r8 - 8004822: 47d0 blx sl - 8004824: 3001 adds r0, #1 - 8004826: d09b beq.n 8004760 <_printf_i+0x164> - 8004828: 3501 adds r5, #1 - 800482a: 68e3 ldr r3, [r4, #12] - 800482c: 9903 ldr r1, [sp, #12] - 800482e: 1a5b subs r3, r3, r1 - 8004830: 42ab cmp r3, r5 - 8004832: dcf2 bgt.n 800481a <_printf_i+0x21e> - 8004834: e7eb b.n 800480e <_printf_i+0x212> - 8004836: 2500 movs r5, #0 - 8004838: f104 0619 add.w r6, r4, #25 - 800483c: e7f5 b.n 800482a <_printf_i+0x22e> - 800483e: bf00 nop - 8004840: 08004c89 .word 0x08004c89 - 8004844: 08004c9a .word 0x08004c9a - -08004848 <_sbrk_r>: - 8004848: b538 push {r3, r4, r5, lr} - 800484a: 4d06 ldr r5, [pc, #24] ; (8004864 <_sbrk_r+0x1c>) - 800484c: 2300 movs r3, #0 - 800484e: 4604 mov r4, r0 - 8004850: 4608 mov r0, r1 - 8004852: 602b str r3, [r5, #0] - 8004854: f7fc fc32 bl 80010bc <_sbrk> - 8004858: 1c43 adds r3, r0, #1 - 800485a: d102 bne.n 8004862 <_sbrk_r+0x1a> - 800485c: 682b ldr r3, [r5, #0] - 800485e: b103 cbz r3, 8004862 <_sbrk_r+0x1a> - 8004860: 6023 str r3, [r4, #0] - 8004862: bd38 pop {r3, r4, r5, pc} - 8004864: 200005e4 .word 0x200005e4 - -08004868 <__sread>: - 8004868: b510 push {r4, lr} - 800486a: 460c mov r4, r1 - 800486c: f9b1 100e ldrsh.w r1, [r1, #14] - 8004870: f000 f8a0 bl 80049b4 <_read_r> - 8004874: 2800 cmp r0, #0 - 8004876: bfab itete ge - 8004878: 6d63 ldrge r3, [r4, #84] ; 0x54 - 800487a: 89a3 ldrhlt r3, [r4, #12] - 800487c: 181b addge r3, r3, r0 - 800487e: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 - 8004882: bfac ite ge - 8004884: 6563 strge r3, [r4, #84] ; 0x54 - 8004886: 81a3 strhlt r3, [r4, #12] - 8004888: bd10 pop {r4, pc} - -0800488a <__swrite>: - 800488a: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} - 800488e: 461f mov r7, r3 - 8004890: 898b ldrh r3, [r1, #12] - 8004892: 05db lsls r3, r3, #23 - 8004894: 4605 mov r5, r0 - 8004896: 460c mov r4, r1 - 8004898: 4616 mov r6, r2 - 800489a: d505 bpl.n 80048a8 <__swrite+0x1e> - 800489c: f9b1 100e ldrsh.w r1, [r1, #14] - 80048a0: 2302 movs r3, #2 - 80048a2: 2200 movs r2, #0 - 80048a4: f000 f868 bl 8004978 <_lseek_r> - 80048a8: 89a3 ldrh r3, [r4, #12] - 80048aa: f9b4 100e ldrsh.w r1, [r4, #14] - 80048ae: f423 5380 bic.w r3, r3, #4096 ; 0x1000 - 80048b2: 81a3 strh r3, [r4, #12] - 80048b4: 4632 mov r2, r6 - 80048b6: 463b mov r3, r7 - 80048b8: 4628 mov r0, r5 - 80048ba: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} - 80048be: f000 b817 b.w 80048f0 <_write_r> - -080048c2 <__sseek>: - 80048c2: b510 push {r4, lr} - 80048c4: 460c mov r4, r1 - 80048c6: f9b1 100e ldrsh.w r1, [r1, #14] - 80048ca: f000 f855 bl 8004978 <_lseek_r> - 80048ce: 1c43 adds r3, r0, #1 - 80048d0: 89a3 ldrh r3, [r4, #12] - 80048d2: bf15 itete ne - 80048d4: 6560 strne r0, [r4, #84] ; 0x54 - 80048d6: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 - 80048da: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 - 80048de: 81a3 strheq r3, [r4, #12] - 80048e0: bf18 it ne - 80048e2: 81a3 strhne r3, [r4, #12] - 80048e4: bd10 pop {r4, pc} - -080048e6 <__sclose>: - 80048e6: f9b1 100e ldrsh.w r1, [r1, #14] - 80048ea: f000 b813 b.w 8004914 <_close_r> +080052a8 <_printf_i>: + 80052a8: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} + 80052ac: 460c mov r4, r1 + 80052ae: 4691 mov r9, r2 + 80052b0: 7e27 ldrb r7, [r4, #24] + 80052b2: 990c ldr r1, [sp, #48] ; 0x30 + 80052b4: 2f78 cmp r7, #120 ; 0x78 + 80052b6: 4680 mov r8, r0 + 80052b8: 469a mov sl, r3 + 80052ba: f104 0243 add.w r2, r4, #67 ; 0x43 + 80052be: d807 bhi.n 80052d0 <_printf_i+0x28> + 80052c0: 2f62 cmp r7, #98 ; 0x62 + 80052c2: d80a bhi.n 80052da <_printf_i+0x32> + 80052c4: 2f00 cmp r7, #0 + 80052c6: f000 80d8 beq.w 800547a <_printf_i+0x1d2> + 80052ca: 2f58 cmp r7, #88 ; 0x58 + 80052cc: f000 80a3 beq.w 8005416 <_printf_i+0x16e> + 80052d0: f104 0642 add.w r6, r4, #66 ; 0x42 + 80052d4: f884 7042 strb.w r7, [r4, #66] ; 0x42 + 80052d8: e03a b.n 8005350 <_printf_i+0xa8> + 80052da: f1a7 0363 sub.w r3, r7, #99 ; 0x63 + 80052de: 2b15 cmp r3, #21 + 80052e0: d8f6 bhi.n 80052d0 <_printf_i+0x28> + 80052e2: a001 add r0, pc, #4 ; (adr r0, 80052e8 <_printf_i+0x40>) + 80052e4: f850 f023 ldr.w pc, [r0, r3, lsl #2] + 80052e8: 08005341 .word 0x08005341 + 80052ec: 08005355 .word 0x08005355 + 80052f0: 080052d1 .word 0x080052d1 + 80052f4: 080052d1 .word 0x080052d1 + 80052f8: 080052d1 .word 0x080052d1 + 80052fc: 080052d1 .word 0x080052d1 + 8005300: 08005355 .word 0x08005355 + 8005304: 080052d1 .word 0x080052d1 + 8005308: 080052d1 .word 0x080052d1 + 800530c: 080052d1 .word 0x080052d1 + 8005310: 080052d1 .word 0x080052d1 + 8005314: 08005461 .word 0x08005461 + 8005318: 08005385 .word 0x08005385 + 800531c: 08005443 .word 0x08005443 + 8005320: 080052d1 .word 0x080052d1 + 8005324: 080052d1 .word 0x080052d1 + 8005328: 08005483 .word 0x08005483 + 800532c: 080052d1 .word 0x080052d1 + 8005330: 08005385 .word 0x08005385 + 8005334: 080052d1 .word 0x080052d1 + 8005338: 080052d1 .word 0x080052d1 + 800533c: 0800544b .word 0x0800544b + 8005340: 680b ldr r3, [r1, #0] + 8005342: 1d1a adds r2, r3, #4 + 8005344: 681b ldr r3, [r3, #0] + 8005346: 600a str r2, [r1, #0] + 8005348: f104 0642 add.w r6, r4, #66 ; 0x42 + 800534c: f884 3042 strb.w r3, [r4, #66] ; 0x42 + 8005350: 2301 movs r3, #1 + 8005352: e0a3 b.n 800549c <_printf_i+0x1f4> + 8005354: 6825 ldr r5, [r4, #0] + 8005356: 6808 ldr r0, [r1, #0] + 8005358: 062e lsls r6, r5, #24 + 800535a: f100 0304 add.w r3, r0, #4 + 800535e: d50a bpl.n 8005376 <_printf_i+0xce> + 8005360: 6805 ldr r5, [r0, #0] + 8005362: 600b str r3, [r1, #0] + 8005364: 2d00 cmp r5, #0 + 8005366: da03 bge.n 8005370 <_printf_i+0xc8> + 8005368: 232d movs r3, #45 ; 0x2d + 800536a: 426d negs r5, r5 + 800536c: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 8005370: 485e ldr r0, [pc, #376] ; (80054ec <_printf_i+0x244>) + 8005372: 230a movs r3, #10 + 8005374: e019 b.n 80053aa <_printf_i+0x102> + 8005376: f015 0f40 tst.w r5, #64 ; 0x40 + 800537a: 6805 ldr r5, [r0, #0] + 800537c: 600b str r3, [r1, #0] + 800537e: bf18 it ne + 8005380: b22d sxthne r5, r5 + 8005382: e7ef b.n 8005364 <_printf_i+0xbc> + 8005384: 680b ldr r3, [r1, #0] + 8005386: 6825 ldr r5, [r4, #0] + 8005388: 1d18 adds r0, r3, #4 + 800538a: 6008 str r0, [r1, #0] + 800538c: 0628 lsls r0, r5, #24 + 800538e: d501 bpl.n 8005394 <_printf_i+0xec> + 8005390: 681d ldr r5, [r3, #0] + 8005392: e002 b.n 800539a <_printf_i+0xf2> + 8005394: 0669 lsls r1, r5, #25 + 8005396: d5fb bpl.n 8005390 <_printf_i+0xe8> + 8005398: 881d ldrh r5, [r3, #0] + 800539a: 4854 ldr r0, [pc, #336] ; (80054ec <_printf_i+0x244>) + 800539c: 2f6f cmp r7, #111 ; 0x6f + 800539e: bf0c ite eq + 80053a0: 2308 moveq r3, #8 + 80053a2: 230a movne r3, #10 + 80053a4: 2100 movs r1, #0 + 80053a6: f884 1043 strb.w r1, [r4, #67] ; 0x43 + 80053aa: 6866 ldr r6, [r4, #4] + 80053ac: 60a6 str r6, [r4, #8] + 80053ae: 2e00 cmp r6, #0 + 80053b0: bfa2 ittt ge + 80053b2: 6821 ldrge r1, [r4, #0] + 80053b4: f021 0104 bicge.w r1, r1, #4 + 80053b8: 6021 strge r1, [r4, #0] + 80053ba: b90d cbnz r5, 80053c0 <_printf_i+0x118> + 80053bc: 2e00 cmp r6, #0 + 80053be: d04d beq.n 800545c <_printf_i+0x1b4> + 80053c0: 4616 mov r6, r2 + 80053c2: fbb5 f1f3 udiv r1, r5, r3 + 80053c6: fb03 5711 mls r7, r3, r1, r5 + 80053ca: 5dc7 ldrb r7, [r0, r7] + 80053cc: f806 7d01 strb.w r7, [r6, #-1]! + 80053d0: 462f mov r7, r5 + 80053d2: 42bb cmp r3, r7 + 80053d4: 460d mov r5, r1 + 80053d6: d9f4 bls.n 80053c2 <_printf_i+0x11a> + 80053d8: 2b08 cmp r3, #8 + 80053da: d10b bne.n 80053f4 <_printf_i+0x14c> + 80053dc: 6823 ldr r3, [r4, #0] + 80053de: 07df lsls r7, r3, #31 + 80053e0: d508 bpl.n 80053f4 <_printf_i+0x14c> + 80053e2: 6923 ldr r3, [r4, #16] + 80053e4: 6861 ldr r1, [r4, #4] + 80053e6: 4299 cmp r1, r3 + 80053e8: bfde ittt le + 80053ea: 2330 movle r3, #48 ; 0x30 + 80053ec: f806 3c01 strble.w r3, [r6, #-1] + 80053f0: f106 36ff addle.w r6, r6, #4294967295 + 80053f4: 1b92 subs r2, r2, r6 + 80053f6: 6122 str r2, [r4, #16] + 80053f8: f8cd a000 str.w sl, [sp] + 80053fc: 464b mov r3, r9 + 80053fe: aa03 add r2, sp, #12 + 8005400: 4621 mov r1, r4 + 8005402: 4640 mov r0, r8 + 8005404: f7ff fee2 bl 80051cc <_printf_common> + 8005408: 3001 adds r0, #1 + 800540a: d14c bne.n 80054a6 <_printf_i+0x1fe> + 800540c: f04f 30ff mov.w r0, #4294967295 + 8005410: b004 add sp, #16 + 8005412: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8005416: 4835 ldr r0, [pc, #212] ; (80054ec <_printf_i+0x244>) + 8005418: f884 7045 strb.w r7, [r4, #69] ; 0x45 + 800541c: 6823 ldr r3, [r4, #0] + 800541e: 680e ldr r6, [r1, #0] + 8005420: 061f lsls r7, r3, #24 + 8005422: f856 5b04 ldr.w r5, [r6], #4 + 8005426: 600e str r6, [r1, #0] + 8005428: d514 bpl.n 8005454 <_printf_i+0x1ac> + 800542a: 07d9 lsls r1, r3, #31 + 800542c: bf44 itt mi + 800542e: f043 0320 orrmi.w r3, r3, #32 + 8005432: 6023 strmi r3, [r4, #0] + 8005434: b91d cbnz r5, 800543e <_printf_i+0x196> + 8005436: 6823 ldr r3, [r4, #0] + 8005438: f023 0320 bic.w r3, r3, #32 + 800543c: 6023 str r3, [r4, #0] + 800543e: 2310 movs r3, #16 + 8005440: e7b0 b.n 80053a4 <_printf_i+0xfc> + 8005442: 6823 ldr r3, [r4, #0] + 8005444: f043 0320 orr.w r3, r3, #32 + 8005448: 6023 str r3, [r4, #0] + 800544a: 2378 movs r3, #120 ; 0x78 + 800544c: 4828 ldr r0, [pc, #160] ; (80054f0 <_printf_i+0x248>) + 800544e: f884 3045 strb.w r3, [r4, #69] ; 0x45 + 8005452: e7e3 b.n 800541c <_printf_i+0x174> + 8005454: 065e lsls r6, r3, #25 + 8005456: bf48 it mi + 8005458: b2ad uxthmi r5, r5 + 800545a: e7e6 b.n 800542a <_printf_i+0x182> + 800545c: 4616 mov r6, r2 + 800545e: e7bb b.n 80053d8 <_printf_i+0x130> + 8005460: 680b ldr r3, [r1, #0] + 8005462: 6826 ldr r6, [r4, #0] + 8005464: 6960 ldr r0, [r4, #20] + 8005466: 1d1d adds r5, r3, #4 + 8005468: 600d str r5, [r1, #0] + 800546a: 0635 lsls r5, r6, #24 + 800546c: 681b ldr r3, [r3, #0] + 800546e: d501 bpl.n 8005474 <_printf_i+0x1cc> + 8005470: 6018 str r0, [r3, #0] + 8005472: e002 b.n 800547a <_printf_i+0x1d2> + 8005474: 0671 lsls r1, r6, #25 + 8005476: d5fb bpl.n 8005470 <_printf_i+0x1c8> + 8005478: 8018 strh r0, [r3, #0] + 800547a: 2300 movs r3, #0 + 800547c: 6123 str r3, [r4, #16] + 800547e: 4616 mov r6, r2 + 8005480: e7ba b.n 80053f8 <_printf_i+0x150> + 8005482: 680b ldr r3, [r1, #0] + 8005484: 1d1a adds r2, r3, #4 + 8005486: 600a str r2, [r1, #0] + 8005488: 681e ldr r6, [r3, #0] + 800548a: 6862 ldr r2, [r4, #4] + 800548c: 2100 movs r1, #0 + 800548e: 4630 mov r0, r6 + 8005490: f7fa fed6 bl 8000240 + 8005494: b108 cbz r0, 800549a <_printf_i+0x1f2> + 8005496: 1b80 subs r0, r0, r6 + 8005498: 6060 str r0, [r4, #4] + 800549a: 6863 ldr r3, [r4, #4] + 800549c: 6123 str r3, [r4, #16] + 800549e: 2300 movs r3, #0 + 80054a0: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 80054a4: e7a8 b.n 80053f8 <_printf_i+0x150> + 80054a6: 6923 ldr r3, [r4, #16] + 80054a8: 4632 mov r2, r6 + 80054aa: 4649 mov r1, r9 + 80054ac: 4640 mov r0, r8 + 80054ae: 47d0 blx sl + 80054b0: 3001 adds r0, #1 + 80054b2: d0ab beq.n 800540c <_printf_i+0x164> + 80054b4: 6823 ldr r3, [r4, #0] + 80054b6: 079b lsls r3, r3, #30 + 80054b8: d413 bmi.n 80054e2 <_printf_i+0x23a> + 80054ba: 68e0 ldr r0, [r4, #12] + 80054bc: 9b03 ldr r3, [sp, #12] + 80054be: 4298 cmp r0, r3 + 80054c0: bfb8 it lt + 80054c2: 4618 movlt r0, r3 + 80054c4: e7a4 b.n 8005410 <_printf_i+0x168> + 80054c6: 2301 movs r3, #1 + 80054c8: 4632 mov r2, r6 + 80054ca: 4649 mov r1, r9 + 80054cc: 4640 mov r0, r8 + 80054ce: 47d0 blx sl + 80054d0: 3001 adds r0, #1 + 80054d2: d09b beq.n 800540c <_printf_i+0x164> + 80054d4: 3501 adds r5, #1 + 80054d6: 68e3 ldr r3, [r4, #12] + 80054d8: 9903 ldr r1, [sp, #12] + 80054da: 1a5b subs r3, r3, r1 + 80054dc: 42ab cmp r3, r5 + 80054de: dcf2 bgt.n 80054c6 <_printf_i+0x21e> + 80054e0: e7eb b.n 80054ba <_printf_i+0x212> + 80054e2: 2500 movs r5, #0 + 80054e4: f104 0619 add.w r6, r4, #25 + 80054e8: e7f5 b.n 80054d6 <_printf_i+0x22e> + 80054ea: bf00 nop + 80054ec: 08005b91 .word 0x08005b91 + 80054f0: 08005ba2 .word 0x08005ba2 + +080054f4 <_sbrk_r>: + 80054f4: b538 push {r3, r4, r5, lr} + 80054f6: 4d06 ldr r5, [pc, #24] ; (8005510 <_sbrk_r+0x1c>) + 80054f8: 2300 movs r3, #0 + 80054fa: 4604 mov r4, r0 + 80054fc: 4608 mov r0, r1 + 80054fe: 602b str r3, [r5, #0] + 8005500: f7fc fa34 bl 800196c <_sbrk> + 8005504: 1c43 adds r3, r0, #1 + 8005506: d102 bne.n 800550e <_sbrk_r+0x1a> + 8005508: 682b ldr r3, [r5, #0] + 800550a: b103 cbz r3, 800550e <_sbrk_r+0x1a> + 800550c: 6023 str r3, [r4, #0] + 800550e: bd38 pop {r3, r4, r5, pc} + 8005510: 20000610 .word 0x20000610 + +08005514 <__sread>: + 8005514: b510 push {r4, lr} + 8005516: 460c mov r4, r1 + 8005518: f9b1 100e ldrsh.w r1, [r1, #14] + 800551c: f000 f8a0 bl 8005660 <_read_r> + 8005520: 2800 cmp r0, #0 + 8005522: bfab itete ge + 8005524: 6d63 ldrge r3, [r4, #84] ; 0x54 + 8005526: 89a3 ldrhlt r3, [r4, #12] + 8005528: 181b addge r3, r3, r0 + 800552a: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 + 800552e: bfac ite ge + 8005530: 6563 strge r3, [r4, #84] ; 0x54 + 8005532: 81a3 strhlt r3, [r4, #12] + 8005534: bd10 pop {r4, pc} + +08005536 <__swrite>: + 8005536: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 800553a: 461f mov r7, r3 + 800553c: 898b ldrh r3, [r1, #12] + 800553e: 05db lsls r3, r3, #23 + 8005540: 4605 mov r5, r0 + 8005542: 460c mov r4, r1 + 8005544: 4616 mov r6, r2 + 8005546: d505 bpl.n 8005554 <__swrite+0x1e> + 8005548: f9b1 100e ldrsh.w r1, [r1, #14] + 800554c: 2302 movs r3, #2 + 800554e: 2200 movs r2, #0 + 8005550: f000 f868 bl 8005624 <_lseek_r> + 8005554: 89a3 ldrh r3, [r4, #12] + 8005556: f9b4 100e ldrsh.w r1, [r4, #14] + 800555a: f423 5380 bic.w r3, r3, #4096 ; 0x1000 + 800555e: 81a3 strh r3, [r4, #12] + 8005560: 4632 mov r2, r6 + 8005562: 463b mov r3, r7 + 8005564: 4628 mov r0, r5 + 8005566: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 800556a: f000 b817 b.w 800559c <_write_r> + +0800556e <__sseek>: + 800556e: b510 push {r4, lr} + 8005570: 460c mov r4, r1 + 8005572: f9b1 100e ldrsh.w r1, [r1, #14] + 8005576: f000 f855 bl 8005624 <_lseek_r> + 800557a: 1c43 adds r3, r0, #1 + 800557c: 89a3 ldrh r3, [r4, #12] + 800557e: bf15 itete ne + 8005580: 6560 strne r0, [r4, #84] ; 0x54 + 8005582: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 + 8005586: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 + 800558a: 81a3 strheq r3, [r4, #12] + 800558c: bf18 it ne + 800558e: 81a3 strhne r3, [r4, #12] + 8005590: bd10 pop {r4, pc} + +08005592 <__sclose>: + 8005592: f9b1 100e ldrsh.w r1, [r1, #14] + 8005596: f000 b813 b.w 80055c0 <_close_r> ... -080048f0 <_write_r>: - 80048f0: b538 push {r3, r4, r5, lr} - 80048f2: 4d07 ldr r5, [pc, #28] ; (8004910 <_write_r+0x20>) - 80048f4: 4604 mov r4, r0 - 80048f6: 4608 mov r0, r1 - 80048f8: 4611 mov r1, r2 - 80048fa: 2200 movs r2, #0 - 80048fc: 602a str r2, [r5, #0] - 80048fe: 461a mov r2, r3 - 8004900: f7fc fb8b bl 800101a <_write> - 8004904: 1c43 adds r3, r0, #1 - 8004906: d102 bne.n 800490e <_write_r+0x1e> - 8004908: 682b ldr r3, [r5, #0] - 800490a: b103 cbz r3, 800490e <_write_r+0x1e> - 800490c: 6023 str r3, [r4, #0] - 800490e: bd38 pop {r3, r4, r5, pc} - 8004910: 200005e4 .word 0x200005e4 - -08004914 <_close_r>: - 8004914: b538 push {r3, r4, r5, lr} - 8004916: 4d06 ldr r5, [pc, #24] ; (8004930 <_close_r+0x1c>) - 8004918: 2300 movs r3, #0 - 800491a: 4604 mov r4, r0 - 800491c: 4608 mov r0, r1 - 800491e: 602b str r3, [r5, #0] - 8004920: f7fc fb97 bl 8001052 <_close> - 8004924: 1c43 adds r3, r0, #1 - 8004926: d102 bne.n 800492e <_close_r+0x1a> - 8004928: 682b ldr r3, [r5, #0] - 800492a: b103 cbz r3, 800492e <_close_r+0x1a> - 800492c: 6023 str r3, [r4, #0] - 800492e: bd38 pop {r3, r4, r5, pc} - 8004930: 200005e4 .word 0x200005e4 - -08004934 <_fstat_r>: - 8004934: b538 push {r3, r4, r5, lr} - 8004936: 4d07 ldr r5, [pc, #28] ; (8004954 <_fstat_r+0x20>) - 8004938: 2300 movs r3, #0 - 800493a: 4604 mov r4, r0 - 800493c: 4608 mov r0, r1 - 800493e: 4611 mov r1, r2 - 8004940: 602b str r3, [r5, #0] - 8004942: f7fc fb92 bl 800106a <_fstat> - 8004946: 1c43 adds r3, r0, #1 - 8004948: d102 bne.n 8004950 <_fstat_r+0x1c> - 800494a: 682b ldr r3, [r5, #0] - 800494c: b103 cbz r3, 8004950 <_fstat_r+0x1c> - 800494e: 6023 str r3, [r4, #0] - 8004950: bd38 pop {r3, r4, r5, pc} - 8004952: bf00 nop - 8004954: 200005e4 .word 0x200005e4 - -08004958 <_isatty_r>: - 8004958: b538 push {r3, r4, r5, lr} - 800495a: 4d06 ldr r5, [pc, #24] ; (8004974 <_isatty_r+0x1c>) - 800495c: 2300 movs r3, #0 - 800495e: 4604 mov r4, r0 - 8004960: 4608 mov r0, r1 - 8004962: 602b str r3, [r5, #0] - 8004964: f7fc fb91 bl 800108a <_isatty> - 8004968: 1c43 adds r3, r0, #1 - 800496a: d102 bne.n 8004972 <_isatty_r+0x1a> - 800496c: 682b ldr r3, [r5, #0] - 800496e: b103 cbz r3, 8004972 <_isatty_r+0x1a> - 8004970: 6023 str r3, [r4, #0] - 8004972: bd38 pop {r3, r4, r5, pc} - 8004974: 200005e4 .word 0x200005e4 - -08004978 <_lseek_r>: - 8004978: b538 push {r3, r4, r5, lr} - 800497a: 4d07 ldr r5, [pc, #28] ; (8004998 <_lseek_r+0x20>) - 800497c: 4604 mov r4, r0 - 800497e: 4608 mov r0, r1 - 8004980: 4611 mov r1, r2 - 8004982: 2200 movs r2, #0 - 8004984: 602a str r2, [r5, #0] - 8004986: 461a mov r2, r3 - 8004988: f7fc fb8a bl 80010a0 <_lseek> - 800498c: 1c43 adds r3, r0, #1 - 800498e: d102 bne.n 8004996 <_lseek_r+0x1e> - 8004990: 682b ldr r3, [r5, #0] - 8004992: b103 cbz r3, 8004996 <_lseek_r+0x1e> - 8004994: 6023 str r3, [r4, #0] - 8004996: bd38 pop {r3, r4, r5, pc} - 8004998: 200005e4 .word 0x200005e4 - -0800499c <__malloc_lock>: - 800499c: 4801 ldr r0, [pc, #4] ; (80049a4 <__malloc_lock+0x8>) - 800499e: f7ff bb55 b.w 800404c <__retarget_lock_acquire_recursive> - 80049a2: bf00 nop - 80049a4: 200005dc .word 0x200005dc - -080049a8 <__malloc_unlock>: - 80049a8: 4801 ldr r0, [pc, #4] ; (80049b0 <__malloc_unlock+0x8>) - 80049aa: f7ff bb50 b.w 800404e <__retarget_lock_release_recursive> - 80049ae: bf00 nop - 80049b0: 200005dc .word 0x200005dc - -080049b4 <_read_r>: - 80049b4: b538 push {r3, r4, r5, lr} - 80049b6: 4d07 ldr r5, [pc, #28] ; (80049d4 <_read_r+0x20>) - 80049b8: 4604 mov r4, r0 - 80049ba: 4608 mov r0, r1 - 80049bc: 4611 mov r1, r2 - 80049be: 2200 movs r2, #0 - 80049c0: 602a str r2, [r5, #0] - 80049c2: 461a mov r2, r3 - 80049c4: f7fc fb0c bl 8000fe0 <_read> - 80049c8: 1c43 adds r3, r0, #1 - 80049ca: d102 bne.n 80049d2 <_read_r+0x1e> - 80049cc: 682b ldr r3, [r5, #0] - 80049ce: b103 cbz r3, 80049d2 <_read_r+0x1e> - 80049d0: 6023 str r3, [r4, #0] - 80049d2: bd38 pop {r3, r4, r5, pc} - 80049d4: 200005e4 .word 0x200005e4 - -080049d8 <_init>: - 80049d8: b5f8 push {r3, r4, r5, r6, r7, lr} - 80049da: bf00 nop - 80049dc: bcf8 pop {r3, r4, r5, r6, r7} - 80049de: bc08 pop {r3} - 80049e0: 469e mov lr, r3 - 80049e2: 4770 bx lr - -080049e4 <_fini>: - 80049e4: b5f8 push {r3, r4, r5, r6, r7, lr} - 80049e6: bf00 nop - 80049e8: bcf8 pop {r3, r4, r5, r6, r7} - 80049ea: bc08 pop {r3} - 80049ec: 469e mov lr, r3 - 80049ee: 4770 bx lr +0800559c <_write_r>: + 800559c: b538 push {r3, r4, r5, lr} + 800559e: 4d07 ldr r5, [pc, #28] ; (80055bc <_write_r+0x20>) + 80055a0: 4604 mov r4, r0 + 80055a2: 4608 mov r0, r1 + 80055a4: 4611 mov r1, r2 + 80055a6: 2200 movs r2, #0 + 80055a8: 602a str r2, [r5, #0] + 80055aa: 461a mov r2, r3 + 80055ac: f7fc f98d bl 80018ca <_write> + 80055b0: 1c43 adds r3, r0, #1 + 80055b2: d102 bne.n 80055ba <_write_r+0x1e> + 80055b4: 682b ldr r3, [r5, #0] + 80055b6: b103 cbz r3, 80055ba <_write_r+0x1e> + 80055b8: 6023 str r3, [r4, #0] + 80055ba: bd38 pop {r3, r4, r5, pc} + 80055bc: 20000610 .word 0x20000610 + +080055c0 <_close_r>: + 80055c0: b538 push {r3, r4, r5, lr} + 80055c2: 4d06 ldr r5, [pc, #24] ; (80055dc <_close_r+0x1c>) + 80055c4: 2300 movs r3, #0 + 80055c6: 4604 mov r4, r0 + 80055c8: 4608 mov r0, r1 + 80055ca: 602b str r3, [r5, #0] + 80055cc: f7fc f999 bl 8001902 <_close> + 80055d0: 1c43 adds r3, r0, #1 + 80055d2: d102 bne.n 80055da <_close_r+0x1a> + 80055d4: 682b ldr r3, [r5, #0] + 80055d6: b103 cbz r3, 80055da <_close_r+0x1a> + 80055d8: 6023 str r3, [r4, #0] + 80055da: bd38 pop {r3, r4, r5, pc} + 80055dc: 20000610 .word 0x20000610 + +080055e0 <_fstat_r>: + 80055e0: b538 push {r3, r4, r5, lr} + 80055e2: 4d07 ldr r5, [pc, #28] ; (8005600 <_fstat_r+0x20>) + 80055e4: 2300 movs r3, #0 + 80055e6: 4604 mov r4, r0 + 80055e8: 4608 mov r0, r1 + 80055ea: 4611 mov r1, r2 + 80055ec: 602b str r3, [r5, #0] + 80055ee: f7fc f994 bl 800191a <_fstat> + 80055f2: 1c43 adds r3, r0, #1 + 80055f4: d102 bne.n 80055fc <_fstat_r+0x1c> + 80055f6: 682b ldr r3, [r5, #0] + 80055f8: b103 cbz r3, 80055fc <_fstat_r+0x1c> + 80055fa: 6023 str r3, [r4, #0] + 80055fc: bd38 pop {r3, r4, r5, pc} + 80055fe: bf00 nop + 8005600: 20000610 .word 0x20000610 + +08005604 <_isatty_r>: + 8005604: b538 push {r3, r4, r5, lr} + 8005606: 4d06 ldr r5, [pc, #24] ; (8005620 <_isatty_r+0x1c>) + 8005608: 2300 movs r3, #0 + 800560a: 4604 mov r4, r0 + 800560c: 4608 mov r0, r1 + 800560e: 602b str r3, [r5, #0] + 8005610: f7fc f993 bl 800193a <_isatty> + 8005614: 1c43 adds r3, r0, #1 + 8005616: d102 bne.n 800561e <_isatty_r+0x1a> + 8005618: 682b ldr r3, [r5, #0] + 800561a: b103 cbz r3, 800561e <_isatty_r+0x1a> + 800561c: 6023 str r3, [r4, #0] + 800561e: bd38 pop {r3, r4, r5, pc} + 8005620: 20000610 .word 0x20000610 + +08005624 <_lseek_r>: + 8005624: b538 push {r3, r4, r5, lr} + 8005626: 4d07 ldr r5, [pc, #28] ; (8005644 <_lseek_r+0x20>) + 8005628: 4604 mov r4, r0 + 800562a: 4608 mov r0, r1 + 800562c: 4611 mov r1, r2 + 800562e: 2200 movs r2, #0 + 8005630: 602a str r2, [r5, #0] + 8005632: 461a mov r2, r3 + 8005634: f7fc f98c bl 8001950 <_lseek> + 8005638: 1c43 adds r3, r0, #1 + 800563a: d102 bne.n 8005642 <_lseek_r+0x1e> + 800563c: 682b ldr r3, [r5, #0] + 800563e: b103 cbz r3, 8005642 <_lseek_r+0x1e> + 8005640: 6023 str r3, [r4, #0] + 8005642: bd38 pop {r3, r4, r5, pc} + 8005644: 20000610 .word 0x20000610 + +08005648 <__malloc_lock>: + 8005648: 4801 ldr r0, [pc, #4] ; (8005650 <__malloc_lock+0x8>) + 800564a: f7ff bb55 b.w 8004cf8 <__retarget_lock_acquire_recursive> + 800564e: bf00 nop + 8005650: 20000608 .word 0x20000608 + +08005654 <__malloc_unlock>: + 8005654: 4801 ldr r0, [pc, #4] ; (800565c <__malloc_unlock+0x8>) + 8005656: f7ff bb50 b.w 8004cfa <__retarget_lock_release_recursive> + 800565a: bf00 nop + 800565c: 20000608 .word 0x20000608 + +08005660 <_read_r>: + 8005660: b538 push {r3, r4, r5, lr} + 8005662: 4d07 ldr r5, [pc, #28] ; (8005680 <_read_r+0x20>) + 8005664: 4604 mov r4, r0 + 8005666: 4608 mov r0, r1 + 8005668: 4611 mov r1, r2 + 800566a: 2200 movs r2, #0 + 800566c: 602a str r2, [r5, #0] + 800566e: 461a mov r2, r3 + 8005670: f7fc f90e bl 8001890 <_read> + 8005674: 1c43 adds r3, r0, #1 + 8005676: d102 bne.n 800567e <_read_r+0x1e> + 8005678: 682b ldr r3, [r5, #0] + 800567a: b103 cbz r3, 800567e <_read_r+0x1e> + 800567c: 6023 str r3, [r4, #0] + 800567e: bd38 pop {r3, r4, r5, pc} + 8005680: 20000610 .word 0x20000610 + +08005684 <_init>: + 8005684: b5f8 push {r3, r4, r5, r6, r7, lr} + 8005686: bf00 nop + 8005688: bcf8 pop {r3, r4, r5, r6, r7} + 800568a: bc08 pop {r3} + 800568c: 469e mov lr, r3 + 800568e: 4770 bx lr + +08005690 <_fini>: + 8005690: b5f8 push {r3, r4, r5, r6, r7, lr} + 8005692: bf00 nop + 8005694: bcf8 pop {r3, r4, r5, r6, r7} + 8005696: bc08 pop {r3} + 8005698: 469e mov lr, r3 + 800569a: 4770 bx lr diff --git a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Debug/Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Debug/Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk index 8a89791..36a70f2 100644 --- a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Debug/Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk +++ b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Debug/Drivers/STM32F7xx_HAL_Driver/Src/subdir.mk @@ -7,6 +7,8 @@ C_SRCS += \ ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c \ ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.c \ +../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.c \ ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c \ ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c \ ../Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c \ @@ -27,6 +29,8 @@ C_SRCS += \ OBJS += \ ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o \ ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.o \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.o \ ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o \ ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o \ ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o \ @@ -47,6 +51,8 @@ OBJS += \ C_DEPS += \ ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.d \ ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.d \ +./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.d \ ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.d \ ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.d \ ./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.d \ diff --git a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Debug/objects.list b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Debug/objects.list index 26ad394..6c31aab 100644 --- a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Debug/objects.list +++ b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Debug/objects.list @@ -8,6 +8,8 @@ "./Core/Startup/startup_stm32f767zitx.o" "./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.o" "./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.o" +"./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.o" "./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.o" "./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.o" "./Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.o" diff --git a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc.h b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc.h new file mode 100644 index 0000000..08a5025 --- /dev/null +++ b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc.h @@ -0,0 +1,343 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_crc.h + * @author MCD Application Team + * @brief Header file of CRC HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_CRC_H +#define STM32F7xx_HAL_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Types CRC Exported Types + * @{ + */ + +/** + * @brief CRC HAL State Structure definition + */ +typedef enum +{ + HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */ + HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */ + HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */ + HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */ + HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */ +} HAL_CRC_StateTypeDef; + +/** + * @brief CRC Init Structure definition + */ +typedef struct +{ + uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used. + If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default + X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1. + In that case, there is no need to set GeneratingPolynomial field. + If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */ + + uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used. + If set to DEFAULT_INIT_VALUE_ENABLE, resort to default + 0xFFFFFFFF value. In that case, there is no need to set InitValue field. + If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */ + + uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree + respectively equal to 7, 8, 16 or 32. This field is written in normal representation, + e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65. + No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */ + + uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length. + Value can be either one of + @arg @ref CRC_POLYLENGTH_32B (32-bit CRC), + @arg @ref CRC_POLYLENGTH_16B (16-bit CRC), + @arg @ref CRC_POLYLENGTH_8B (8-bit CRC), + @arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */ + + uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse + is set to DEFAULT_INIT_VALUE_ENABLE. */ + + uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode. + Can be either one of the following values + @arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion + @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2 + @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C + @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */ + + uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode. + Can be either + @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, + @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */ +} CRC_InitTypeDef; + +/** + * @brief CRC Handle Structure definition + */ +typedef struct +{ + CRC_TypeDef *Instance; /*!< Register base address */ + + CRC_InitTypeDef Init; /*!< CRC configuration parameters */ + + HAL_LockTypeDef Lock; /*!< CRC Locking object */ + + __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */ + + uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format. + Can be either + @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data) + @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data) + @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data) + + Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error + must occur if InputBufferFormat is not one of the three values listed above */ +} CRC_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRC_Exported_Constants CRC Exported Constants + * @{ + */ + +/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial + * @{ + */ +#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */ +/** + * @} + */ + +/** @defgroup CRC_Default_InitValue Default CRC computation initialization value + * @{ + */ +#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */ +/** + * @} + */ + +/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used + * @{ + */ +#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */ +#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */ +/** + * @} + */ + +/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used + * @{ + */ +#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */ +#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */ +/** + * @} + */ + +/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral + * @{ + */ +#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */ +#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */ +#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */ +#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */ +/** + * @} + */ + +/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions + * @{ + */ +#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */ +#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */ +#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */ +#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */ +/** + * @} + */ + +/** @defgroup CRC_Input_Buffer_Format Input Buffer Format + * @{ + */ +/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but + * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set + * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for + * the CRC APIs to provide a correct result */ +#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */ +#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */ +#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */ +#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */ +/** + * @} + */ + +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CRC_Exported_Macros CRC Exported Macros + * @{ + */ + +/** @brief Reset CRC handle state. + * @param __HANDLE__ CRC handle. + * @retval None + */ +#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) + +/** + * @brief Reset CRC Data Register. + * @param __HANDLE__ CRC handle + * @retval None + */ +#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET) + +/** + * @brief Set CRC INIT non-default value + * @param __HANDLE__ CRC handle + * @param __INIT__ 32-bit initial value + * @retval None + */ +#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) + +/** + * @brief Store data in the Independent Data (ID) register. + * @param __HANDLE__ CRC handle + * @param __VALUE__ Value to be stored in the ID register + * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits + * @retval None + */ +#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) + +/** + * @brief Return the data stored in the Independent Data (ID) register. + * @param __HANDLE__ CRC handle + * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits + * @retval Value of the ID register + */ +#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) +/** + * @} + */ + + +/* Private macros --------------------------------------------------------*/ +/** @defgroup CRC_Private_Macros CRC Private Macros + * @{ + */ + +#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \ + ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE)) + +#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \ + ((VALUE) == DEFAULT_INIT_VALUE_DISABLE)) + +#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \ + ((LENGTH) == CRC_POLYLENGTH_16B) || \ + ((LENGTH) == CRC_POLYLENGTH_8B) || \ + ((LENGTH) == CRC_POLYLENGTH_7B)) + +#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \ + ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \ + ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS)) + +/** + * @} + */ + +/* Include CRC HAL Extended module */ +#include "stm32f7xx_hal_crc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRC_Exported_Functions CRC Exported Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc); +HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc); +void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc); +void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc); +/** + * @} + */ + +/* Peripheral Control functions ***********************************************/ +/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); +/** + * @} + */ + +/* Peripheral State and Error functions ***************************************/ +/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions + * @{ + */ +HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_CRC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc_ex.h b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc_ex.h new file mode 100644 index 0000000..f2ebba1 --- /dev/null +++ b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc_ex.h @@ -0,0 +1,153 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_crc_ex.h + * @author MCD Application Team + * @brief Header file of CRC HAL extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_CRC_EX_H +#define STM32F7xx_HAL_CRC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup CRCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants + * @{ + */ + +/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes + * @{ + */ +#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */ +#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */ +#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */ +#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */ +/** + * @} + */ + +/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes + * @{ + */ +#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */ +#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros + * @{ + */ + +/** + * @brief Set CRC output reversal + * @param __HANDLE__ CRC handle + * @retval None + */ +#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT) + +/** + * @brief Unset CRC output reversal + * @param __HANDLE__ CRC handle + * @retval None + */ +#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT)) + +/** + * @brief Set CRC non-default polynomial + * @param __HANDLE__ CRC handle + * @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial + * @retval None + */ +#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__)) + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros + * @{ + */ + +#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \ + ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \ + ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \ + ((MODE) == CRC_INPUTDATA_INVERSION_WORD)) + +#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \ + ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup CRCEx_Exported_Functions + * @{ + */ + +/** @addtogroup CRCEx_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength); +HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode); +HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_CRC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.c b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.c new file mode 100644 index 0000000..1ba51ad --- /dev/null +++ b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.c @@ -0,0 +1,518 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_crc.c + * @author MCD Application Team + * @brief CRC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Cyclic Redundancy Check (CRC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE(); + (+) Initialize CRC calculator + (++) specify generating polynomial (peripheral default or non-default one) + (++) specify initialization value (peripheral default or non-default one) + (++) specify input data format + (++) specify input or output data inversion mode if any + (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the + input data buffer starting with the previously computed CRC as + initialization value + (+) Use HAL_CRC_Calculate() function to compute the CRC value of the + input data buffer starting with the defined initialization value + (default or non-default) to initiate CRC calculation + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup CRC CRC + * @brief CRC HAL module driver. + * @{ + */ + +#ifdef HAL_CRC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup CRC_Private_Functions CRC Private Functions + * @{ + */ +static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength); +static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CRC_Exported_Functions CRC Exported Functions + * @{ + */ + +/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the CRC according to the specified parameters + in the CRC_InitTypeDef and create the associated handle + (+) DeInitialize the CRC peripheral + (+) Initialize the CRC MSP (MCU Specific Package) + (+) DeInitialize the CRC MSP + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the CRC according to the specified + * parameters in the CRC_InitTypeDef and create the associated handle. + * @param hcrc CRC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) +{ + /* Check the CRC handle allocation */ + if (hcrc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); + + if (hcrc->State == HAL_CRC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcrc->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_CRC_MspInit(hcrc); + } + + hcrc->State = HAL_CRC_STATE_BUSY; + + /* check whether or not non-default generating polynomial has been + * picked up by user */ + assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); + if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) + { + /* initialize peripheral with default generating polynomial */ + WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); + } + else + { + /* initialize CRC peripheral with generating polynomial defined by user */ + if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK) + { + return HAL_ERROR; + } + } + + /* check whether or not non-default CRC initial value has been + * picked up by user */ + assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse)); + if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) + { + WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); + } + else + { + WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); + } + + + /* set input data inversion mode */ + assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); + + /* set output data inversion mode */ + assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); + + /* makes sure the input data format (bytes, halfwords or words stream) + * is properly specified by user */ + assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat)); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitialize the CRC peripheral. + * @param hcrc CRC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) +{ + /* Check the CRC handle allocation */ + if (hcrc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); + + /* Check the CRC peripheral state */ + if (hcrc->State == HAL_CRC_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* Reset CRC calculation unit */ + __HAL_CRC_DR_RESET(hcrc); + + /* Reset IDR register content */ + CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR); + + /* DeInit the low level hardware */ + HAL_CRC_MspDeInit(hcrc); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_RESET; + + /* Process unlocked */ + __HAL_UNLOCK(hcrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CRC MSP. + * @param hcrc CRC handle + * @retval None + */ +__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcrc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CRC_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the CRC MSP. + * @param hcrc CRC handle + * @retval None + */ +__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcrc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CRC_MspDeInit can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions. + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + using combination of the previous CRC value and the new one. + + [..] or + + (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + independently of the previous CRC value. + +@endverbatim + * @{ + */ + +/** + * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + * starting with the previously computed CRC as initialization value. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer, exact input data format is + * provided by hcrc->InputDataFormat. + * @param BufferLength input data buffer length (number of bytes if pBuffer + * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, + * number of words if pBuffer type is * uint32_t). + * @note By default, the API expects a uint32_t pointer as input buffer parameter. + * Input buffer pointers with other types simply need to be cast in uint32_t + * and the API will internally adjust its input data processing based on the + * handle field hcrc->InputDataFormat. + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + switch (hcrc->InputDataFormat) + { + case CRC_INPUTDATA_FORMAT_WORDS: + /* Enter Data to the CRC calculator */ + for (index = 0U; index < BufferLength; index++) + { + hcrc->Instance->DR = pBuffer[index]; + } + temp = hcrc->Instance->DR; + break; + + case CRC_INPUTDATA_FORMAT_BYTES: + temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); + break; + + case CRC_INPUTDATA_FORMAT_HALFWORDS: + temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ + break; + default: + break; + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return the CRC computed value */ + return temp; +} + +/** + * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + * starting with hcrc->Instance->INIT as initialization value. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer, exact input data format is + * provided by hcrc->InputDataFormat. + * @param BufferLength input data buffer length (number of bytes if pBuffer + * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, + * number of words if pBuffer type is * uint32_t). + * @note By default, the API expects a uint32_t pointer as input buffer parameter. + * Input buffer pointers with other types simply need to be cast in uint32_t + * and the API will internally adjust its input data processing based on the + * handle field hcrc->InputDataFormat. + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* Reset CRC Calculation Unit (hcrc->Instance->INIT is + * written in hcrc->Instance->DR) */ + __HAL_CRC_DR_RESET(hcrc); + + switch (hcrc->InputDataFormat) + { + case CRC_INPUTDATA_FORMAT_WORDS: + /* Enter 32-bit input data to the CRC calculator */ + for (index = 0U; index < BufferLength; index++) + { + hcrc->Instance->DR = pBuffer[index]; + } + temp = hcrc->Instance->DR; + break; + + case CRC_INPUTDATA_FORMAT_BYTES: + /* Specific 8-bit input data handling */ + temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); + break; + + case CRC_INPUTDATA_FORMAT_HALFWORDS: + /* Specific 16-bit input data handling */ + temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ + break; + + default: + break; + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return the CRC computed value */ + return temp; +} + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Return the CRC handle state. + * @param hcrc CRC handle + * @retval HAL state + */ +HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) +{ + /* Return CRC handle state */ + return hcrc->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Functions + * @{ + */ + +/** + * @brief Enter 8-bit input data to the CRC calculator. + * Specific data handling to optimize processing time. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) +{ + uint32_t i; /* input data buffer index */ + uint16_t data; + __IO uint16_t *pReg; + + /* Processing time optimization: 4 bytes are entered in a row with a single word write, + * last bytes must be carefully fed to the CRC calculator to ensure a correct type + * handling by the peripheral */ + for (i = 0U; i < (BufferLength / 4U); i++) + { + hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ + ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ + ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ + (uint32_t)pBuffer[(4U * i) + 3U]; + } + /* last bytes specific handling */ + if ((BufferLength % 4U) != 0U) + { + if ((BufferLength % 4U) == 1U) + { + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ + } + if ((BufferLength % 4U) == 2U) + { + data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ + *pReg = data; + } + if ((BufferLength % 4U) == 3U) + { + data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ + *pReg = data; + + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ + } + } + + /* Return the CRC computed value */ + return hcrc->Instance->DR; +} + +/** + * @brief Enter 16-bit input data to the CRC calculator. + * Specific data handling to optimize processing time. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) +{ + uint32_t i; /* input data buffer index */ + __IO uint16_t *pReg; + + /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, + * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure + * a correct type handling by the peripheral */ + for (i = 0U; i < (BufferLength / 2U); i++) + { + hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U]; + } + if ((BufferLength % 2U) != 0U) + { + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ + *pReg = pBuffer[2U * i]; + } + + /* Return the CRC computed value */ + return hcrc->Instance->DR; +} + +/** + * @} + */ + +#endif /* HAL_CRC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.c b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.c new file mode 100644 index 0000000..d542da1 --- /dev/null +++ b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/Bootloader/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.c @@ -0,0 +1,225 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_crc_ex.c + * @author MCD Application Team + * @brief Extended CRC HAL module driver. + * This file provides firmware functions to manage the extended + * functionalities of the CRC peripheral. + * + @verbatim +================================================================================ + ##### How to use this driver ##### +================================================================================ + [..] + (+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set() + (+) Configure Input or Output data inversion + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup CRCEx CRCEx + * @brief CRC Extended HAL module driver + * @{ + */ + +#ifdef HAL_CRC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions + * @{ + */ + +/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions + * @brief Extended Initialization and Configuration functions. + * +@verbatim + =============================================================================== + ##### Extended configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the generating polynomial + (+) Configure the input data inversion + (+) Configure the output data inversion + +@endverbatim + * @{ + */ + + +/** + * @brief Initialize the CRC polynomial if different from default one. + * @param hcrc CRC handle + * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long). + * This parameter is written in normal representation, e.g. + * @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 + * @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021 + * @param PolyLength CRC polynomial length. + * This parameter can be one of the following values: + * @arg @ref CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7) + * @arg @ref CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8) + * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16) + * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */ + + /* Check the parameters */ + assert_param(IS_CRC_POL_LENGTH(PolyLength)); + + /* check polynomial definition vs polynomial size: + * polynomial length must be aligned with polynomial + * definition. HAL_ERROR is reported if Pol degree is + * larger than that indicated by PolyLength. + * Look for MSB position: msb will contain the degree of + * the second to the largest polynomial member. E.g., for + * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ + while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) + { + } + + switch (PolyLength) + { + case CRC_POLYLENGTH_7B: + if (msb >= HAL_CRC_LENGTH_7B) + { + status = HAL_ERROR; + } + break; + case CRC_POLYLENGTH_8B: + if (msb >= HAL_CRC_LENGTH_8B) + { + status = HAL_ERROR; + } + break; + case CRC_POLYLENGTH_16B: + if (msb >= HAL_CRC_LENGTH_16B) + { + status = HAL_ERROR; + } + break; + + case CRC_POLYLENGTH_32B: + /* no polynomial definition vs. polynomial length issue possible */ + break; + default: + status = HAL_ERROR; + break; + } + if (status == HAL_OK) + { + /* set generating polynomial */ + WRITE_REG(hcrc->Instance->POL, Pol); + + /* set generating polynomial size */ + MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); + } + /* Return function status */ + return status; +} + +/** + * @brief Set the Reverse Input data mode. + * @param hcrc CRC handle + * @param InputReverseMode Input Data inversion mode. + * This parameter can be one of the following values: + * @arg @ref CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value) + * @arg @ref CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal + * @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal + * @arg @ref CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode) +{ + /* Check the parameters */ + assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode)); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* set input data inversion mode */ + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode); + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set the Reverse Output data mode. + * @param hcrc CRC handle + * @param OutputReverseMode Output Data inversion mode. + * This parameter can be one of the following values: + * @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value) + * @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode) +{ + /* Check the parameters */ + assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode)); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* set output data inversion mode */ + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + + + + +/** + * @} + */ + + +/** + * @} + */ + + +#endif /* HAL_CRC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/HostApp/PcTool/etx_ota_app.exe b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/HostApp/PcTool/etx_ota_app.exe index 13876d8..1254e57 100644 Binary files a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/HostApp/PcTool/etx_ota_app.exe and b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/HostApp/PcTool/etx_ota_app.exe differ diff --git a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/HostApp/PcTool/etx_ota_update_main.c b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/HostApp/PcTool/etx_ota_update_main.c index fa994b0..2d87f65 100644 --- a/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/HostApp/PcTool/etx_ota_update_main.c +++ b/Microcontrollers/STM32/STM32F7xx/Bootloader_Example/HostApp/PcTool/etx_ota_update_main.c @@ -24,6 +24,37 @@ compile with the command: gcc etx_ota_update_main.c RS232\rs232.c -IRS232 -Wall uint8_t DATA_BUF[ETX_OTA_PACKET_MAX_SIZE]; uint8_t APP_BIN[ETX_OTA_MAX_FW_SIZE]; +static const uint32_t crc_table[0x100] = { + 0x00000000, 0x04C11DB7, 0x09823B6E, 0x0D4326D9, 0x130476DC, 0x17C56B6B, 0x1A864DB2, 0x1E475005, 0x2608EDB8, 0x22C9F00F, 0x2F8AD6D6, 0x2B4BCB61, 0x350C9B64, 0x31CD86D3, 0x3C8EA00A, 0x384FBDBD, + 0x4C11DB70, 0x48D0C6C7, 0x4593E01E, 0x4152FDA9, 0x5F15ADAC, 0x5BD4B01B, 0x569796C2, 0x52568B75, 0x6A1936C8, 0x6ED82B7F, 0x639B0DA6, 0x675A1011, 0x791D4014, 0x7DDC5DA3, 0x709F7B7A, 0x745E66CD, + 0x9823B6E0, 0x9CE2AB57, 0x91A18D8E, 0x95609039, 0x8B27C03C, 0x8FE6DD8B, 0x82A5FB52, 0x8664E6E5, 0xBE2B5B58, 0xBAEA46EF, 0xB7A96036, 0xB3687D81, 0xAD2F2D84, 0xA9EE3033, 0xA4AD16EA, 0xA06C0B5D, + 0xD4326D90, 0xD0F37027, 0xDDB056FE, 0xD9714B49, 0xC7361B4C, 0xC3F706FB, 0xCEB42022, 0xCA753D95, 0xF23A8028, 0xF6FB9D9F, 0xFBB8BB46, 0xFF79A6F1, 0xE13EF6F4, 0xE5FFEB43, 0xE8BCCD9A, 0xEC7DD02D, + 0x34867077, 0x30476DC0, 0x3D044B19, 0x39C556AE, 0x278206AB, 0x23431B1C, 0x2E003DC5, 0x2AC12072, 0x128E9DCF, 0x164F8078, 0x1B0CA6A1, 0x1FCDBB16, 0x018AEB13, 0x054BF6A4, 0x0808D07D, 0x0CC9CDCA, + 0x7897AB07, 0x7C56B6B0, 0x71159069, 0x75D48DDE, 0x6B93DDDB, 0x6F52C06C, 0x6211E6B5, 0x66D0FB02, 0x5E9F46BF, 0x5A5E5B08, 0x571D7DD1, 0x53DC6066, 0x4D9B3063, 0x495A2DD4, 0x44190B0D, 0x40D816BA, + 0xACA5C697, 0xA864DB20, 0xA527FDF9, 0xA1E6E04E, 0xBFA1B04B, 0xBB60ADFC, 0xB6238B25, 0xB2E29692, 0x8AAD2B2F, 0x8E6C3698, 0x832F1041, 0x87EE0DF6, 0x99A95DF3, 0x9D684044, 0x902B669D, 0x94EA7B2A, + 0xE0B41DE7, 0xE4750050, 0xE9362689, 0xEDF73B3E, 0xF3B06B3B, 0xF771768C, 0xFA325055, 0xFEF34DE2, 0xC6BCF05F, 0xC27DEDE8, 0xCF3ECB31, 0xCBFFD686, 0xD5B88683, 0xD1799B34, 0xDC3ABDED, 0xD8FBA05A, + 0x690CE0EE, 0x6DCDFD59, 0x608EDB80, 0x644FC637, 0x7A089632, 0x7EC98B85, 0x738AAD5C, 0x774BB0EB, 0x4F040D56, 0x4BC510E1, 0x46863638, 0x42472B8F, 0x5C007B8A, 0x58C1663D, 0x558240E4, 0x51435D53, + 0x251D3B9E, 0x21DC2629, 0x2C9F00F0, 0x285E1D47, 0x36194D42, 0x32D850F5, 0x3F9B762C, 0x3B5A6B9B, 0x0315D626, 0x07D4CB91, 0x0A97ED48, 0x0E56F0FF, 0x1011A0FA, 0x14D0BD4D, 0x19939B94, 0x1D528623, + 0xF12F560E, 0xF5EE4BB9, 0xF8AD6D60, 0xFC6C70D7, 0xE22B20D2, 0xE6EA3D65, 0xEBA91BBC, 0xEF68060B, 0xD727BBB6, 0xD3E6A601, 0xDEA580D8, 0xDA649D6F, 0xC423CD6A, 0xC0E2D0DD, 0xCDA1F604, 0xC960EBB3, + 0xBD3E8D7E, 0xB9FF90C9, 0xB4BCB610, 0xB07DABA7, 0xAE3AFBA2, 0xAAFBE615, 0xA7B8C0CC, 0xA379DD7B, 0x9B3660C6, 0x9FF77D71, 0x92B45BA8, 0x9675461F, 0x8832161A, 0x8CF30BAD, 0x81B02D74, 0x857130C3, + 0x5D8A9099, 0x594B8D2E, 0x5408ABF7, 0x50C9B640, 0x4E8EE645, 0x4A4FFBF2, 0x470CDD2B, 0x43CDC09C, 0x7B827D21, 0x7F436096, 0x7200464F, 0x76C15BF8, 0x68860BFD, 0x6C47164A, 0x61043093, 0x65C52D24, + 0x119B4BE9, 0x155A565E, 0x18197087, 0x1CD86D30, 0x029F3D35, 0x065E2082, 0x0B1D065B, 0x0FDC1BEC, 0x3793A651, 0x3352BBE6, 0x3E119D3F, 0x3AD08088, 0x2497D08D, 0x2056CD3A, 0x2D15EBE3, 0x29D4F654, + 0xC5A92679, 0xC1683BCE, 0xCC2B1D17, 0xC8EA00A0, 0xD6AD50A5, 0xD26C4D12, 0xDF2F6BCB, 0xDBEE767C, 0xE3A1CBC1, 0xE760D676, 0xEA23F0AF, 0xEEE2ED18, 0xF0A5BD1D, 0xF464A0AA, 0xF9278673, 0xFDE69BC4, + 0x89B8FD09, 0x8D79E0BE, 0x803AC667, 0x84FBDBD0, 0x9ABC8BD5, 0x9E7D9662, 0x933EB0BB, 0x97FFAD0C, 0xAFB010B1, 0xAB710D06, 0xA6322BDF, 0xA2F33668, 0xBCB4666D, 0xB8757BDA, 0xB5365D03, 0xB1F740B4, +}; + +uint32_t CalcCRC(uint8_t * pData, uint32_t DataLength) +{ + uint32_t Checksum = 0xFFFFFFFF; + for(unsigned int i=0; i < DataLength; i++) + { + uint8_t top = (uint8_t)(Checksum >> 24); + top ^= pData[i]; + Checksum = (Checksum << 8) ^ crc_table[top]; + } + return Checksum; +} + void delay(uint32_t us) { #ifdef _WIN32 @@ -55,11 +86,13 @@ bool is_ack_resp_received( int comport ) ETX_OTA_RESP_ *resp = (ETX_OTA_RESP_*) DATA_BUF; if( resp->packet_type == ETX_OTA_PACKET_TYPE_RESPONSE ) { - //TODO: Add CRC check - if( resp->status == ETX_OTA_ACK ) + if( resp->crc == CalcCRC(&resp->status, 1) ) { - //ACK received - is_ack = true; + if( resp->status == ETX_OTA_ACK ) + { + //ACK received + is_ack = true; + } } } } @@ -80,7 +113,7 @@ int send_ota_start(int comport) ota_start->packet_type = ETX_OTA_PACKET_TYPE_CMD; ota_start->data_len = 1; ota_start->cmd = ETX_OTA_CMD_START; - ota_start->crc = 0x00; //TODO: Add CRC + ota_start->crc = CalcCRC( &ota_start->cmd, 1); ota_start->eof = ETX_OTA_EOF; len = sizeof(ETX_OTA_COMMAND_); @@ -124,7 +157,7 @@ uint16_t send_ota_end(int comport) ota_end->packet_type = ETX_OTA_PACKET_TYPE_CMD; ota_end->data_len = 1; ota_end->cmd = ETX_OTA_CMD_END; - ota_end->crc = 0x00; //TODO: Add CRC + ota_end->crc = CalcCRC( &ota_end->cmd, 1); ota_end->eof = ETX_OTA_EOF; len = sizeof(ETX_OTA_COMMAND_); @@ -167,7 +200,7 @@ int send_ota_header(int comport, meta_info *ota_info) ota_header->sof = ETX_OTA_SOF; ota_header->packet_type = ETX_OTA_PACKET_TYPE_HEADER; ota_header->data_len = sizeof(meta_info); - ota_header->crc = 0x00; //TODO: Add CRC + ota_header->crc = CalcCRC( (uint8_t*)ota_info, sizeof(meta_info)); ota_header->eof = ETX_OTA_EOF; memcpy(&ota_header->meta_data, ota_info, sizeof(meta_info) ); @@ -218,9 +251,9 @@ int send_ota_data(int comport, uint8_t *data, uint16_t data_len) //Copy the data memcpy(&DATA_BUF[len], data, data_len ); len += data_len; - uint32_t crc = 0u; //TODO: Add CRC - //Copy the crc + //Calculate and Copy the crc + uint32_t crc = CalcCRC( data, data_len); memcpy(&DATA_BUF[len], (uint8_t*)&crc, sizeof(crc) ); len += sizeof(crc); @@ -313,10 +346,18 @@ int main(int argc, char *argv[]) printf("File size = %d\n", app_size); + //read the full image + if( fread( APP_BIN, 1, app_size, Fptr ) != app_size ) + { + printf("App/FW read Error\n"); + ex = -1; + break; + } + //Send OTA Header meta_info ota_info; ota_info.package_size = app_size; - ota_info.package_crc = 0; //TODO: Add CRC + ota_info.package_crc = CalcCRC( APP_BIN, app_size); ex = send_ota_header( comport, &ota_info ); if( ex < 0 ) @@ -325,14 +366,6 @@ int main(int argc, char *argv[]) break; } - //read the full image - if( fread( APP_BIN, 1, app_size, Fptr ) != app_size ) - { - printf("App/FW read Error\n"); - ex = -1; - break; - } - uint16_t size = 0; for( uint32_t i = 0; i < app_size; )