Skip to content

Commit 9b66bfb

Browse files
torvaldstorvalds
committed
Merge branch 'x86-uv-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 UV debug changes from Ingo Molnar: "Various SGI UV debuggability improvements, amongst them KDB support, with related core KDB enabling patches changing kernel/debug/kdb/" * 'x86-uv-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: Revert "x86/UV: Add uvtrace support" x86/UV: Add call to KGDB/KDB from NMI handler kdb: Add support for external NMI handler to call KGDB/KDB x86/UV: Check for alloc_cpumask_var() failures properly in uv_nmi_setup() x86/UV: Add uvtrace support x86/UV: Add kdump to UV NMI handler x86/UV: Add summary of cpu activity to UV NMI handler x86/UV: Update UV support for external NMI signals x86/UV: Move NMI support
2 parents c213630 + b5dfcb0 commit 9b66bfb

12 files changed

Lines changed: 832 additions & 75 deletions

File tree

‎arch/x86/include/asm/uv/uv.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@ extern enum uv_system_type get_uv_system_type(void);
1212
extern int is_uv_system(void);
1313
extern void uv_cpu_init(void);
1414
extern void uv_nmi_init(void);
15+
extern void uv_register_nmi_notifier(void);
1516
extern void uv_system_init(void);
1617
extern const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
1718
struct mm_struct *mm,
@@ -25,6 +26,7 @@ static inline enum uv_system_type get_uv_system_type(void) { return UV_NONE; }
2526
static inline int is_uv_system(void) { return 0; }
2627
static inline void uv_cpu_init(void) { }
2728
static inline void uv_system_init(void) { }
29+
static inline void uv_register_nmi_notifier(void) { }
2830
static inline const struct cpumask *
2931
uv_flush_tlb_others(const struct cpumask *cpumask, struct mm_struct *mm,
3032
unsigned long start, unsigned long end, unsigned int cpu)

‎arch/x86/include/asm/uv/uv_hub.h‎

Lines changed: 55 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -502,8 +502,8 @@ struct uv_blade_info {
502502
unsigned short nr_online_cpus;
503503
unsigned short pnode;
504504
short memory_nid;
505-
spinlock_t nmi_lock;
506-
unsigned long nmi_count;
505+
spinlock_t nmi_lock; /* obsolete, see uv_hub_nmi */
506+
unsigned long nmi_count; /* obsolete, see uv_hub_nmi */
507507
};
508508
extern struct uv_blade_info *uv_blade_info;
509509
extern short *uv_node_to_blade;
@@ -576,6 +576,59 @@ static inline int uv_num_possible_blades(void)
576576
return uv_possible_blades;
577577
}
578578

579+
/* Per Hub NMI support */
580+
extern void uv_nmi_setup(void);
581+
582+
/* BMC sets a bit this MMR non-zero before sending an NMI */
583+
#define UVH_NMI_MMR UVH_SCRATCH5
584+
#define UVH_NMI_MMR_CLEAR UVH_SCRATCH5_ALIAS
585+
#define UVH_NMI_MMR_SHIFT 63
586+
#define UVH_NMI_MMR_TYPE "SCRATCH5"
587+
588+
/* Newer SMM NMI handler, not present in all systems */
589+
#define UVH_NMI_MMRX UVH_EVENT_OCCURRED0
590+
#define UVH_NMI_MMRX_CLEAR UVH_EVENT_OCCURRED0_ALIAS
591+
#define UVH_NMI_MMRX_SHIFT (is_uv1_hub() ? \
592+
UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT :\
593+
UVXH_EVENT_OCCURRED0_EXTIO_INT0_SHFT)
594+
#define UVH_NMI_MMRX_TYPE "EXTIO_INT0"
595+
596+
/* Non-zero indicates newer SMM NMI handler present */
597+
#define UVH_NMI_MMRX_SUPPORTED UVH_EXTIO_INT0_BROADCAST
598+
599+
/* Indicates to BIOS that we want to use the newer SMM NMI handler */
600+
#define UVH_NMI_MMRX_REQ UVH_SCRATCH5_ALIAS_2
601+
#define UVH_NMI_MMRX_REQ_SHIFT 62
602+
603+
struct uv_hub_nmi_s {
604+
raw_spinlock_t nmi_lock;
605+
atomic_t in_nmi; /* flag this node in UV NMI IRQ */
606+
atomic_t cpu_owner; /* last locker of this struct */
607+
atomic_t read_mmr_count; /* count of MMR reads */
608+
atomic_t nmi_count; /* count of true UV NMIs */
609+
unsigned long nmi_value; /* last value read from NMI MMR */
610+
};
611+
612+
struct uv_cpu_nmi_s {
613+
struct uv_hub_nmi_s *hub;
614+
atomic_t state;
615+
atomic_t pinging;
616+
int queries;
617+
int pings;
618+
};
619+
620+
DECLARE_PER_CPU(struct uv_cpu_nmi_s, __uv_cpu_nmi);
621+
#define uv_cpu_nmi (__get_cpu_var(__uv_cpu_nmi))
622+
#define uv_hub_nmi (uv_cpu_nmi.hub)
623+
#define uv_cpu_nmi_per(cpu) (per_cpu(__uv_cpu_nmi, cpu))
624+
#define uv_hub_nmi_per(cpu) (uv_cpu_nmi_per(cpu).hub)
625+
626+
/* uv_cpu_nmi_states */
627+
#define UV_NMI_STATE_OUT 0
628+
#define UV_NMI_STATE_IN 1
629+
#define UV_NMI_STATE_DUMP 2
630+
#define UV_NMI_STATE_DUMP_DONE 3
631+
579632
/* Update SCIR state */
580633
static inline void uv_set_scir_bits(unsigned char value)
581634
{

‎arch/x86/include/asm/uv/uv_mmrs.h‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -460,6 +460,23 @@ union uvh_event_occurred0_u {
460460
#define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0
461461

462462

463+
/* ========================================================================= */
464+
/* UVH_EXTIO_INT0_BROADCAST */
465+
/* ========================================================================= */
466+
#define UVH_EXTIO_INT0_BROADCAST 0x61448UL
467+
#define UVH_EXTIO_INT0_BROADCAST_32 0x3f0
468+
469+
#define UVH_EXTIO_INT0_BROADCAST_ENABLE_SHFT 0
470+
#define UVH_EXTIO_INT0_BROADCAST_ENABLE_MASK 0x0000000000000001UL
471+
472+
union uvh_extio_int0_broadcast_u {
473+
unsigned long v;
474+
struct uvh_extio_int0_broadcast_s {
475+
unsigned long enable:1; /* RW */
476+
unsigned long rsvd_1_63:63;
477+
} s;
478+
};
479+
463480
/* ========================================================================= */
464481
/* UVH_GR0_TLB_INT0_CONFIG */
465482
/* ========================================================================= */
@@ -2605,6 +2622,20 @@ union uvh_scratch5_u {
26052622
} s;
26062623
};
26072624

2625+
/* ========================================================================= */
2626+
/* UVH_SCRATCH5_ALIAS */
2627+
/* ========================================================================= */
2628+
#define UVH_SCRATCH5_ALIAS 0x2d0208UL
2629+
#define UVH_SCRATCH5_ALIAS_32 0x780
2630+
2631+
2632+
/* ========================================================================= */
2633+
/* UVH_SCRATCH5_ALIAS_2 */
2634+
/* ========================================================================= */
2635+
#define UVH_SCRATCH5_ALIAS_2 0x2d0210UL
2636+
#define UVH_SCRATCH5_ALIAS_2_32 0x788
2637+
2638+
26082639
/* ========================================================================= */
26092640
/* UVXH_EVENT_OCCURRED2 */
26102641
/* ========================================================================= */

‎arch/x86/kernel/apic/x2apic_uv_x.c‎

Lines changed: 1 addition & 69 deletions
Original file line numberDiff line numberDiff line change
@@ -39,12 +39,6 @@
3939
#include <asm/x86_init.h>
4040
#include <asm/nmi.h>
4141

42-
/* BMC sets a bit this MMR non-zero before sending an NMI */
43-
#define UVH_NMI_MMR UVH_SCRATCH5
44-
#define UVH_NMI_MMR_CLEAR (UVH_NMI_MMR + 8)
45-
#define UV_NMI_PENDING_MASK (1UL << 63)
46-
DEFINE_PER_CPU(unsigned long, cpu_last_nmi_count);
47-
4842
DEFINE_PER_CPU(int, x2apic_extra_bits);
4943

5044
#define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args)
@@ -58,7 +52,6 @@ int uv_min_hub_revision_id;
5852
EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
5953
unsigned int uv_apicid_hibits;
6054
EXPORT_SYMBOL_GPL(uv_apicid_hibits);
61-
static DEFINE_SPINLOCK(uv_nmi_lock);
6255

6356
static struct apic apic_x2apic_uv_x;
6457

@@ -847,68 +840,6 @@ void uv_cpu_init(void)
847840
set_x2apic_extra_bits(uv_hub_info->pnode);
848841
}
849842

850-
/*
851-
* When NMI is received, print a stack trace.
852-
*/
853-
int uv_handle_nmi(unsigned int reason, struct pt_regs *regs)
854-
{
855-
unsigned long real_uv_nmi;
856-
int bid;
857-
858-
/*
859-
* Each blade has an MMR that indicates when an NMI has been sent
860-
* to cpus on the blade. If an NMI is detected, atomically
861-
* clear the MMR and update a per-blade NMI count used to
862-
* cause each cpu on the blade to notice a new NMI.
863-
*/
864-
bid = uv_numa_blade_id();
865-
real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK);
866-
867-
if (unlikely(real_uv_nmi)) {
868-
spin_lock(&uv_blade_info[bid].nmi_lock);
869-
real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK);
870-
if (real_uv_nmi) {
871-
uv_blade_info[bid].nmi_count++;
872-
uv_write_local_mmr(UVH_NMI_MMR_CLEAR, UV_NMI_PENDING_MASK);
873-
}
874-
spin_unlock(&uv_blade_info[bid].nmi_lock);
875-
}
876-
877-
if (likely(__get_cpu_var(cpu_last_nmi_count) == uv_blade_info[bid].nmi_count))
878-
return NMI_DONE;
879-
880-
__get_cpu_var(cpu_last_nmi_count) = uv_blade_info[bid].nmi_count;
881-
882-
/*
883-
* Use a lock so only one cpu prints at a time.
884-
* This prevents intermixed output.
885-
*/
886-
spin_lock(&uv_nmi_lock);
887-
pr_info("UV NMI stack dump cpu %u:\n", smp_processor_id());
888-
dump_stack();
889-
spin_unlock(&uv_nmi_lock);
890-
891-
return NMI_HANDLED;
892-
}
893-
894-
void uv_register_nmi_notifier(void)
895-
{
896-
if (register_nmi_handler(NMI_UNKNOWN, uv_handle_nmi, 0, "uv"))
897-
printk(KERN_WARNING "UV NMI handler failed to register\n");
898-
}
899-
900-
void uv_nmi_init(void)
901-
{
902-
unsigned int value;
903-
904-
/*
905-
* Unmask NMI on all cpus
906-
*/
907-
value = apic_read(APIC_LVT1) | APIC_DM_NMI;
908-
value &= ~APIC_LVT_MASKED;
909-
apic_write(APIC_LVT1, value);
910-
}
911-
912843
void __init uv_system_init(void)
913844
{
914845
union uvh_rh_gam_config_mmr_u m_n_config;
@@ -1046,6 +977,7 @@ void __init uv_system_init(void)
1046977
map_mmr_high(max_pnode);
1047978
map_mmioh_high(min_pnode, max_pnode);
1048979

980+
uv_nmi_setup();
1049981
uv_cpu_init();
1050982
uv_scir_register_cpu_notifier();
1051983
uv_register_nmi_notifier();

‎arch/x86/platform/uv/Makefile‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
obj-$(CONFIG_X86_UV) += tlb_uv.o bios_uv.o uv_irq.o uv_sysfs.o uv_time.o
1+
obj-$(CONFIG_X86_UV) += tlb_uv.o bios_uv.o uv_irq.o uv_sysfs.o uv_time.o uv_nmi.o

0 commit comments

Comments
 (0)