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Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer changes from Ingo Molnar: "Main changes in this cycle were: - Updated full dynticks support. - Event stream support for architected (ARM) timers. - ARM clocksource driver updates. - Move arm64 to using the generic sched_clock framework & resulting cleanup in the generic sched_clock code. - Misc fixes and cleanups" * 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (50 commits) x86/time: Honor ACPI FADT flag indicating absence of a CMOS RTC clocksource: sun4i: remove IRQF_DISABLED clocksource: sun4i: Report the minimum tick that we can program clocksource: sun4i: Select CLKSRC_MMIO clocksource: Provide timekeeping for efm32 SoCs clocksource: em_sti: convert to clk_prepare/unprepare time: Fix signedness bug in sysfs_get_uname() and its callers timekeeping: Fix some trivial typos in comments alarmtimer: return EINVAL instead of ENOTSUPP if rtcdev doesn't exist clocksource: arch_timer: Do not register arch_sys_counter twice timer stats: Add a 'Collection: active/inactive' line to timer usage statistics sched_clock: Remove sched_clock_func() hook arch_timer: Move to generic sched_clock framework clocksource: tcb_clksrc: Remove IRQF_DISABLED clocksource: tcb_clksrc: Improve driver robustness clocksource: tcb_clksrc: Replace clk_enable/disable with clk_prepare_enable/disable_unprepare clocksource: arm_arch_timer: Use clocksource for suspend timekeeping clocksource: dw_apb_timer_of: Mark a few more functions as __init clocksource: Put nodes passed to CLOCKSOURCE_OF_DECLARE callbacks centrally arm: zynq: Enable arm_global_timer ...
2 parents 39cf275 + ee5872b commit 8709382

54 files changed

Lines changed: 717 additions & 189 deletions

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‎Documentation/devicetree/bindings/timer/efm32,timer.txt‎

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@@ -0,0 +1,23 @@
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* EFM32 timer hardware
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The efm32 Giant Gecko SoCs come with four 16 bit timers. Two counters can be
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connected to form a 32 bit counter. Each timer has three Compare/Capture
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channels and can be used as PWM or Quadrature Decoder. Available clock sources
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are the cpu's HFPERCLK (with a 10-bit prescaler) or an external pin.
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Required properties:
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- compatible : Should be efm32,timer
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- reg : Address and length of the register set
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- clocks : Should contain a reference to the HFPERCLK
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Optional properties:
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- interrupts : Reference to the timer interrupt
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Example:
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timer@40010c00 {
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compatible = "efm32,timer";
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reg = <0x40010c00 0x400>;
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interrupts = <14>;
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clocks = <&cmu clk_HFPERCLKTIMER3>;
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};

‎arch/Kconfig‎

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@@ -353,6 +353,18 @@ config HAVE_CONTEXT_TRACKING
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config HAVE_VIRT_CPU_ACCOUNTING
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bool
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config HAVE_VIRT_CPU_ACCOUNTING_GEN
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bool
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default y if 64BIT
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help
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With VIRT_CPU_ACCOUNTING_GEN, cputime_t becomes 64-bit.
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Before enabling this option, arch code must be audited
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to ensure there are no races in concurrent read/write of
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cputime_t. For example, reading/writing 64-bit cputime_t on
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some 32-bit arches may require multiple accesses, so proper
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locking is needed to protect against concurrent accesses.
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config HAVE_IRQ_TIME_ACCOUNTING
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bool
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help

‎arch/arm/Kconfig‎

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@@ -54,6 +54,7 @@ config ARM
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select HAVE_REGS_AND_STACK_ACCESS_API
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select HAVE_SYSCALL_TRACEPOINTS
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select HAVE_UID16
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select HAVE_VIRT_CPU_ACCOUNTING_GEN
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select IRQ_FORCED_THREADING
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select KTIME_SCALAR
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select MODULES_USE_ELF_REL

‎arch/arm/boot/dts/zynq-7000.dtsi‎

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@@ -92,6 +92,14 @@
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};
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};
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global_timer: timer@f8f00200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0xf8f00200 0x20>;
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interrupts = <1 11 0x301>;
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interrupt-parent = <&intc>;
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clocks = <&clkc 4>;
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};
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ttc0: ttc0@f8001000 {
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interrupt-parent = <&intc>;
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interrupts = < 0 10 4 0 11 4 0 12 4 >;

‎arch/arm/include/asm/arch_timer.h‎

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@@ -87,17 +87,43 @@ static inline u64 arch_counter_get_cntvct(void)
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return cval;
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}
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static inline void arch_counter_set_user_access(void)
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static inline u32 arch_timer_get_cntkctl(void)
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{
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u32 cntkctl;
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asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl));
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return cntkctl;
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}
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/* disable user access to everything */
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cntkctl &= ~((3 << 8) | (7 << 0));
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static inline void arch_timer_set_cntkctl(u32 cntkctl)
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{
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asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
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}
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static inline void arch_counter_set_user_access(void)
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{
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u32 cntkctl = arch_timer_get_cntkctl();
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/* Disable user access to both physical/virtual counters/timers */
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/* Also disable virtual event stream */
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cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
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| ARCH_TIMER_USR_VT_ACCESS_EN
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| ARCH_TIMER_VIRT_EVT_EN
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| ARCH_TIMER_USR_VCT_ACCESS_EN
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| ARCH_TIMER_USR_PCT_ACCESS_EN);
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arch_timer_set_cntkctl(cntkctl);
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}
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static inline void arch_timer_evtstrm_enable(int divider)
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{
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u32 cntkctl = arch_timer_get_cntkctl();
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cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
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/* Set the divider and enable virtual event stream */
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cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
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| ARCH_TIMER_VIRT_EVT_EN;
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arch_timer_set_cntkctl(cntkctl);
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elf_hwcap |= HWCAP_EVTSTRM;
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}
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#endif
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#endif

‎arch/arm/include/uapi/asm/hwcap.h‎

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#define HWCAP_VFPD32 (1 << 19) /* set if VFP has 32 regs (not 16) */
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#define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT)
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#define HWCAP_LPAE (1 << 20)
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#define HWCAP_EVTSTRM (1 << 21)
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#endif /* _UAPI__ASMARM_HWCAP_H */

‎arch/arm/kernel/arch_timer.c‎

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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/sched_clock.h>
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#include <asm/delay.h>
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return arch_timer_read_counter();
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}
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static u32 sched_clock_mult __read_mostly;
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static unsigned long long notrace arch_timer_sched_clock(void)
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{
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return arch_timer_read_counter() * sched_clock_mult;
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}
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static struct delay_timer arch_delay_timer;
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static void __init arch_timer_delay_timer_register(void)
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arch_timer_delay_timer_register();
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/* Cache the sched_clock multiplier to save a divide in the hot path. */
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sched_clock_mult = NSEC_PER_SEC / arch_timer_rate;
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sched_clock_func = arch_timer_sched_clock;
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pr_info("sched_clock: ARM arch timer >56 bits at %ukHz, resolution %uns\n",
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arch_timer_rate / 1000, sched_clock_mult);
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return 0;
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}

‎arch/arm/kernel/setup.c‎

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"idivt",
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"vfpd32",
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"lpae",
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"evtstrm",
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NULL
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};
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‎arch/arm/mach-msm/timer.c‎

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pr_err("Unknown frequency\n");
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return;
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}
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of_node_put(np);
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event_base = base + 0x4;
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sts_base = base + 0x88;

‎arch/arm/mach-zynq/Kconfig‎

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select HAVE_SMP
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select SPARSE_IRQ
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select CADENCE_TTC_TIMER
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select ARM_GLOBAL_TIMER
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help
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Support for Xilinx Zynq ARM Cortex A9 Platform

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