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Merge tag 'rtc-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
Pull RTC updates from Alexandre Belloni: "Subsystem: - constify rtc_class_ops structures New driver: - STM32 Drivers: - armada38x: fix errata, Armada 7K/8K support - ds3232: fix wakeup support - gemini: DT support - m48t86: huge cleanup and platform_data removal - mcp795: alarm support - sun6i: proper oscillator handling - tegra: proper clock handling - tps65910: calibration support" * tag 'rtc-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux: (44 commits) rtc: ds3232: Call device_init_wakeup before device_register rtc: pcf2127: bulk read only date and time registers. rtc: armada38x: Add support for Armada 7K/8K rtc: armada38x: Prepare driver to manage different versions rtc: ds3232: Add regmap max_register definition. rtc: ds3232: Cleanup whitespace around register and bit definitions. rtc: m48t86: remove unused platform_data ARM: Orion5x: ts78xx: allow rtc-m48t86 to manage it's own resources ARM: Orion5x: ts78xx: remove RTC detection ARM: ep93xx: ts72xx: allow rtc-m48t86 to manage its own resources rtc: m48t86: verify that the RTC is actually present rtc: m48t86: add NVRAM support rtc: m48t86: allow driver to manage its resources rtc: m48t86: shorten register name defines bindings: rtc: correct wrong reference in required properties rtc: sun6i: Fix return value check in sun6i_rtc_clk_init() rtc: sun6i: extend test coverage rtc: sun6i: Fix compatibility with old DT binding rtc: snvs: add a missing write sync rtc: bq32000: add support to enable disable the trickle charge FET bypass ...
2 parents 45554b2 + d4f6c6f commit 5782fd1

35 files changed

Lines changed: 1956 additions & 376 deletions

‎Documentation/ABI/testing/sysfs-bus-i2c-devices-bq32k‎

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What: /sys/bus/i2c/devices/.../trickle_charge_bypass
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Date: Jan 2017
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KernelVersion: 4.11
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Contact: Enric Balletbo i Serra <eballetbo@gmail.com>
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Description: Attribute for enable/disable the trickle charge bypass
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The trickle_charge_bypass attribute allows the userspace to
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enable/disable the Trickle charge FET bypass.

‎Documentation/devicetree/bindings/rtc/armada-380-rtc.txt‎

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* Real Time Clock of the Armada 38x SoCs
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* Real Time Clock of the Armada 38x/7K/8K SoCs
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3-
RTC controller for the Armada 38x SoCs
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RTC controller for the Armada 38x, 7K and 8K SoCs
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Required properties:
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- compatible : Should be "marvell,armada-380-rtc"
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- compatible : Should be one of the following:
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"marvell,armada-380-rtc" for Armada 38x SoC
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"marvell,armada-8k-rtc" for Aramda 7K/8K SoCs
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- reg: a list of base address and size pairs, one for each entry in
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reg-names
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- reg names: should contain:

‎Documentation/devicetree/bindings/rtc/cortina,gemini.txt‎

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* Cortina Systems Gemini RTC
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Gemini SoC real-time clock.
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Required properties:
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- compatible : Should be "cortina,gemini-rtc"
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Examples:
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rtc@45000000 {
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compatible = "cortina,gemini-rtc";
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reg = <0x45000000 0x100>;
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interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
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};

‎Documentation/devicetree/bindings/rtc/imxdi-rtc.txt‎

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@@ -8,10 +8,13 @@ Required properties:
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region.
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- interrupts: rtc alarm interrupt
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Optional properties:
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- interrupts: dryice security violation interrupt
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Example:
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rtc@80056000 {
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compatible = "fsl,imx53-rtc", "fsl,imx25-rtc";
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reg = <0x80056000 2000>;
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interrupts = <29>;
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interrupts = <29 56>;
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};

‎Documentation/devicetree/bindings/rtc/maxim,ds3231.txt‎

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* Maxim DS3231 Real Time Clock
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Required properties:
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see: Documentation/devicetree/bindings/i2c/trivial-admin-guide/devices.rst
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- compatible: Should contain "maxim,ds3231".
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- reg: I2C address for chip.
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Optional property:
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- #clock-cells: Should be 1.

‎Documentation/devicetree/bindings/rtc/pcf8563.txt‎

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@@ -3,7 +3,8 @@
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Philips PCF8563/Epson RTC8564 Real Time Clock
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Required properties:
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see: Documentation/devicetree/bindings/i2c/trivial-admin-guide/devices.rst
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- compatible: Should contain "nxp,pcf8563".
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- reg: I2C address for chip.
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Optional property:
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- #clock-cells: Should be 0.

‎Documentation/devicetree/bindings/rtc/st,stm32-rtc.txt‎

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STM32 Real Time Clock
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Required properties:
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- compatible: "st,stm32-rtc".
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- reg: address range of rtc register set.
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- clocks: reference to the clock entry ck_rtc.
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- interrupt-parent: phandle for the interrupt controller.
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- interrupts: rtc alarm interrupt.
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- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
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(RTC registers) write protection.
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Optional properties (to override default ck_rtc parent clock):
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- assigned-clocks: reference to the ck_rtc clock entry.
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- assigned-clock-parents: phandle of the new parent clock of ck_rtc.
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Example:
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rtc: rtc@40002800 {
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compatible = "st,stm32-rtc";
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reg = <0x40002800 0x400>;
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clocks = <&rcc 1 CLK_RTC>;
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assigned-clocks = <&rcc 1 CLK_RTC>;
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assigned-clock-parents = <&rcc 1 CLK_LSE>;
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interrupt-parent = <&exti>;
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interrupts = <17 1>;
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st,syscfg = <&pwrcfg>;
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};

‎Documentation/devicetree/bindings/rtc/sun6i-rtc.txt‎

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memory mapped region.
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- interrupts : IRQ lines for the RTC alarm 0 and alarm 1, in that order.
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Required properties for new device trees
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- clocks : phandle to the 32kHz external oscillator
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- clock-output-names : name of the LOSC clock created
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- #clock-cells : must be equals to 1. The RTC provides two clocks: the
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LOSC and its external output, with index 0 and 1
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respectively.
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Example:
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rtc: rtc@01f00000 {
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compatible = "allwinner,sun6i-a31-rtc";
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reg = <0x01f00000 0x54>;
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interrupts = <0 40 4>, <0 41 4>;
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clock-output-names = "osc32k";
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clocks = <&ext_osc32k>;
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#clock-cells = <1>;
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};

‎arch/arm/mach-ep93xx/ts72xx.c‎

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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/platform_data/rtc-m48t86.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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.pfn = __phys_to_pfn(TS72XX_OPTIONS2_PHYS_BASE),
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.length = TS72XX_OPTIONS2_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)TS72XX_RTC_INDEX_VIRT_BASE,
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.pfn = __phys_to_pfn(TS72XX_RTC_INDEX_PHYS_BASE),
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.length = TS72XX_RTC_INDEX_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)TS72XX_RTC_DATA_VIRT_BASE,
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.pfn = __phys_to_pfn(TS72XX_RTC_DATA_PHYS_BASE),
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.length = TS72XX_RTC_DATA_SIZE,
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.type = MT_DEVICE,
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}
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};
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}
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}
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/*************************************************************************
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* RTC M48T86
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*************************************************************************/
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#define TS72XX_RTC_INDEX_PHYS_BASE (EP93XX_CS1_PHYS_BASE + 0x00800000)
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#define TS72XX_RTC_DATA_PHYS_BASE (EP93XX_CS1_PHYS_BASE + 0x01700000)
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183-
static unsigned char ts72xx_rtc_readbyte(unsigned long addr)
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{
185-
__raw_writeb(addr, TS72XX_RTC_INDEX_VIRT_BASE);
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return __raw_readb(TS72XX_RTC_DATA_VIRT_BASE);
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}
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189-
static void ts72xx_rtc_writebyte(unsigned char value, unsigned long addr)
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{
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__raw_writeb(addr, TS72XX_RTC_INDEX_VIRT_BASE);
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__raw_writeb(value, TS72XX_RTC_DATA_VIRT_BASE);
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}
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195-
static struct m48t86_ops ts72xx_rtc_ops = {
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.readbyte = ts72xx_rtc_readbyte,
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.writebyte = ts72xx_rtc_writebyte,
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static struct resource ts72xx_rtc_resources[] = {
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DEFINE_RES_MEM(TS72XX_RTC_INDEX_PHYS_BASE, 0x01),
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DEFINE_RES_MEM(TS72XX_RTC_DATA_PHYS_BASE, 0x01),
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};
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200182
static struct platform_device ts72xx_rtc_device = {
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.name = "rtc-m48t86",
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.id = -1,
203-
.dev = {
204-
.platform_data = &ts72xx_rtc_ops,
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},
206-
.num_resources = 0,
185+
.resource = ts72xx_rtc_resources,
186+
.num_resources = ARRAY_SIZE(ts72xx_rtc_resources),
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};
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209189
static struct resource ts72xx_wdt_resources[] = {

‎arch/arm/mach-ep93xx/ts72xx.h‎

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* febff000 22000000 4K model number register (bits 0-2)
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* febfe000 22400000 4K options register
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* febfd000 22800000 4K options register #2
12-
* febf9000 10800000 4K TS-5620 RTC index register
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* febf8000 11700000 4K TS-5620 RTC data register
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*/
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#define TS72XX_MODEL_PHYS_BASE 0x22000000
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#define TS72XX_OPTIONS2_TS9420 0x04
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#define TS72XX_OPTIONS2_TS9420_BOOT 0x02
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44-
#define TS72XX_RTC_INDEX_VIRT_BASE IOMEM(0xfebf9000)
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#define TS72XX_RTC_INDEX_PHYS_BASE 0x10800000
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#define TS72XX_RTC_INDEX_SIZE 0x00001000
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48-
#define TS72XX_RTC_DATA_VIRT_BASE IOMEM(0xfebf8000)
49-
#define TS72XX_RTC_DATA_PHYS_BASE 0x11700000
50-
#define TS72XX_RTC_DATA_SIZE 0x00001000
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#define TS72XX_WDT_CONTROL_PHYS_BASE 0x23800000
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#define TS72XX_WDT_FEED_PHYS_BASE 0x23c00000
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