Experimental methodology tested to improve bimodal and perceptron branching #721

I've developing a generic methodology to improve performance of data processing algorithms, including branch caching algorithms.

This is the first experiment. I've attempted to significantly improve performance within hardware, and simulation results are very promising. I cannot test further, and cannot determine power improvements, if any, so the experiment is over.

The conclusion is that the methodology, when applied to the source code, produces identical operation, decreased workload and overall better efficiency in the algorithms - to a worthwhile degree. This result confirms further development of the methodology is warranted.

The methodology is not currently disclosed. I would love to hear if anyone can test this further, as CPU Architecture is not a subject I know a lot about. Details here:

https://github.com/SimBuddy/WOBBranchPredictor/blob/main/README.md