Modeling Bandwidth in Caches #529

I'm trying to model the Golden Cove architecture, but it looks like I cannot actually limit ChampSim's bandwidth between the different caches. For example, to model a 16 byte/cycle bandwidth between the L1I and L2C caches, I would expect to set L1I's FILL_LATENCY to 4 and its MAX_FILL to 1. The intuition behind this is that the L1I cache can fill one cache block at a time, and it takes four cycles to fill that cache block. However, MAX_FILL does not limit the number of cache blocks that can be transmitted between two caches, it only limits the number of cache blocks that can be returned each cycle. Each cache block that needs to be filled will be ready to return to the upper level exactly FILL_LATENCY cycles after it is returned by the lower level cache. Thus, if the lower level cache happens to return several cache blocks within quick succession, the overall bandwidth can surpass the desired limit.

To double-check that my understanding of the code is correct, I instrumented ChampSim to print out the number of actively filling cache blocks each cycle. Even with MAX_FILL=1, there are many times where more than one cache block is being actively filled from the lower level cache.

This does have a performance impact: consider an example with a desired bandwidth of 16 bytes/cycle, where FILL_LATENCY=4 and MAX_FILL = 1. The lower level cache returns two cache blocks at times 0 and 1, respectively. The desired behavior is for it to take 8 cycles to transmit both cache blocks (bw = 128 / 8 = 16). However, ChampSim will transmit both cache blocks by cycle 5, surpassing the desired bandwidth (bw = 128 / 5 > 16).

This isn't necessarily a bug in ChampSim, but I don't believe it is desired behavior. A potential solution is to wait to start transmitting a cache block from the lower level cache until there are less than MAX_FILL currently transmitting cache blocks.