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Make stand alone logic analyzer circuits.
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‎Benchy_Sump_LogicAnalyzer_Standalone/Benchy_Sump_LogicAnalyzer_Standalone.ino‎

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/*
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Gadget Factory - Project Name
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Stand Alone Sump "Blaze" Logic Analyzer with 32 BRAM blocks (64KB) and 16 channels.
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To learn more about using DesignLab please visit http://learn.gadgetfactory.net
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Tutorials:
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Related library documentation:
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Hardware:
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Special Notes:
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If you want to generate a signal to test with then you can load this sketch to the AVR of the Papilio DUO. You will see a UART signal on channel0
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created 2014
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by Jack Gassett
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http://www.gadgetfactory.net
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This example code is in the public domain.
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*/
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int counter = 0;
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void setup() {
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// put your setup code here, to run once:
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Serial1.begin(115200);
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}
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void loop() {
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// put your main code here, to run repeatedly:
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Serial1.write(counter);
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counter++;
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delay(1);
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}

‎Benchy_Sump_LogicAnalyzer_Standalone/circuit/250K/Papilio_One_250K.ut‎

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-w
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-g DebugBitstream:No
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-g Binary:no
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-g CRC:Enable
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-g ConfigRate:1
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-g ProgPin:PullUp
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-g DonePin:PullUp
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-g TckPin:PullUp
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-g TdiPin:PullUp
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-g TdoPin:PullUp
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-g TmsPin:PullUp
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-g UnusedPin:PullDown
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-g UserID:0xFFFFFFFF
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-g DCMShutdown:Disable
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-g StartUpClk:CClk
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-g DONE_cycle:4
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-g GTS_cycle:5
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-g GWE_cycle:6
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-g LCK_cycle:NoWait
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-g Security:None
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-g DonePipe:Yes
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-g DriveDone:No

‎Benchy_Sump_LogicAnalyzer_Standalone/circuit/250K/papilio_one_250k.bit‎

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‎Benchy_Sump_LogicAnalyzer_Standalone/circuit/DUO_LX9/Papilio_DUO_LX9.ut‎

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-w
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-g DebugBitstream:No
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-g Binary:no
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-g CRC:Enable
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-g Reset_on_err:No
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-g ConfigRate:2
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-g ProgPin:PullUp
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-g TckPin:PullUp
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-g TdiPin:PullUp
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-g TdoPin:PullUp
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-g TmsPin:PullUp
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-g UnusedPin:PullDown
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-g UserID:0xFFFFFFFF
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-g ExtMasterCclk_en:No
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-g SPI_buswidth:1
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-g TIMER_CFG:0xFFFF
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-g multipin_wakeup:No
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-g StartUpClk:CClk
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-g DONE_cycle:4
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-g GTS_cycle:5
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-g GWE_cycle:6
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-g LCK_cycle:NoWait
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-g Security:None
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-g DonePipe:Yes
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-g DriveDone:No
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-g en_sw_gsr:No
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-g drive_awake:No
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-g sw_clk:Startupclk
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-g sw_gwe_cycle:5
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-g sw_gts_cycle:4

‎Benchy_Sump_LogicAnalyzer_Standalone/circuit/DUO_LX9/papilio_duo_lx9.bit‎

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‎Benchy_Sump_LogicAnalyzer_Standalone/circuit/LX9/Papilio_Pro.ut‎

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-w
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-g DebugBitstream:No
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-g Binary:no
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-g CRC:Enable
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-g Reset_on_err:No
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-g ConfigRate:2
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-g ProgPin:PullUp
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-g TckPin:PullUp
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-g TdiPin:PullUp
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-g TdoPin:PullUp
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-g TmsPin:PullUp
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-g UnusedPin:PullDown
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-g UserID:0xFFFFFFFF
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-g ExtMasterCclk_en:No
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-g SPI_buswidth:1
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-g TIMER_CFG:0xFFFF
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-g multipin_wakeup:No
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-g StartUpClk:CClk
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-g DONE_cycle:4
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-g GTS_cycle:5
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-g GWE_cycle:6
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-g LCK_cycle:NoWait
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-g Security:None
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-g DonePipe:Yes
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-g DriveDone:No
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-g en_sw_gsr:No
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-g drive_awake:No
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-g sw_clk:Startupclk
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-g sw_gwe_cycle:5
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-g sw_gts_cycle:4

‎Benchy_Sump_LogicAnalyzer_Standalone/circuit/LX9/papilio_pro.bit‎

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‎Benchy_Sump_LogicAnalyzer_Standalone/circuit/PSL_Papilio_DUO_LX9.xise‎

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‎Benchy_Sump_LogicAnalyzer_Standalone/circuit/PSL_Papilio_One_250K.xise‎

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‎Benchy_Sump_LogicAnalyzer_Standalone/circuit/PSL_Papilio_One_500K.xise‎

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