Add riscv64 support in x9 and rANS (#15669)

Mahsuba · web-flow · commit 5d1f5199b8e6 · 2026-08-07T17:11:28.000+02:00
- x9.c: add a riscv64 branch to the arch guards, emitting the PAUSE hint (Zihintpause) as a raw .4byte encoding so it assembles regardless of -march and is a NOP on cores without the extension. - rANS defines.h: add riscv64 (64-bit) to the coder-detection guard so the existing scalar Compat/SingleStream coders are selected; no SIMD. Refs #15664
diff --git a/Framework/Foundation/3rdparty/x9/x9.c b/Framework/Foundation/3rdparty/x9/x9.c
@@ -38,6 +38,7 @@
 #if defined(__x86_64__) || defined(__i386__)
 #include <immintrin.h> /* _mm_pause */
 #elif defined(__aarch64__)
+#elif defined(__riscv)
 #else
 #error Not supported architecture
 #endif
@@ -370,6 +371,8 @@ void x9_read_from_inbox_spin(x9_inbox* const inbox,
     _mm_pause();
 #elif defined(__aarch64__)
     __asm__ __volatile__ ("yield");
+#elif defined(__riscv)
+    __asm__ __volatile__ (".4byte 0x0100000F"); /* PAUSE hint (Zihintpause); NOP if unsupported */
 #else
 #error Not supported architecture
 #endif
diff --git a/Utilities/rANS/include/rANS/internal/common/defines.h b/Utilities/rANS/include/rANS/internal/common/defines.h
@@ -40,7 +40,7 @@
 #error RANS_FMA cannot be directly set
 #endif
 
-#if (defined(__x86_64__) || defined(__aarch64__))
+#if (defined(__x86_64__) || defined(__aarch64__) || (defined(__riscv) && __riscv_xlen == 64))
 #define RANS_COMPAT
 #if defined(__SIZEOF_INT128__)
 #define RANS_SINGLE_STREAM
