| 1 | /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
| 2 | /* Copyright (c) 2021, Microsoft Corporation. */ |
| 3 | |
| 4 | #ifndef _HW_CHANNEL_H |
| 5 | #define _HW_CHANNEL_H |
| 6 | |
| 7 | #define DEFAULT_LOG2_THROTTLING_FOR_ERROR_EQ 4 |
| 8 | |
| 9 | #define HW_CHANNEL_MAX_REQUEST_SIZE 0x1000 |
| 10 | #define HW_CHANNEL_MAX_RESPONSE_SIZE 0x1000 |
| 11 | |
| 12 | #define HW_CHANNEL_VF_BOOTSTRAP_QUEUE_DEPTH 1 |
| 13 | |
| 14 | #define HWC_INIT_DATA_CQID 1 |
| 15 | #define HWC_INIT_DATA_RQID 2 |
| 16 | #define HWC_INIT_DATA_SQID 3 |
| 17 | #define HWC_INIT_DATA_QUEUE_DEPTH 4 |
| 18 | #define HWC_INIT_DATA_MAX_REQUEST 5 |
| 19 | #define HWC_INIT_DATA_MAX_RESPONSE 6 |
| 20 | #define HWC_INIT_DATA_MAX_NUM_CQS 7 |
| 21 | #define HWC_INIT_DATA_PDID 8 |
| 22 | #define HWC_INIT_DATA_GPA_MKEY 9 |
| 23 | #define HWC_INIT_DATA_PF_DEST_RQ_ID 10 |
| 24 | #define HWC_INIT_DATA_PF_DEST_CQ_ID 11 |
| 25 | |
| 26 | #define HWC_DATA_CFG_HWC_TIMEOUT 1 |
| 27 | #define HWC_DATA_HW_LINK_CONNECT 2 |
| 28 | #define HWC_DATA_HW_LINK_DISCONNECT 3 |
| 29 | |
| 30 | #define HW_CHANNEL_WAIT_RESOURCE_TIMEOUT_MS 30000 |
| 31 | |
| 32 | /* Structures labeled with "HW DATA" are exchanged with the hardware. All of |
| 33 | * them are naturally aligned and hence don't need __packed. |
| 34 | */ |
| 35 | |
| 36 | union hwc_init_eq_id_db { |
| 37 | u32 as_uint32; |
| 38 | |
| 39 | struct { |
| 40 | u32 eq_id : 16; |
| 41 | u32 doorbell : 16; |
| 42 | }; |
| 43 | }; /* HW DATA */ |
| 44 | |
| 45 | union hwc_init_type_data { |
| 46 | u32 as_uint32; |
| 47 | |
| 48 | struct { |
| 49 | u32 value : 24; |
| 50 | u32 type : 8; |
| 51 | }; |
| 52 | }; /* HW DATA */ |
| 53 | |
| 54 | union hwc_init_soc_service_type { |
| 55 | u32 as_uint32; |
| 56 | |
| 57 | struct { |
| 58 | u32 value : 28; |
| 59 | u32 type : 4; |
| 60 | }; |
| 61 | }; /* HW DATA */ |
| 62 | |
| 63 | struct hwc_rx_oob { |
| 64 | u32 type : 6; |
| 65 | u32 eom : 1; |
| 66 | u32 som : 1; |
| 67 | u32 vendor_err : 8; |
| 68 | u32 reserved1 : 16; |
| 69 | |
| 70 | u32 src_virt_wq : 24; |
| 71 | u32 src_vfid : 8; |
| 72 | |
| 73 | u32 reserved2; |
| 74 | |
| 75 | union { |
| 76 | u32 wqe_addr_low; |
| 77 | u32 wqe_offset; |
| 78 | }; |
| 79 | |
| 80 | u32 wqe_addr_high; |
| 81 | |
| 82 | u32 client_data_unit : 14; |
| 83 | u32 reserved3 : 18; |
| 84 | |
| 85 | u32 tx_oob_data_size; |
| 86 | |
| 87 | u32 chunk_offset : 21; |
| 88 | u32 reserved4 : 11; |
| 89 | }; /* HW DATA */ |
| 90 | |
| 91 | struct hwc_tx_oob { |
| 92 | u32 reserved1; |
| 93 | |
| 94 | u32 reserved2; |
| 95 | |
| 96 | u32 vrq_id : 24; |
| 97 | u32 dest_vfid : 8; |
| 98 | |
| 99 | u32 vrcq_id : 24; |
| 100 | u32 reserved3 : 8; |
| 101 | |
| 102 | u32 vscq_id : 24; |
| 103 | u32 loopback : 1; |
| 104 | u32 lso_override: 1; |
| 105 | u32 dest_pf : 1; |
| 106 | u32 reserved4 : 5; |
| 107 | |
| 108 | u32 vsq_id : 24; |
| 109 | u32 reserved5 : 8; |
| 110 | }; /* HW DATA */ |
| 111 | |
| 112 | struct hwc_work_request { |
| 113 | void *buf_va; |
| 114 | void *buf_sge_addr; |
| 115 | u32 buf_len; |
| 116 | u32 msg_size; |
| 117 | |
| 118 | struct gdma_wqe_request wqe_req; |
| 119 | struct hwc_tx_oob tx_oob; |
| 120 | |
| 121 | struct gdma_sge sge; |
| 122 | }; |
| 123 | |
| 124 | /* hwc_dma_buf represents the array of in-flight WQEs. |
| 125 | * mem_info as know as the GDMA mapped memory is partitioned and used by |
| 126 | * in-flight WQEs. |
| 127 | * The number of WQEs is determined by the number of in-flight messages. |
| 128 | */ |
| 129 | struct hwc_dma_buf { |
| 130 | struct gdma_mem_info mem_info; |
| 131 | |
| 132 | u32 gpa_mkey; |
| 133 | |
| 134 | u32 num_reqs; |
| 135 | struct hwc_work_request reqs[] __counted_by(num_reqs); |
| 136 | }; |
| 137 | |
| 138 | typedef void hwc_rx_event_handler_t(void *ctx, u32 gdma_rxq_id, |
| 139 | const struct hwc_rx_oob *rx_oob); |
| 140 | |
| 141 | typedef void hwc_tx_event_handler_t(void *ctx, u32 gdma_txq_id, |
| 142 | const struct hwc_rx_oob *rx_oob); |
| 143 | |
| 144 | struct hwc_cq { |
| 145 | struct hw_channel_context *hwc; |
| 146 | |
| 147 | struct gdma_queue *gdma_cq; |
| 148 | struct gdma_queue *gdma_eq; |
| 149 | struct gdma_comp *comp_buf; |
| 150 | u16 queue_depth; |
| 151 | |
| 152 | hwc_rx_event_handler_t *rx_event_handler; |
| 153 | void *rx_event_ctx; |
| 154 | |
| 155 | hwc_tx_event_handler_t *tx_event_handler; |
| 156 | void *tx_event_ctx; |
| 157 | }; |
| 158 | |
| 159 | struct hwc_wq { |
| 160 | struct hw_channel_context *hwc; |
| 161 | |
| 162 | struct gdma_queue *gdma_wq; |
| 163 | struct hwc_dma_buf *msg_buf; |
| 164 | u16 queue_depth; |
| 165 | |
| 166 | struct hwc_cq *hwc_cq; |
| 167 | }; |
| 168 | |
| 169 | struct hwc_caller_ctx { |
| 170 | struct completion comp_event; |
| 171 | void *output_buf; |
| 172 | u32 output_buflen; |
| 173 | |
| 174 | u32 error; /* Linux error code */ |
| 175 | u32 status_code; |
| 176 | }; |
| 177 | |
| 178 | struct hw_channel_context { |
| 179 | struct gdma_dev *gdma_dev; |
| 180 | struct device *dev; |
| 181 | |
| 182 | u16 num_inflight_msg; |
| 183 | u32 max_req_msg_size; |
| 184 | |
| 185 | u16 hwc_init_q_depth_max; |
| 186 | u32 hwc_init_max_req_msg_size; |
| 187 | u32 hwc_init_max_resp_msg_size; |
| 188 | |
| 189 | struct completion hwc_init_eqe_comp; |
| 190 | |
| 191 | struct hwc_wq *rxq; |
| 192 | struct hwc_wq *txq; |
| 193 | struct hwc_cq *cq; |
| 194 | |
| 195 | struct semaphore sema; |
| 196 | struct gdma_resource inflight_msg_res; |
| 197 | |
| 198 | u32 pf_dest_vrq_id; |
| 199 | u32 pf_dest_vrcq_id; |
| 200 | u32 hwc_timeout; |
| 201 | |
| 202 | struct hwc_caller_ctx *caller_ctx; |
| 203 | }; |
| 204 | |
| 205 | int mana_hwc_create_channel(struct gdma_context *gc); |
| 206 | void mana_hwc_destroy_channel(struct gdma_context *gc); |
| 207 | |
| 208 | int mana_hwc_send_request(struct hw_channel_context *hwc, u32 req_len, |
| 209 | const void *req, u32 resp_len, void *resp); |
| 210 | |
| 211 | #endif /* _HW_CHANNEL_H */ |
| 212 | |