| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright 2020,2022 NXP |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __PHY_LVDS_H_ |
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| 7 | #define __PHY_LVDS_H_ |
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| 8 | |
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| 9 | /** |
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| 10 | * struct phy_configure_opts_lvds - LVDS configuration set |
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| 11 | * @bits_per_lane_and_dclk_cycle: Number of bits per lane per differential |
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| 12 | * clock cycle. |
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| 13 | * @differential_clk_rate: Clock rate, in Hertz, of the LVDS |
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| 14 | * differential clock. |
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| 15 | * @lanes: Number of active, consecutive, |
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| 16 | * data lanes, starting from lane 0, |
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| 17 | * used for the transmissions. |
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| 18 | * @is_slave: Boolean, true if the phy is a slave |
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| 19 | * which works together with a master |
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| 20 | * phy to support dual link transmission, |
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| 21 | * otherwise a regular phy or a master phy. |
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| 22 | * |
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| 23 | * This structure is used to represent the configuration state of a LVDS phy. |
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| 24 | */ |
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| 25 | struct phy_configure_opts_lvds { |
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| 26 | unsigned int bits_per_lane_and_dclk_cycle; |
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| 27 | unsigned long differential_clk_rate; |
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| 28 | unsigned int lanes; |
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| 29 | bool is_slave; |
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| 30 | }; |
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| 31 | |
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| 32 | #endif /* __PHY_LVDS_H_ */ |
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| 33 | |
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