1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * QCOM QPIC common APIs header file
4 *
5 * Copyright (c) 2023 Qualcomm Inc.
6 * Authors: Md sadre Alam <quic_mdalam@quicinc.com>
7 *
8 */
9#ifndef __MTD_NAND_QPIC_COMMON_H__
10#define __MTD_NAND_QPIC_COMMON_H__
11
12/* NANDc reg offsets */
13#define NAND_FLASH_CMD 0x00
14#define NAND_ADDR0 0x04
15#define NAND_ADDR1 0x08
16#define NAND_FLASH_CHIP_SELECT 0x0c
17#define NAND_EXEC_CMD 0x10
18#define NAND_FLASH_STATUS 0x14
19#define NAND_BUFFER_STATUS 0x18
20#define NAND_DEV0_CFG0 0x20
21#define NAND_DEV0_CFG1 0x24
22#define NAND_DEV0_ECC_CFG 0x28
23#define NAND_AUTO_STATUS_EN 0x2c
24#define NAND_DEV1_CFG0 0x30
25#define NAND_DEV1_CFG1 0x34
26#define NAND_READ_ID 0x40
27#define NAND_READ_STATUS 0x44
28#define NAND_DEV_CMD0 0xa0
29#define NAND_DEV_CMD1 0xa4
30#define NAND_DEV_CMD2 0xa8
31#define NAND_DEV_CMD_VLD 0xac
32#define SFLASHC_BURST_CFG 0xe0
33#define NAND_ERASED_CW_DETECT_CFG 0xe8
34#define NAND_ERASED_CW_DETECT_STATUS 0xec
35#define NAND_EBI2_ECC_BUF_CFG 0xf0
36#define FLASH_BUF_ACC 0x100
37
38#define NAND_CTRL 0xf00
39#define NAND_VERSION 0xf08
40#define NAND_READ_LOCATION_0 0xf20
41#define NAND_READ_LOCATION_1 0xf24
42#define NAND_READ_LOCATION_2 0xf28
43#define NAND_READ_LOCATION_3 0xf2c
44#define NAND_READ_LOCATION_LAST_CW_0 0xf40
45#define NAND_READ_LOCATION_LAST_CW_1 0xf44
46#define NAND_READ_LOCATION_LAST_CW_2 0xf48
47#define NAND_READ_LOCATION_LAST_CW_3 0xf4c
48
49/* dummy register offsets, used by qcom_write_reg_dma */
50#define NAND_DEV_CMD1_RESTORE 0xdead
51#define NAND_DEV_CMD_VLD_RESTORE 0xbeef
52
53/* NAND_FLASH_CMD bits */
54#define PAGE_ACC BIT(4)
55#define LAST_PAGE BIT(5)
56
57/* NAND_FLASH_CHIP_SELECT bits */
58#define NAND_DEV_SEL 0
59#define DM_EN BIT(2)
60
61/* NAND_FLASH_STATUS bits */
62#define FS_OP_ERR BIT(4)
63#define FS_READY_BSY_N BIT(5)
64#define FS_MPU_ERR BIT(8)
65#define FS_DEVICE_STS_ERR BIT(16)
66#define FS_DEVICE_WP BIT(23)
67
68/* NAND_BUFFER_STATUS bits */
69#define BS_UNCORRECTABLE_BIT BIT(8)
70#define BS_CORRECTABLE_ERR_MSK 0x1f
71
72/* NAND_DEVn_CFG0 bits */
73#define DISABLE_STATUS_AFTER_WRITE BIT(4)
74#define CW_PER_PAGE_MASK GENMASK(8, 6)
75#define UD_SIZE_BYTES_MASK GENMASK(18, 9)
76#define ECC_PARITY_SIZE_BYTES_RS GENMASK(22, 19)
77#define SPARE_SIZE_BYTES_MASK GENMASK(26, 23)
78#define NUM_ADDR_CYCLES_MASK GENMASK(29, 27)
79#define STATUS_BFR_READ BIT(30)
80#define SET_RD_MODE_AFTER_STATUS BIT(31)
81
82/* NAND_DEVn_CFG0 bits */
83#define DEV0_CFG1_ECC_DISABLE BIT(0)
84#define WIDE_FLASH BIT(1)
85#define NAND_RECOVERY_CYCLES_MASK GENMASK(4, 2)
86#define CS_ACTIVE_BSY BIT(5)
87#define BAD_BLOCK_BYTE_NUM_MASK GENMASK(15, 6)
88#define BAD_BLOCK_IN_SPARE_AREA BIT(16)
89#define WR_RD_BSY_GAP_MASK GENMASK(22, 17)
90#define ENABLE_BCH_ECC BIT(27)
91
92/* NAND_DEV0_ECC_CFG bits */
93#define ECC_CFG_ECC_DISABLE BIT(0)
94#define ECC_SW_RESET BIT(1)
95#define ECC_MODE_MASK GENMASK(5, 4)
96#define ECC_MODE_4BIT 0
97#define ECC_MODE_8BIT 1
98#define ECC_PARITY_SIZE_BYTES_BCH_MASK GENMASK(12, 8)
99#define ECC_NUM_DATA_BYTES_MASK GENMASK(25, 16)
100#define ECC_FORCE_CLK_OPEN BIT(30)
101
102/* NAND_DEV_CMD1 bits */
103#define READ_ADDR_MASK GENMASK(7, 0)
104
105/* NAND_DEV_CMD_VLD bits */
106#define READ_START_VLD BIT(0)
107#define READ_STOP_VLD BIT(1)
108#define WRITE_START_VLD BIT(2)
109#define ERASE_START_VLD BIT(3)
110#define SEQ_READ_START_VLD BIT(4)
111
112/* NAND_EBI2_ECC_BUF_CFG bits */
113#define NUM_STEPS_MASK GENMASK(9, 0)
114
115/* NAND_ERASED_CW_DETECT_CFG bits */
116#define ERASED_CW_ECC_MASK 1
117#define AUTO_DETECT_RES 0
118#define MASK_ECC BIT(ERASED_CW_ECC_MASK)
119#define RESET_ERASED_DET BIT(AUTO_DETECT_RES)
120#define ACTIVE_ERASED_DET (0 << AUTO_DETECT_RES)
121#define CLR_ERASED_PAGE_DET (RESET_ERASED_DET | MASK_ECC)
122#define SET_ERASED_PAGE_DET (ACTIVE_ERASED_DET | MASK_ECC)
123
124/* NAND_ERASED_CW_DETECT_STATUS bits */
125#define PAGE_ALL_ERASED BIT(7)
126#define CODEWORD_ALL_ERASED BIT(6)
127#define PAGE_ERASED BIT(5)
128#define CODEWORD_ERASED BIT(4)
129#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
130#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
131
132/* NAND_READ_LOCATION_n bits */
133#define READ_LOCATION_OFFSET_MASK GENMASK(9, 0)
134#define READ_LOCATION_SIZE_MASK GENMASK(25, 16)
135#define READ_LOCATION_LAST_MASK BIT(31)
136
137/* Version Mask */
138#define NAND_VERSION_MAJOR_MASK 0xf0000000
139#define NAND_VERSION_MAJOR_SHIFT 28
140#define NAND_VERSION_MINOR_MASK 0x0fff0000
141#define NAND_VERSION_MINOR_SHIFT 16
142
143/* NAND OP_CMDs */
144#define OP_PAGE_READ 0x2
145#define OP_PAGE_READ_WITH_ECC 0x3
146#define OP_PAGE_READ_WITH_ECC_SPARE 0x4
147#define OP_PAGE_READ_ONFI_READ 0x5
148#define OP_PROGRAM_PAGE 0x6
149#define OP_PAGE_PROGRAM_WITH_ECC 0x7
150#define OP_PROGRAM_PAGE_SPARE 0x9
151#define OP_BLOCK_ERASE 0xa
152#define OP_CHECK_STATUS 0xc
153#define OP_FETCH_ID 0xb
154#define OP_RESET_DEVICE 0xd
155
156/* Default Value for NAND_DEV_CMD_VLD */
157#define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \
158 ERASE_START_VLD | SEQ_READ_START_VLD)
159
160/* NAND_CTRL bits */
161#define BAM_MODE_EN BIT(0)
162
163/*
164 * the NAND controller performs reads/writes with ECC in 516 byte chunks.
165 * the driver calls the chunks 'step' or 'codeword' interchangeably
166 */
167#define NANDC_STEP_SIZE 512
168
169/*
170 * the largest page size we support is 8K, this will have 16 steps/codewords
171 * of 512 bytes each
172 */
173#define MAX_NUM_STEPS (SZ_8K / NANDC_STEP_SIZE)
174
175/* we read at most 3 registers per codeword scan */
176#define MAX_REG_RD (3 * MAX_NUM_STEPS)
177
178/* ECC modes supported by the controller */
179#define ECC_NONE BIT(0)
180#define ECC_RS_4BIT BIT(1)
181#define ECC_BCH_4BIT BIT(2)
182#define ECC_BCH_8BIT BIT(3)
183
184/*
185 * Returns the actual register address for all NAND_DEV_ registers
186 * (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and NAND_DEV_CMD_VLD)
187 */
188#define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
189
190/* Returns the dma address for reg read buffer */
191#define reg_buf_dma_addr(chip, vaddr) \
192 ((chip)->reg_read_dma + \
193 ((u8 *)(vaddr) - (u8 *)(chip)->reg_read_buf))
194
195#define QPIC_PER_CW_CMD_ELEMENTS 32
196#define QPIC_PER_CW_CMD_SGL 32
197#define QPIC_PER_CW_DATA_SGL 8
198
199#define QPIC_NAND_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
200
201/*
202 * Flags used in DMA descriptor preparation helper functions
203 * (i.e. qcom_read_reg_dma/qcom_write_reg_dma/qcom_read_data_dma/qcom_write_data_dma)
204 */
205/* Don't set the EOT in current tx BAM sgl */
206#define NAND_BAM_NO_EOT BIT(0)
207/* Set the NWD flag in current BAM sgl */
208#define NAND_BAM_NWD BIT(1)
209/* Finish writing in the current BAM sgl and start writing in another BAM sgl */
210#define NAND_BAM_NEXT_SGL BIT(2)
211/*
212 * Erased codeword status is being used two times in single transfer so this
213 * flag will determine the current value of erased codeword status register
214 */
215#define NAND_ERASED_CW_SET BIT(4)
216
217#define MAX_ADDRESS_CYCLE 5
218
219/*
220 * This data type corresponds to the BAM transaction which will be used for all
221 * NAND transfers.
222 * @bam_ce - the array of BAM command elements
223 * @cmd_sgl - sgl for NAND BAM command pipe
224 * @data_sgl - sgl for NAND BAM consumer/producer pipe
225 * @last_data_desc - last DMA desc in data channel (tx/rx).
226 * @last_cmd_desc - last DMA desc in command channel.
227 * @txn_done - completion for NAND transfer.
228 * @bam_ce_nitems - the number of elements in the @bam_ce array
229 * @cmd_sgl_nitems - the number of elements in the @cmd_sgl array
230 * @data_sgl_nitems - the number of elements in the @data_sgl array
231 * @bam_ce_pos - the index in bam_ce which is available for next sgl
232 * @bam_ce_start - the index in bam_ce which marks the start position ce
233 * for current sgl. It will be used for size calculation
234 * for current sgl
235 * @cmd_sgl_pos - current index in command sgl.
236 * @cmd_sgl_start - start index in command sgl.
237 * @tx_sgl_pos - current index in data sgl for tx.
238 * @tx_sgl_start - start index in data sgl for tx.
239 * @rx_sgl_pos - current index in data sgl for rx.
240 * @rx_sgl_start - start index in data sgl for rx.
241 */
242struct bam_transaction {
243 struct bam_cmd_element *bam_ce;
244 struct scatterlist *cmd_sgl;
245 struct scatterlist *data_sgl;
246 struct dma_async_tx_descriptor *last_data_desc;
247 struct dma_async_tx_descriptor *last_cmd_desc;
248 struct completion txn_done;
249
250 unsigned int bam_ce_nitems;
251 unsigned int cmd_sgl_nitems;
252 unsigned int data_sgl_nitems;
253
254 struct_group(bam_positions,
255 u32 bam_ce_pos;
256 u32 bam_ce_start;
257 u32 cmd_sgl_pos;
258 u32 cmd_sgl_start;
259 u32 tx_sgl_pos;
260 u32 tx_sgl_start;
261 u32 rx_sgl_pos;
262 u32 rx_sgl_start;
263
264 );
265};
266
267/*
268 * This data type corresponds to the nand dma descriptor
269 * @dma_desc - low level DMA engine descriptor
270 * @list - list for desc_info
271 *
272 * @adm_sgl - sgl which will be used for single sgl dma descriptor. Only used by
273 * ADM
274 * @bam_sgl - sgl which will be used for dma descriptor. Only used by BAM
275 * @sgl_cnt - number of SGL in bam_sgl. Only used by BAM
276 * @dir - DMA transfer direction
277 */
278struct desc_info {
279 struct dma_async_tx_descriptor *dma_desc;
280 struct list_head node;
281
282 union {
283 struct scatterlist adm_sgl;
284 struct {
285 struct scatterlist *bam_sgl;
286 int sgl_cnt;
287 };
288 };
289 enum dma_data_direction dir;
290};
291
292/*
293 * holds the current register values that we want to write. acts as a contiguous
294 * chunk of memory which we use to write the controller registers through DMA.
295 */
296struct nandc_regs {
297 __le32 cmd;
298 __le32 addr0;
299 __le32 addr1;
300 __le32 chip_sel;
301 __le32 exec;
302
303 __le32 cfg0;
304 __le32 cfg1;
305 __le32 ecc_bch_cfg;
306
307 __le32 clrflashstatus;
308 __le32 clrreadstatus;
309
310 __le32 cmd1;
311 __le32 vld;
312
313 __le32 orig_cmd1;
314 __le32 orig_vld;
315
316 __le32 ecc_buf_cfg;
317 __le32 read_location0;
318 __le32 read_location1;
319 __le32 read_location2;
320 __le32 read_location3;
321 __le32 read_location_last0;
322 __le32 read_location_last1;
323 __le32 read_location_last2;
324 __le32 read_location_last3;
325 __le32 spi_cfg;
326 __le32 num_addr_cycle;
327 __le32 busy_wait_cnt;
328 __le32 flash_feature;
329
330 __le32 erased_cw_detect_cfg_clr;
331 __le32 erased_cw_detect_cfg_set;
332};
333
334/*
335 * NAND controller data struct
336 *
337 * @dev: parent device
338 *
339 * @base: MMIO base
340 *
341 * @core_clk: controller clock
342 * @aon_clk: another controller clock
343 * @iomacro_clk: io macro clock
344 *
345 * @regs: a contiguous chunk of memory for DMA register
346 * writes. contains the register values to be
347 * written to controller
348 *
349 * @props: properties of current NAND controller,
350 * initialized via DT match data
351 *
352 * @controller: base controller structure
353 * @qspi: qpic spi structure
354 * @host_list: list containing all the chips attached to the
355 * controller
356 *
357 * @chan: dma channel
358 * @cmd_crci: ADM DMA CRCI for command flow control
359 * @data_crci: ADM DMA CRCI for data flow control
360 *
361 * @desc_list: DMA descriptor list (list of desc_infos)
362 *
363 * @data_buffer: our local DMA buffer for page read/writes,
364 * used when we can't use the buffer provided
365 * by upper layers directly
366 * @reg_read_buf: local buffer for reading back registers via DMA
367 *
368 * @base_phys: physical base address of controller registers
369 * @base_dma: dma base address of controller registers
370 * @reg_read_dma: contains dma address for register read buffer
371 *
372 * @buf_size/count/start: markers for chip->legacy.read_buf/write_buf
373 * functions
374 * @max_cwperpage: maximum QPIC codewords required. calculated
375 * from all connected NAND devices pagesize
376 *
377 * @reg_read_pos: marker for data read in reg_read_buf
378 *
379 * @cmd1/vld: some fixed controller register values
380 *
381 * @exec_opwrite: flag to select correct number of code word
382 * while reading status
383 */
384struct qcom_nand_controller {
385 struct device *dev;
386
387 void __iomem *base;
388
389 struct clk *core_clk;
390 struct clk *aon_clk;
391
392 struct nandc_regs *regs;
393 struct bam_transaction *bam_txn;
394
395 const struct qcom_nandc_props *props;
396
397 struct nand_controller *controller;
398 struct qpic_spi_nand *qspi;
399 struct list_head host_list;
400
401 union {
402 /* will be used only by QPIC for BAM DMA */
403 struct {
404 struct dma_chan *tx_chan;
405 struct dma_chan *rx_chan;
406 struct dma_chan *cmd_chan;
407 };
408
409 /* will be used only by EBI2 for ADM DMA */
410 struct {
411 struct dma_chan *chan;
412 unsigned int cmd_crci;
413 unsigned int data_crci;
414 };
415 };
416
417 struct list_head desc_list;
418
419 u8 *data_buffer;
420 __le32 *reg_read_buf;
421
422 phys_addr_t base_phys;
423 dma_addr_t base_dma;
424 dma_addr_t reg_read_dma;
425
426 int buf_size;
427 int buf_count;
428 int buf_start;
429 unsigned int max_cwperpage;
430
431 int reg_read_pos;
432
433 u32 cmd1, vld;
434 bool exec_opwrite;
435};
436
437/*
438 * This data type corresponds to the NAND controller properties which varies
439 * among different NAND controllers.
440 * @ecc_modes - ecc mode for NAND
441 * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
442 * @supports_bam - whether NAND controller is using BAM
443 * @nandc_part_of_qpic - whether NAND controller is part of qpic IP
444 * @qpic_version2 - flag to indicate QPIC IP version 2
445 * @use_codeword_fixup - whether NAND has different layout for boot partitions
446 */
447struct qcom_nandc_props {
448 u32 ecc_modes;
449 u32 dev_cmd_reg_start;
450 u32 bam_offset;
451 bool supports_bam;
452 bool nandc_part_of_qpic;
453 bool qpic_version2;
454 bool use_codeword_fixup;
455};
456
457void qcom_free_bam_transaction(struct qcom_nand_controller *nandc);
458struct bam_transaction *qcom_alloc_bam_transaction(struct qcom_nand_controller *nandc);
459void qcom_clear_bam_transaction(struct qcom_nand_controller *nandc);
460void qcom_qpic_bam_dma_done(void *data);
461void qcom_nandc_dev_to_mem(struct qcom_nand_controller *nandc, bool is_cpu);
462int qcom_prepare_bam_async_desc(struct qcom_nand_controller *nandc,
463 struct dma_chan *chan, unsigned long flags);
464int qcom_prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
465 int reg_off, const void *vaddr, int size, unsigned int flags);
466int qcom_prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
467 const void *vaddr, int size, unsigned int flags);
468int qcom_prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read, int reg_off,
469 const void *vaddr, int size, bool flow_control);
470int qcom_read_reg_dma(struct qcom_nand_controller *nandc, int first, int num_regs,
471 unsigned int flags);
472int qcom_write_reg_dma(struct qcom_nand_controller *nandc, __le32 *vaddr, int first,
473 int num_regs, unsigned int flags);
474int qcom_read_data_dma(struct qcom_nand_controller *nandc, int reg_off, const u8 *vaddr,
475 int size, unsigned int flags);
476int qcom_write_data_dma(struct qcom_nand_controller *nandc, int reg_off, const u8 *vaddr,
477 int size, unsigned int flags);
478int qcom_submit_descs(struct qcom_nand_controller *nandc);
479void qcom_clear_read_regs(struct qcom_nand_controller *nandc);
480void qcom_nandc_unalloc(struct qcom_nand_controller *nandc);
481int qcom_nandc_alloc(struct qcom_nand_controller *nandc);
482#endif
483
484

source code of linux/include/linux/mtd/nand-qpic-common.h