1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> et al.
4 */
5
6#ifndef __MTD_CFI_H__
7#define __MTD_CFI_H__
8
9#include <linux/delay.h>
10#include <linux/types.h>
11#include <linux/bug.h>
12#include <linux/interrupt.h>
13#include <linux/mtd/flashchip.h>
14#include <linux/mtd/map.h>
15#include <linux/mtd/cfi_endian.h>
16#include <linux/mtd/xip.h>
17
18#ifdef CONFIG_MTD_CFI_I1
19#define cfi_interleave(cfi) 1
20#define cfi_interleave_is_1(cfi) (cfi_interleave(cfi) == 1)
21#else
22#define cfi_interleave_is_1(cfi) (0)
23#endif
24
25#ifdef CONFIG_MTD_CFI_I2
26# ifdef cfi_interleave
27# undef cfi_interleave
28# define cfi_interleave(cfi) ((cfi)->interleave)
29# else
30# define cfi_interleave(cfi) 2
31# endif
32#define cfi_interleave_is_2(cfi) (cfi_interleave(cfi) == 2)
33#else
34#define cfi_interleave_is_2(cfi) (0)
35#endif
36
37#ifdef CONFIG_MTD_CFI_I4
38# ifdef cfi_interleave
39# undef cfi_interleave
40# define cfi_interleave(cfi) ((cfi)->interleave)
41# else
42# define cfi_interleave(cfi) 4
43# endif
44#define cfi_interleave_is_4(cfi) (cfi_interleave(cfi) == 4)
45#else
46#define cfi_interleave_is_4(cfi) (0)
47#endif
48
49#ifdef CONFIG_MTD_CFI_I8
50# ifdef cfi_interleave
51# undef cfi_interleave
52# define cfi_interleave(cfi) ((cfi)->interleave)
53# else
54# define cfi_interleave(cfi) 8
55# endif
56#define cfi_interleave_is_8(cfi) (cfi_interleave(cfi) == 8)
57#else
58#define cfi_interleave_is_8(cfi) (0)
59#endif
60
61#ifndef cfi_interleave
62#warning No CONFIG_MTD_CFI_Ix selected. No NOR chip support can work.
63static inline int cfi_interleave(void *cfi)
64{
65 BUG();
66 return 0;
67}
68#endif
69
70static inline int cfi_interleave_supported(int i)
71{
72 switch (i) {
73#ifdef CONFIG_MTD_CFI_I1
74 case 1:
75#endif
76#ifdef CONFIG_MTD_CFI_I2
77 case 2:
78#endif
79#ifdef CONFIG_MTD_CFI_I4
80 case 4:
81#endif
82#ifdef CONFIG_MTD_CFI_I8
83 case 8:
84#endif
85 return 1;
86
87 default:
88 return 0;
89 }
90}
91
92
93/* NB: these values must represents the number of bytes needed to meet the
94 * device type (x8, x16, x32). Eg. a 32 bit device is 4 x 8 bytes.
95 * These numbers are used in calculations.
96 */
97#define CFI_DEVICETYPE_X8 (8 / 8)
98#define CFI_DEVICETYPE_X16 (16 / 8)
99#define CFI_DEVICETYPE_X32 (32 / 8)
100#define CFI_DEVICETYPE_X64 (64 / 8)
101
102
103/* Device Interface Code Assignments from the "Common Flash Memory Interface
104 * Publication 100" dated December 1, 2001.
105 */
106#define CFI_INTERFACE_X8_ASYNC 0x0000
107#define CFI_INTERFACE_X16_ASYNC 0x0001
108#define CFI_INTERFACE_X8_BY_X16_ASYNC 0x0002
109#define CFI_INTERFACE_X32_ASYNC 0x0003
110#define CFI_INTERFACE_X16_BY_X32_ASYNC 0x0005
111#define CFI_INTERFACE_NOT_ALLOWED 0xffff
112
113
114/* NB: We keep these structures in memory in HOST byteorder, except
115 * where individually noted.
116 */
117
118/* Basic Query Structure */
119struct cfi_ident {
120 uint8_t qry[3];
121 uint16_t P_ID;
122 uint16_t P_ADR;
123 uint16_t A_ID;
124 uint16_t A_ADR;
125 uint8_t VccMin;
126 uint8_t VccMax;
127 uint8_t VppMin;
128 uint8_t VppMax;
129 uint8_t WordWriteTimeoutTyp;
130 uint8_t BufWriteTimeoutTyp;
131 uint8_t BlockEraseTimeoutTyp;
132 uint8_t ChipEraseTimeoutTyp;
133 uint8_t WordWriteTimeoutMax;
134 uint8_t BufWriteTimeoutMax;
135 uint8_t BlockEraseTimeoutMax;
136 uint8_t ChipEraseTimeoutMax;
137 uint8_t DevSize;
138 uint16_t InterfaceDesc;
139 uint16_t MaxBufWriteSize;
140 uint8_t NumEraseRegions;
141 uint32_t EraseRegionInfo[]; /* Not host ordered */
142} __packed;
143
144/* Extended Query Structure for both PRI and ALT */
145
146struct cfi_extquery {
147 uint8_t pri[3];
148 uint8_t MajorVersion;
149 uint8_t MinorVersion;
150} __packed;
151
152/* Vendor-Specific PRI for Intel/Sharp Extended Command Set (0x0001) */
153
154struct cfi_pri_intelext {
155 uint8_t pri[3];
156 uint8_t MajorVersion;
157 uint8_t MinorVersion;
158 uint32_t FeatureSupport; /* if bit 31 is set then an additional uint32_t feature
159 block follows - FIXME - not currently supported */
160 uint8_t SuspendCmdSupport;
161 uint16_t BlkStatusRegMask;
162 uint8_t VccOptimal;
163 uint8_t VppOptimal;
164 uint8_t NumProtectionFields;
165 uint16_t ProtRegAddr;
166 uint8_t FactProtRegSize;
167 uint8_t UserProtRegSize;
168 uint8_t extra[];
169} __packed;
170
171struct cfi_intelext_otpinfo {
172 uint32_t ProtRegAddr;
173 uint16_t FactGroups;
174 uint8_t FactProtRegSize;
175 uint16_t UserGroups;
176 uint8_t UserProtRegSize;
177} __packed;
178
179struct cfi_intelext_blockinfo {
180 uint16_t NumIdentBlocks;
181 uint16_t BlockSize;
182 uint16_t MinBlockEraseCycles;
183 uint8_t BitsPerCell;
184 uint8_t BlockCap;
185} __packed;
186
187struct cfi_intelext_regioninfo {
188 uint16_t NumIdentPartitions;
189 uint8_t NumOpAllowed;
190 uint8_t NumOpAllowedSimProgMode;
191 uint8_t NumOpAllowedSimEraMode;
192 uint8_t NumBlockTypes;
193 struct cfi_intelext_blockinfo BlockTypes[1];
194} __packed;
195
196struct cfi_intelext_programming_regioninfo {
197 uint8_t ProgRegShift;
198 uint8_t Reserved1;
199 uint8_t ControlValid;
200 uint8_t Reserved2;
201 uint8_t ControlInvalid;
202 uint8_t Reserved3;
203} __packed;
204
205/* Vendor-Specific PRI for AMD/Fujitsu Extended Command Set (0x0002) */
206
207struct cfi_pri_amdstd {
208 uint8_t pri[3];
209 uint8_t MajorVersion;
210 uint8_t MinorVersion;
211 uint8_t SiliconRevision; /* bits 1-0: Address Sensitive Unlock */
212 uint8_t EraseSuspend;
213 uint8_t BlkProt;
214 uint8_t TmpBlkUnprotect;
215 uint8_t BlkProtUnprot;
216 uint8_t SimultaneousOps;
217 uint8_t BurstMode;
218 uint8_t PageMode;
219 uint8_t VppMin;
220 uint8_t VppMax;
221 uint8_t TopBottom;
222 /* Below field are added from version 1.5 */
223 uint8_t ProgramSuspend;
224 uint8_t UnlockBypass;
225 uint8_t SecureSiliconSector;
226 uint8_t SoftwareFeatures;
227#define CFI_POLL_STATUS_REG BIT(0)
228#define CFI_POLL_DQ BIT(1)
229} __packed;
230
231/* Vendor-Specific PRI for Atmel chips (command set 0x0002) */
232
233struct cfi_pri_atmel {
234 uint8_t pri[3];
235 uint8_t MajorVersion;
236 uint8_t MinorVersion;
237 uint8_t Features;
238 uint8_t BottomBoot;
239 uint8_t BurstMode;
240 uint8_t PageMode;
241} __packed;
242
243struct cfi_pri_query {
244 uint8_t NumFields;
245 uint32_t ProtField[1]; /* Not host ordered */
246} __packed;
247
248struct cfi_bri_query {
249 uint8_t PageModeReadCap;
250 uint8_t NumFields;
251 uint32_t ConfField[1]; /* Not host ordered */
252} __packed;
253
254#define P_ID_NONE 0x0000
255#define P_ID_INTEL_EXT 0x0001
256#define P_ID_AMD_STD 0x0002
257#define P_ID_INTEL_STD 0x0003
258#define P_ID_AMD_EXT 0x0004
259#define P_ID_WINBOND 0x0006
260#define P_ID_ST_ADV 0x0020
261#define P_ID_MITSUBISHI_STD 0x0100
262#define P_ID_MITSUBISHI_EXT 0x0101
263#define P_ID_SST_PAGE 0x0102
264#define P_ID_SST_OLD 0x0701
265#define P_ID_INTEL_PERFORMANCE 0x0200
266#define P_ID_INTEL_DATA 0x0210
267#define P_ID_RESERVED 0xffff
268
269
270#define CFI_MODE_CFI 1
271#define CFI_MODE_JEDEC 0
272
273struct cfi_private {
274 uint16_t cmdset;
275 void *cmdset_priv;
276 int interleave;
277 int device_type;
278 int cfi_mode; /* Are we a JEDEC device pretending to be CFI? */
279 int addr_unlock1;
280 int addr_unlock2;
281 struct mtd_info *(*cmdset_setup)(struct map_info *);
282 struct cfi_ident *cfiq; /* For now only one. We insist that all devs
283 must be of the same type. */
284 int mfr, id;
285 int numchips;
286 map_word sector_erase_cmd;
287 unsigned long chipshift; /* Because they're of the same type */
288 const char *im_name; /* inter_module name for cmdset_setup */
289 unsigned long quirks;
290 struct flchip chips[] __counted_by(numchips); /* per-chip data structure for each chip */
291};
292
293uint32_t cfi_build_cmd_addr(uint32_t cmd_ofs,
294 struct map_info *map, struct cfi_private *cfi);
295
296map_word cfi_build_cmd(u_long cmd, struct map_info *map, struct cfi_private *cfi);
297#define CMD(x) cfi_build_cmd((x), map, cfi)
298
299unsigned long cfi_merge_status(map_word val, struct map_info *map,
300 struct cfi_private *cfi);
301#define MERGESTATUS(x) cfi_merge_status((x), map, cfi)
302
303uint32_t cfi_send_gen_cmd(u_char cmd, uint32_t cmd_addr, uint32_t base,
304 struct map_info *map, struct cfi_private *cfi,
305 int type, map_word *prev_val);
306
307static inline uint8_t cfi_read_query(struct map_info *map, uint32_t addr)
308{
309 map_word val = map_read(map, addr);
310
311 if (map_bankwidth_is_1(map))
312 return val.x[0];
313 if (map_bankwidth_is_2(map))
314 return cfi16_to_cpu(map, val.x[0]);
315 /*
316 * No point in a 64-bit byteswap since that would just be
317 * swapping the responses from different chips, and we are
318 * only interested in one chip (a representative sample)
319 */
320 return cfi32_to_cpu(map, val.x[0]);
321}
322
323static inline uint16_t cfi_read_query16(struct map_info *map, uint32_t addr)
324{
325 map_word val = map_read(map, addr);
326
327 if (map_bankwidth_is_1(map))
328 return val.x[0] & 0xff;
329 if (map_bankwidth_is_2(map))
330 return cfi16_to_cpu(map, val.x[0]);
331 /*
332 * No point in a 64-bit byteswap since that would just be
333 * swapping the responses from different chips, and we are
334 * only interested in one chip (a representative sample)
335 */
336 return cfi32_to_cpu(map, val.x[0]);
337}
338
339void cfi_udelay(int us);
340
341int __xipram cfi_qry_present(struct map_info *map, __u32 base,
342 struct cfi_private *cfi);
343int __xipram cfi_qry_mode_on(uint32_t base, struct map_info *map,
344 struct cfi_private *cfi);
345void __xipram cfi_qry_mode_off(uint32_t base, struct map_info *map,
346 struct cfi_private *cfi);
347
348struct cfi_extquery *cfi_read_pri(struct map_info *map, uint16_t adr, uint16_t size,
349 const char* name);
350struct cfi_fixup {
351 uint16_t mfr;
352 uint16_t id;
353 void (*fixup)(struct mtd_info *mtd);
354};
355
356#define CFI_MFR_ANY 0xFFFF
357#define CFI_ID_ANY 0xFFFF
358#define CFI_MFR_CONTINUATION 0x007F
359
360#define CFI_MFR_AMD 0x0001
361#define CFI_MFR_AMIC 0x0037
362#define CFI_MFR_ATMEL 0x001F
363#define CFI_MFR_EON 0x001C
364#define CFI_MFR_FUJITSU 0x0004
365#define CFI_MFR_HYUNDAI 0x00AD
366#define CFI_MFR_INTEL 0x0089
367#define CFI_MFR_MACRONIX 0x00C2
368#define CFI_MFR_NEC 0x0010
369#define CFI_MFR_PMC 0x009D
370#define CFI_MFR_SAMSUNG 0x00EC
371#define CFI_MFR_SHARP 0x00B0
372#define CFI_MFR_SST 0x00BF
373#define CFI_MFR_ST 0x0020 /* STMicroelectronics */
374#define CFI_MFR_MICRON 0x002C /* Micron */
375#define CFI_MFR_TOSHIBA 0x0098
376#define CFI_MFR_WINBOND 0x00DA
377
378void cfi_fixup(struct mtd_info *mtd, struct cfi_fixup* fixups);
379
380typedef int (*varsize_frob_t)(struct map_info *map, struct flchip *chip,
381 unsigned long adr, int len, void *thunk);
382
383int cfi_varsize_frob(struct mtd_info *mtd, varsize_frob_t frob,
384 loff_t ofs, size_t len, void *thunk);
385
386
387#endif /* __MTD_CFI_H__ */
388

source code of linux/include/linux/mtd/cfi.h