| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2021 MediaTek Inc. |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __MFD_MT6359_REGISTERS_H__ |
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| 7 | #define __MFD_MT6359_REGISTERS_H__ |
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| 8 | |
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| 9 | /* PMIC Registers */ |
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| 10 | #define MT6359_SWCID 0xa |
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| 11 | #define MT6359_TOPSTATUS 0x2a |
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| 12 | #define MT6359_TOP_RST_MISC 0x14c |
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| 13 | #define MT6359_MISC_TOP_INT_CON0 0x188 |
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| 14 | #define MT6359_MISC_TOP_INT_STATUS0 0x194 |
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| 15 | #define MT6359_TOP_INT_STATUS0 0x19e |
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| 16 | #define MT6359_SCK_TOP_INT_CON0 0x528 |
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| 17 | #define MT6359_SCK_TOP_INT_STATUS0 0x534 |
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| 18 | #define MT6359_EOSC_CALI_CON0 0x53a |
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| 19 | #define MT6359_EOSC_CALI_CON1 0x53c |
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| 20 | #define MT6359_RTC_MIX_CON0 0x53e |
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| 21 | #define MT6359_RTC_MIX_CON1 0x540 |
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| 22 | #define MT6359_RTC_MIX_CON2 0x542 |
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| 23 | #define MT6359_RTC_DSN_ID 0x580 |
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| 24 | #define MT6359_RTC_DSN_REV0 0x582 |
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| 25 | #define MT6359_RTC_DBI 0x584 |
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| 26 | #define MT6359_RTC_DXI 0x586 |
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| 27 | #define MT6359_RTC_BBPU 0x588 |
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| 28 | #define MT6359_RTC_IRQ_STA 0x58a |
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| 29 | #define MT6359_RTC_IRQ_EN 0x58c |
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| 30 | #define MT6359_RTC_CII_EN 0x58e |
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| 31 | #define MT6359_RTC_AL_MASK 0x590 |
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| 32 | #define MT6359_RTC_TC_SEC 0x592 |
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| 33 | #define MT6359_RTC_TC_MIN 0x594 |
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| 34 | #define MT6359_RTC_TC_HOU 0x596 |
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| 35 | #define MT6359_RTC_TC_DOM 0x598 |
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| 36 | #define MT6359_RTC_TC_DOW 0x59a |
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| 37 | #define MT6359_RTC_TC_MTH 0x59c |
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| 38 | #define MT6359_RTC_TC_YEA 0x59e |
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| 39 | #define MT6359_RTC_AL_SEC 0x5a0 |
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| 40 | #define MT6359_RTC_AL_MIN 0x5a2 |
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| 41 | #define MT6359_RTC_AL_HOU 0x5a4 |
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| 42 | #define MT6359_RTC_AL_DOM 0x5a6 |
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| 43 | #define MT6359_RTC_AL_DOW 0x5a8 |
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| 44 | #define MT6359_RTC_AL_MTH 0x5aa |
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| 45 | #define MT6359_RTC_AL_YEA 0x5ac |
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| 46 | #define MT6359_RTC_OSC32CON 0x5ae |
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| 47 | #define MT6359_RTC_POWERKEY1 0x5b0 |
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| 48 | #define MT6359_RTC_POWERKEY2 0x5b2 |
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| 49 | #define MT6359_RTC_PDN1 0x5b4 |
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| 50 | #define MT6359_RTC_PDN2 0x5b6 |
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| 51 | #define MT6359_RTC_SPAR0 0x5b8 |
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| 52 | #define MT6359_RTC_SPAR1 0x5ba |
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| 53 | #define MT6359_RTC_PROT 0x5bc |
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| 54 | #define MT6359_RTC_DIFF 0x5be |
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| 55 | #define MT6359_RTC_CALI 0x5c0 |
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| 56 | #define MT6359_RTC_WRTGR 0x5c2 |
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| 57 | #define MT6359_RTC_CON 0x5c4 |
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| 58 | #define MT6359_RTC_SEC_CTRL 0x5c6 |
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| 59 | #define MT6359_RTC_INT_CNT 0x5c8 |
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| 60 | #define MT6359_RTC_SEC_DAT0 0x5ca |
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| 61 | #define MT6359_RTC_SEC_DAT1 0x5cc |
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| 62 | #define MT6359_RTC_SEC_DAT2 0x5ce |
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| 63 | #define MT6359_RTC_SEC_DSN_ID 0x600 |
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| 64 | #define MT6359_RTC_SEC_DSN_REV0 0x602 |
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| 65 | #define MT6359_RTC_SEC_DBI 0x604 |
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| 66 | #define MT6359_RTC_SEC_DXI 0x606 |
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| 67 | #define MT6359_RTC_TC_SEC_SEC 0x608 |
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| 68 | #define MT6359_RTC_TC_MIN_SEC 0x60a |
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| 69 | #define MT6359_RTC_TC_HOU_SEC 0x60c |
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| 70 | #define MT6359_RTC_TC_DOM_SEC 0x60e |
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| 71 | #define MT6359_RTC_TC_DOW_SEC 0x610 |
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| 72 | #define MT6359_RTC_TC_MTH_SEC 0x612 |
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| 73 | #define MT6359_RTC_TC_YEA_SEC 0x614 |
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| 74 | #define MT6359_RTC_SEC_CK_PDN 0x616 |
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| 75 | #define MT6359_RTC_SEC_WRTGR 0x618 |
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| 76 | #define MT6359_PSC_TOP_INT_CON0 0x910 |
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| 77 | #define MT6359_PSC_TOP_INT_STATUS0 0x91c |
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| 78 | #define MT6359_BM_TOP_INT_CON0 0xc32 |
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| 79 | #define MT6359_BM_TOP_INT_CON1 0xc38 |
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| 80 | #define MT6359_BM_TOP_INT_STATUS0 0xc4a |
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| 81 | #define MT6359_BM_TOP_INT_STATUS1 0xc4c |
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| 82 | #define MT6359_HK_TOP_INT_CON0 0xf92 |
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| 83 | #define MT6359_HK_TOP_INT_STATUS0 0xf9e |
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| 84 | #define MT6359_BUCK_TOP_INT_CON0 0x1418 |
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| 85 | #define MT6359_BUCK_TOP_INT_STATUS0 0x1424 |
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| 86 | #define MT6359_BUCK_VPU_CON0 0x1488 |
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| 87 | #define MT6359_BUCK_VPU_DBG0 0x14a6 |
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| 88 | #define MT6359_BUCK_VPU_DBG1 0x14a8 |
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| 89 | #define MT6359_BUCK_VPU_ELR0 0x14ac |
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| 90 | #define MT6359_BUCK_VCORE_CON0 0x1508 |
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| 91 | #define MT6359_BUCK_VCORE_DBG0 0x1526 |
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| 92 | #define MT6359_BUCK_VCORE_DBG1 0x1528 |
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| 93 | #define MT6359_BUCK_VCORE_SSHUB_CON0 0x152a |
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| 94 | #define MT6359_BUCK_VCORE_ELR0 0x1534 |
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| 95 | #define MT6359_BUCK_VGPU11_CON0 0x1588 |
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| 96 | #define MT6359_BUCK_VGPU11_DBG0 0x15a6 |
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| 97 | #define MT6359_BUCK_VGPU11_DBG1 0x15a8 |
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| 98 | #define MT6359_BUCK_VGPU11_ELR0 0x15ac |
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| 99 | #define MT6359_BUCK_VMODEM_CON0 0x1688 |
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| 100 | #define MT6359_BUCK_VMODEM_DBG0 0x16a6 |
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| 101 | #define MT6359_BUCK_VMODEM_DBG1 0x16a8 |
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| 102 | #define MT6359_BUCK_VMODEM_ELR0 0x16ae |
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| 103 | #define MT6359_BUCK_VPROC1_CON0 0x1708 |
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| 104 | #define MT6359_BUCK_VPROC1_DBG0 0x1726 |
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| 105 | #define MT6359_BUCK_VPROC1_DBG1 0x1728 |
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| 106 | #define MT6359_BUCK_VPROC1_ELR0 0x172e |
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| 107 | #define MT6359_BUCK_VPROC2_CON0 0x1788 |
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| 108 | #define MT6359_BUCK_VPROC2_DBG0 0x17a6 |
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| 109 | #define MT6359_BUCK_VPROC2_DBG1 0x17a8 |
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| 110 | #define MT6359_BUCK_VPROC2_ELR0 0x17b2 |
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| 111 | #define MT6359_BUCK_VS1_CON0 0x1808 |
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| 112 | #define MT6359_BUCK_VS1_DBG0 0x1826 |
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| 113 | #define MT6359_BUCK_VS1_DBG1 0x1828 |
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| 114 | #define MT6359_BUCK_VS1_ELR0 0x1834 |
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| 115 | #define MT6359_BUCK_VS2_CON0 0x1888 |
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| 116 | #define MT6359_BUCK_VS2_DBG0 0x18a6 |
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| 117 | #define MT6359_BUCK_VS2_DBG1 0x18a8 |
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| 118 | #define MT6359_BUCK_VS2_ELR0 0x18b4 |
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| 119 | #define MT6359_BUCK_VPA_CON0 0x1908 |
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| 120 | #define MT6359_BUCK_VPA_CON1 0x190e |
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| 121 | #define MT6359_BUCK_VPA_CFG0 0x1910 |
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| 122 | #define MT6359_BUCK_VPA_CFG1 0x1912 |
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| 123 | #define MT6359_BUCK_VPA_DBG0 0x1914 |
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| 124 | #define MT6359_BUCK_VPA_DBG1 0x1916 |
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| 125 | #define MT6359_VGPUVCORE_ANA_CON2 0x198e |
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| 126 | #define MT6359_VGPUVCORE_ANA_CON13 0x19a4 |
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| 127 | #define MT6359_VPROC1_ANA_CON3 0x19b2 |
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| 128 | #define MT6359_VPROC2_ANA_CON3 0x1a0e |
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| 129 | #define MT6359_VMODEM_ANA_CON3 0x1a1a |
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| 130 | #define MT6359_VPU_ANA_CON3 0x1a26 |
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| 131 | #define MT6359_VS1_ANA_CON0 0x1a2c |
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| 132 | #define MT6359_VS2_ANA_CON0 0x1a34 |
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| 133 | #define MT6359_VPA_ANA_CON0 0x1a3c |
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| 134 | #define MT6359_LDO_TOP_INT_CON0 0x1b14 |
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| 135 | #define MT6359_LDO_TOP_INT_CON1 0x1b1a |
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| 136 | #define MT6359_LDO_TOP_INT_STATUS0 0x1b28 |
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| 137 | #define MT6359_LDO_TOP_INT_STATUS1 0x1b2a |
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| 138 | #define MT6359_LDO_VSRAM_PROC1_ELR 0x1b40 |
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| 139 | #define MT6359_LDO_VSRAM_PROC2_ELR 0x1b42 |
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| 140 | #define MT6359_LDO_VSRAM_OTHERS_ELR 0x1b44 |
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| 141 | #define MT6359_LDO_VSRAM_MD_ELR 0x1b46 |
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| 142 | #define MT6359_LDO_VFE28_CON0 0x1b88 |
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| 143 | #define MT6359_LDO_VFE28_MON 0x1b8a |
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| 144 | #define MT6359_LDO_VXO22_CON0 0x1b98 |
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| 145 | #define MT6359_LDO_VXO22_MON 0x1b9a |
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| 146 | #define MT6359_LDO_VRF18_CON0 0x1ba8 |
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| 147 | #define MT6359_LDO_VRF18_MON 0x1baa |
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| 148 | #define MT6359_LDO_VRF12_CON0 0x1bb8 |
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| 149 | #define MT6359_LDO_VRF12_MON 0x1bba |
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| 150 | #define MT6359_LDO_VEFUSE_CON0 0x1bc8 |
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| 151 | #define MT6359_LDO_VEFUSE_MON 0x1bca |
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| 152 | #define MT6359_LDO_VCN33_1_CON0 0x1bd8 |
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| 153 | #define MT6359_LDO_VCN33_1_MON 0x1bda |
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| 154 | #define MT6359_LDO_VCN33_1_MULTI_SW 0x1be8 |
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| 155 | #define MT6359_LDO_VCN33_2_CON0 0x1c08 |
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| 156 | #define MT6359_LDO_VCN33_2_MON 0x1c0a |
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| 157 | #define MT6359_LDO_VCN33_2_MULTI_SW 0x1c18 |
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| 158 | #define MT6359_LDO_VCN13_CON0 0x1c1a |
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| 159 | #define MT6359_LDO_VCN13_MON 0x1c1c |
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| 160 | #define MT6359_LDO_VCN18_CON0 0x1c2a |
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| 161 | #define MT6359_LDO_VCN18_MON 0x1c2c |
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| 162 | #define MT6359_LDO_VA09_CON0 0x1c3a |
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| 163 | #define MT6359_LDO_VA09_MON 0x1c3c |
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| 164 | #define MT6359_LDO_VCAMIO_CON0 0x1c4a |
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| 165 | #define MT6359_LDO_VCAMIO_MON 0x1c4c |
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| 166 | #define MT6359_LDO_VA12_CON0 0x1c5a |
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| 167 | #define MT6359_LDO_VA12_MON 0x1c5c |
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| 168 | #define MT6359_LDO_VAUX18_CON0 0x1c88 |
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| 169 | #define MT6359_LDO_VAUX18_MON 0x1c8a |
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| 170 | #define MT6359_LDO_VAUD18_CON0 0x1c98 |
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| 171 | #define MT6359_LDO_VAUD18_MON 0x1c9a |
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| 172 | #define MT6359_LDO_VIO18_CON0 0x1ca8 |
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| 173 | #define MT6359_LDO_VIO18_MON 0x1caa |
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| 174 | #define MT6359_LDO_VEMC_CON0 0x1cb8 |
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| 175 | #define MT6359_LDO_VEMC_MON 0x1cba |
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| 176 | #define MT6359_LDO_VSIM1_CON0 0x1cc8 |
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| 177 | #define MT6359_LDO_VSIM1_MON 0x1cca |
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| 178 | #define MT6359_LDO_VSIM2_CON0 0x1cd8 |
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| 179 | #define MT6359_LDO_VSIM2_MON 0x1cda |
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| 180 | #define MT6359_LDO_VUSB_CON0 0x1d08 |
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| 181 | #define MT6359_LDO_VUSB_MON 0x1d0a |
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| 182 | #define MT6359_LDO_VUSB_MULTI_SW 0x1d18 |
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| 183 | #define MT6359_LDO_VRFCK_CON0 0x1d1a |
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| 184 | #define MT6359_LDO_VRFCK_MON 0x1d1c |
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| 185 | #define MT6359_LDO_VBBCK_CON0 0x1d2a |
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| 186 | #define MT6359_LDO_VBBCK_MON 0x1d2c |
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| 187 | #define MT6359_LDO_VBIF28_CON0 0x1d3a |
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| 188 | #define MT6359_LDO_VBIF28_MON 0x1d3c |
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| 189 | #define MT6359_LDO_VIBR_CON0 0x1d4a |
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| 190 | #define MT6359_LDO_VIBR_MON 0x1d4c |
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| 191 | #define MT6359_LDO_VIO28_CON0 0x1d5a |
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| 192 | #define MT6359_LDO_VIO28_MON 0x1d5c |
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| 193 | #define MT6359_LDO_VM18_CON0 0x1d88 |
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| 194 | #define MT6359_LDO_VM18_MON 0x1d8a |
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| 195 | #define MT6359_LDO_VUFS_CON0 0x1d98 |
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| 196 | #define MT6359_LDO_VUFS_MON 0x1d9a |
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| 197 | #define MT6359_LDO_VSRAM_PROC1_CON0 0x1e88 |
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| 198 | #define MT6359_LDO_VSRAM_PROC1_MON 0x1e8a |
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| 199 | #define MT6359_LDO_VSRAM_PROC1_VOSEL1 0x1e8e |
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| 200 | #define MT6359_LDO_VSRAM_PROC2_CON0 0x1ea6 |
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| 201 | #define MT6359_LDO_VSRAM_PROC2_MON 0x1ea8 |
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| 202 | #define MT6359_LDO_VSRAM_PROC2_VOSEL1 0x1eac |
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| 203 | #define MT6359_LDO_VSRAM_OTHERS_CON0 0x1f08 |
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| 204 | #define MT6359_LDO_VSRAM_OTHERS_MON 0x1f0a |
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| 205 | #define MT6359_LDO_VSRAM_OTHERS_VOSEL1 0x1f0e |
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| 206 | #define MT6359_LDO_VSRAM_OTHERS_SSHUB 0x1f26 |
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| 207 | #define MT6359_LDO_VSRAM_MD_CON0 0x1f2c |
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| 208 | #define MT6359_LDO_VSRAM_MD_MON 0x1f2e |
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| 209 | #define MT6359_LDO_VSRAM_MD_VOSEL1 0x1f32 |
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| 210 | #define MT6359_VFE28_ANA_CON0 0x1f88 |
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| 211 | #define MT6359_VAUX18_ANA_CON0 0x1f8c |
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| 212 | #define MT6359_VUSB_ANA_CON0 0x1f90 |
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| 213 | #define MT6359_VBIF28_ANA_CON0 0x1f94 |
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| 214 | #define MT6359_VCN33_1_ANA_CON0 0x1f98 |
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| 215 | #define MT6359_VCN33_2_ANA_CON0 0x1f9c |
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| 216 | #define MT6359_VEMC_ANA_CON0 0x1fa0 |
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| 217 | #define MT6359_VSIM1_ANA_CON0 0x1fa4 |
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| 218 | #define MT6359_VSIM2_ANA_CON0 0x1fa8 |
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| 219 | #define MT6359_VIO28_ANA_CON0 0x1fac |
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| 220 | #define MT6359_VIBR_ANA_CON0 0x1fb0 |
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| 221 | #define MT6359_VRF18_ANA_CON0 0x2008 |
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| 222 | #define MT6359_VEFUSE_ANA_CON0 0x200c |
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| 223 | #define MT6359_VCN18_ANA_CON0 0x2010 |
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| 224 | #define MT6359_VCAMIO_ANA_CON0 0x2014 |
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| 225 | #define MT6359_VAUD18_ANA_CON0 0x2018 |
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| 226 | #define MT6359_VIO18_ANA_CON0 0x201c |
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| 227 | #define MT6359_VM18_ANA_CON0 0x2020 |
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| 228 | #define MT6359_VUFS_ANA_CON0 0x2024 |
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| 229 | #define MT6359_VRF12_ANA_CON0 0x202a |
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| 230 | #define MT6359_VCN13_ANA_CON0 0x202e |
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| 231 | #define MT6359_VA09_ANA_CON0 0x2032 |
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| 232 | #define MT6359_VA12_ANA_CON0 0x2036 |
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| 233 | #define MT6359_VXO22_ANA_CON0 0x2088 |
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| 234 | #define MT6359_VRFCK_ANA_CON0 0x208c |
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| 235 | #define MT6359_VBBCK_ANA_CON0 0x2094 |
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| 236 | #define MT6359_AUD_TOP_INT_CON0 0x2328 |
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| 237 | #define MT6359_AUD_TOP_INT_STATUS0 0x2334 |
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| 238 | |
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| 239 | #define MT6359_RG_BUCK_VPU_EN_ADDR MT6359_BUCK_VPU_CON0 |
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| 240 | #define MT6359_RG_BUCK_VPU_LP_ADDR MT6359_BUCK_VPU_CON0 |
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| 241 | #define MT6359_RG_BUCK_VPU_LP_SHIFT 1 |
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| 242 | #define MT6359_DA_VPU_VOSEL_ADDR MT6359_BUCK_VPU_DBG0 |
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| 243 | #define MT6359_DA_VPU_VOSEL_MASK 0x7F |
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| 244 | #define MT6359_DA_VPU_VOSEL_SHIFT 0 |
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| 245 | #define MT6359_DA_VPU_EN_ADDR MT6359_BUCK_VPU_DBG1 |
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| 246 | #define MT6359_RG_BUCK_VPU_VOSEL_ADDR MT6359_BUCK_VPU_ELR0 |
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| 247 | #define MT6359_RG_BUCK_VPU_VOSEL_MASK 0x7F |
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| 248 | #define MT6359_RG_BUCK_VPU_VOSEL_SHIFT 0 |
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| 249 | #define MT6359_RG_BUCK_VCORE_EN_ADDR MT6359_BUCK_VCORE_CON0 |
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| 250 | #define MT6359_RG_BUCK_VCORE_LP_ADDR MT6359_BUCK_VCORE_CON0 |
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| 251 | #define MT6359_RG_BUCK_VCORE_LP_SHIFT 1 |
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| 252 | #define MT6359_DA_VCORE_VOSEL_ADDR MT6359_BUCK_VCORE_DBG0 |
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| 253 | #define MT6359_DA_VCORE_VOSEL_MASK 0x7F |
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| 254 | #define MT6359_DA_VCORE_VOSEL_SHIFT 0 |
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| 255 | #define MT6359_DA_VCORE_EN_ADDR MT6359_BUCK_VCORE_DBG1 |
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| 256 | #define MT6359_RG_BUCK_VCORE_SSHUB_EN_ADDR MT6359_BUCK_VCORE_SSHUB_CON0 |
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| 257 | #define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_ADDR MT6359_BUCK_VCORE_SSHUB_CON0 |
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| 258 | #define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_MASK 0x7F |
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| 259 | #define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_SHIFT 4 |
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| 260 | #define MT6359_RG_BUCK_VCORE_VOSEL_ADDR MT6359_BUCK_VCORE_ELR0 |
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| 261 | #define MT6359_RG_BUCK_VCORE_VOSEL_MASK 0x7F |
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| 262 | #define MT6359_RG_BUCK_VCORE_VOSEL_SHIFT 0 |
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| 263 | #define MT6359_RG_BUCK_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_CON0 |
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| 264 | #define MT6359_RG_BUCK_VGPU11_LP_ADDR MT6359_BUCK_VGPU11_CON0 |
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| 265 | #define MT6359_RG_BUCK_VGPU11_LP_SHIFT 1 |
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| 266 | #define MT6359_DA_VGPU11_VOSEL_ADDR MT6359_BUCK_VGPU11_DBG0 |
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| 267 | #define MT6359_DA_VGPU11_VOSEL_MASK 0x7F |
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| 268 | #define MT6359_DA_VGPU11_VOSEL_SHIFT 0 |
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| 269 | #define MT6359_DA_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_DBG1 |
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| 270 | #define MT6359_RG_BUCK_VGPU11_VOSEL_ADDR MT6359_BUCK_VGPU11_ELR0 |
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| 271 | #define MT6359_RG_BUCK_VGPU11_VOSEL_MASK 0x7F |
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| 272 | #define MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT 0 |
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| 273 | #define MT6359_RG_BUCK_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_CON0 |
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| 274 | #define MT6359_RG_BUCK_VMODEM_LP_ADDR MT6359_BUCK_VMODEM_CON0 |
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| 275 | #define MT6359_RG_BUCK_VMODEM_LP_SHIFT 1 |
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| 276 | #define MT6359_DA_VMODEM_VOSEL_ADDR MT6359_BUCK_VMODEM_DBG0 |
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| 277 | #define MT6359_DA_VMODEM_VOSEL_MASK 0x7F |
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| 278 | #define MT6359_DA_VMODEM_VOSEL_SHIFT 0 |
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| 279 | #define MT6359_DA_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_DBG1 |
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| 280 | #define MT6359_RG_BUCK_VMODEM_VOSEL_ADDR MT6359_BUCK_VMODEM_ELR0 |
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| 281 | #define MT6359_RG_BUCK_VMODEM_VOSEL_MASK 0x7F |
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| 282 | #define MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT 0 |
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| 283 | #define MT6359_RG_BUCK_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_CON0 |
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| 284 | #define MT6359_RG_BUCK_VPROC1_LP_ADDR MT6359_BUCK_VPROC1_CON0 |
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| 285 | #define MT6359_RG_BUCK_VPROC1_LP_SHIFT 1 |
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| 286 | #define MT6359_DA_VPROC1_VOSEL_ADDR MT6359_BUCK_VPROC1_DBG0 |
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| 287 | #define MT6359_DA_VPROC1_VOSEL_MASK 0x7F |
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| 288 | #define MT6359_DA_VPROC1_VOSEL_SHIFT 0 |
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| 289 | #define MT6359_DA_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_DBG1 |
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| 290 | #define MT6359_RG_BUCK_VPROC1_VOSEL_ADDR MT6359_BUCK_VPROC1_ELR0 |
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| 291 | #define MT6359_RG_BUCK_VPROC1_VOSEL_MASK 0x7F |
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| 292 | #define MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT 0 |
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| 293 | #define MT6359_RG_BUCK_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_CON0 |
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| 294 | #define MT6359_RG_BUCK_VPROC2_LP_ADDR MT6359_BUCK_VPROC2_CON0 |
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| 295 | #define MT6359_RG_BUCK_VPROC2_LP_SHIFT 1 |
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| 296 | #define MT6359_DA_VPROC2_VOSEL_ADDR MT6359_BUCK_VPROC2_DBG0 |
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| 297 | #define MT6359_DA_VPROC2_VOSEL_MASK 0x7F |
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| 298 | #define MT6359_DA_VPROC2_VOSEL_SHIFT 0 |
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| 299 | #define MT6359_DA_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_DBG1 |
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| 300 | #define MT6359_RG_BUCK_VPROC2_VOSEL_ADDR MT6359_BUCK_VPROC2_ELR0 |
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| 301 | #define MT6359_RG_BUCK_VPROC2_VOSEL_MASK 0x7F |
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| 302 | #define MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT 0 |
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| 303 | #define MT6359_RG_BUCK_VS1_EN_ADDR MT6359_BUCK_VS1_CON0 |
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| 304 | #define MT6359_RG_BUCK_VS1_LP_ADDR MT6359_BUCK_VS1_CON0 |
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| 305 | #define MT6359_RG_BUCK_VS1_LP_SHIFT 1 |
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| 306 | #define MT6359_DA_VS1_VOSEL_ADDR MT6359_BUCK_VS1_DBG0 |
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| 307 | #define MT6359_DA_VS1_VOSEL_MASK 0x7F |
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| 308 | #define MT6359_DA_VS1_VOSEL_SHIFT 0 |
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| 309 | #define MT6359_DA_VS1_EN_ADDR MT6359_BUCK_VS1_DBG1 |
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| 310 | #define MT6359_RG_BUCK_VS1_VOSEL_ADDR MT6359_BUCK_VS1_ELR0 |
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| 311 | #define MT6359_RG_BUCK_VS1_VOSEL_MASK 0x7F |
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| 312 | #define MT6359_RG_BUCK_VS1_VOSEL_SHIFT 0 |
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| 313 | #define MT6359_RG_BUCK_VS2_EN_ADDR MT6359_BUCK_VS2_CON0 |
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| 314 | #define MT6359_RG_BUCK_VS2_LP_ADDR MT6359_BUCK_VS2_CON0 |
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| 315 | #define MT6359_RG_BUCK_VS2_LP_SHIFT 1 |
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| 316 | #define MT6359_DA_VS2_VOSEL_ADDR MT6359_BUCK_VS2_DBG0 |
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| 317 | #define MT6359_DA_VS2_VOSEL_MASK 0x7F |
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| 318 | #define MT6359_DA_VS2_VOSEL_SHIFT 0 |
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| 319 | #define MT6359_DA_VS2_EN_ADDR MT6359_BUCK_VS2_DBG1 |
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| 320 | #define MT6359_RG_BUCK_VS2_VOSEL_ADDR MT6359_BUCK_VS2_ELR0 |
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| 321 | #define MT6359_RG_BUCK_VS2_VOSEL_MASK 0x7F |
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| 322 | #define MT6359_RG_BUCK_VS2_VOSEL_SHIFT 0 |
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| 323 | #define MT6359_RG_BUCK_VPA_EN_ADDR MT6359_BUCK_VPA_CON0 |
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| 324 | #define MT6359_RG_BUCK_VPA_LP_ADDR MT6359_BUCK_VPA_CON0 |
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| 325 | #define MT6359_RG_BUCK_VPA_LP_SHIFT 1 |
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| 326 | #define MT6359_RG_BUCK_VPA_VOSEL_ADDR MT6359_BUCK_VPA_CON1 |
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| 327 | #define MT6359_RG_BUCK_VPA_VOSEL_MASK 0x3F |
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| 328 | #define MT6359_RG_BUCK_VPA_VOSEL_SHIFT 0 |
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| 329 | #define MT6359_DA_VPA_VOSEL_ADDR MT6359_BUCK_VPA_DBG0 |
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| 330 | #define MT6359_DA_VPA_VOSEL_MASK 0x3F |
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| 331 | #define MT6359_DA_VPA_VOSEL_SHIFT 0 |
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| 332 | #define MT6359_DA_VPA_EN_ADDR MT6359_BUCK_VPA_DBG1 |
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| 333 | #define MT6359_RG_VGPU11_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON2 |
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| 334 | #define MT6359_RG_VGPU11_FCCM_SHIFT 9 |
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| 335 | #define MT6359_RG_VCORE_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON13 |
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| 336 | #define MT6359_RG_VCORE_FCCM_SHIFT 5 |
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| 337 | #define MT6359_RG_VPROC1_FCCM_ADDR MT6359_VPROC1_ANA_CON3 |
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| 338 | #define MT6359_RG_VPROC1_FCCM_SHIFT 1 |
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| 339 | #define MT6359_RG_VPROC2_FCCM_ADDR MT6359_VPROC2_ANA_CON3 |
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| 340 | #define MT6359_RG_VPROC2_FCCM_SHIFT 1 |
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| 341 | #define MT6359_RG_VMODEM_FCCM_ADDR MT6359_VMODEM_ANA_CON3 |
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| 342 | #define MT6359_RG_VMODEM_FCCM_SHIFT 1 |
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| 343 | #define MT6359_RG_VPU_FCCM_ADDR MT6359_VPU_ANA_CON3 |
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| 344 | #define MT6359_RG_VPU_FCCM_SHIFT 1 |
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| 345 | #define MT6359_RG_VS1_FPWM_ADDR MT6359_VS1_ANA_CON0 |
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| 346 | #define MT6359_RG_VS1_FPWM_SHIFT 3 |
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| 347 | #define MT6359_RG_VS2_FPWM_ADDR MT6359_VS2_ANA_CON0 |
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| 348 | #define MT6359_RG_VS2_FPWM_SHIFT 3 |
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| 349 | #define MT6359_RG_VPA_MODESET_ADDR MT6359_VPA_ANA_CON0 |
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| 350 | #define MT6359_RG_VPA_MODESET_SHIFT 1 |
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| 351 | #define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_ADDR MT6359_LDO_VSRAM_PROC1_ELR |
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| 352 | #define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK 0x7F |
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| 353 | #define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT 0 |
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| 354 | #define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_ADDR MT6359_LDO_VSRAM_PROC2_ELR |
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| 355 | #define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK 0x7F |
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| 356 | #define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT 0 |
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| 357 | #define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR MT6359_LDO_VSRAM_OTHERS_ELR |
|---|
| 358 | #define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK 0x7F |
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| 359 | #define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT 0 |
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| 360 | #define MT6359_RG_LDO_VSRAM_MD_VOSEL_ADDR MT6359_LDO_VSRAM_MD_ELR |
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| 361 | #define MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK 0x7F |
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| 362 | #define MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT 0 |
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| 363 | #define MT6359_RG_LDO_VFE28_EN_ADDR MT6359_LDO_VFE28_CON0 |
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| 364 | #define MT6359_DA_VFE28_B_EN_ADDR MT6359_LDO_VFE28_MON |
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| 365 | #define MT6359_RG_LDO_VXO22_EN_ADDR MT6359_LDO_VXO22_CON0 |
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| 366 | #define MT6359_RG_LDO_VXO22_EN_SHIFT 0 |
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| 367 | #define MT6359_DA_VXO22_B_EN_ADDR MT6359_LDO_VXO22_MON |
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| 368 | #define MT6359_RG_LDO_VRF18_EN_ADDR MT6359_LDO_VRF18_CON0 |
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| 369 | #define MT6359_RG_LDO_VRF18_EN_SHIFT 0 |
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| 370 | #define MT6359_DA_VRF18_B_EN_ADDR MT6359_LDO_VRF18_MON |
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| 371 | #define MT6359_RG_LDO_VRF12_EN_ADDR MT6359_LDO_VRF12_CON0 |
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| 372 | #define MT6359_RG_LDO_VRF12_EN_SHIFT 0 |
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| 373 | #define MT6359_DA_VRF12_B_EN_ADDR MT6359_LDO_VRF12_MON |
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| 374 | #define MT6359_RG_LDO_VEFUSE_EN_ADDR MT6359_LDO_VEFUSE_CON0 |
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| 375 | #define MT6359_RG_LDO_VEFUSE_EN_SHIFT 0 |
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| 376 | #define MT6359_DA_VEFUSE_B_EN_ADDR MT6359_LDO_VEFUSE_MON |
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| 377 | #define MT6359_RG_LDO_VCN33_1_EN_0_ADDR MT6359_LDO_VCN33_1_CON0 |
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| 378 | #define MT6359_RG_LDO_VCN33_1_EN_0_MASK 0x1 |
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| 379 | #define MT6359_RG_LDO_VCN33_1_EN_0_SHIFT 0 |
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| 380 | #define MT6359_DA_VCN33_1_B_EN_ADDR MT6359_LDO_VCN33_1_MON |
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| 381 | #define MT6359_RG_LDO_VCN33_1_EN_1_ADDR MT6359_LDO_VCN33_1_MULTI_SW |
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| 382 | #define MT6359_RG_LDO_VCN33_1_EN_1_SHIFT 15 |
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| 383 | #define MT6359_RG_LDO_VCN33_2_EN_0_ADDR MT6359_LDO_VCN33_2_CON0 |
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| 384 | #define MT6359_RG_LDO_VCN33_2_EN_0_SHIFT 0 |
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| 385 | #define MT6359_DA_VCN33_2_B_EN_ADDR MT6359_LDO_VCN33_2_MON |
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| 386 | #define MT6359_RG_LDO_VCN33_2_EN_1_ADDR MT6359_LDO_VCN33_2_MULTI_SW |
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| 387 | #define MT6359_RG_LDO_VCN33_2_EN_1_MASK 0x1 |
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| 388 | #define MT6359_RG_LDO_VCN33_2_EN_1_SHIFT 15 |
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| 389 | #define MT6359_RG_LDO_VCN13_EN_ADDR MT6359_LDO_VCN13_CON0 |
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| 390 | #define MT6359_RG_LDO_VCN13_EN_SHIFT 0 |
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| 391 | #define MT6359_DA_VCN13_B_EN_ADDR MT6359_LDO_VCN13_MON |
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| 392 | #define MT6359_RG_LDO_VCN18_EN_ADDR MT6359_LDO_VCN18_CON0 |
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| 393 | #define MT6359_DA_VCN18_B_EN_ADDR MT6359_LDO_VCN18_MON |
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| 394 | #define MT6359_RG_LDO_VA09_EN_ADDR MT6359_LDO_VA09_CON0 |
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| 395 | #define MT6359_RG_LDO_VA09_EN_SHIFT 0 |
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| 396 | #define MT6359_DA_VA09_B_EN_ADDR MT6359_LDO_VA09_MON |
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| 397 | #define MT6359_RG_LDO_VCAMIO_EN_ADDR MT6359_LDO_VCAMIO_CON0 |
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| 398 | #define MT6359_RG_LDO_VCAMIO_EN_SHIFT 0 |
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| 399 | #define MT6359_DA_VCAMIO_B_EN_ADDR MT6359_LDO_VCAMIO_MON |
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| 400 | #define MT6359_RG_LDO_VA12_EN_ADDR MT6359_LDO_VA12_CON0 |
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| 401 | #define MT6359_RG_LDO_VA12_EN_SHIFT 0 |
|---|
| 402 | #define MT6359_DA_VA12_B_EN_ADDR MT6359_LDO_VA12_MON |
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| 403 | #define MT6359_RG_LDO_VAUX18_EN_ADDR MT6359_LDO_VAUX18_CON0 |
|---|
| 404 | #define MT6359_DA_VAUX18_B_EN_ADDR MT6359_LDO_VAUX18_MON |
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| 405 | #define MT6359_RG_LDO_VAUD18_EN_ADDR MT6359_LDO_VAUD18_CON0 |
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| 406 | #define MT6359_DA_VAUD18_B_EN_ADDR MT6359_LDO_VAUD18_MON |
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| 407 | #define MT6359_RG_LDO_VIO18_EN_ADDR MT6359_LDO_VIO18_CON0 |
|---|
| 408 | #define MT6359_RG_LDO_VIO18_EN_SHIFT 0 |
|---|
| 409 | #define MT6359_DA_VIO18_B_EN_ADDR MT6359_LDO_VIO18_MON |
|---|
| 410 | #define MT6359_RG_LDO_VEMC_EN_ADDR MT6359_LDO_VEMC_CON0 |
|---|
| 411 | #define MT6359_RG_LDO_VEMC_EN_SHIFT 0 |
|---|
| 412 | #define MT6359_DA_VEMC_B_EN_ADDR MT6359_LDO_VEMC_MON |
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| 413 | #define MT6359_RG_LDO_VSIM1_EN_ADDR MT6359_LDO_VSIM1_CON0 |
|---|
| 414 | #define MT6359_RG_LDO_VSIM1_EN_SHIFT 0 |
|---|
| 415 | #define MT6359_DA_VSIM1_B_EN_ADDR MT6359_LDO_VSIM1_MON |
|---|
| 416 | #define MT6359_RG_LDO_VSIM2_EN_ADDR MT6359_LDO_VSIM2_CON0 |
|---|
| 417 | #define MT6359_RG_LDO_VSIM2_EN_SHIFT 0 |
|---|
| 418 | #define MT6359_DA_VSIM2_B_EN_ADDR MT6359_LDO_VSIM2_MON |
|---|
| 419 | #define MT6359_RG_LDO_VUSB_EN_0_ADDR MT6359_LDO_VUSB_CON0 |
|---|
| 420 | #define MT6359_RG_LDO_VUSB_EN_0_MASK 0x1 |
|---|
| 421 | #define MT6359_RG_LDO_VUSB_EN_0_SHIFT 0 |
|---|
| 422 | #define MT6359_DA_VUSB_B_EN_ADDR MT6359_LDO_VUSB_MON |
|---|
| 423 | #define MT6359_RG_LDO_VUSB_EN_1_ADDR MT6359_LDO_VUSB_MULTI_SW |
|---|
| 424 | #define MT6359_RG_LDO_VUSB_EN_1_MASK 0x1 |
|---|
| 425 | #define MT6359_RG_LDO_VUSB_EN_1_SHIFT 15 |
|---|
| 426 | #define MT6359_RG_LDO_VRFCK_EN_ADDR MT6359_LDO_VRFCK_CON0 |
|---|
| 427 | #define MT6359_RG_LDO_VRFCK_EN_SHIFT 0 |
|---|
| 428 | #define MT6359_DA_VRFCK_B_EN_ADDR MT6359_LDO_VRFCK_MON |
|---|
| 429 | #define MT6359_RG_LDO_VBBCK_EN_ADDR MT6359_LDO_VBBCK_CON0 |
|---|
| 430 | #define MT6359_RG_LDO_VBBCK_EN_SHIFT 0 |
|---|
| 431 | #define MT6359_DA_VBBCK_B_EN_ADDR MT6359_LDO_VBBCK_MON |
|---|
| 432 | #define MT6359_RG_LDO_VBIF28_EN_ADDR MT6359_LDO_VBIF28_CON0 |
|---|
| 433 | #define MT6359_DA_VBIF28_B_EN_ADDR MT6359_LDO_VBIF28_MON |
|---|
| 434 | #define MT6359_RG_LDO_VIBR_EN_ADDR MT6359_LDO_VIBR_CON0 |
|---|
| 435 | #define MT6359_RG_LDO_VIBR_EN_SHIFT 0 |
|---|
| 436 | #define MT6359_DA_VIBR_B_EN_ADDR MT6359_LDO_VIBR_MON |
|---|
| 437 | #define MT6359_RG_LDO_VIO28_EN_ADDR MT6359_LDO_VIO28_CON0 |
|---|
| 438 | #define MT6359_RG_LDO_VIO28_EN_SHIFT 0 |
|---|
| 439 | #define MT6359_DA_VIO28_B_EN_ADDR MT6359_LDO_VIO28_MON |
|---|
| 440 | #define MT6359_RG_LDO_VM18_EN_ADDR MT6359_LDO_VM18_CON0 |
|---|
| 441 | #define MT6359_RG_LDO_VM18_EN_SHIFT 0 |
|---|
| 442 | #define MT6359_DA_VM18_B_EN_ADDR MT6359_LDO_VM18_MON |
|---|
| 443 | #define MT6359_RG_LDO_VUFS_EN_ADDR MT6359_LDO_VUFS_CON0 |
|---|
| 444 | #define MT6359_RG_LDO_VUFS_EN_SHIFT 0 |
|---|
| 445 | #define MT6359_DA_VUFS_B_EN_ADDR MT6359_LDO_VUFS_MON |
|---|
| 446 | #define MT6359_RG_LDO_VSRAM_PROC1_EN_ADDR MT6359_LDO_VSRAM_PROC1_CON0 |
|---|
| 447 | #define MT6359_DA_VSRAM_PROC1_B_EN_ADDR MT6359_LDO_VSRAM_PROC1_MON |
|---|
| 448 | #define MT6359_DA_VSRAM_PROC1_VOSEL_ADDR MT6359_LDO_VSRAM_PROC1_VOSEL1 |
|---|
| 449 | #define MT6359_DA_VSRAM_PROC1_VOSEL_MASK 0x7F |
|---|
| 450 | #define MT6359_DA_VSRAM_PROC1_VOSEL_SHIFT 8 |
|---|
| 451 | #define MT6359_RG_LDO_VSRAM_PROC2_EN_ADDR MT6359_LDO_VSRAM_PROC2_CON0 |
|---|
| 452 | #define MT6359_DA_VSRAM_PROC2_B_EN_ADDR MT6359_LDO_VSRAM_PROC2_MON |
|---|
| 453 | #define MT6359_DA_VSRAM_PROC2_VOSEL_ADDR MT6359_LDO_VSRAM_PROC2_VOSEL1 |
|---|
| 454 | #define MT6359_DA_VSRAM_PROC2_VOSEL_MASK 0x7F |
|---|
| 455 | #define MT6359_DA_VSRAM_PROC2_VOSEL_SHIFT 8 |
|---|
| 456 | #define MT6359_RG_LDO_VSRAM_OTHERS_EN_ADDR MT6359_LDO_VSRAM_OTHERS_CON0 |
|---|
| 457 | #define MT6359_DA_VSRAM_OTHERS_B_EN_ADDR MT6359_LDO_VSRAM_OTHERS_MON |
|---|
| 458 | #define MT6359_DA_VSRAM_OTHERS_VOSEL_ADDR MT6359_LDO_VSRAM_OTHERS_VOSEL1 |
|---|
| 459 | #define MT6359_DA_VSRAM_OTHERS_VOSEL_MASK 0x7F |
|---|
| 460 | #define MT6359_DA_VSRAM_OTHERS_VOSEL_SHIFT 8 |
|---|
| 461 | #define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR MT6359_LDO_VSRAM_OTHERS_SSHUB |
|---|
| 462 | #define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR MT6359_LDO_VSRAM_OTHERS_SSHUB |
|---|
| 463 | #define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK 0x7F |
|---|
| 464 | #define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT 1 |
|---|
| 465 | #define MT6359_RG_LDO_VSRAM_MD_EN_ADDR MT6359_LDO_VSRAM_MD_CON0 |
|---|
| 466 | #define MT6359_DA_VSRAM_MD_B_EN_ADDR MT6359_LDO_VSRAM_MD_MON |
|---|
| 467 | #define MT6359_DA_VSRAM_MD_VOSEL_ADDR MT6359_LDO_VSRAM_MD_VOSEL1 |
|---|
| 468 | #define MT6359_DA_VSRAM_MD_VOSEL_MASK 0x7F |
|---|
| 469 | #define MT6359_DA_VSRAM_MD_VOSEL_SHIFT 8 |
|---|
| 470 | #define MT6359_RG_VCN33_1_VOSEL_ADDR MT6359_VCN33_1_ANA_CON0 |
|---|
| 471 | #define MT6359_RG_VCN33_1_VOSEL_MASK 0xF |
|---|
| 472 | #define MT6359_RG_VCN33_1_VOSEL_SHIFT 8 |
|---|
| 473 | #define MT6359_RG_VCN33_2_VOSEL_ADDR MT6359_VCN33_2_ANA_CON0 |
|---|
| 474 | #define MT6359_RG_VCN33_2_VOSEL_MASK 0xF |
|---|
| 475 | #define MT6359_RG_VCN33_2_VOSEL_SHIFT 8 |
|---|
| 476 | #define MT6359_RG_VEMC_VOSEL_ADDR MT6359_VEMC_ANA_CON0 |
|---|
| 477 | #define MT6359_RG_VEMC_VOSEL_MASK 0xF |
|---|
| 478 | #define MT6359_RG_VEMC_VOSEL_SHIFT 8 |
|---|
| 479 | #define MT6359_RG_VSIM1_VOSEL_ADDR MT6359_VSIM1_ANA_CON0 |
|---|
| 480 | #define MT6359_RG_VSIM1_VOSEL_MASK 0xF |
|---|
| 481 | #define MT6359_RG_VSIM1_VOSEL_SHIFT 8 |
|---|
| 482 | #define MT6359_RG_VSIM2_VOSEL_ADDR MT6359_VSIM2_ANA_CON0 |
|---|
| 483 | #define MT6359_RG_VSIM2_VOSEL_MASK 0xF |
|---|
| 484 | #define MT6359_RG_VSIM2_VOSEL_SHIFT 8 |
|---|
| 485 | #define MT6359_RG_VIO28_VOSEL_ADDR MT6359_VIO28_ANA_CON0 |
|---|
| 486 | #define MT6359_RG_VIO28_VOSEL_MASK 0xF |
|---|
| 487 | #define MT6359_RG_VIO28_VOSEL_SHIFT 8 |
|---|
| 488 | #define MT6359_RG_VIBR_VOSEL_ADDR MT6359_VIBR_ANA_CON0 |
|---|
| 489 | #define MT6359_RG_VIBR_VOSEL_MASK 0xF |
|---|
| 490 | #define MT6359_RG_VIBR_VOSEL_SHIFT 8 |
|---|
| 491 | #define MT6359_RG_VRF18_VOSEL_ADDR MT6359_VRF18_ANA_CON0 |
|---|
| 492 | #define MT6359_RG_VRF18_VOSEL_MASK 0xF |
|---|
| 493 | #define MT6359_RG_VRF18_VOSEL_SHIFT 8 |
|---|
| 494 | #define MT6359_RG_VEFUSE_VOSEL_ADDR MT6359_VEFUSE_ANA_CON0 |
|---|
| 495 | #define MT6359_RG_VEFUSE_VOSEL_MASK 0xF |
|---|
| 496 | #define MT6359_RG_VEFUSE_VOSEL_SHIFT 8 |
|---|
| 497 | #define MT6359_RG_VCAMIO_VOSEL_ADDR MT6359_VCAMIO_ANA_CON0 |
|---|
| 498 | #define MT6359_RG_VCAMIO_VOSEL_MASK 0xF |
|---|
| 499 | #define MT6359_RG_VCAMIO_VOSEL_SHIFT 8 |
|---|
| 500 | #define MT6359_RG_VIO18_VOSEL_ADDR MT6359_VIO18_ANA_CON0 |
|---|
| 501 | #define MT6359_RG_VIO18_VOSEL_MASK 0xF |
|---|
| 502 | #define MT6359_RG_VIO18_VOSEL_SHIFT 8 |
|---|
| 503 | #define MT6359_RG_VM18_VOSEL_ADDR MT6359_VM18_ANA_CON0 |
|---|
| 504 | #define MT6359_RG_VM18_VOSEL_MASK 0xF |
|---|
| 505 | #define MT6359_RG_VM18_VOSEL_SHIFT 8 |
|---|
| 506 | #define MT6359_RG_VUFS_VOSEL_ADDR MT6359_VUFS_ANA_CON0 |
|---|
| 507 | #define MT6359_RG_VUFS_VOSEL_MASK 0xF |
|---|
| 508 | #define MT6359_RG_VUFS_VOSEL_SHIFT 8 |
|---|
| 509 | #define MT6359_RG_VRF12_VOSEL_ADDR MT6359_VRF12_ANA_CON0 |
|---|
| 510 | #define MT6359_RG_VRF12_VOSEL_MASK 0xF |
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| 511 | #define MT6359_RG_VRF12_VOSEL_SHIFT 8 |
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| 512 | #define MT6359_RG_VCN13_VOSEL_ADDR MT6359_VCN13_ANA_CON0 |
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| 513 | #define MT6359_RG_VCN13_VOSEL_MASK 0xF |
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| 514 | #define MT6359_RG_VCN13_VOSEL_SHIFT 8 |
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| 515 | #define MT6359_RG_VA09_VOSEL_ADDR MT6359_VA09_ANA_CON0 |
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| 516 | #define MT6359_RG_VA09_VOSEL_MASK 0xF |
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| 517 | #define MT6359_RG_VA09_VOSEL_SHIFT 8 |
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| 518 | #define MT6359_RG_VA12_VOSEL_ADDR MT6359_VA12_ANA_CON0 |
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| 519 | #define MT6359_RG_VA12_VOSEL_MASK 0xF |
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| 520 | #define MT6359_RG_VA12_VOSEL_SHIFT 8 |
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| 521 | #define MT6359_RG_VXO22_VOSEL_ADDR MT6359_VXO22_ANA_CON0 |
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| 522 | #define MT6359_RG_VXO22_VOSEL_MASK 0xF |
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| 523 | #define MT6359_RG_VXO22_VOSEL_SHIFT 8 |
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| 524 | #define MT6359_RG_VRFCK_VOSEL_ADDR MT6359_VRFCK_ANA_CON0 |
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| 525 | #define MT6359_RG_VRFCK_VOSEL_MASK 0xF |
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| 526 | #define MT6359_RG_VRFCK_VOSEL_SHIFT 8 |
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| 527 | #define MT6359_RG_VBBCK_VOSEL_ADDR MT6359_VBBCK_ANA_CON0 |
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| 528 | #define MT6359_RG_VBBCK_VOSEL_MASK 0xF |
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| 529 | #define MT6359_RG_VBBCK_VOSEL_SHIFT 8 |
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| 530 | |
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| 531 | #endif /* __MFD_MT6359_REGISTERS_H__ */ |
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| 532 | |
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