| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2022 AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __MFD_MT6331_REGISTERS_H__ |
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| 7 | #define __MFD_MT6331_REGISTERS_H__ |
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| 8 | |
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| 9 | /* PMIC Registers */ |
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| 10 | #define MT6331_STRUP_CON0 0x0 |
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| 11 | #define MT6331_STRUP_CON2 0x2 |
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| 12 | #define MT6331_STRUP_CON3 0x4 |
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| 13 | #define MT6331_STRUP_CON4 0x6 |
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| 14 | #define MT6331_STRUP_CON5 0x8 |
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| 15 | #define MT6331_STRUP_CON6 0xA |
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| 16 | #define MT6331_STRUP_CON7 0xC |
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| 17 | #define MT6331_STRUP_CON8 0xE |
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| 18 | #define MT6331_STRUP_CON9 0x10 |
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| 19 | #define MT6331_STRUP_CON10 0x12 |
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| 20 | #define MT6331_STRUP_CON11 0x14 |
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| 21 | #define MT6331_STRUP_CON12 0x16 |
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| 22 | #define MT6331_STRUP_CON13 0x18 |
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| 23 | #define MT6331_STRUP_CON14 0x1A |
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| 24 | #define MT6331_STRUP_CON15 0x1C |
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| 25 | #define MT6331_STRUP_CON16 0x1E |
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| 26 | #define MT6331_STRUP_CON17 0x20 |
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| 27 | #define MT6331_STRUP_CON18 0x22 |
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| 28 | #define MT6331_HWCID 0x100 |
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| 29 | #define MT6331_SWCID 0x102 |
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| 30 | #define MT6331_EXT_PMIC_STATUS 0x104 |
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| 31 | #define MT6331_TOP_CON 0x106 |
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| 32 | #define MT6331_TEST_OUT 0x108 |
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| 33 | #define MT6331_TEST_CON0 0x10A |
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| 34 | #define MT6331_TEST_CON1 0x10C |
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| 35 | #define MT6331_TESTMODE_SW 0x10E |
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| 36 | #define MT6331_EN_STATUS0 0x110 |
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| 37 | #define MT6331_EN_STATUS1 0x112 |
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| 38 | #define MT6331_EN_STATUS2 0x114 |
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| 39 | #define MT6331_OCSTATUS0 0x116 |
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| 40 | #define MT6331_OCSTATUS1 0x118 |
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| 41 | #define MT6331_OCSTATUS2 0x11A |
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| 42 | #define MT6331_PGSTATUS 0x11C |
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| 43 | #define MT6331_TOPSTATUS 0x11E |
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| 44 | #define MT6331_TDSEL_CON 0x120 |
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| 45 | #define MT6331_RDSEL_CON 0x122 |
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| 46 | #define MT6331_SMT_CON0 0x124 |
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| 47 | #define MT6331_SMT_CON1 0x126 |
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| 48 | #define MT6331_SMT_CON2 0x128 |
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| 49 | #define MT6331_DRV_CON0 0x12A |
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| 50 | #define MT6331_DRV_CON1 0x12C |
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| 51 | #define MT6331_DRV_CON2 0x12E |
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| 52 | #define MT6331_DRV_CON3 0x130 |
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| 53 | #define MT6331_TOP_STATUS 0x132 |
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| 54 | #define MT6331_TOP_STATUS_SET 0x134 |
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| 55 | #define MT6331_TOP_STATUS_CLR 0x136 |
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| 56 | #define MT6331_TOP_CKPDN_CON0 0x138 |
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| 57 | #define MT6331_TOP_CKPDN_CON0_SET 0x13A |
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| 58 | #define MT6331_TOP_CKPDN_CON0_CLR 0x13C |
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| 59 | #define MT6331_TOP_CKPDN_CON1 0x13E |
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| 60 | #define MT6331_TOP_CKPDN_CON1_SET 0x140 |
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| 61 | #define MT6331_TOP_CKPDN_CON1_CLR 0x142 |
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| 62 | #define MT6331_TOP_CKPDN_CON2 0x144 |
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| 63 | #define MT6331_TOP_CKPDN_CON2_SET 0x146 |
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| 64 | #define MT6331_TOP_CKPDN_CON2_CLR 0x148 |
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| 65 | #define MT6331_TOP_CKSEL_CON 0x14A |
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| 66 | #define MT6331_TOP_CKSEL_CON_SET 0x14C |
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| 67 | #define MT6331_TOP_CKSEL_CON_CLR 0x14E |
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| 68 | #define MT6331_TOP_CKHWEN_CON 0x150 |
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| 69 | #define MT6331_TOP_CKHWEN_CON_SET 0x152 |
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| 70 | #define MT6331_TOP_CKHWEN_CON_CLR 0x154 |
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| 71 | #define MT6331_TOP_CKTST_CON0 0x156 |
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| 72 | #define MT6331_TOP_CKTST_CON1 0x158 |
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| 73 | #define MT6331_TOP_CLKSQ 0x15A |
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| 74 | #define MT6331_TOP_CLKSQ_SET 0x15C |
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| 75 | #define MT6331_TOP_CLKSQ_CLR 0x15E |
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| 76 | #define MT6331_TOP_RST_CON 0x160 |
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| 77 | #define MT6331_TOP_RST_CON_SET 0x162 |
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| 78 | #define MT6331_TOP_RST_CON_CLR 0x164 |
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| 79 | #define MT6331_TOP_RST_MISC 0x166 |
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| 80 | #define MT6331_TOP_RST_MISC_SET 0x168 |
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| 81 | #define MT6331_TOP_RST_MISC_CLR 0x16A |
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| 82 | #define MT6331_INT_CON0 0x16C |
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| 83 | #define MT6331_INT_CON0_SET 0x16E |
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| 84 | #define MT6331_INT_CON0_CLR 0x170 |
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| 85 | #define MT6331_INT_CON1 0x172 |
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| 86 | #define MT6331_INT_CON1_SET 0x174 |
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| 87 | #define MT6331_INT_CON1_CLR 0x176 |
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| 88 | #define MT6331_INT_MISC_CON 0x178 |
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| 89 | #define MT6331_INT_MISC_CON_SET 0x17A |
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| 90 | #define MT6331_INT_MISC_CON_CLR 0x17C |
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| 91 | #define MT6331_INT_STATUS_CON0 0x17E |
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| 92 | #define MT6331_INT_STATUS_CON1 0x180 |
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| 93 | #define MT6331_OC_GEAR_0 0x182 |
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| 94 | #define MT6331_FQMTR_CON0 0x184 |
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| 95 | #define MT6331_FQMTR_CON1 0x186 |
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| 96 | #define MT6331_FQMTR_CON2 0x188 |
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| 97 | #define MT6331_RG_SPI_CON 0x18A |
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| 98 | #define MT6331_DEW_DIO_EN 0x18C |
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| 99 | #define MT6331_DEW_READ_TEST 0x18E |
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| 100 | #define MT6331_DEW_WRITE_TEST 0x190 |
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| 101 | #define MT6331_DEW_CRC_SWRST 0x192 |
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| 102 | #define MT6331_DEW_CRC_EN 0x194 |
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| 103 | #define MT6331_DEW_CRC_VAL 0x196 |
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| 104 | #define MT6331_DEW_DBG_MON_SEL 0x198 |
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| 105 | #define MT6331_DEW_CIPHER_KEY_SEL 0x19A |
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| 106 | #define MT6331_DEW_CIPHER_IV_SEL 0x19C |
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| 107 | #define MT6331_DEW_CIPHER_EN 0x19E |
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| 108 | #define MT6331_DEW_CIPHER_RDY 0x1A0 |
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| 109 | #define MT6331_DEW_CIPHER_MODE 0x1A2 |
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| 110 | #define MT6331_DEW_CIPHER_SWRST 0x1A4 |
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| 111 | #define MT6331_DEW_RDDMY_NO 0x1A6 |
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| 112 | #define MT6331_INT_TYPE_CON0 0x1A8 |
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| 113 | #define MT6331_INT_TYPE_CON0_SET 0x1AA |
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| 114 | #define MT6331_INT_TYPE_CON0_CLR 0x1AC |
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| 115 | #define MT6331_INT_TYPE_CON1 0x1AE |
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| 116 | #define MT6331_INT_TYPE_CON1_SET 0x1B0 |
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| 117 | #define MT6331_INT_TYPE_CON1_CLR 0x1B2 |
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| 118 | #define MT6331_INT_STA 0x1B4 |
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| 119 | #define MT6331_BUCK_ALL_CON0 0x200 |
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| 120 | #define MT6331_BUCK_ALL_CON1 0x202 |
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| 121 | #define MT6331_BUCK_ALL_CON2 0x204 |
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| 122 | #define MT6331_BUCK_ALL_CON3 0x206 |
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| 123 | #define MT6331_BUCK_ALL_CON4 0x208 |
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| 124 | #define MT6331_BUCK_ALL_CON5 0x20A |
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| 125 | #define MT6331_BUCK_ALL_CON6 0x20C |
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| 126 | #define MT6331_BUCK_ALL_CON7 0x20E |
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| 127 | #define MT6331_BUCK_ALL_CON8 0x210 |
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| 128 | #define MT6331_BUCK_ALL_CON9 0x212 |
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| 129 | #define MT6331_BUCK_ALL_CON10 0x214 |
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| 130 | #define MT6331_BUCK_ALL_CON11 0x216 |
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| 131 | #define MT6331_BUCK_ALL_CON12 0x218 |
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| 132 | #define MT6331_BUCK_ALL_CON13 0x21A |
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| 133 | #define MT6331_BUCK_ALL_CON14 0x21C |
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| 134 | #define MT6331_BUCK_ALL_CON15 0x21E |
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| 135 | #define MT6331_BUCK_ALL_CON16 0x220 |
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| 136 | #define MT6331_BUCK_ALL_CON17 0x222 |
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| 137 | #define MT6331_BUCK_ALL_CON18 0x224 |
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| 138 | #define MT6331_BUCK_ALL_CON19 0x226 |
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| 139 | #define MT6331_BUCK_ALL_CON20 0x228 |
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| 140 | #define MT6331_BUCK_ALL_CON21 0x22A |
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| 141 | #define MT6331_BUCK_ALL_CON22 0x22C |
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| 142 | #define MT6331_BUCK_ALL_CON23 0x22E |
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| 143 | #define MT6331_BUCK_ALL_CON24 0x230 |
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| 144 | #define MT6331_BUCK_ALL_CON25 0x232 |
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| 145 | #define MT6331_BUCK_ALL_CON26 0x234 |
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| 146 | #define MT6331_VDVFS11_CON0 0x236 |
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| 147 | #define MT6331_VDVFS11_CON1 0x238 |
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| 148 | #define MT6331_VDVFS11_CON2 0x23A |
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| 149 | #define MT6331_VDVFS11_CON3 0x23C |
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| 150 | #define MT6331_VDVFS11_CON4 0x23E |
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| 151 | #define MT6331_VDVFS11_CON5 0x240 |
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| 152 | #define MT6331_VDVFS11_CON6 0x242 |
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| 153 | #define MT6331_VDVFS11_CON7 0x244 |
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| 154 | #define MT6331_VDVFS11_CON8 0x246 |
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| 155 | #define MT6331_VDVFS11_CON9 0x248 |
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| 156 | #define MT6331_VDVFS11_CON10 0x24A |
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| 157 | #define MT6331_VDVFS11_CON11 0x24C |
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| 158 | #define MT6331_VDVFS11_CON12 0x24E |
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| 159 | #define MT6331_VDVFS11_CON13 0x250 |
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| 160 | #define MT6331_VDVFS11_CON14 0x252 |
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| 161 | #define MT6331_VDVFS11_CON18 0x25A |
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| 162 | #define MT6331_VDVFS11_CON19 0x25C |
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| 163 | #define MT6331_VDVFS11_CON20 0x25E |
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| 164 | #define MT6331_VDVFS11_CON21 0x260 |
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| 165 | #define MT6331_VDVFS11_CON22 0x262 |
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| 166 | #define MT6331_VDVFS11_CON23 0x264 |
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| 167 | #define MT6331_VDVFS11_CON24 0x266 |
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| 168 | #define MT6331_VDVFS11_CON25 0x268 |
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| 169 | #define MT6331_VDVFS11_CON26 0x26A |
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| 170 | #define MT6331_VDVFS11_CON27 0x26C |
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| 171 | #define MT6331_VDVFS12_CON0 0x26E |
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| 172 | #define MT6331_VDVFS12_CON1 0x270 |
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| 173 | #define MT6331_VDVFS12_CON2 0x272 |
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| 174 | #define MT6331_VDVFS12_CON3 0x274 |
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| 175 | #define MT6331_VDVFS12_CON4 0x276 |
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| 176 | #define MT6331_VDVFS12_CON5 0x278 |
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| 177 | #define MT6331_VDVFS12_CON6 0x27A |
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| 178 | #define MT6331_VDVFS12_CON7 0x27C |
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| 179 | #define MT6331_VDVFS12_CON8 0x27E |
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| 180 | #define MT6331_VDVFS12_CON9 0x280 |
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| 181 | #define MT6331_VDVFS12_CON10 0x282 |
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| 182 | #define MT6331_VDVFS12_CON11 0x284 |
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| 183 | #define MT6331_VDVFS12_CON12 0x286 |
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| 184 | #define MT6331_VDVFS12_CON13 0x288 |
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| 185 | #define MT6331_VDVFS12_CON14 0x28A |
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| 186 | #define MT6331_VDVFS12_CON18 0x292 |
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| 187 | #define MT6331_VDVFS12_CON19 0x294 |
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| 188 | #define MT6331_VDVFS12_CON20 0x296 |
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| 189 | #define MT6331_VDVFS13_CON0 0x298 |
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| 190 | #define MT6331_VDVFS13_CON1 0x29A |
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| 191 | #define MT6331_VDVFS13_CON2 0x29C |
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| 192 | #define MT6331_VDVFS13_CON3 0x29E |
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| 193 | #define MT6331_VDVFS13_CON4 0x2A0 |
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| 194 | #define MT6331_VDVFS13_CON5 0x2A2 |
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| 195 | #define MT6331_VDVFS13_CON6 0x2A4 |
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| 196 | #define MT6331_VDVFS13_CON7 0x2A6 |
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| 197 | #define MT6331_VDVFS13_CON8 0x2A8 |
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| 198 | #define MT6331_VDVFS13_CON9 0x2AA |
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| 199 | #define MT6331_VDVFS13_CON10 0x2AC |
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| 200 | #define MT6331_VDVFS13_CON11 0x2AE |
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| 201 | #define MT6331_VDVFS13_CON12 0x2B0 |
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| 202 | #define MT6331_VDVFS13_CON13 0x2B2 |
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| 203 | #define MT6331_VDVFS13_CON14 0x2B4 |
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| 204 | #define MT6331_VDVFS13_CON18 0x2BC |
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| 205 | #define MT6331_VDVFS13_CON19 0x2BE |
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| 206 | #define MT6331_VDVFS13_CON20 0x2C0 |
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| 207 | #define MT6331_VDVFS14_CON0 0x2C2 |
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| 208 | #define MT6331_VDVFS14_CON1 0x2C4 |
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| 209 | #define MT6331_VDVFS14_CON2 0x2C6 |
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| 210 | #define MT6331_VDVFS14_CON3 0x2C8 |
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| 211 | #define MT6331_VDVFS14_CON4 0x2CA |
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| 212 | #define MT6331_VDVFS14_CON5 0x2CC |
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| 213 | #define MT6331_VDVFS14_CON6 0x2CE |
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| 214 | #define MT6331_VDVFS14_CON7 0x2D0 |
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| 215 | #define MT6331_VDVFS14_CON8 0x2D2 |
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| 216 | #define MT6331_VDVFS14_CON9 0x2D4 |
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| 217 | #define MT6331_VDVFS14_CON10 0x2D6 |
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| 218 | #define MT6331_VDVFS14_CON11 0x2D8 |
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| 219 | #define MT6331_VDVFS14_CON12 0x2DA |
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| 220 | #define MT6331_VDVFS14_CON13 0x2DC |
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| 221 | #define MT6331_VDVFS14_CON14 0x2DE |
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| 222 | #define MT6331_VDVFS14_CON18 0x2E6 |
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| 223 | #define MT6331_VDVFS14_CON19 0x2E8 |
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| 224 | #define MT6331_VDVFS14_CON20 0x2EA |
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| 225 | #define MT6331_VGPU_CON0 0x300 |
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| 226 | #define MT6331_VGPU_CON1 0x302 |
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| 227 | #define MT6331_VGPU_CON2 0x304 |
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| 228 | #define MT6331_VGPU_CON3 0x306 |
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| 229 | #define MT6331_VGPU_CON4 0x308 |
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| 230 | #define MT6331_VGPU_CON5 0x30A |
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| 231 | #define MT6331_VGPU_CON6 0x30C |
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| 232 | #define MT6331_VGPU_CON7 0x30E |
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| 233 | #define MT6331_VGPU_CON8 0x310 |
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| 234 | #define MT6331_VGPU_CON9 0x312 |
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| 235 | #define MT6331_VGPU_CON10 0x314 |
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| 236 | #define MT6331_VGPU_CON11 0x316 |
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| 237 | #define MT6331_VGPU_CON12 0x318 |
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| 238 | #define MT6331_VGPU_CON13 0x31A |
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| 239 | #define MT6331_VGPU_CON14 0x31C |
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| 240 | #define MT6331_VGPU_CON15 0x31E |
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| 241 | #define MT6331_VGPU_CON16 0x320 |
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| 242 | #define MT6331_VGPU_CON17 0x322 |
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| 243 | #define MT6331_VGPU_CON18 0x324 |
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| 244 | #define MT6331_VGPU_CON19 0x326 |
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| 245 | #define MT6331_VGPU_CON20 0x328 |
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| 246 | #define MT6331_VCORE1_CON0 0x32A |
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| 247 | #define MT6331_VCORE1_CON1 0x32C |
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| 248 | #define MT6331_VCORE1_CON2 0x32E |
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| 249 | #define MT6331_VCORE1_CON3 0x330 |
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| 250 | #define MT6331_VCORE1_CON4 0x332 |
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| 251 | #define MT6331_VCORE1_CON5 0x334 |
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| 252 | #define MT6331_VCORE1_CON6 0x336 |
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| 253 | #define MT6331_VCORE1_CON7 0x338 |
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| 254 | #define MT6331_VCORE1_CON8 0x33A |
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| 255 | #define MT6331_VCORE1_CON9 0x33C |
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| 256 | #define MT6331_VCORE1_CON10 0x33E |
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| 257 | #define MT6331_VCORE1_CON11 0x340 |
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| 258 | #define MT6331_VCORE1_CON12 0x342 |
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| 259 | #define MT6331_VCORE1_CON13 0x344 |
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| 260 | #define MT6331_VCORE1_CON14 0x346 |
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| 261 | #define MT6331_VCORE1_CON15 0x348 |
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| 262 | #define MT6331_VCORE1_CON16 0x34A |
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| 263 | #define MT6331_VCORE1_CON17 0x34C |
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| 264 | #define MT6331_VCORE1_CON18 0x34E |
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| 265 | #define MT6331_VCORE1_CON19 0x350 |
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| 266 | #define MT6331_VCORE1_CON20 0x352 |
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| 267 | #define MT6331_VCORE2_CON0 0x354 |
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| 268 | #define MT6331_VCORE2_CON1 0x356 |
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| 269 | #define MT6331_VCORE2_CON2 0x358 |
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| 270 | #define MT6331_VCORE2_CON3 0x35A |
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| 271 | #define MT6331_VCORE2_CON4 0x35C |
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| 272 | #define MT6331_VCORE2_CON5 0x35E |
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| 273 | #define MT6331_VCORE2_CON6 0x360 |
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| 274 | #define MT6331_VCORE2_CON7 0x362 |
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| 275 | #define MT6331_VCORE2_CON8 0x364 |
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| 276 | #define MT6331_VCORE2_CON9 0x366 |
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| 277 | #define MT6331_VCORE2_CON10 0x368 |
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| 278 | #define MT6331_VCORE2_CON11 0x36A |
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| 279 | #define MT6331_VCORE2_CON12 0x36C |
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| 280 | #define MT6331_VCORE2_CON13 0x36E |
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| 281 | #define MT6331_VCORE2_CON14 0x370 |
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| 282 | #define MT6331_VCORE2_CON15 0x372 |
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| 283 | #define MT6331_VCORE2_CON16 0x374 |
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| 284 | #define MT6331_VCORE2_CON17 0x376 |
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| 285 | #define MT6331_VCORE2_CON18 0x378 |
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| 286 | #define MT6331_VCORE2_CON19 0x37A |
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| 287 | #define MT6331_VCORE2_CON20 0x37C |
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| 288 | #define MT6331_VCORE2_CON21 0x37E |
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| 289 | #define MT6331_VIO18_CON0 0x380 |
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| 290 | #define MT6331_VIO18_CON1 0x382 |
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| 291 | #define MT6331_VIO18_CON2 0x384 |
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| 292 | #define MT6331_VIO18_CON3 0x386 |
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| 293 | #define MT6331_VIO18_CON4 0x388 |
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| 294 | #define MT6331_VIO18_CON5 0x38A |
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| 295 | #define MT6331_VIO18_CON6 0x38C |
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| 296 | #define MT6331_VIO18_CON7 0x38E |
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| 297 | #define MT6331_VIO18_CON8 0x390 |
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| 298 | #define MT6331_VIO18_CON9 0x392 |
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| 299 | #define MT6331_VIO18_CON10 0x394 |
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| 300 | #define MT6331_VIO18_CON11 0x396 |
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| 301 | #define MT6331_VIO18_CON12 0x398 |
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| 302 | #define MT6331_VIO18_CON13 0x39A |
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| 303 | #define MT6331_VIO18_CON14 0x39C |
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| 304 | #define MT6331_VIO18_CON15 0x39E |
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| 305 | #define MT6331_VIO18_CON16 0x3A0 |
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| 306 | #define MT6331_VIO18_CON17 0x3A2 |
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| 307 | #define MT6331_VIO18_CON18 0x3A4 |
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| 308 | #define MT6331_VIO18_CON19 0x3A6 |
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| 309 | #define MT6331_VIO18_CON20 0x3A8 |
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| 310 | #define MT6331_BUCK_K_CON0 0x3AA |
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| 311 | #define MT6331_BUCK_K_CON1 0x3AC |
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| 312 | #define MT6331_BUCK_K_CON2 0x3AE |
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| 313 | #define MT6331_BUCK_K_CON3 0x3B0 |
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| 314 | #define MT6331_ZCD_CON0 0x400 |
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| 315 | #define MT6331_ZCD_CON1 0x402 |
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| 316 | #define MT6331_ZCD_CON2 0x404 |
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| 317 | #define MT6331_ZCD_CON3 0x406 |
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| 318 | #define MT6331_ZCD_CON4 0x408 |
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| 319 | #define MT6331_ZCD_CON5 0x40A |
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| 320 | #define MT6331_ISINK0_CON0 0x40C |
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| 321 | #define MT6331_ISINK0_CON1 0x40E |
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| 322 | #define MT6331_ISINK0_CON2 0x410 |
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| 323 | #define MT6331_ISINK0_CON3 0x412 |
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| 324 | #define MT6331_ISINK0_CON4 0x414 |
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| 325 | #define MT6331_ISINK1_CON0 0x416 |
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| 326 | #define MT6331_ISINK1_CON1 0x418 |
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| 327 | #define MT6331_ISINK1_CON2 0x41A |
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| 328 | #define MT6331_ISINK1_CON3 0x41C |
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| 329 | #define MT6331_ISINK1_CON4 0x41E |
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| 330 | #define MT6331_ISINK2_CON0 0x420 |
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| 331 | #define MT6331_ISINK2_CON1 0x422 |
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| 332 | #define MT6331_ISINK2_CON2 0x424 |
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| 333 | #define MT6331_ISINK2_CON3 0x426 |
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| 334 | #define MT6331_ISINK2_CON4 0x428 |
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| 335 | #define MT6331_ISINK3_CON0 0x42A |
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| 336 | #define MT6331_ISINK3_CON1 0x42C |
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| 337 | #define MT6331_ISINK3_CON2 0x42E |
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| 338 | #define MT6331_ISINK3_CON3 0x430 |
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| 339 | #define MT6331_ISINK3_CON4 0x432 |
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| 340 | #define MT6331_ISINK_ANA0 0x434 |
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| 341 | #define MT6331_ISINK_ANA1 0x436 |
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| 342 | #define MT6331_ISINK_PHASE_DLY 0x438 |
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| 343 | #define MT6331_ISINK_EN_CTRL 0x43A |
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| 344 | #define MT6331_ANALDO_CON0 0x500 |
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| 345 | #define MT6331_ANALDO_CON1 0x502 |
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| 346 | #define MT6331_ANALDO_CON2 0x504 |
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| 347 | #define MT6331_ANALDO_CON3 0x506 |
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| 348 | #define MT6331_ANALDO_CON4 0x508 |
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| 349 | #define MT6331_ANALDO_CON5 0x50A |
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| 350 | #define MT6331_ANALDO_CON6 0x50C |
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| 351 | #define MT6331_ANALDO_CON7 0x50E |
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| 352 | #define MT6331_ANALDO_CON8 0x510 |
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| 353 | #define MT6331_ANALDO_CON9 0x512 |
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| 354 | #define MT6331_ANALDO_CON10 0x514 |
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| 355 | #define MT6331_ANALDO_CON11 0x516 |
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| 356 | #define MT6331_ANALDO_CON12 0x518 |
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| 357 | #define MT6331_ANALDO_CON13 0x51A |
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| 358 | #define MT6331_SYSLDO_CON0 0x51C |
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| 359 | #define MT6331_SYSLDO_CON1 0x51E |
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| 360 | #define MT6331_SYSLDO_CON2 0x520 |
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| 361 | #define MT6331_SYSLDO_CON3 0x522 |
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| 362 | #define MT6331_SYSLDO_CON4 0x524 |
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| 363 | #define MT6331_SYSLDO_CON5 0x526 |
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| 364 | #define MT6331_SYSLDO_CON6 0x528 |
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| 365 | #define MT6331_SYSLDO_CON7 0x52A |
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| 366 | #define MT6331_SYSLDO_CON8 0x52C |
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| 367 | #define MT6331_SYSLDO_CON9 0x52E |
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| 368 | #define MT6331_SYSLDO_CON10 0x530 |
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| 369 | #define MT6331_SYSLDO_CON11 0x532 |
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| 370 | #define MT6331_SYSLDO_CON12 0x534 |
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| 371 | #define MT6331_SYSLDO_CON13 0x536 |
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| 372 | #define MT6331_SYSLDO_CON14 0x538 |
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| 373 | #define MT6331_SYSLDO_CON15 0x53A |
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| 374 | #define MT6331_SYSLDO_CON16 0x53C |
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| 375 | #define MT6331_SYSLDO_CON17 0x53E |
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| 376 | #define MT6331_SYSLDO_CON18 0x540 |
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| 377 | #define MT6331_SYSLDO_CON19 0x542 |
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| 378 | #define MT6331_SYSLDO_CON20 0x544 |
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| 379 | #define MT6331_SYSLDO_CON21 0x546 |
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| 380 | #define MT6331_DIGLDO_CON0 0x548 |
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| 381 | #define MT6331_DIGLDO_CON1 0x54A |
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| 382 | #define MT6331_DIGLDO_CON2 0x54C |
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| 383 | #define MT6331_DIGLDO_CON3 0x54E |
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| 384 | #define MT6331_DIGLDO_CON4 0x550 |
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| 385 | #define MT6331_DIGLDO_CON5 0x552 |
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| 386 | #define MT6331_DIGLDO_CON6 0x554 |
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| 387 | #define MT6331_DIGLDO_CON7 0x556 |
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| 388 | #define MT6331_DIGLDO_CON8 0x558 |
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| 389 | #define MT6331_DIGLDO_CON9 0x55A |
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| 390 | #define MT6331_DIGLDO_CON10 0x55C |
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| 391 | #define MT6331_DIGLDO_CON11 0x55E |
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| 392 | #define MT6331_DIGLDO_CON12 0x560 |
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| 393 | #define MT6331_DIGLDO_CON13 0x562 |
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| 394 | #define MT6331_DIGLDO_CON14 0x564 |
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| 395 | #define MT6331_DIGLDO_CON15 0x566 |
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| 396 | #define MT6331_DIGLDO_CON16 0x568 |
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| 397 | #define MT6331_DIGLDO_CON17 0x56A |
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| 398 | #define MT6331_DIGLDO_CON18 0x56C |
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| 399 | #define MT6331_DIGLDO_CON19 0x56E |
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| 400 | #define MT6331_DIGLDO_CON20 0x570 |
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| 401 | #define MT6331_DIGLDO_CON21 0x572 |
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| 402 | #define MT6331_DIGLDO_CON22 0x574 |
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| 403 | #define MT6331_DIGLDO_CON23 0x576 |
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| 404 | #define MT6331_DIGLDO_CON24 0x578 |
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| 405 | #define MT6331_DIGLDO_CON25 0x57A |
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| 406 | #define MT6331_DIGLDO_CON26 0x57C |
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| 407 | #define MT6331_DIGLDO_CON27 0x57E |
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| 408 | #define MT6331_DIGLDO_CON28 0x580 |
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| 409 | #define MT6331_OTP_CON0 0x600 |
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| 410 | #define MT6331_OTP_CON1 0x602 |
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| 411 | #define MT6331_OTP_CON2 0x604 |
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| 412 | #define MT6331_OTP_CON3 0x606 |
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| 413 | #define MT6331_OTP_CON4 0x608 |
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| 414 | #define MT6331_OTP_CON5 0x60A |
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| 415 | #define MT6331_OTP_CON6 0x60C |
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| 416 | #define MT6331_OTP_CON7 0x60E |
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| 417 | #define MT6331_OTP_CON8 0x610 |
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| 418 | #define MT6331_OTP_CON9 0x612 |
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| 419 | #define MT6331_OTP_CON10 0x614 |
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| 420 | #define MT6331_OTP_CON11 0x616 |
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| 421 | #define MT6331_OTP_CON12 0x618 |
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| 422 | #define MT6331_OTP_CON13 0x61A |
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| 423 | #define MT6331_OTP_CON14 0x61C |
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| 424 | #define MT6331_OTP_DOUT_0_15 0x61E |
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| 425 | #define MT6331_OTP_DOUT_16_31 0x620 |
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| 426 | #define MT6331_OTP_DOUT_32_47 0x622 |
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| 427 | #define MT6331_OTP_DOUT_48_63 0x624 |
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| 428 | #define MT6331_OTP_DOUT_64_79 0x626 |
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| 429 | #define MT6331_OTP_DOUT_80_95 0x628 |
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| 430 | #define MT6331_OTP_DOUT_96_111 0x62A |
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| 431 | #define MT6331_OTP_DOUT_112_127 0x62C |
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| 432 | #define MT6331_OTP_DOUT_128_143 0x62E |
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| 433 | #define MT6331_OTP_DOUT_144_159 0x630 |
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| 434 | #define MT6331_OTP_DOUT_160_175 0x632 |
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| 435 | #define MT6331_OTP_DOUT_176_191 0x634 |
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| 436 | #define MT6331_OTP_DOUT_192_207 0x636 |
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| 437 | #define MT6331_OTP_DOUT_208_223 0x638 |
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| 438 | #define MT6331_OTP_DOUT_224_239 0x63A |
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| 439 | #define MT6331_OTP_DOUT_240_255 0x63C |
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| 440 | #define MT6331_OTP_VAL_0_15 0x63E |
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| 441 | #define MT6331_OTP_VAL_16_31 0x640 |
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| 442 | #define MT6331_OTP_VAL_32_47 0x642 |
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| 443 | #define MT6331_OTP_VAL_48_63 0x644 |
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| 444 | #define MT6331_OTP_VAL_64_79 0x646 |
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| 445 | #define MT6331_OTP_VAL_80_95 0x648 |
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| 446 | #define MT6331_OTP_VAL_96_111 0x64A |
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| 447 | #define MT6331_OTP_VAL_112_127 0x64C |
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| 448 | #define MT6331_OTP_VAL_128_143 0x64E |
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| 449 | #define MT6331_OTP_VAL_144_159 0x650 |
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| 450 | #define MT6331_OTP_VAL_160_175 0x652 |
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| 451 | #define MT6331_OTP_VAL_176_191 0x654 |
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| 452 | #define MT6331_OTP_VAL_192_207 0x656 |
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| 453 | #define MT6331_OTP_VAL_208_223 0x658 |
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| 454 | #define MT6331_OTP_VAL_224_239 0x65A |
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| 455 | #define MT6331_OTP_VAL_240_255 0x65C |
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| 456 | #define MT6331_RTC_MIX_CON0 0x65E |
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| 457 | #define MT6331_RTC_MIX_CON1 0x660 |
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| 458 | #define MT6331_AUDDAC_CFG0 0x662 |
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| 459 | #define MT6331_AUDBUF_CFG0 0x664 |
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| 460 | #define MT6331_AUDBUF_CFG1 0x666 |
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| 461 | #define MT6331_AUDBUF_CFG2 0x668 |
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| 462 | #define MT6331_AUDBUF_CFG3 0x66A |
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| 463 | #define MT6331_AUDBUF_CFG4 0x66C |
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| 464 | #define MT6331_AUDBUF_CFG5 0x66E |
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| 465 | #define MT6331_AUDBUF_CFG6 0x670 |
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| 466 | #define MT6331_AUDBUF_CFG7 0x672 |
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| 467 | #define MT6331_AUDBUF_CFG8 0x674 |
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| 468 | #define MT6331_IBIASDIST_CFG0 0x676 |
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| 469 | #define MT6331_AUDCLKGEN_CFG0 0x678 |
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| 470 | #define MT6331_AUDLDO_CFG0 0x67A |
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| 471 | #define MT6331_AUDDCDC_CFG0 0x67C |
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| 472 | #define MT6331_AUDDCDC_CFG1 0x67E |
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| 473 | #define MT6331_AUDNVREGGLB_CFG0 0x680 |
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| 474 | #define MT6331_AUD_NCP0 0x682 |
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| 475 | #define MT6331_AUD_ZCD_CFG0 0x684 |
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| 476 | #define MT6331_AUDPREAMP_CFG0 0x686 |
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| 477 | #define MT6331_AUDPREAMP_CFG1 0x688 |
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| 478 | #define MT6331_AUDPREAMP_CFG2 0x68A |
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| 479 | #define MT6331_AUDADC_CFG0 0x68C |
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| 480 | #define MT6331_AUDADC_CFG1 0x68E |
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| 481 | #define MT6331_AUDADC_CFG2 0x690 |
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| 482 | #define MT6331_AUDADC_CFG3 0x692 |
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| 483 | #define MT6331_AUDADC_CFG4 0x694 |
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| 484 | #define MT6331_AUDADC_CFG5 0x696 |
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| 485 | #define MT6331_AUDDIGMI_CFG0 0x698 |
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| 486 | #define MT6331_AUDDIGMI_CFG1 0x69A |
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| 487 | #define MT6331_AUDMICBIAS_CFG0 0x69C |
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| 488 | #define MT6331_AUDMICBIAS_CFG1 0x69E |
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| 489 | #define MT6331_AUDENCSPARE_CFG0 0x6A0 |
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| 490 | #define MT6331_AUDPREAMPGAIN_CFG0 0x6A2 |
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| 491 | #define MT6331_AUDMADPLL_CFG0 0x6A4 |
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| 492 | #define MT6331_AUDMADPLL_CFG1 0x6A6 |
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| 493 | #define MT6331_AUDMADPLL_CFG2 0x6A8 |
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| 494 | #define MT6331_AUDLDO_NVREG_CFG0 0x6AA |
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| 495 | #define MT6331_AUDLDO_NVREG_CFG1 0x6AC |
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| 496 | #define MT6331_AUDLDO_NVREG_CFG2 0x6AE |
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| 497 | #define MT6331_AUXADC_ADC0 0x700 |
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| 498 | #define MT6331_AUXADC_ADC1 0x702 |
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| 499 | #define MT6331_AUXADC_ADC2 0x704 |
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| 500 | #define MT6331_AUXADC_ADC3 0x706 |
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| 501 | #define MT6331_AUXADC_ADC4 0x708 |
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| 502 | #define MT6331_AUXADC_ADC5 0x70A |
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| 503 | #define MT6331_AUXADC_ADC6 0x70C |
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| 504 | #define MT6331_AUXADC_ADC7 0x70E |
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| 505 | #define MT6331_AUXADC_ADC8 0x710 |
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| 506 | #define MT6331_AUXADC_ADC9 0x712 |
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| 507 | #define MT6331_AUXADC_ADC10 0x714 |
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| 508 | #define MT6331_AUXADC_ADC11 0x716 |
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| 509 | #define MT6331_AUXADC_ADC12 0x718 |
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| 510 | #define MT6331_AUXADC_ADC13 0x71A |
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| 511 | #define MT6331_AUXADC_ADC14 0x71C |
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| 512 | #define MT6331_AUXADC_ADC15 0x71E |
|---|
| 513 | #define MT6331_AUXADC_ADC16 0x720 |
|---|
| 514 | #define MT6331_AUXADC_ADC17 0x722 |
|---|
| 515 | #define MT6331_AUXADC_ADC18 0x724 |
|---|
| 516 | #define MT6331_AUXADC_ADC19 0x726 |
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| 517 | #define MT6331_AUXADC_STA0 0x728 |
|---|
| 518 | #define MT6331_AUXADC_STA1 0x72A |
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| 519 | #define MT6331_AUXADC_RQST0 0x72C |
|---|
| 520 | #define MT6331_AUXADC_RQST0_SET 0x72E |
|---|
| 521 | #define MT6331_AUXADC_RQST0_CLR 0x730 |
|---|
| 522 | #define MT6331_AUXADC_RQST1 0x732 |
|---|
| 523 | #define MT6331_AUXADC_RQST1_SET 0x734 |
|---|
| 524 | #define MT6331_AUXADC_RQST1_CLR 0x736 |
|---|
| 525 | #define MT6331_AUXADC_CON0 0x738 |
|---|
| 526 | #define MT6331_AUXADC_CON1 0x73A |
|---|
| 527 | #define MT6331_AUXADC_CON2 0x73C |
|---|
| 528 | #define MT6331_AUXADC_CON3 0x73E |
|---|
| 529 | #define MT6331_AUXADC_CON4 0x740 |
|---|
| 530 | #define MT6331_AUXADC_CON5 0x742 |
|---|
| 531 | #define MT6331_AUXADC_CON6 0x744 |
|---|
| 532 | #define MT6331_AUXADC_CON7 0x746 |
|---|
| 533 | #define MT6331_AUXADC_CON8 0x748 |
|---|
| 534 | #define MT6331_AUXADC_CON9 0x74A |
|---|
| 535 | #define MT6331_AUXADC_CON10 0x74C |
|---|
| 536 | #define MT6331_AUXADC_CON11 0x74E |
|---|
| 537 | #define MT6331_AUXADC_CON12 0x750 |
|---|
| 538 | #define MT6331_AUXADC_CON13 0x752 |
|---|
| 539 | #define MT6331_AUXADC_CON14 0x754 |
|---|
| 540 | #define MT6331_AUXADC_CON15 0x756 |
|---|
| 541 | #define MT6331_AUXADC_CON16 0x758 |
|---|
| 542 | #define MT6331_AUXADC_CON17 0x75A |
|---|
| 543 | #define MT6331_AUXADC_CON18 0x75C |
|---|
| 544 | #define MT6331_AUXADC_CON19 0x75E |
|---|
| 545 | #define MT6331_AUXADC_CON20 0x760 |
|---|
| 546 | #define MT6331_AUXADC_CON21 0x762 |
|---|
| 547 | #define MT6331_AUXADC_CON22 0x764 |
|---|
| 548 | #define MT6331_AUXADC_CON23 0x766 |
|---|
| 549 | #define MT6331_AUXADC_CON24 0x768 |
|---|
| 550 | #define MT6331_AUXADC_CON25 0x76A |
|---|
| 551 | #define MT6331_AUXADC_CON26 0x76C |
|---|
| 552 | #define MT6331_AUXADC_CON27 0x76E |
|---|
| 553 | #define MT6331_AUXADC_CON28 0x770 |
|---|
| 554 | #define MT6331_AUXADC_CON29 0x772 |
|---|
| 555 | #define MT6331_AUXADC_CON30 0x774 |
|---|
| 556 | #define MT6331_AUXADC_CON31 0x776 |
|---|
| 557 | #define MT6331_AUXADC_CON32 0x778 |
|---|
| 558 | #define MT6331_ACCDET_CON0 0x77A |
|---|
| 559 | #define MT6331_ACCDET_CON1 0x77C |
|---|
| 560 | #define MT6331_ACCDET_CON2 0x77E |
|---|
| 561 | #define MT6331_ACCDET_CON3 0x780 |
|---|
| 562 | #define MT6331_ACCDET_CON4 0x782 |
|---|
| 563 | #define MT6331_ACCDET_CON5 0x784 |
|---|
| 564 | #define MT6331_ACCDET_CON6 0x786 |
|---|
| 565 | #define MT6331_ACCDET_CON7 0x788 |
|---|
| 566 | #define MT6331_ACCDET_CON8 0x78A |
|---|
| 567 | #define MT6331_ACCDET_CON9 0x78C |
|---|
| 568 | #define MT6331_ACCDET_CON10 0x78E |
|---|
| 569 | #define MT6331_ACCDET_CON11 0x790 |
|---|
| 570 | #define MT6331_ACCDET_CON12 0x792 |
|---|
| 571 | #define MT6331_ACCDET_CON13 0x794 |
|---|
| 572 | #define MT6331_ACCDET_CON14 0x796 |
|---|
| 573 | #define MT6331_ACCDET_CON15 0x798 |
|---|
| 574 | #define MT6331_ACCDET_CON16 0x79A |
|---|
| 575 | #define MT6331_ACCDET_CON17 0x79C |
|---|
| 576 | #define MT6331_ACCDET_CON18 0x79E |
|---|
| 577 | #define MT6331_ACCDET_CON19 0x7A0 |
|---|
| 578 | #define MT6331_ACCDET_CON20 0x7A2 |
|---|
| 579 | #define MT6331_ACCDET_CON21 0x7A4 |
|---|
| 580 | #define MT6331_ACCDET_CON22 0x7A6 |
|---|
| 581 | #define MT6331_ACCDET_CON23 0x7A8 |
|---|
| 582 | #define MT6331_ACCDET_CON24 0x7AA |
|---|
| 583 | |
|---|
| 584 | #endif /* __MFD_MT6331_REGISTERS_H__ */ |
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| 585 | |
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