| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #ifndef __LINUX_MFD_MAX7360_H |
| 4 | #define __LINUX_MFD_MAX7360_H |
| 5 | |
| 6 | #include <linux/bits.h> |
| 7 | |
| 8 | #define MAX7360_MAX_KEY_ROWS 8 |
| 9 | #define MAX7360_MAX_KEY_COLS 8 |
| 10 | #define MAX7360_MAX_KEY_NUM (MAX7360_MAX_KEY_ROWS * MAX7360_MAX_KEY_COLS) |
| 11 | #define MAX7360_ROW_SHIFT 3 |
| 12 | |
| 13 | #define MAX7360_MAX_GPIO 8 |
| 14 | #define MAX7360_MAX_GPO 6 |
| 15 | #define MAX7360_PORT_PWM_COUNT 8 |
| 16 | #define MAX7360_PORT_RTR_PIN (MAX7360_PORT_PWM_COUNT - 1) |
| 17 | |
| 18 | /* |
| 19 | * MAX7360 registers |
| 20 | */ |
| 21 | #define MAX7360_REG_KEYFIFO 0x00 |
| 22 | #define MAX7360_REG_CONFIG 0x01 |
| 23 | #define MAX7360_REG_DEBOUNCE 0x02 |
| 24 | #define MAX7360_REG_INTERRUPT 0x03 |
| 25 | #define MAX7360_REG_PORTS 0x04 |
| 26 | #define MAX7360_REG_KEYREP 0x05 |
| 27 | #define MAX7360_REG_SLEEP 0x06 |
| 28 | |
| 29 | /* |
| 30 | * MAX7360 GPIO registers |
| 31 | * |
| 32 | * All these registers are reset together when writing bit 3 of |
| 33 | * MAX7360_REG_GPIOCFG. |
| 34 | */ |
| 35 | #define MAX7360_REG_GPIOCFG 0x40 |
| 36 | #define MAX7360_REG_GPIOCTRL 0x41 |
| 37 | #define MAX7360_REG_GPIODEB 0x42 |
| 38 | #define MAX7360_REG_GPIOCURR 0x43 |
| 39 | #define MAX7360_REG_GPIOOUTM 0x44 |
| 40 | #define MAX7360_REG_PWMCOM 0x45 |
| 41 | #define MAX7360_REG_RTRCFG 0x46 |
| 42 | #define MAX7360_REG_I2C_TIMEOUT 0x48 |
| 43 | #define MAX7360_REG_GPIOIN 0x49 |
| 44 | #define MAX7360_REG_RTR_CNT 0x4A |
| 45 | #define MAX7360_REG_PWMBASE 0x50 |
| 46 | #define MAX7360_REG_PWMCFGBASE 0x58 |
| 47 | |
| 48 | #define MAX7360_REG_GPIO_LAST 0x5F |
| 49 | |
| 50 | #define MAX7360_REG_PWM(x) (MAX7360_REG_PWMBASE + (x)) |
| 51 | #define MAX7360_REG_PWMCFG(x) (MAX7360_REG_PWMCFGBASE + (x)) |
| 52 | |
| 53 | /* |
| 54 | * Configuration register bits |
| 55 | */ |
| 56 | #define MAX7360_FIFO_EMPTY 0x3F |
| 57 | #define MAX7360_FIFO_OVERFLOW 0x7F |
| 58 | #define MAX7360_FIFO_RELEASE BIT(6) |
| 59 | #define MAX7360_FIFO_COL GENMASK(5, 3) |
| 60 | #define MAX7360_FIFO_ROW GENMASK(2, 0) |
| 61 | |
| 62 | #define MAX7360_CFG_SLEEP BIT(7) |
| 63 | #define MAX7360_CFG_INTERRUPT BIT(5) |
| 64 | #define MAX7360_CFG_KEY_RELEASE BIT(3) |
| 65 | #define MAX7360_CFG_WAKEUP BIT(1) |
| 66 | #define MAX7360_CFG_TIMEOUT BIT(0) |
| 67 | |
| 68 | #define MAX7360_DEBOUNCE GENMASK(4, 0) |
| 69 | #define MAX7360_DEBOUNCE_MIN 9 |
| 70 | #define MAX7360_DEBOUNCE_MAX 40 |
| 71 | #define MAX7360_PORTS GENMASK(8, 5) |
| 72 | |
| 73 | #define MAX7360_INTERRUPT_TIME_MASK GENMASK(4, 0) |
| 74 | #define MAX7360_INTERRUPT_FIFO_MASK GENMASK(7, 5) |
| 75 | |
| 76 | #define MAX7360_PORT_CFG_INTERRUPT_MASK BIT(7) |
| 77 | #define MAX7360_PORT_CFG_INTERRUPT_EDGES BIT(6) |
| 78 | #define MAX7360_PORT_CFG_COMMON_PWM BIT(5) |
| 79 | |
| 80 | /* |
| 81 | * Autosleep register values |
| 82 | */ |
| 83 | #define MAX7360_AUTOSLEEP_8192MS 0x01 |
| 84 | #define MAX7360_AUTOSLEEP_4096MS 0x02 |
| 85 | #define MAX7360_AUTOSLEEP_2048MS 0x03 |
| 86 | #define MAX7360_AUTOSLEEP_1024MS 0x04 |
| 87 | #define MAX7360_AUTOSLEEP_512MS 0x05 |
| 88 | #define MAX7360_AUTOSLEEP_256MS 0x06 |
| 89 | |
| 90 | #define MAX7360_GPIO_CFG_RTR_EN BIT(7) |
| 91 | #define MAX7360_GPIO_CFG_GPIO_EN BIT(4) |
| 92 | #define MAX7360_GPIO_CFG_GPIO_RST BIT(3) |
| 93 | |
| 94 | #define MAX7360_ROT_DEBOUNCE GENMASK(3, 0) |
| 95 | #define MAX7360_ROT_DEBOUNCE_MIN 0 |
| 96 | #define MAX7360_ROT_DEBOUNCE_MAX 15 |
| 97 | #define MAX7360_ROT_INTCNT GENMASK(6, 4) |
| 98 | #define MAX7360_ROT_INTCNT_DLY BIT(7) |
| 99 | |
| 100 | #define MAX7360_INT_INTI 0 |
| 101 | #define MAX7360_INT_INTK 1 |
| 102 | |
| 103 | #define MAX7360_INT_GPIO 0 |
| 104 | #define MAX7360_INT_KEYPAD 1 |
| 105 | #define MAX7360_INT_ROTARY 2 |
| 106 | |
| 107 | #define MAX7360_NR_INTERNAL_IRQS 3 |
| 108 | |
| 109 | #endif |
| 110 | |