| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* |
| 3 | * Functions and registers to access AXP20X power management chip. |
| 4 | * |
| 5 | * Copyright (C) 2013, Carlo Caione <carlo@caione.org> |
| 6 | */ |
| 7 | |
| 8 | #ifndef __LINUX_MFD_AXP20X_H |
| 9 | #define __LINUX_MFD_AXP20X_H |
| 10 | |
| 11 | #include <linux/regmap.h> |
| 12 | |
| 13 | enum axp20x_variants { |
| 14 | AXP152_ID = 0, |
| 15 | AXP192_ID, |
| 16 | AXP202_ID, |
| 17 | AXP209_ID, |
| 18 | AXP221_ID, |
| 19 | AXP223_ID, |
| 20 | AXP288_ID, |
| 21 | AXP313A_ID, |
| 22 | AXP323_ID, |
| 23 | AXP717_ID, |
| 24 | AXP803_ID, |
| 25 | AXP806_ID, |
| 26 | AXP809_ID, |
| 27 | AXP813_ID, |
| 28 | AXP15060_ID, |
| 29 | NR_AXP20X_VARIANTS, |
| 30 | }; |
| 31 | |
| 32 | #define AXP192_DATACACHE(m) (0x06 + (m)) |
| 33 | #define AXP20X_DATACACHE(m) (0x04 + (m)) |
| 34 | |
| 35 | /* Power supply */ |
| 36 | #define AXP152_PWR_OP_MODE 0x01 |
| 37 | #define AXP152_LDO3456_DC1234_CTRL 0x12 |
| 38 | #define AXP152_ALDO_OP_MODE 0x13 |
| 39 | #define AXP152_LDO0_CTRL 0x15 |
| 40 | #define AXP152_DCDC2_V_OUT 0x23 |
| 41 | #define AXP152_DCDC2_V_RAMP 0x25 |
| 42 | #define AXP152_DCDC1_V_OUT 0x26 |
| 43 | #define AXP152_DCDC3_V_OUT 0x27 |
| 44 | #define AXP152_ALDO12_V_OUT 0x28 |
| 45 | #define AXP152_DLDO1_V_OUT 0x29 |
| 46 | #define AXP152_DLDO2_V_OUT 0x2a |
| 47 | #define AXP152_DCDC4_V_OUT 0x2b |
| 48 | #define AXP152_V_OFF 0x31 |
| 49 | #define AXP152_OFF_CTRL 0x32 |
| 50 | #define AXP152_PEK_KEY 0x36 |
| 51 | #define AXP152_DCDC_FREQ 0x37 |
| 52 | #define AXP152_DCDC_MODE 0x80 |
| 53 | |
| 54 | #define AXP192_USB_OTG_STATUS 0x04 |
| 55 | #define AXP192_PWR_OUT_CTRL 0x12 |
| 56 | #define AXP192_DCDC2_V_OUT 0x23 |
| 57 | #define AXP192_DCDC1_V_OUT 0x26 |
| 58 | #define AXP192_DCDC3_V_OUT 0x27 |
| 59 | #define AXP192_LDO2_3_V_OUT 0x28 |
| 60 | |
| 61 | #define AXP20X_PWR_INPUT_STATUS 0x00 |
| 62 | #define AXP20X_PWR_OP_MODE 0x01 |
| 63 | #define AXP20X_USB_OTG_STATUS 0x02 |
| 64 | #define AXP20X_PWR_OUT_CTRL 0x12 |
| 65 | #define AXP20X_DCDC2_V_OUT 0x23 |
| 66 | #define AXP20X_DCDC2_LDO3_V_RAMP 0x25 |
| 67 | #define AXP20X_DCDC3_V_OUT 0x27 |
| 68 | #define AXP20X_LDO24_V_OUT 0x28 |
| 69 | #define AXP20X_LDO3_V_OUT 0x29 |
| 70 | #define AXP20X_VBUS_IPSOUT_MGMT 0x30 |
| 71 | #define AXP20X_V_OFF 0x31 |
| 72 | #define AXP20X_OFF_CTRL 0x32 |
| 73 | #define AXP20X_CHRG_CTRL1 0x33 |
| 74 | #define AXP20X_CHRG_CTRL2 0x34 |
| 75 | #define AXP20X_CHRG_BAK_CTRL 0x35 |
| 76 | #define AXP20X_PEK_KEY 0x36 |
| 77 | #define AXP20X_DCDC_FREQ 0x37 |
| 78 | #define AXP20X_V_LTF_CHRG 0x38 |
| 79 | #define AXP20X_V_HTF_CHRG 0x39 |
| 80 | #define AXP20X_APS_WARN_L1 0x3a |
| 81 | #define AXP20X_APS_WARN_L2 0x3b |
| 82 | #define AXP20X_V_LTF_DISCHRG 0x3c |
| 83 | #define AXP20X_V_HTF_DISCHRG 0x3d |
| 84 | |
| 85 | #define AXP22X_PWR_OUT_CTRL1 0x10 |
| 86 | #define AXP22X_PWR_OUT_CTRL2 0x12 |
| 87 | #define AXP22X_PWR_OUT_CTRL3 0x13 |
| 88 | #define AXP22X_DLDO1_V_OUT 0x15 |
| 89 | #define AXP22X_DLDO2_V_OUT 0x16 |
| 90 | #define AXP22X_DLDO3_V_OUT 0x17 |
| 91 | #define AXP22X_DLDO4_V_OUT 0x18 |
| 92 | #define AXP22X_ELDO1_V_OUT 0x19 |
| 93 | #define AXP22X_ELDO2_V_OUT 0x1a |
| 94 | #define AXP22X_ELDO3_V_OUT 0x1b |
| 95 | #define AXP22X_DC5LDO_V_OUT 0x1c |
| 96 | #define AXP22X_DCDC1_V_OUT 0x21 |
| 97 | #define AXP22X_DCDC2_V_OUT 0x22 |
| 98 | #define AXP22X_DCDC3_V_OUT 0x23 |
| 99 | #define AXP22X_DCDC4_V_OUT 0x24 |
| 100 | #define AXP22X_DCDC5_V_OUT 0x25 |
| 101 | #define AXP22X_DCDC23_V_RAMP_CTRL 0x27 |
| 102 | #define AXP22X_ALDO1_V_OUT 0x28 |
| 103 | #define AXP22X_ALDO2_V_OUT 0x29 |
| 104 | #define AXP22X_ALDO3_V_OUT 0x2a |
| 105 | #define AXP22X_CHRG_CTRL3 0x35 |
| 106 | |
| 107 | #define AXP313A_ON_INDICATE 0x00 |
| 108 | #define AXP313A_OUTPUT_CONTROL 0x10 |
| 109 | #define AXP313A_DCDC1_CONTROL 0x13 |
| 110 | #define AXP313A_DCDC2_CONTROL 0x14 |
| 111 | #define AXP313A_DCDC3_CONTROL 0x15 |
| 112 | #define AXP313A_ALDO1_CONTROL 0x16 |
| 113 | #define AXP313A_DLDO1_CONTROL 0x17 |
| 114 | #define AXP313A_SHUTDOWN_CTRL 0x1a |
| 115 | #define AXP313A_IRQ_EN 0x20 |
| 116 | #define AXP313A_IRQ_STATE 0x21 |
| 117 | #define AXP323_DCDC_MODE_CTRL2 0x22 |
| 118 | |
| 119 | #define AXP717_ON_INDICATE 0x00 |
| 120 | #define AXP717_PMU_STATUS_2 0x01 |
| 121 | #define AXP717_BC_DETECT 0x05 |
| 122 | #define AXP717_PMU_FAULT 0x08 |
| 123 | #define AXP717_MODULE_EN_CONTROL_1 0x0b |
| 124 | #define AXP717_MIN_SYS_V_CONTROL 0x15 |
| 125 | #define AXP717_INPUT_VOL_LIMIT_CTRL 0x16 |
| 126 | #define AXP717_INPUT_CUR_LIMIT_CTRL 0x17 |
| 127 | #define AXP717_MODULE_EN_CONTROL_2 0x19 |
| 128 | #define AXP717_BOOST_CONTROL 0x1e |
| 129 | #define AXP717_VSYS_V_POWEROFF 0x24 |
| 130 | #define AXP717_IRQ0_EN 0x40 |
| 131 | #define AXP717_IRQ1_EN 0x41 |
| 132 | #define AXP717_IRQ2_EN 0x42 |
| 133 | #define AXP717_IRQ3_EN 0x43 |
| 134 | #define AXP717_IRQ4_EN 0x44 |
| 135 | #define AXP717_IRQ0_STATE 0x48 |
| 136 | #define AXP717_IRQ1_STATE 0x49 |
| 137 | #define AXP717_IRQ2_STATE 0x4a |
| 138 | #define AXP717_IRQ3_STATE 0x4b |
| 139 | #define AXP717_IRQ4_STATE 0x4c |
| 140 | #define AXP717_TS_PIN_CFG 0x50 |
| 141 | #define AXP717_ICC_CHG_SET 0x62 |
| 142 | #define AXP717_ITERM_CHG_SET 0x63 |
| 143 | #define AXP717_CV_CHG_SET 0x64 |
| 144 | #define AXP717_DCDC_OUTPUT_CONTROL 0x80 |
| 145 | #define AXP717_DCDC1_CONTROL 0x83 |
| 146 | #define AXP717_DCDC2_CONTROL 0x84 |
| 147 | #define AXP717_DCDC3_CONTROL 0x85 |
| 148 | #define AXP717_DCDC4_CONTROL 0x86 |
| 149 | #define AXP717_LDO0_OUTPUT_CONTROL 0x90 |
| 150 | #define AXP717_LDO1_OUTPUT_CONTROL 0x91 |
| 151 | #define AXP717_ALDO1_CONTROL 0x93 |
| 152 | #define AXP717_ALDO2_CONTROL 0x94 |
| 153 | #define AXP717_ALDO3_CONTROL 0x95 |
| 154 | #define AXP717_ALDO4_CONTROL 0x96 |
| 155 | #define AXP717_BLDO1_CONTROL 0x97 |
| 156 | #define AXP717_BLDO2_CONTROL 0x98 |
| 157 | #define AXP717_BLDO3_CONTROL 0x99 |
| 158 | #define AXP717_BLDO4_CONTROL 0x9a |
| 159 | #define AXP717_CLDO1_CONTROL 0x9b |
| 160 | #define AXP717_CLDO2_CONTROL 0x9c |
| 161 | #define AXP717_CLDO3_CONTROL 0x9d |
| 162 | #define AXP717_CLDO4_CONTROL 0x9e |
| 163 | #define AXP717_CPUSLDO_CONTROL 0x9f |
| 164 | #define AXP717_BATT_PERCENT_DATA 0xa4 |
| 165 | #define AXP717_ADC_CH_EN_CONTROL 0xc0 |
| 166 | #define AXP717_BATT_V_H 0xc4 |
| 167 | #define AXP717_BATT_V_L 0xc5 |
| 168 | #define AXP717_VBUS_V_H 0xc6 |
| 169 | #define AXP717_VBUS_V_L 0xc7 |
| 170 | #define AXP717_VSYS_V_H 0xc8 |
| 171 | #define AXP717_VSYS_V_L 0xc9 |
| 172 | #define AXP717_BATT_CHRG_I_H 0xca |
| 173 | #define AXP717_BATT_CHRG_I_L 0xcb |
| 174 | #define AXP717_ADC_DATA_SEL 0xcd |
| 175 | #define AXP717_ADC_DATA_H 0xce |
| 176 | #define AXP717_ADC_DATA_L 0xcf |
| 177 | |
| 178 | #define AXP806_STARTUP_SRC 0x00 |
| 179 | #define AXP806_CHIP_ID 0x03 |
| 180 | #define AXP806_PWR_OUT_CTRL1 0x10 |
| 181 | #define AXP806_PWR_OUT_CTRL2 0x11 |
| 182 | #define AXP806_DCDCA_V_CTRL 0x12 |
| 183 | #define AXP806_DCDCB_V_CTRL 0x13 |
| 184 | #define AXP806_DCDCC_V_CTRL 0x14 |
| 185 | #define AXP806_DCDCD_V_CTRL 0x15 |
| 186 | #define AXP806_DCDCE_V_CTRL 0x16 |
| 187 | #define AXP806_ALDO1_V_CTRL 0x17 |
| 188 | #define AXP806_ALDO2_V_CTRL 0x18 |
| 189 | #define AXP806_ALDO3_V_CTRL 0x19 |
| 190 | #define AXP806_DCDC_MODE_CTRL1 0x1a |
| 191 | #define AXP806_DCDC_MODE_CTRL2 0x1b |
| 192 | #define AXP806_DCDC_FREQ_CTRL 0x1c |
| 193 | #define AXP806_BLDO1_V_CTRL 0x20 |
| 194 | #define AXP806_BLDO2_V_CTRL 0x21 |
| 195 | #define AXP806_BLDO3_V_CTRL 0x22 |
| 196 | #define AXP806_BLDO4_V_CTRL 0x23 |
| 197 | #define AXP806_CLDO1_V_CTRL 0x24 |
| 198 | #define AXP806_CLDO2_V_CTRL 0x25 |
| 199 | #define AXP806_CLDO3_V_CTRL 0x26 |
| 200 | #define AXP806_VREF_TEMP_WARN_L 0xf3 |
| 201 | #define AXP806_BUS_ADDR_EXT 0xfe |
| 202 | #define AXP806_REG_ADDR_EXT 0xff |
| 203 | |
| 204 | #define AXP803_POLYPHASE_CTRL 0x14 |
| 205 | #define AXP803_FLDO1_V_OUT 0x1c |
| 206 | #define AXP803_FLDO2_V_OUT 0x1d |
| 207 | #define AXP803_DCDC1_V_OUT 0x20 |
| 208 | #define AXP803_DCDC2_V_OUT 0x21 |
| 209 | #define AXP803_DCDC3_V_OUT 0x22 |
| 210 | #define AXP803_DCDC4_V_OUT 0x23 |
| 211 | #define AXP803_DCDC5_V_OUT 0x24 |
| 212 | #define AXP803_DCDC6_V_OUT 0x25 |
| 213 | #define AXP803_DCDC_FREQ_CTRL 0x3b |
| 214 | |
| 215 | /* Other DCDC regulator control registers are the same as AXP803 */ |
| 216 | #define AXP813_DCDC7_V_OUT 0x26 |
| 217 | |
| 218 | #define AXP15060_STARTUP_SRC 0x00 |
| 219 | #define AXP15060_PWR_OUT_CTRL1 0x10 |
| 220 | #define AXP15060_PWR_OUT_CTRL2 0x11 |
| 221 | #define AXP15060_PWR_OUT_CTRL3 0x12 |
| 222 | #define AXP15060_DCDC1_V_CTRL 0x13 |
| 223 | #define AXP15060_DCDC2_V_CTRL 0x14 |
| 224 | #define AXP15060_DCDC3_V_CTRL 0x15 |
| 225 | #define AXP15060_DCDC4_V_CTRL 0x16 |
| 226 | #define AXP15060_DCDC5_V_CTRL 0x17 |
| 227 | #define AXP15060_DCDC6_V_CTRL 0x18 |
| 228 | #define AXP15060_ALDO1_V_CTRL 0x19 |
| 229 | #define AXP15060_DCDC_MODE_CTRL1 0x1a |
| 230 | #define AXP15060_DCDC_MODE_CTRL2 0x1b |
| 231 | #define AXP15060_OUTPUT_MONITOR_DISCHARGE 0x1e |
| 232 | #define AXP15060_IRQ_PWROK_VOFF 0x1f |
| 233 | #define AXP15060_ALDO2_V_CTRL 0x20 |
| 234 | #define AXP15060_ALDO3_V_CTRL 0x21 |
| 235 | #define AXP15060_ALDO4_V_CTRL 0x22 |
| 236 | #define AXP15060_ALDO5_V_CTRL 0x23 |
| 237 | #define AXP15060_BLDO1_V_CTRL 0x24 |
| 238 | #define AXP15060_BLDO2_V_CTRL 0x25 |
| 239 | #define AXP15060_BLDO3_V_CTRL 0x26 |
| 240 | #define AXP15060_BLDO4_V_CTRL 0x27 |
| 241 | #define AXP15060_BLDO5_V_CTRL 0x28 |
| 242 | #define AXP15060_CLDO1_V_CTRL 0x29 |
| 243 | #define AXP15060_CLDO2_V_CTRL 0x2a |
| 244 | #define AXP15060_CLDO3_V_CTRL 0x2b |
| 245 | #define AXP15060_CLDO4_V_CTRL 0x2d |
| 246 | #define AXP15060_CPUSLDO_V_CTRL 0x2e |
| 247 | #define AXP15060_PWR_WAKEUP_CTRL 0x31 |
| 248 | #define AXP15060_PWR_DISABLE_DOWN_SEQ 0x32 |
| 249 | #define AXP15060_PEK_KEY 0x36 |
| 250 | |
| 251 | /* Interrupt */ |
| 252 | #define AXP152_IRQ1_EN 0x40 |
| 253 | #define AXP152_IRQ2_EN 0x41 |
| 254 | #define AXP152_IRQ3_EN 0x42 |
| 255 | #define AXP152_IRQ1_STATE 0x48 |
| 256 | #define AXP152_IRQ2_STATE 0x49 |
| 257 | #define AXP152_IRQ3_STATE 0x4a |
| 258 | |
| 259 | #define AXP192_IRQ1_EN 0x40 |
| 260 | #define AXP192_IRQ2_EN 0x41 |
| 261 | #define AXP192_IRQ3_EN 0x42 |
| 262 | #define AXP192_IRQ4_EN 0x43 |
| 263 | #define AXP192_IRQ1_STATE 0x44 |
| 264 | #define AXP192_IRQ2_STATE 0x45 |
| 265 | #define AXP192_IRQ3_STATE 0x46 |
| 266 | #define AXP192_IRQ4_STATE 0x47 |
| 267 | #define AXP192_IRQ5_EN 0x4a |
| 268 | #define AXP192_IRQ5_STATE 0x4d |
| 269 | |
| 270 | #define AXP20X_IRQ1_EN 0x40 |
| 271 | #define AXP20X_IRQ2_EN 0x41 |
| 272 | #define AXP20X_IRQ3_EN 0x42 |
| 273 | #define AXP20X_IRQ4_EN 0x43 |
| 274 | #define AXP20X_IRQ5_EN 0x44 |
| 275 | #define AXP20X_IRQ6_EN 0x45 |
| 276 | #define AXP20X_IRQ1_STATE 0x48 |
| 277 | #define AXP20X_IRQ2_STATE 0x49 |
| 278 | #define AXP20X_IRQ3_STATE 0x4a |
| 279 | #define AXP20X_IRQ4_STATE 0x4b |
| 280 | #define AXP20X_IRQ5_STATE 0x4c |
| 281 | #define AXP20X_IRQ6_STATE 0x4d |
| 282 | |
| 283 | #define AXP15060_IRQ1_EN 0x40 |
| 284 | #define AXP15060_IRQ2_EN 0x41 |
| 285 | #define AXP15060_IRQ1_STATE 0x48 |
| 286 | #define AXP15060_IRQ2_STATE 0x49 |
| 287 | |
| 288 | /* ADC */ |
| 289 | #define AXP192_GPIO2_V_ADC_H 0x68 |
| 290 | #define AXP192_GPIO2_V_ADC_L 0x69 |
| 291 | #define AXP192_GPIO3_V_ADC_H 0x6a |
| 292 | #define AXP192_GPIO3_V_ADC_L 0x6b |
| 293 | |
| 294 | #define AXP20X_ACIN_V_ADC_H 0x56 |
| 295 | #define AXP20X_ACIN_V_ADC_L 0x57 |
| 296 | #define AXP20X_ACIN_I_ADC_H 0x58 |
| 297 | #define AXP20X_ACIN_I_ADC_L 0x59 |
| 298 | #define AXP20X_VBUS_V_ADC_H 0x5a |
| 299 | #define AXP20X_VBUS_V_ADC_L 0x5b |
| 300 | #define AXP20X_VBUS_I_ADC_H 0x5c |
| 301 | #define AXP20X_VBUS_I_ADC_L 0x5d |
| 302 | #define AXP20X_TEMP_ADC_H 0x5e |
| 303 | #define AXP20X_TEMP_ADC_L 0x5f |
| 304 | #define AXP20X_TS_IN_H 0x62 |
| 305 | #define AXP20X_TS_IN_L 0x63 |
| 306 | #define AXP20X_GPIO0_V_ADC_H 0x64 |
| 307 | #define AXP20X_GPIO0_V_ADC_L 0x65 |
| 308 | #define AXP20X_GPIO1_V_ADC_H 0x66 |
| 309 | #define AXP20X_GPIO1_V_ADC_L 0x67 |
| 310 | #define AXP20X_PWR_BATT_H 0x70 |
| 311 | #define AXP20X_PWR_BATT_M 0x71 |
| 312 | #define AXP20X_PWR_BATT_L 0x72 |
| 313 | #define AXP20X_BATT_V_H 0x78 |
| 314 | #define AXP20X_BATT_V_L 0x79 |
| 315 | #define AXP20X_BATT_CHRG_I_H 0x7a |
| 316 | #define AXP20X_BATT_CHRG_I_L 0x7b |
| 317 | #define AXP20X_BATT_DISCHRG_I_H 0x7c |
| 318 | #define AXP20X_BATT_DISCHRG_I_L 0x7d |
| 319 | #define AXP20X_IPSOUT_V_HIGH_H 0x7e |
| 320 | #define AXP20X_IPSOUT_V_HIGH_L 0x7f |
| 321 | |
| 322 | /* Power supply */ |
| 323 | #define AXP192_GPIO30_IN_RANGE 0x85 |
| 324 | |
| 325 | #define AXP20X_DCDC_MODE 0x80 |
| 326 | #define AXP20X_ADC_EN1 0x82 |
| 327 | #define AXP20X_ADC_EN2 0x83 |
| 328 | #define AXP20X_ADC_RATE 0x84 |
| 329 | #define AXP20X_GPIO10_IN_RANGE 0x85 |
| 330 | #define AXP20X_GPIO1_ADC_IRQ_RIS 0x86 |
| 331 | #define AXP20X_GPIO1_ADC_IRQ_FAL 0x87 |
| 332 | #define AXP20X_TIMER_CTRL 0x8a |
| 333 | #define AXP20X_VBUS_MON 0x8b |
| 334 | #define AXP20X_OVER_TMP 0x8f |
| 335 | |
| 336 | #define AXP22X_PWREN_CTRL1 0x8c |
| 337 | #define AXP22X_PWREN_CTRL2 0x8d |
| 338 | |
| 339 | /* GPIO */ |
| 340 | #define AXP152_GPIO0_CTRL 0x90 |
| 341 | #define AXP152_GPIO1_CTRL 0x91 |
| 342 | #define AXP152_GPIO2_CTRL 0x92 |
| 343 | #define AXP152_GPIO3_CTRL 0x93 |
| 344 | #define AXP152_LDOGPIO2_V_OUT 0x96 |
| 345 | #define AXP152_GPIO_INPUT 0x97 |
| 346 | #define AXP152_PWM0_FREQ_X 0x98 |
| 347 | #define AXP152_PWM0_FREQ_Y 0x99 |
| 348 | #define AXP152_PWM0_DUTY_CYCLE 0x9a |
| 349 | #define AXP152_PWM1_FREQ_X 0x9b |
| 350 | #define AXP152_PWM1_FREQ_Y 0x9c |
| 351 | #define AXP152_PWM1_DUTY_CYCLE 0x9d |
| 352 | |
| 353 | #define AXP192_GPIO0_CTRL 0x90 |
| 354 | #define AXP192_LDO_IO0_V_OUT 0x91 |
| 355 | #define AXP192_GPIO1_CTRL 0x92 |
| 356 | #define AXP192_GPIO2_CTRL 0x93 |
| 357 | #define AXP192_GPIO2_0_STATE 0x94 |
| 358 | #define AXP192_GPIO4_3_CTRL 0x95 |
| 359 | #define AXP192_GPIO4_3_STATE 0x96 |
| 360 | #define AXP192_GPIO2_0_PULL 0x97 |
| 361 | #define AXP192_N_RSTO_CTRL 0x9e |
| 362 | |
| 363 | #define AXP20X_GPIO0_CTRL 0x90 |
| 364 | #define AXP20X_LDO5_V_OUT 0x91 |
| 365 | #define AXP20X_GPIO1_CTRL 0x92 |
| 366 | #define AXP20X_GPIO2_CTRL 0x93 |
| 367 | #define AXP20X_GPIO20_SS 0x94 |
| 368 | #define AXP20X_GPIO3_CTRL 0x95 |
| 369 | |
| 370 | #define AXP22X_LDO_IO0_V_OUT 0x91 |
| 371 | #define AXP22X_LDO_IO1_V_OUT 0x93 |
| 372 | #define AXP22X_GPIO_STATE 0x94 |
| 373 | #define AXP22X_GPIO_PULL_DOWN 0x95 |
| 374 | |
| 375 | #define AXP15060_CLDO4_GPIO2_MODESET 0x2c |
| 376 | |
| 377 | /* Battery */ |
| 378 | #define AXP20X_CHRG_CC_31_24 0xb0 |
| 379 | #define AXP20X_CHRG_CC_23_16 0xb1 |
| 380 | #define AXP20X_CHRG_CC_15_8 0xb2 |
| 381 | #define AXP20X_CHRG_CC_7_0 0xb3 |
| 382 | #define AXP20X_DISCHRG_CC_31_24 0xb4 |
| 383 | #define AXP20X_DISCHRG_CC_23_16 0xb5 |
| 384 | #define AXP20X_DISCHRG_CC_15_8 0xb6 |
| 385 | #define AXP20X_DISCHRG_CC_7_0 0xb7 |
| 386 | #define AXP20X_CC_CTRL 0xb8 |
| 387 | #define AXP20X_FG_RES 0xb9 |
| 388 | |
| 389 | /* OCV */ |
| 390 | #define AXP20X_RDC_H 0xba |
| 391 | #define AXP20X_RDC_L 0xbb |
| 392 | #define AXP20X_OCV(m) (0xc0 + (m)) |
| 393 | #define AXP20X_OCV_MAX 0xf |
| 394 | |
| 395 | /* AXP22X specific registers */ |
| 396 | #define AXP22X_PMIC_TEMP_H 0x56 |
| 397 | #define AXP22X_PMIC_TEMP_L 0x57 |
| 398 | #define AXP22X_TS_ADC_H 0x58 |
| 399 | #define AXP22X_TS_ADC_L 0x59 |
| 400 | #define AXP22X_BATLOW_THRES1 0xe6 |
| 401 | |
| 402 | /* AXP288/AXP803 specific registers */ |
| 403 | #define AXP288_POWER_REASON 0x02 |
| 404 | #define AXP288_BC_GLOBAL 0x2c |
| 405 | #define AXP288_BC_VBUS_CNTL 0x2d |
| 406 | #define AXP288_BC_USB_STAT 0x2e |
| 407 | #define AXP288_BC_DET_STAT 0x2f |
| 408 | #define AXP288_PMIC_ADC_H 0x56 |
| 409 | #define AXP288_PMIC_ADC_L 0x57 |
| 410 | #define AXP288_TS_ADC_H 0x58 |
| 411 | #define AXP288_TS_ADC_L 0x59 |
| 412 | #define AXP288_GP_ADC_H 0x5a |
| 413 | #define AXP288_GP_ADC_L 0x5b |
| 414 | #define AXP288_ADC_TS_PIN_CTRL 0x84 |
| 415 | #define AXP288_RT_BATT_V_H 0xa0 |
| 416 | #define AXP288_RT_BATT_V_L 0xa1 |
| 417 | |
| 418 | #define AXP813_ACIN_PATH_CTRL 0x3a |
| 419 | #define AXP813_ADC_RATE 0x85 |
| 420 | |
| 421 | /* Fuel Gauge */ |
| 422 | #define AXP288_FG_RDC1_REG 0xba |
| 423 | #define AXP288_FG_RDC0_REG 0xbb |
| 424 | #define AXP288_FG_OCVH_REG 0xbc |
| 425 | #define AXP288_FG_OCVL_REG 0xbd |
| 426 | #define AXP288_FG_OCV_CURVE_REG 0xc0 |
| 427 | #define AXP288_FG_DES_CAP1_REG 0xe0 |
| 428 | #define AXP288_FG_DES_CAP0_REG 0xe1 |
| 429 | #define AXP288_FG_CC_MTR1_REG 0xe2 |
| 430 | #define AXP288_FG_CC_MTR0_REG 0xe3 |
| 431 | #define AXP288_FG_OCV_CAP_REG 0xe4 |
| 432 | #define AXP288_FG_CC_CAP_REG 0xe5 |
| 433 | #define AXP288_FG_LOW_CAP_REG 0xe6 |
| 434 | #define AXP288_FG_TUNE0 0xe8 |
| 435 | #define AXP288_FG_TUNE1 0xe9 |
| 436 | #define AXP288_FG_TUNE2 0xea |
| 437 | #define AXP288_FG_TUNE3 0xeb |
| 438 | #define AXP288_FG_TUNE4 0xec |
| 439 | #define AXP288_FG_TUNE5 0xed |
| 440 | |
| 441 | /* Regulators IDs */ |
| 442 | enum { |
| 443 | AXP192_DCDC1 = 0, |
| 444 | AXP192_DCDC2, |
| 445 | AXP192_DCDC3, |
| 446 | AXP192_LDO1, |
| 447 | AXP192_LDO2, |
| 448 | AXP192_LDO3, |
| 449 | AXP192_LDO_IO0, |
| 450 | AXP192_REG_ID_MAX |
| 451 | }; |
| 452 | |
| 453 | enum { |
| 454 | AXP20X_LDO1 = 0, |
| 455 | AXP20X_LDO2, |
| 456 | AXP20X_LDO3, |
| 457 | AXP20X_LDO4, |
| 458 | AXP20X_LDO5, |
| 459 | AXP20X_DCDC2, |
| 460 | AXP20X_DCDC3, |
| 461 | AXP20X_REG_ID_MAX, |
| 462 | }; |
| 463 | |
| 464 | enum { |
| 465 | AXP22X_DCDC1 = 0, |
| 466 | AXP22X_DCDC2, |
| 467 | AXP22X_DCDC3, |
| 468 | AXP22X_DCDC4, |
| 469 | AXP22X_DCDC5, |
| 470 | AXP22X_DC1SW, |
| 471 | AXP22X_DC5LDO, |
| 472 | AXP22X_ALDO1, |
| 473 | AXP22X_ALDO2, |
| 474 | AXP22X_ALDO3, |
| 475 | AXP22X_ELDO1, |
| 476 | AXP22X_ELDO2, |
| 477 | AXP22X_ELDO3, |
| 478 | AXP22X_DLDO1, |
| 479 | AXP22X_DLDO2, |
| 480 | AXP22X_DLDO3, |
| 481 | AXP22X_DLDO4, |
| 482 | AXP22X_RTC_LDO, |
| 483 | AXP22X_LDO_IO0, |
| 484 | AXP22X_LDO_IO1, |
| 485 | AXP22X_REG_ID_MAX, |
| 486 | }; |
| 487 | |
| 488 | enum { |
| 489 | AXP313A_DCDC1 = 0, |
| 490 | AXP313A_DCDC2, |
| 491 | AXP313A_DCDC3, |
| 492 | AXP313A_ALDO1, |
| 493 | AXP313A_DLDO1, |
| 494 | AXP313A_RTC_LDO, |
| 495 | AXP313A_REG_ID_MAX, |
| 496 | }; |
| 497 | |
| 498 | enum { |
| 499 | AXP717_DCDC1 = 0, |
| 500 | AXP717_DCDC2, |
| 501 | AXP717_DCDC3, |
| 502 | AXP717_DCDC4, |
| 503 | AXP717_ALDO1, |
| 504 | AXP717_ALDO2, |
| 505 | AXP717_ALDO3, |
| 506 | AXP717_ALDO4, |
| 507 | AXP717_BLDO1, |
| 508 | AXP717_BLDO2, |
| 509 | AXP717_BLDO3, |
| 510 | AXP717_BLDO4, |
| 511 | AXP717_CLDO1, |
| 512 | AXP717_CLDO2, |
| 513 | AXP717_CLDO3, |
| 514 | AXP717_CLDO4, |
| 515 | AXP717_CPUSLDO, |
| 516 | AXP717_BOOST, |
| 517 | AXP717_REG_ID_MAX, |
| 518 | }; |
| 519 | |
| 520 | enum { |
| 521 | AXP806_DCDCA = 0, |
| 522 | AXP806_DCDCB, |
| 523 | AXP806_DCDCC, |
| 524 | AXP806_DCDCD, |
| 525 | AXP806_DCDCE, |
| 526 | AXP806_ALDO1, |
| 527 | AXP806_ALDO2, |
| 528 | AXP806_ALDO3, |
| 529 | AXP806_BLDO1, |
| 530 | AXP806_BLDO2, |
| 531 | AXP806_BLDO3, |
| 532 | AXP806_BLDO4, |
| 533 | AXP806_CLDO1, |
| 534 | AXP806_CLDO2, |
| 535 | AXP806_CLDO3, |
| 536 | AXP806_SW, |
| 537 | AXP806_REG_ID_MAX, |
| 538 | }; |
| 539 | |
| 540 | enum { |
| 541 | AXP809_DCDC1 = 0, |
| 542 | AXP809_DCDC2, |
| 543 | AXP809_DCDC3, |
| 544 | AXP809_DCDC4, |
| 545 | AXP809_DCDC5, |
| 546 | AXP809_DC1SW, |
| 547 | AXP809_DC5LDO, |
| 548 | AXP809_ALDO1, |
| 549 | AXP809_ALDO2, |
| 550 | AXP809_ALDO3, |
| 551 | AXP809_ELDO1, |
| 552 | AXP809_ELDO2, |
| 553 | AXP809_ELDO3, |
| 554 | AXP809_DLDO1, |
| 555 | AXP809_DLDO2, |
| 556 | AXP809_RTC_LDO, |
| 557 | AXP809_LDO_IO0, |
| 558 | AXP809_LDO_IO1, |
| 559 | AXP809_SW, |
| 560 | AXP809_REG_ID_MAX, |
| 561 | }; |
| 562 | |
| 563 | enum { |
| 564 | AXP803_DCDC1 = 0, |
| 565 | AXP803_DCDC2, |
| 566 | AXP803_DCDC3, |
| 567 | AXP803_DCDC4, |
| 568 | AXP803_DCDC5, |
| 569 | AXP803_DCDC6, |
| 570 | AXP803_DC1SW, |
| 571 | AXP803_ALDO1, |
| 572 | AXP803_ALDO2, |
| 573 | AXP803_ALDO3, |
| 574 | AXP803_DLDO1, |
| 575 | AXP803_DLDO2, |
| 576 | AXP803_DLDO3, |
| 577 | AXP803_DLDO4, |
| 578 | AXP803_ELDO1, |
| 579 | AXP803_ELDO2, |
| 580 | AXP803_ELDO3, |
| 581 | AXP803_FLDO1, |
| 582 | AXP803_FLDO2, |
| 583 | AXP803_RTC_LDO, |
| 584 | AXP803_LDO_IO0, |
| 585 | AXP803_LDO_IO1, |
| 586 | AXP803_REG_ID_MAX, |
| 587 | }; |
| 588 | |
| 589 | enum { |
| 590 | AXP813_DCDC1 = 0, |
| 591 | AXP813_DCDC2, |
| 592 | AXP813_DCDC3, |
| 593 | AXP813_DCDC4, |
| 594 | AXP813_DCDC5, |
| 595 | AXP813_DCDC6, |
| 596 | AXP813_DCDC7, |
| 597 | AXP813_ALDO1, |
| 598 | AXP813_ALDO2, |
| 599 | AXP813_ALDO3, |
| 600 | AXP813_DLDO1, |
| 601 | AXP813_DLDO2, |
| 602 | AXP813_DLDO3, |
| 603 | AXP813_DLDO4, |
| 604 | AXP813_ELDO1, |
| 605 | AXP813_ELDO2, |
| 606 | AXP813_ELDO3, |
| 607 | AXP813_FLDO1, |
| 608 | AXP813_FLDO2, |
| 609 | AXP813_FLDO3, |
| 610 | AXP813_RTC_LDO, |
| 611 | AXP813_LDO_IO0, |
| 612 | AXP813_LDO_IO1, |
| 613 | AXP813_SW, |
| 614 | AXP813_REG_ID_MAX, |
| 615 | }; |
| 616 | |
| 617 | enum { |
| 618 | AXP15060_DCDC1 = 0, |
| 619 | AXP15060_DCDC2, |
| 620 | AXP15060_DCDC3, |
| 621 | AXP15060_DCDC4, |
| 622 | AXP15060_DCDC5, |
| 623 | AXP15060_DCDC6, |
| 624 | AXP15060_ALDO1, |
| 625 | AXP15060_ALDO2, |
| 626 | AXP15060_ALDO3, |
| 627 | AXP15060_ALDO4, |
| 628 | AXP15060_ALDO5, |
| 629 | AXP15060_BLDO1, |
| 630 | AXP15060_BLDO2, |
| 631 | AXP15060_BLDO3, |
| 632 | AXP15060_BLDO4, |
| 633 | AXP15060_BLDO5, |
| 634 | AXP15060_CLDO1, |
| 635 | AXP15060_CLDO2, |
| 636 | AXP15060_CLDO3, |
| 637 | AXP15060_CLDO4, |
| 638 | AXP15060_CPUSLDO, |
| 639 | AXP15060_SW, |
| 640 | AXP15060_RTC_LDO, |
| 641 | AXP15060_REG_ID_MAX, |
| 642 | }; |
| 643 | |
| 644 | /* IRQs */ |
| 645 | enum { |
| 646 | AXP152_IRQ_LDO0IN_CONNECT = 1, |
| 647 | AXP152_IRQ_LDO0IN_REMOVAL, |
| 648 | AXP152_IRQ_ALDO0IN_CONNECT, |
| 649 | AXP152_IRQ_ALDO0IN_REMOVAL, |
| 650 | AXP152_IRQ_DCDC1_V_LOW, |
| 651 | AXP152_IRQ_DCDC2_V_LOW, |
| 652 | AXP152_IRQ_DCDC3_V_LOW, |
| 653 | AXP152_IRQ_DCDC4_V_LOW, |
| 654 | AXP152_IRQ_PEK_SHORT, |
| 655 | AXP152_IRQ_PEK_LONG, |
| 656 | AXP152_IRQ_TIMER, |
| 657 | /* out of bit order to make sure the press event is handled first */ |
| 658 | AXP152_IRQ_PEK_FAL_EDGE, |
| 659 | AXP152_IRQ_PEK_RIS_EDGE, |
| 660 | AXP152_IRQ_GPIO3_INPUT, |
| 661 | AXP152_IRQ_GPIO2_INPUT, |
| 662 | AXP152_IRQ_GPIO1_INPUT, |
| 663 | AXP152_IRQ_GPIO0_INPUT, |
| 664 | }; |
| 665 | |
| 666 | enum axp192_irqs { |
| 667 | AXP192_IRQ_ACIN_OVER_V = 1, |
| 668 | AXP192_IRQ_ACIN_PLUGIN, |
| 669 | AXP192_IRQ_ACIN_REMOVAL, |
| 670 | AXP192_IRQ_VBUS_OVER_V, |
| 671 | AXP192_IRQ_VBUS_PLUGIN, |
| 672 | AXP192_IRQ_VBUS_REMOVAL, |
| 673 | AXP192_IRQ_VBUS_V_LOW, |
| 674 | AXP192_IRQ_BATT_PLUGIN, |
| 675 | AXP192_IRQ_BATT_REMOVAL, |
| 676 | AXP192_IRQ_BATT_ENT_ACT_MODE, |
| 677 | AXP192_IRQ_BATT_EXIT_ACT_MODE, |
| 678 | AXP192_IRQ_CHARG, |
| 679 | AXP192_IRQ_CHARG_DONE, |
| 680 | AXP192_IRQ_BATT_TEMP_HIGH, |
| 681 | AXP192_IRQ_BATT_TEMP_LOW, |
| 682 | AXP192_IRQ_DIE_TEMP_HIGH, |
| 683 | AXP192_IRQ_CHARG_I_LOW, |
| 684 | AXP192_IRQ_DCDC1_V_LONG, |
| 685 | AXP192_IRQ_DCDC2_V_LONG, |
| 686 | AXP192_IRQ_DCDC3_V_LONG, |
| 687 | AXP192_IRQ_PEK_SHORT = 22, |
| 688 | AXP192_IRQ_PEK_LONG, |
| 689 | AXP192_IRQ_N_OE_PWR_ON, |
| 690 | AXP192_IRQ_N_OE_PWR_OFF, |
| 691 | AXP192_IRQ_VBUS_VALID, |
| 692 | AXP192_IRQ_VBUS_NOT_VALID, |
| 693 | AXP192_IRQ_VBUS_SESS_VALID, |
| 694 | AXP192_IRQ_VBUS_SESS_END, |
| 695 | AXP192_IRQ_LOW_PWR_LVL = 31, |
| 696 | AXP192_IRQ_TIMER, |
| 697 | AXP192_IRQ_GPIO2_INPUT = 37, |
| 698 | AXP192_IRQ_GPIO1_INPUT, |
| 699 | AXP192_IRQ_GPIO0_INPUT, |
| 700 | }; |
| 701 | |
| 702 | enum { |
| 703 | AXP20X_IRQ_ACIN_OVER_V = 1, |
| 704 | AXP20X_IRQ_ACIN_PLUGIN, |
| 705 | AXP20X_IRQ_ACIN_REMOVAL, |
| 706 | AXP20X_IRQ_VBUS_OVER_V, |
| 707 | AXP20X_IRQ_VBUS_PLUGIN, |
| 708 | AXP20X_IRQ_VBUS_REMOVAL, |
| 709 | AXP20X_IRQ_VBUS_V_LOW, |
| 710 | AXP20X_IRQ_BATT_PLUGIN, |
| 711 | AXP20X_IRQ_BATT_REMOVAL, |
| 712 | AXP20X_IRQ_BATT_ENT_ACT_MODE, |
| 713 | AXP20X_IRQ_BATT_EXIT_ACT_MODE, |
| 714 | AXP20X_IRQ_CHARG, |
| 715 | AXP20X_IRQ_CHARG_DONE, |
| 716 | AXP20X_IRQ_BATT_TEMP_HIGH, |
| 717 | AXP20X_IRQ_BATT_TEMP_LOW, |
| 718 | AXP20X_IRQ_DIE_TEMP_HIGH, |
| 719 | AXP20X_IRQ_CHARG_I_LOW, |
| 720 | AXP20X_IRQ_DCDC1_V_LONG, |
| 721 | AXP20X_IRQ_DCDC2_V_LONG, |
| 722 | AXP20X_IRQ_DCDC3_V_LONG, |
| 723 | AXP20X_IRQ_PEK_SHORT = 22, |
| 724 | AXP20X_IRQ_PEK_LONG, |
| 725 | AXP20X_IRQ_N_OE_PWR_ON, |
| 726 | AXP20X_IRQ_N_OE_PWR_OFF, |
| 727 | AXP20X_IRQ_VBUS_VALID, |
| 728 | AXP20X_IRQ_VBUS_NOT_VALID, |
| 729 | AXP20X_IRQ_VBUS_SESS_VALID, |
| 730 | AXP20X_IRQ_VBUS_SESS_END, |
| 731 | AXP20X_IRQ_LOW_PWR_LVL1, |
| 732 | AXP20X_IRQ_LOW_PWR_LVL2, |
| 733 | AXP20X_IRQ_TIMER, |
| 734 | /* out of bit order to make sure the press event is handled first */ |
| 735 | AXP20X_IRQ_PEK_FAL_EDGE, |
| 736 | AXP20X_IRQ_PEK_RIS_EDGE, |
| 737 | AXP20X_IRQ_GPIO3_INPUT, |
| 738 | AXP20X_IRQ_GPIO2_INPUT, |
| 739 | AXP20X_IRQ_GPIO1_INPUT, |
| 740 | AXP20X_IRQ_GPIO0_INPUT, |
| 741 | }; |
| 742 | |
| 743 | enum axp22x_irqs { |
| 744 | AXP22X_IRQ_ACIN_OVER_V = 1, |
| 745 | AXP22X_IRQ_ACIN_PLUGIN, |
| 746 | AXP22X_IRQ_ACIN_REMOVAL, |
| 747 | AXP22X_IRQ_VBUS_OVER_V, |
| 748 | AXP22X_IRQ_VBUS_PLUGIN, |
| 749 | AXP22X_IRQ_VBUS_REMOVAL, |
| 750 | AXP22X_IRQ_VBUS_V_LOW, |
| 751 | AXP22X_IRQ_BATT_PLUGIN, |
| 752 | AXP22X_IRQ_BATT_REMOVAL, |
| 753 | AXP22X_IRQ_BATT_ENT_ACT_MODE, |
| 754 | AXP22X_IRQ_BATT_EXIT_ACT_MODE, |
| 755 | AXP22X_IRQ_CHARG, |
| 756 | AXP22X_IRQ_CHARG_DONE, |
| 757 | AXP22X_IRQ_BATT_TEMP_HIGH, |
| 758 | AXP22X_IRQ_BATT_TEMP_LOW, |
| 759 | AXP22X_IRQ_DIE_TEMP_HIGH, |
| 760 | AXP22X_IRQ_PEK_SHORT, |
| 761 | AXP22X_IRQ_PEK_LONG, |
| 762 | AXP22X_IRQ_LOW_PWR_LVL1, |
| 763 | AXP22X_IRQ_LOW_PWR_LVL2, |
| 764 | AXP22X_IRQ_TIMER, |
| 765 | /* out of bit order to make sure the press event is handled first */ |
| 766 | AXP22X_IRQ_PEK_FAL_EDGE, |
| 767 | AXP22X_IRQ_PEK_RIS_EDGE, |
| 768 | AXP22X_IRQ_GPIO1_INPUT, |
| 769 | AXP22X_IRQ_GPIO0_INPUT, |
| 770 | }; |
| 771 | |
| 772 | enum axp288_irqs { |
| 773 | AXP288_IRQ_VBUS_FALL = 2, |
| 774 | AXP288_IRQ_VBUS_RISE, |
| 775 | AXP288_IRQ_OV, |
| 776 | AXP288_IRQ_FALLING_ALT, |
| 777 | AXP288_IRQ_RISING_ALT, |
| 778 | AXP288_IRQ_OV_ALT, |
| 779 | AXP288_IRQ_DONE = 10, |
| 780 | AXP288_IRQ_CHARGING, |
| 781 | AXP288_IRQ_SAFE_QUIT, |
| 782 | AXP288_IRQ_SAFE_ENTER, |
| 783 | AXP288_IRQ_ABSENT, |
| 784 | AXP288_IRQ_APPEND, |
| 785 | AXP288_IRQ_QWBTU, |
| 786 | AXP288_IRQ_WBTU, |
| 787 | AXP288_IRQ_QWBTO, |
| 788 | AXP288_IRQ_WBTO, |
| 789 | AXP288_IRQ_QCBTU, |
| 790 | AXP288_IRQ_CBTU, |
| 791 | AXP288_IRQ_QCBTO, |
| 792 | AXP288_IRQ_CBTO, |
| 793 | AXP288_IRQ_WL2, |
| 794 | AXP288_IRQ_WL1, |
| 795 | AXP288_IRQ_GPADC, |
| 796 | AXP288_IRQ_OT = 31, |
| 797 | AXP288_IRQ_GPIO0, |
| 798 | AXP288_IRQ_GPIO1, |
| 799 | AXP288_IRQ_POKO, |
| 800 | AXP288_IRQ_POKL, |
| 801 | AXP288_IRQ_POKS, |
| 802 | AXP288_IRQ_POKN, |
| 803 | AXP288_IRQ_POKP, |
| 804 | AXP288_IRQ_TIMER, |
| 805 | AXP288_IRQ_MV_CHNG, |
| 806 | AXP288_IRQ_BC_USB_CHNG, |
| 807 | }; |
| 808 | |
| 809 | enum axp313a_irqs { |
| 810 | AXP313A_IRQ_DIE_TEMP_HIGH, |
| 811 | AXP313A_IRQ_DCDC2_V_LOW = 2, |
| 812 | AXP313A_IRQ_DCDC3_V_LOW, |
| 813 | AXP313A_IRQ_PEK_LONG, |
| 814 | AXP313A_IRQ_PEK_SHORT, |
| 815 | AXP313A_IRQ_PEK_FAL_EDGE, |
| 816 | AXP313A_IRQ_PEK_RIS_EDGE, |
| 817 | }; |
| 818 | |
| 819 | enum axp717_irqs { |
| 820 | AXP717_IRQ_VBUS_FAULT, |
| 821 | AXP717_IRQ_VBUS_OVER_V, |
| 822 | AXP717_IRQ_BOOST_OVER_V, |
| 823 | AXP717_IRQ_GAUGE_NEW_SOC = 4, |
| 824 | AXP717_IRQ_SOC_DROP_LVL1 = 6, |
| 825 | AXP717_IRQ_SOC_DROP_LVL2, |
| 826 | AXP717_IRQ_PEK_RIS_EDGE, |
| 827 | AXP717_IRQ_PEK_FAL_EDGE, |
| 828 | AXP717_IRQ_PEK_LONG, |
| 829 | AXP717_IRQ_PEK_SHORT, |
| 830 | AXP717_IRQ_BATT_REMOVAL, |
| 831 | AXP717_IRQ_BATT_PLUGIN, |
| 832 | AXP717_IRQ_VBUS_REMOVAL, |
| 833 | AXP717_IRQ_VBUS_PLUGIN, |
| 834 | AXP717_IRQ_BATT_OVER_V, |
| 835 | AXP717_IRQ_CHARG_TIMER, |
| 836 | AXP717_IRQ_DIE_TEMP_HIGH, |
| 837 | AXP717_IRQ_CHARG, |
| 838 | AXP717_IRQ_CHARG_DONE, |
| 839 | AXP717_IRQ_BATT_OVER_CURR, |
| 840 | AXP717_IRQ_LDO_OVER_CURR, |
| 841 | AXP717_IRQ_WDOG_EXPIRE, |
| 842 | AXP717_IRQ_BATT_ACT_TEMP_LOW, |
| 843 | AXP717_IRQ_BATT_ACT_TEMP_HIGH, |
| 844 | AXP717_IRQ_BATT_CHG_TEMP_LOW, |
| 845 | AXP717_IRQ_BATT_CHG_TEMP_HIGH, |
| 846 | AXP717_IRQ_BATT_QUIT_TEMP_HIGH, |
| 847 | AXP717_IRQ_BC_USB_CHNG = 30, |
| 848 | AXP717_IRQ_BC_USB_DONE, |
| 849 | AXP717_IRQ_TYPEC_PLUGIN = 37, |
| 850 | AXP717_IRQ_TYPEC_REMOVE, |
| 851 | }; |
| 852 | |
| 853 | enum axp803_irqs { |
| 854 | AXP803_IRQ_ACIN_OVER_V = 1, |
| 855 | AXP803_IRQ_ACIN_PLUGIN, |
| 856 | AXP803_IRQ_ACIN_REMOVAL, |
| 857 | AXP803_IRQ_VBUS_OVER_V, |
| 858 | AXP803_IRQ_VBUS_PLUGIN, |
| 859 | AXP803_IRQ_VBUS_REMOVAL, |
| 860 | AXP803_IRQ_BATT_PLUGIN, |
| 861 | AXP803_IRQ_BATT_REMOVAL, |
| 862 | AXP803_IRQ_BATT_ENT_ACT_MODE, |
| 863 | AXP803_IRQ_BATT_EXIT_ACT_MODE, |
| 864 | AXP803_IRQ_CHARG, |
| 865 | AXP803_IRQ_CHARG_DONE, |
| 866 | AXP803_IRQ_BATT_CHG_TEMP_HIGH, |
| 867 | AXP803_IRQ_BATT_CHG_TEMP_HIGH_END, |
| 868 | AXP803_IRQ_BATT_CHG_TEMP_LOW, |
| 869 | AXP803_IRQ_BATT_CHG_TEMP_LOW_END, |
| 870 | AXP803_IRQ_BATT_ACT_TEMP_HIGH, |
| 871 | AXP803_IRQ_BATT_ACT_TEMP_HIGH_END, |
| 872 | AXP803_IRQ_BATT_ACT_TEMP_LOW, |
| 873 | AXP803_IRQ_BATT_ACT_TEMP_LOW_END, |
| 874 | AXP803_IRQ_DIE_TEMP_HIGH, |
| 875 | AXP803_IRQ_GPADC, |
| 876 | AXP803_IRQ_LOW_PWR_LVL1, |
| 877 | AXP803_IRQ_LOW_PWR_LVL2, |
| 878 | AXP803_IRQ_TIMER, |
| 879 | /* out of bit order to make sure the press event is handled first */ |
| 880 | AXP803_IRQ_PEK_FAL_EDGE, |
| 881 | AXP803_IRQ_PEK_RIS_EDGE, |
| 882 | AXP803_IRQ_PEK_SHORT, |
| 883 | AXP803_IRQ_PEK_LONG, |
| 884 | AXP803_IRQ_PEK_OVER_OFF, |
| 885 | AXP803_IRQ_GPIO1_INPUT, |
| 886 | AXP803_IRQ_GPIO0_INPUT, |
| 887 | AXP803_IRQ_BC_USB_CHNG, |
| 888 | AXP803_IRQ_MV_CHNG, |
| 889 | }; |
| 890 | |
| 891 | enum axp806_irqs { |
| 892 | AXP806_IRQ_DIE_TEMP_HIGH_LV1, |
| 893 | AXP806_IRQ_DIE_TEMP_HIGH_LV2, |
| 894 | AXP806_IRQ_DCDCA_V_LOW, |
| 895 | AXP806_IRQ_DCDCB_V_LOW, |
| 896 | AXP806_IRQ_DCDCC_V_LOW, |
| 897 | AXP806_IRQ_DCDCD_V_LOW, |
| 898 | AXP806_IRQ_DCDCE_V_LOW, |
| 899 | AXP806_IRQ_POK_LONG, |
| 900 | AXP806_IRQ_POK_SHORT, |
| 901 | AXP806_IRQ_WAKEUP, |
| 902 | AXP806_IRQ_POK_FALL, |
| 903 | AXP806_IRQ_POK_RISE, |
| 904 | }; |
| 905 | |
| 906 | enum axp809_irqs { |
| 907 | AXP809_IRQ_ACIN_OVER_V = 1, |
| 908 | AXP809_IRQ_ACIN_PLUGIN, |
| 909 | AXP809_IRQ_ACIN_REMOVAL, |
| 910 | AXP809_IRQ_VBUS_OVER_V, |
| 911 | AXP809_IRQ_VBUS_PLUGIN, |
| 912 | AXP809_IRQ_VBUS_REMOVAL, |
| 913 | AXP809_IRQ_VBUS_V_LOW, |
| 914 | AXP809_IRQ_BATT_PLUGIN, |
| 915 | AXP809_IRQ_BATT_REMOVAL, |
| 916 | AXP809_IRQ_BATT_ENT_ACT_MODE, |
| 917 | AXP809_IRQ_BATT_EXIT_ACT_MODE, |
| 918 | AXP809_IRQ_CHARG, |
| 919 | AXP809_IRQ_CHARG_DONE, |
| 920 | AXP809_IRQ_BATT_CHG_TEMP_HIGH, |
| 921 | AXP809_IRQ_BATT_CHG_TEMP_HIGH_END, |
| 922 | AXP809_IRQ_BATT_CHG_TEMP_LOW, |
| 923 | AXP809_IRQ_BATT_CHG_TEMP_LOW_END, |
| 924 | AXP809_IRQ_BATT_ACT_TEMP_HIGH, |
| 925 | AXP809_IRQ_BATT_ACT_TEMP_HIGH_END, |
| 926 | AXP809_IRQ_BATT_ACT_TEMP_LOW, |
| 927 | AXP809_IRQ_BATT_ACT_TEMP_LOW_END, |
| 928 | AXP809_IRQ_DIE_TEMP_HIGH, |
| 929 | AXP809_IRQ_LOW_PWR_LVL1, |
| 930 | AXP809_IRQ_LOW_PWR_LVL2, |
| 931 | AXP809_IRQ_TIMER, |
| 932 | /* out of bit order to make sure the press event is handled first */ |
| 933 | AXP809_IRQ_PEK_FAL_EDGE, |
| 934 | AXP809_IRQ_PEK_RIS_EDGE, |
| 935 | AXP809_IRQ_PEK_SHORT, |
| 936 | AXP809_IRQ_PEK_LONG, |
| 937 | AXP809_IRQ_PEK_OVER_OFF, |
| 938 | AXP809_IRQ_GPIO1_INPUT, |
| 939 | AXP809_IRQ_GPIO0_INPUT, |
| 940 | }; |
| 941 | |
| 942 | enum axp15060_irqs { |
| 943 | AXP15060_IRQ_DIE_TEMP_HIGH_LV1 = 1, |
| 944 | AXP15060_IRQ_DIE_TEMP_HIGH_LV2, |
| 945 | AXP15060_IRQ_DCDC1_V_LOW, |
| 946 | AXP15060_IRQ_DCDC2_V_LOW, |
| 947 | AXP15060_IRQ_DCDC3_V_LOW, |
| 948 | AXP15060_IRQ_DCDC4_V_LOW, |
| 949 | AXP15060_IRQ_DCDC5_V_LOW, |
| 950 | AXP15060_IRQ_DCDC6_V_LOW, |
| 951 | AXP15060_IRQ_PEK_LONG, |
| 952 | AXP15060_IRQ_PEK_SHORT, |
| 953 | AXP15060_IRQ_GPIO1_INPUT, |
| 954 | AXP15060_IRQ_PEK_FAL_EDGE, |
| 955 | AXP15060_IRQ_PEK_RIS_EDGE, |
| 956 | AXP15060_IRQ_GPIO2_INPUT, |
| 957 | }; |
| 958 | |
| 959 | struct axp20x_dev { |
| 960 | struct device *dev; |
| 961 | int irq; |
| 962 | unsigned long irq_flags; |
| 963 | struct regmap *regmap; |
| 964 | struct regmap_irq_chip_data *regmap_irqc; |
| 965 | enum axp20x_variants variant; |
| 966 | int nr_cells; |
| 967 | const struct mfd_cell *cells; |
| 968 | const struct regmap_config *regmap_cfg; |
| 969 | const struct regmap_irq_chip *regmap_irq_chip; |
| 970 | }; |
| 971 | |
| 972 | /* generic helper function for reading 9-16 bit wide regs */ |
| 973 | static inline int axp20x_read_variable_width(struct regmap *regmap, |
| 974 | unsigned int reg, unsigned int width) |
| 975 | { |
| 976 | unsigned int reg_val, result; |
| 977 | int err; |
| 978 | |
| 979 | err = regmap_read(map: regmap, reg, val: ®_val); |
| 980 | if (err) |
| 981 | return err; |
| 982 | |
| 983 | result = reg_val << (width - 8); |
| 984 | |
| 985 | err = regmap_read(map: regmap, reg: reg + 1, val: ®_val); |
| 986 | if (err) |
| 987 | return err; |
| 988 | |
| 989 | result |= reg_val; |
| 990 | |
| 991 | return result; |
| 992 | } |
| 993 | |
| 994 | /** |
| 995 | * axp20x_match_device(): Setup axp20x variant related fields |
| 996 | * |
| 997 | * @axp20x: axp20x device to setup (.dev field must be set) |
| 998 | * @dev: device associated with this axp20x device |
| 999 | * |
| 1000 | * This lets the axp20x core configure the mfd cells and register maps |
| 1001 | * for later use. |
| 1002 | */ |
| 1003 | int axp20x_match_device(struct axp20x_dev *axp20x); |
| 1004 | |
| 1005 | /** |
| 1006 | * axp20x_device_probe(): Probe a configured axp20x device |
| 1007 | * |
| 1008 | * @axp20x: axp20x device to probe (must be configured) |
| 1009 | * |
| 1010 | * This function lets the axp20x core register the axp20x mfd devices |
| 1011 | * and irqchip. The axp20x device passed in must be fully configured |
| 1012 | * with axp20x_match_device, its irq set, and regmap created. |
| 1013 | */ |
| 1014 | int axp20x_device_probe(struct axp20x_dev *axp20x); |
| 1015 | |
| 1016 | /** |
| 1017 | * axp20x_device_remove(): Remove a axp20x device |
| 1018 | * |
| 1019 | * @axp20x: axp20x device to remove |
| 1020 | * |
| 1021 | * This tells the axp20x core to remove the associated mfd devices |
| 1022 | */ |
| 1023 | void axp20x_device_remove(struct axp20x_dev *axp20x); |
| 1024 | |
| 1025 | #endif /* __LINUX_MFD_AXP20X_H */ |
| 1026 | |