1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Type definitions for the Microsoft hypervisor.
4 */
5#ifndef _HV_HVGDK_MINI_H
6#define _HV_HVGDK_MINI_H
7
8#include <linux/types.h>
9#include <linux/bits.h>
10
11struct hv_u128 {
12 u64 low_part;
13 u64 high_part;
14} __packed;
15
16/* NOTE: when adding below, update hv_result_to_string() */
17#define HV_STATUS_SUCCESS 0x0
18#define HV_STATUS_INVALID_HYPERCALL_CODE 0x2
19#define HV_STATUS_INVALID_HYPERCALL_INPUT 0x3
20#define HV_STATUS_INVALID_ALIGNMENT 0x4
21#define HV_STATUS_INVALID_PARAMETER 0x5
22#define HV_STATUS_ACCESS_DENIED 0x6
23#define HV_STATUS_INVALID_PARTITION_STATE 0x7
24#define HV_STATUS_OPERATION_DENIED 0x8
25#define HV_STATUS_UNKNOWN_PROPERTY 0x9
26#define HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE 0xA
27#define HV_STATUS_INSUFFICIENT_MEMORY 0xB
28#define HV_STATUS_INVALID_PARTITION_ID 0xD
29#define HV_STATUS_INVALID_VP_INDEX 0xE
30#define HV_STATUS_NOT_FOUND 0x10
31#define HV_STATUS_INVALID_PORT_ID 0x11
32#define HV_STATUS_INVALID_CONNECTION_ID 0x12
33#define HV_STATUS_INSUFFICIENT_BUFFERS 0x13
34#define HV_STATUS_NOT_ACKNOWLEDGED 0x14
35#define HV_STATUS_INVALID_VP_STATE 0x15
36#define HV_STATUS_NO_RESOURCES 0x1D
37#define HV_STATUS_PROCESSOR_FEATURE_NOT_SUPPORTED 0x20
38#define HV_STATUS_INVALID_LP_INDEX 0x41
39#define HV_STATUS_INVALID_REGISTER_VALUE 0x50
40#define HV_STATUS_OPERATION_FAILED 0x71
41#define HV_STATUS_TIME_OUT 0x78
42#define HV_STATUS_CALL_PENDING 0x79
43#define HV_STATUS_VTL_ALREADY_ENABLED 0x86
44
45/*
46 * The Hyper-V TimeRefCount register and the TSC
47 * page provide a guest VM clock with 100ns tick rate
48 */
49#define HV_CLOCK_HZ (NSEC_PER_SEC / 100)
50
51#define HV_HYP_PAGE_SHIFT 12
52#define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT)
53#define HV_HYP_PAGE_MASK (~(HV_HYP_PAGE_SIZE - 1))
54#define HV_HYP_LARGE_PAGE_SHIFT 21
55
56#define HV_PARTITION_ID_INVALID ((u64)0)
57#define HV_PARTITION_ID_SELF ((u64)-1)
58
59/* Hyper-V specific model specific registers (MSRs) */
60
61#if defined(CONFIG_X86)
62/* HV_X64_SYNTHETIC_MSR */
63#define HV_X64_MSR_GUEST_OS_ID 0x40000000
64#define HV_X64_MSR_HYPERCALL 0x40000001
65#define HV_X64_MSR_VP_INDEX 0x40000002
66#define HV_X64_MSR_RESET 0x40000003
67#define HV_X64_MSR_VP_RUNTIME 0x40000010
68#define HV_X64_MSR_TIME_REF_COUNT 0x40000020
69#define HV_X64_MSR_REFERENCE_TSC 0x40000021
70#define HV_X64_MSR_TSC_FREQUENCY 0x40000022
71#define HV_X64_MSR_APIC_FREQUENCY 0x40000023
72
73/* Define the virtual APIC registers */
74#define HV_X64_MSR_EOI 0x40000070
75#define HV_X64_MSR_ICR 0x40000071
76#define HV_X64_MSR_TPR 0x40000072
77#define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073
78
79/* Define synthetic interrupt controller model specific registers. */
80#define HV_X64_MSR_SCONTROL 0x40000080
81#define HV_X64_MSR_SVERSION 0x40000081
82#define HV_X64_MSR_SIEFP 0x40000082
83#define HV_X64_MSR_SIMP 0x40000083
84#define HV_X64_MSR_EOM 0x40000084
85#define HV_X64_MSR_SIRBP 0x40000085
86#define HV_X64_MSR_SINT0 0x40000090
87#define HV_X64_MSR_SINT1 0x40000091
88#define HV_X64_MSR_SINT2 0x40000092
89#define HV_X64_MSR_SINT3 0x40000093
90#define HV_X64_MSR_SINT4 0x40000094
91#define HV_X64_MSR_SINT5 0x40000095
92#define HV_X64_MSR_SINT6 0x40000096
93#define HV_X64_MSR_SINT7 0x40000097
94#define HV_X64_MSR_SINT8 0x40000098
95#define HV_X64_MSR_SINT9 0x40000099
96#define HV_X64_MSR_SINT10 0x4000009A
97#define HV_X64_MSR_SINT11 0x4000009B
98#define HV_X64_MSR_SINT12 0x4000009C
99#define HV_X64_MSR_SINT13 0x4000009D
100#define HV_X64_MSR_SINT14 0x4000009E
101#define HV_X64_MSR_SINT15 0x4000009F
102
103/* Define synthetic interrupt controller model specific registers for nested hypervisor */
104#define HV_X64_MSR_NESTED_SCONTROL 0x40001080
105#define HV_X64_MSR_NESTED_SVERSION 0x40001081
106#define HV_X64_MSR_NESTED_SIEFP 0x40001082
107#define HV_X64_MSR_NESTED_SIMP 0x40001083
108#define HV_X64_MSR_NESTED_EOM 0x40001084
109#define HV_X64_MSR_NESTED_SINT0 0x40001090
110
111/*
112 * Synthetic Timer MSRs. Four timers per vcpu.
113 */
114#define HV_X64_MSR_STIMER0_CONFIG 0x400000B0
115#define HV_X64_MSR_STIMER0_COUNT 0x400000B1
116#define HV_X64_MSR_STIMER1_CONFIG 0x400000B2
117#define HV_X64_MSR_STIMER1_COUNT 0x400000B3
118#define HV_X64_MSR_STIMER2_CONFIG 0x400000B4
119#define HV_X64_MSR_STIMER2_COUNT 0x400000B5
120#define HV_X64_MSR_STIMER3_CONFIG 0x400000B6
121#define HV_X64_MSR_STIMER3_COUNT 0x400000B7
122
123/* Hyper-V guest idle MSR */
124#define HV_X64_MSR_GUEST_IDLE 0x400000F0
125
126/* Hyper-V guest crash notification MSR's */
127#define HV_X64_MSR_CRASH_P0 0x40000100
128#define HV_X64_MSR_CRASH_P1 0x40000101
129#define HV_X64_MSR_CRASH_P2 0x40000102
130#define HV_X64_MSR_CRASH_P3 0x40000103
131#define HV_X64_MSR_CRASH_P4 0x40000104
132#define HV_X64_MSR_CRASH_CTL 0x40000105
133
134#define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001
135#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
136#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \
137 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
138
139#define HV_X64_MSR_CRASH_PARAMS \
140 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
141
142#define HV_IPI_LOW_VECTOR 0x10
143#define HV_IPI_HIGH_VECTOR 0xff
144
145#define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001
146#define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12
147#define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \
148 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
149
150/* Hyper-V Enlightened VMCS version mask in nested features CPUID */
151#define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff
152
153#define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001
154#define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12
155
156/* Number of XMM registers used in hypercall input/output */
157#define HV_HYPERCALL_MAX_XMM_REGISTERS 6
158
159struct hv_reenlightenment_control {
160 u64 vector : 8;
161 u64 reserved1 : 8;
162 u64 enabled : 1;
163 u64 reserved2 : 15;
164 u64 target_vp : 32;
165} __packed;
166
167struct hv_tsc_emulation_status { /* HV_TSC_EMULATION_STATUS */
168 u64 inprogress : 1;
169 u64 reserved : 63;
170} __packed;
171
172struct hv_tsc_emulation_control { /* HV_TSC_INVARIANT_CONTROL */
173 u64 enabled : 1;
174 u64 reserved : 63;
175} __packed;
176
177/* TSC emulation after migration */
178#define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106
179#define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107
180#define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108
181#define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118
182#define HV_EXPOSE_INVARIANT_TSC BIT_ULL(0)
183
184#endif /* CONFIG_X86 */
185
186struct hv_output_get_partition_id {
187 u64 partition_id;
188} __packed;
189
190/* HV_CRASH_CTL_REG_CONTENTS */
191#define HV_CRASH_CTL_CRASH_NOTIFY_MSG BIT_ULL(62)
192#define HV_CRASH_CTL_CRASH_NOTIFY BIT_ULL(63)
193
194union hv_reference_tsc_msr {
195 u64 as_uint64;
196 struct {
197 u64 enable : 1;
198 u64 reserved : 11;
199 u64 pfn : 52;
200 } __packed;
201};
202
203/* The maximum number of sparse vCPU banks which can be encoded by 'struct hv_vpset' */
204#define HV_MAX_SPARSE_VCPU_BANKS (64)
205/* The number of vCPUs in one sparse bank */
206#define HV_VCPUS_PER_SPARSE_BANK (64)
207
208/*
209 * Some of Hyper-V structs do not use hv_vpset where linux uses them.
210 *
211 * struct hv_vpset is usually used as part of hypercall input. The portion
212 * that counts as "fixed size input header" vs. "variable size input header"
213 * varies per hypercall. See comments at relevant hypercall call sites as to
214 * how the "valid_bank_mask" field should be accounted.
215 */
216struct hv_vpset { /* HV_VP_SET */
217 u64 format;
218 u64 valid_bank_mask;
219 u64 bank_contents[];
220} __packed;
221
222/*
223 * Version info reported by hypervisor
224 * Changed to a union for convenience
225 */
226union hv_hypervisor_version_info {
227 struct {
228 u32 build_number;
229
230 u32 minor_version : 16;
231 u32 major_version : 16;
232
233 u32 service_pack;
234
235 u32 service_number : 24;
236 u32 service_branch : 8;
237 };
238 struct {
239 u32 eax;
240 u32 ebx;
241 u32 ecx;
242 u32 edx;
243 };
244};
245
246/* HV_CPUID_FUNCTION */
247#define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000
248#define HYPERV_CPUID_INTERFACE 0x40000001
249#define HYPERV_CPUID_VERSION 0x40000002
250#define HYPERV_CPUID_FEATURES 0x40000003
251#define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004
252#define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005
253#define HYPERV_CPUID_CPU_MANAGEMENT_FEATURES 0x40000007
254#define HYPERV_CPUID_NESTED_FEATURES 0x4000000A
255#define HYPERV_CPUID_ISOLATION_CONFIG 0x4000000C
256
257#define HYPERV_CPUID_VIRT_STACK_INTERFACE 0x40000081
258#define HYPERV_VS_INTERFACE_EAX_SIGNATURE 0x31235356 /* "VS#1" */
259
260#define HYPERV_CPUID_VIRT_STACK_PROPERTIES 0x40000082
261/* Support for the extended IOAPIC RTE format */
262#define HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE BIT(2)
263#define HYPERV_VS_PROPERTIES_EAX_CONFIDENTIAL_VMBUS_AVAILABLE BIT(3)
264
265#define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000
266#define HYPERV_CPUID_MIN 0x40000005
267#define HYPERV_CPUID_MAX 0x4000ffff
268
269/*
270 * HV_X64_HYPERVISOR_FEATURES (EAX), or
271 * HV_PARTITION_PRIVILEGE_MASK [31-0]
272 */
273#define HV_MSR_VP_RUNTIME_AVAILABLE BIT(0)
274#define HV_MSR_TIME_REF_COUNT_AVAILABLE BIT(1)
275#define HV_MSR_SYNIC_AVAILABLE BIT(2)
276#define HV_MSR_SYNTIMER_AVAILABLE BIT(3)
277#define HV_MSR_APIC_ACCESS_AVAILABLE BIT(4)
278#define HV_MSR_HYPERCALL_AVAILABLE BIT(5)
279#define HV_MSR_VP_INDEX_AVAILABLE BIT(6)
280#define HV_MSR_RESET_AVAILABLE BIT(7)
281#define HV_MSR_STAT_PAGES_AVAILABLE BIT(8)
282#define HV_MSR_REFERENCE_TSC_AVAILABLE BIT(9)
283#define HV_MSR_GUEST_IDLE_AVAILABLE BIT(10)
284#define HV_ACCESS_FREQUENCY_MSRS BIT(11)
285#define HV_ACCESS_REENLIGHTENMENT BIT(13)
286#define HV_ACCESS_TSC_INVARIANT BIT(15)
287
288/*
289 * HV_X64_HYPERVISOR_FEATURES (EBX), or
290 * HV_PARTITION_PRIVILEGE_MASK [63-32]
291 */
292#define HV_CREATE_PARTITIONS BIT(0)
293#define HV_ACCESS_PARTITION_ID BIT(1)
294#define HV_ACCESS_MEMORY_POOL BIT(2)
295#define HV_ADJUST_MESSAGE_BUFFERS BIT(3)
296#define HV_POST_MESSAGES BIT(4)
297#define HV_SIGNAL_EVENTS BIT(5)
298#define HV_CREATE_PORT BIT(6)
299#define HV_CONNECT_PORT BIT(7)
300#define HV_ACCESS_STATS BIT(8)
301#define HV_DEBUGGING BIT(11)
302#define HV_CPU_MANAGEMENT BIT(12)
303#define HV_ENABLE_EXTENDED_HYPERCALLS BIT(20)
304#define HV_ISOLATION BIT(22)
305
306#if defined(CONFIG_X86)
307/* HV_X64_HYPERVISOR_FEATURES (EDX) */
308#define HV_X64_MWAIT_AVAILABLE BIT(0)
309#define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1)
310#define HV_X64_PERF_MONITOR_AVAILABLE BIT(2)
311#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3)
312#define HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE BIT(4)
313#define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5)
314#define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8)
315#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10)
316#define HV_FEATURE_DEBUG_MSRS_AVAILABLE BIT(11)
317#define HV_FEATURE_EXT_GVA_RANGES_FLUSH BIT(14)
318/*
319 * Support for returning hypercall output block via XMM
320 * registers is available
321 */
322#define HV_X64_HYPERCALL_XMM_OUTPUT_AVAILABLE BIT(15)
323/* stimer Direct Mode is available */
324#define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19)
325
326/*
327 * Implementation recommendations. Indicates which behaviors the hypervisor
328 * recommends the OS implement for optimal performance.
329 * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits.
330 */
331/* HV_X64_ENLIGHTENMENT_INFORMATION */
332#define HV_X64_AS_SWITCH_RECOMMENDED BIT(0)
333#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1)
334#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2)
335#define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3)
336#define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4)
337#define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5)
338#define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9)
339#define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10)
340#define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11)
341#define HV_X64_HYPERV_NESTED BIT(12)
342#define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14)
343#define HV_X64_USE_MMIO_HYPERCALLS BIT(21)
344
345/*
346 * CPU management features identification.
347 * These are HYPERV_CPUID_CPU_MANAGEMENT_FEATURES.EAX bits.
348 */
349#define HV_X64_START_LOGICAL_PROCESSOR BIT(0)
350#define HV_X64_CREATE_ROOT_VIRTUAL_PROCESSOR BIT(1)
351#define HV_X64_PERFORMANCE_COUNTER_SYNC BIT(2)
352#define HV_X64_RESERVED_IDENTITY_BIT BIT(31)
353
354/*
355 * Virtual processor will never share a physical core with another virtual
356 * processor, except for virtual processors that are reported as sibling SMT
357 * threads.
358 */
359#define HV_X64_NO_NONARCH_CORESHARING BIT(18)
360
361/* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */
362#define HV_X64_NESTED_DIRECT_FLUSH BIT(17)
363#define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18)
364#define HV_X64_NESTED_MSR_BITMAP BIT(19)
365
366/* Nested features #2. These are HYPERV_CPUID_NESTED_FEATURES.EBX bits. */
367#define HV_X64_NESTED_EVMCS1_PERF_GLOBAL_CTRL BIT(0)
368
369/*
370 * This is specific to AMD and specifies that enlightened TLB flush is
371 * supported. If guest opts in to this feature, ASID invalidations only
372 * flushes gva -> hpa mapping entries. To flush the TLB entries derived
373 * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace
374 * or HvFlushGuestPhysicalAddressList).
375 */
376#define HV_X64_NESTED_ENLIGHTENED_TLB BIT(22)
377
378/* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */
379#define HV_PARAVISOR_PRESENT BIT(0)
380
381/* HYPERV_CPUID_ISOLATION_CONFIG.EBX bits. */
382#define HV_ISOLATION_TYPE GENMASK(3, 0)
383#define HV_SHARED_GPA_BOUNDARY_ACTIVE BIT(5)
384#define HV_SHARED_GPA_BOUNDARY_BITS GENMASK(11, 6)
385
386/* HYPERV_CPUID_FEATURES.ECX bits. */
387#define HV_VP_DISPATCH_INTERRUPT_INJECTION_AVAILABLE BIT(9)
388#define HV_VP_GHCB_ROOT_MAPPING_AVAILABLE BIT(10)
389
390enum hv_isolation_type {
391 HV_ISOLATION_TYPE_NONE = 0, /* HV_PARTITION_ISOLATION_TYPE_NONE */
392 HV_ISOLATION_TYPE_VBS = 1,
393 HV_ISOLATION_TYPE_SNP = 2,
394 HV_ISOLATION_TYPE_TDX = 3
395};
396
397union hv_x64_msr_hypercall_contents {
398 u64 as_uint64;
399 struct {
400 u64 enable : 1;
401 u64 reserved : 11;
402 u64 guest_physical_address : 52;
403 } __packed;
404};
405#endif /* CONFIG_X86 */
406
407#if defined(CONFIG_ARM64)
408#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(8)
409#define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(13)
410#endif /* CONFIG_ARM64 */
411
412#if defined(CONFIG_X86)
413#define HV_MAXIMUM_PROCESSORS 2048
414#elif defined(CONFIG_ARM64) /* CONFIG_X86 */
415#define HV_MAXIMUM_PROCESSORS 320
416#endif /* CONFIG_ARM64 */
417
418#define HV_MAX_VP_INDEX (HV_MAXIMUM_PROCESSORS - 1)
419#define HV_VP_INDEX_SELF ((u32)-2)
420#define HV_ANY_VP ((u32)-1)
421
422union hv_vp_assist_msr_contents { /* HV_REGISTER_VP_ASSIST_PAGE */
423 u64 as_uint64;
424 struct {
425 u64 enable : 1;
426 u64 reserved : 11;
427 u64 pfn : 52;
428 } __packed;
429};
430
431/* Declare the various hypercall operations. */
432/* HV_CALL_CODE */
433#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002
434#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003
435#define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008
436#define HVCALL_SEND_IPI 0x000b
437#define HVCALL_ENABLE_VP_VTL 0x000f
438#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013
439#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014
440#define HVCALL_SEND_IPI_EX 0x0015
441#define HVCALL_CREATE_PARTITION 0x0040
442#define HVCALL_INITIALIZE_PARTITION 0x0041
443#define HVCALL_FINALIZE_PARTITION 0x0042
444#define HVCALL_DELETE_PARTITION 0x0043
445#define HVCALL_GET_PARTITION_PROPERTY 0x0044
446#define HVCALL_SET_PARTITION_PROPERTY 0x0045
447#define HVCALL_GET_PARTITION_ID 0x0046
448#define HVCALL_DEPOSIT_MEMORY 0x0048
449#define HVCALL_WITHDRAW_MEMORY 0x0049
450#define HVCALL_MAP_GPA_PAGES 0x004b
451#define HVCALL_UNMAP_GPA_PAGES 0x004c
452#define HVCALL_INSTALL_INTERCEPT 0x004d
453#define HVCALL_CREATE_VP 0x004e
454#define HVCALL_DELETE_VP 0x004f
455#define HVCALL_GET_VP_REGISTERS 0x0050
456#define HVCALL_SET_VP_REGISTERS 0x0051
457#define HVCALL_TRANSLATE_VIRTUAL_ADDRESS 0x0052
458#define HVCALL_CLEAR_VIRTUAL_INTERRUPT 0x0056
459#define HVCALL_DELETE_PORT 0x0058
460#define HVCALL_DISCONNECT_PORT 0x005b
461#define HVCALL_POST_MESSAGE 0x005c
462#define HVCALL_SIGNAL_EVENT 0x005d
463#define HVCALL_POST_DEBUG_DATA 0x0069
464#define HVCALL_RETRIEVE_DEBUG_DATA 0x006a
465#define HVCALL_RESET_DEBUG_SESSION 0x006b
466#define HVCALL_MAP_STATS_PAGE 0x006c
467#define HVCALL_UNMAP_STATS_PAGE 0x006d
468#define HVCALL_SET_SYSTEM_PROPERTY 0x006f
469#define HVCALL_ADD_LOGICAL_PROCESSOR 0x0076
470#define HVCALL_GET_SYSTEM_PROPERTY 0x007b
471#define HVCALL_MAP_DEVICE_INTERRUPT 0x007c
472#define HVCALL_UNMAP_DEVICE_INTERRUPT 0x007d
473#define HVCALL_RETARGET_INTERRUPT 0x007e
474#define HVCALL_NOTIFY_PARTITION_EVENT 0x0087
475#define HVCALL_ENTER_SLEEP_STATE 0x0084
476#define HVCALL_NOTIFY_PORT_RING_EMPTY 0x008b
477#define HVCALL_REGISTER_INTERCEPT_RESULT 0x0091
478#define HVCALL_ASSERT_VIRTUAL_INTERRUPT 0x0094
479#define HVCALL_CREATE_PORT 0x0095
480#define HVCALL_CONNECT_PORT 0x0096
481#define HVCALL_START_VP 0x0099
482#define HVCALL_GET_VP_INDEX_FROM_APIC_ID 0x009a
483#define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE 0x00af
484#define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_LIST 0x00b0
485#define HVCALL_SIGNAL_EVENT_DIRECT 0x00c0
486#define HVCALL_POST_MESSAGE_DIRECT 0x00c1
487#define HVCALL_DISPATCH_VP 0x00c2
488#define HVCALL_GET_GPA_PAGES_ACCESS_STATES 0x00c9
489#define HVCALL_ACQUIRE_SPARSE_SPA_PAGE_HOST_ACCESS 0x00d7
490#define HVCALL_RELEASE_SPARSE_SPA_PAGE_HOST_ACCESS 0x00d8
491#define HVCALL_MODIFY_SPARSE_GPA_PAGE_HOST_VISIBILITY 0x00db
492#define HVCALL_MAP_VP_STATE_PAGE 0x00e1
493#define HVCALL_UNMAP_VP_STATE_PAGE 0x00e2
494#define HVCALL_GET_VP_STATE 0x00e3
495#define HVCALL_SET_VP_STATE 0x00e4
496#define HVCALL_GET_VP_CPUID_VALUES 0x00f4
497#define HVCALL_GET_PARTITION_PROPERTY_EX 0x0101
498#define HVCALL_MMIO_READ 0x0106
499#define HVCALL_MMIO_WRITE 0x0107
500#define HVCALL_DISABLE_HYP_EX 0x010f
501#define HVCALL_MAP_STATS_PAGE2 0x0131
502
503/* HV_HYPERCALL_INPUT */
504#define HV_HYPERCALL_RESULT_MASK GENMASK_ULL(15, 0)
505#define HV_HYPERCALL_FAST_BIT BIT(16)
506#define HV_HYPERCALL_VARHEAD_OFFSET 17
507#define HV_HYPERCALL_VARHEAD_MASK GENMASK_ULL(26, 17)
508#define HV_HYPERCALL_RSVD0_MASK GENMASK_ULL(31, 27)
509#define HV_HYPERCALL_NESTED BIT_ULL(31)
510#define HV_HYPERCALL_REP_COMP_OFFSET 32
511#define HV_HYPERCALL_REP_COMP_1 BIT_ULL(32)
512#define HV_HYPERCALL_REP_COMP_MASK GENMASK_ULL(43, 32)
513#define HV_HYPERCALL_RSVD1_MASK GENMASK_ULL(47, 44)
514#define HV_HYPERCALL_REP_START_OFFSET 48
515#define HV_HYPERCALL_REP_START_MASK GENMASK_ULL(59, 48)
516#define HV_HYPERCALL_RSVD2_MASK GENMASK_ULL(63, 60)
517#define HV_HYPERCALL_RSVD_MASK (HV_HYPERCALL_RSVD0_MASK | \
518 HV_HYPERCALL_RSVD1_MASK | \
519 HV_HYPERCALL_RSVD2_MASK)
520
521/* HvFlushGuestPhysicalAddressSpace hypercalls */
522struct hv_guest_mapping_flush {
523 u64 address_space;
524 u64 flags;
525} __packed;
526
527/*
528 * HV_MAX_FLUSH_PAGES = "additional_pages" + 1. It's limited
529 * by the bitwidth of "additional_pages" in union hv_gpa_page_range.
530 */
531#define HV_MAX_FLUSH_PAGES (2048)
532#define HV_GPA_PAGE_RANGE_PAGE_SIZE_2MB 0
533#define HV_GPA_PAGE_RANGE_PAGE_SIZE_1GB 1
534
535#define HV_FLUSH_ALL_PROCESSORS BIT(0)
536#define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1)
537#define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2)
538#define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3)
539
540/* HvFlushGuestPhysicalAddressList, HvExtCallMemoryHeatHint hypercall */
541union hv_gpa_page_range {
542 u64 address_space;
543 struct {
544 u64 additional_pages : 11;
545 u64 largepage : 1;
546 u64 basepfn : 52;
547 } page;
548 struct {
549 u64 reserved : 12;
550 u64 page_size : 1;
551 u64 reserved1 : 8;
552 u64 base_large_pfn : 43;
553 };
554};
555
556/*
557 * All input flush parameters should be in single page. The max flush
558 * count is equal with how many entries of union hv_gpa_page_range can
559 * be populated into the input parameter page.
560 */
561#define HV_MAX_FLUSH_REP_COUNT ((HV_HYP_PAGE_SIZE - 2 * sizeof(u64)) / \
562 sizeof(union hv_gpa_page_range))
563
564struct hv_guest_mapping_flush_list {
565 u64 address_space;
566 u64 flags;
567 union hv_gpa_page_range gpa_list[HV_MAX_FLUSH_REP_COUNT];
568};
569
570struct hv_tlb_flush { /* HV_INPUT_FLUSH_VIRTUAL_ADDRESS_LIST */
571 u64 address_space;
572 u64 flags;
573 u64 processor_mask;
574 u64 gva_list[];
575} __packed;
576
577/* HvFlushVirtualAddressSpaceEx, HvFlushVirtualAddressListEx hypercalls */
578struct hv_tlb_flush_ex {
579 u64 address_space;
580 u64 flags;
581 __TRAILING_OVERLAP(struct hv_vpset, hv_vp_set, bank_contents, __packed,
582 u64 gva_list[];
583 );
584} __packed;
585static_assert(offsetof(struct hv_tlb_flush_ex, hv_vp_set.bank_contents) ==
586 offsetof(struct hv_tlb_flush_ex, gva_list));
587
588struct ms_hyperv_tsc_page { /* HV_REFERENCE_TSC_PAGE */
589 volatile u32 tsc_sequence;
590 u32 reserved1;
591 volatile u64 tsc_scale;
592 volatile s64 tsc_offset;
593} __packed;
594
595/* Define the number of synthetic interrupt sources. */
596#define HV_SYNIC_SINT_COUNT (16)
597
598/* Define the expected SynIC version. */
599#define HV_SYNIC_VERSION_1 (0x1)
600/* Valid SynIC vectors are 16-255. */
601#define HV_SYNIC_FIRST_VALID_VECTOR (16)
602
603#define HV_SYNIC_CONTROL_ENABLE (1ULL << 0)
604#define HV_SYNIC_SIMP_ENABLE (1ULL << 0)
605#define HV_SYNIC_SIEFP_ENABLE (1ULL << 0)
606#define HV_SYNIC_SINT_MASKED (1ULL << 16)
607#define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17)
608#define HV_SYNIC_SINT_VECTOR_MASK (0xFF)
609
610/* Hyper-V defined statically assigned SINTs */
611#define HV_SYNIC_INTERCEPTION_SINT_INDEX 0x00000000
612#define HV_SYNIC_IOMMU_FAULT_SINT_INDEX 0x00000001
613#define HV_SYNIC_VMBUS_SINT_INDEX 0x00000002
614#define HV_SYNIC_FIRST_UNUSED_SINT_INDEX 0x00000005
615
616/* mshv assigned SINT for doorbell */
617#define HV_SYNIC_DOORBELL_SINT_INDEX HV_SYNIC_FIRST_UNUSED_SINT_INDEX
618
619enum hv_interrupt_type {
620 HV_X64_INTERRUPT_TYPE_FIXED = 0x0000,
621 HV_X64_INTERRUPT_TYPE_LOWESTPRIORITY = 0x0001,
622 HV_X64_INTERRUPT_TYPE_SMI = 0x0002,
623 HV_X64_INTERRUPT_TYPE_REMOTEREAD = 0x0003,
624 HV_X64_INTERRUPT_TYPE_NMI = 0x0004,
625 HV_X64_INTERRUPT_TYPE_INIT = 0x0005,
626 HV_X64_INTERRUPT_TYPE_SIPI = 0x0006,
627 HV_X64_INTERRUPT_TYPE_EXTINT = 0x0007,
628 HV_X64_INTERRUPT_TYPE_LOCALINT0 = 0x0008,
629 HV_X64_INTERRUPT_TYPE_LOCALINT1 = 0x0009,
630 HV_X64_INTERRUPT_TYPE_MAXIMUM = 0x000A,
631};
632
633/* Define synthetic interrupt source. */
634union hv_synic_sint {
635 u64 as_uint64;
636 struct {
637 u64 vector : 8;
638 u64 reserved1 : 8;
639 u64 masked : 1;
640 u64 auto_eoi : 1;
641 u64 polling : 1;
642 u64 as_intercept : 1;
643 u64 proxy : 1;
644 u64 reserved2 : 43;
645 } __packed;
646};
647
648union hv_x64_xsave_xfem_register {
649 u64 as_uint64;
650 struct {
651 u32 low_uint32;
652 u32 high_uint32;
653 } __packed;
654 struct {
655 u64 legacy_x87 : 1;
656 u64 legacy_sse : 1;
657 u64 avx : 1;
658 u64 mpx_bndreg : 1;
659 u64 mpx_bndcsr : 1;
660 u64 avx_512_op_mask : 1;
661 u64 avx_512_zmmhi : 1;
662 u64 avx_512_zmm16_31 : 1;
663 u64 rsvd8_9 : 2;
664 u64 pasid : 1;
665 u64 cet_u : 1;
666 u64 cet_s : 1;
667 u64 rsvd13_16 : 4;
668 u64 xtile_cfg : 1;
669 u64 xtile_data : 1;
670 u64 rsvd19_63 : 45;
671 } __packed;
672};
673
674/* Synthetic timer configuration */
675union hv_stimer_config { /* HV_X64_MSR_STIMER_CONFIG_CONTENTS */
676 u64 as_uint64;
677 struct {
678 u64 enable : 1;
679 u64 periodic : 1;
680 u64 lazy : 1;
681 u64 auto_enable : 1;
682 u64 apic_vector : 8;
683 u64 direct_mode : 1;
684 u64 reserved_z0 : 3;
685 u64 sintx : 4;
686 u64 reserved_z1 : 44;
687 } __packed;
688};
689
690/* Define the number of synthetic timers */
691#define HV_SYNIC_STIMER_COUNT (4)
692
693/* Define port identifier type. */
694union hv_port_id {
695 u32 asu32;
696 struct {
697 u32 id : 24;
698 u32 reserved : 8;
699 } __packed u;
700};
701
702#define HV_MESSAGE_SIZE (256)
703#define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240)
704#define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30)
705
706/* Define hypervisor message types. */
707enum hv_message_type {
708 HVMSG_NONE = 0x00000000,
709
710 /* Memory access messages. */
711 HVMSG_UNMAPPED_GPA = 0x80000000,
712 HVMSG_GPA_INTERCEPT = 0x80000001,
713
714 /* Timer notification messages. */
715 HVMSG_TIMER_EXPIRED = 0x80000010,
716
717 /* Error messages. */
718 HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020,
719 HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021,
720 HVMSG_UNSUPPORTED_FEATURE = 0x80000022,
721
722 /*
723 * Opaque intercept message. The original intercept message is only
724 * accessible from the mapped intercept message page.
725 */
726 HVMSG_OPAQUE_INTERCEPT = 0x8000003F,
727
728 /* Trace buffer complete messages. */
729 HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040,
730
731 /* Hypercall intercept */
732 HVMSG_HYPERCALL_INTERCEPT = 0x80000050,
733
734 /* SynIC intercepts */
735 HVMSG_SYNIC_EVENT_INTERCEPT = 0x80000060,
736 HVMSG_SYNIC_SINT_INTERCEPT = 0x80000061,
737 HVMSG_SYNIC_SINT_DELIVERABLE = 0x80000062,
738
739 /* Async call completion intercept */
740 HVMSG_ASYNC_CALL_COMPLETION = 0x80000070,
741
742 /* Root scheduler messages */
743 HVMSG_SCHEDULER_VP_SIGNAL_BITSET = 0x80000100,
744 HVMSG_SCHEDULER_VP_SIGNAL_PAIR = 0x80000101,
745
746 /* Platform-specific processor intercept messages. */
747 HVMSG_X64_IO_PORT_INTERCEPT = 0x80010000,
748 HVMSG_X64_MSR_INTERCEPT = 0x80010001,
749 HVMSG_X64_CPUID_INTERCEPT = 0x80010002,
750 HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003,
751 HVMSG_X64_APIC_EOI = 0x80010004,
752 HVMSG_X64_LEGACY_FP_ERROR = 0x80010005,
753 HVMSG_X64_IOMMU_PRQ = 0x80010006,
754 HVMSG_X64_HALT = 0x80010007,
755 HVMSG_X64_INTERRUPTION_DELIVERABLE = 0x80010008,
756 HVMSG_X64_SIPI_INTERCEPT = 0x80010009,
757};
758
759/* Define the format of the SIMP register */
760union hv_synic_simp {
761 u64 as_uint64;
762 struct {
763 u64 simp_enabled : 1;
764 u64 preserved : 11;
765 u64 base_simp_gpa : 52;
766 } __packed;
767};
768
769union hv_message_flags {
770 u8 asu8;
771 struct {
772 u8 msg_pending : 1;
773 u8 reserved : 7;
774 } __packed;
775};
776
777struct hv_message_header {
778 u32 message_type;
779 u8 payload_size;
780 union hv_message_flags message_flags;
781 u8 reserved[2];
782 union {
783 u64 sender;
784 union hv_port_id port;
785 };
786} __packed;
787
788/*
789 * Message format for notifications delivered via
790 * intercept message(as_intercept=1)
791 */
792struct hv_notification_message_payload {
793 u32 sint_index;
794} __packed;
795
796struct hv_message {
797 struct hv_message_header header;
798 union {
799 u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
800 } u;
801} __packed;
802
803/* Define the synthetic interrupt message page layout. */
804struct hv_message_page {
805 struct hv_message sint_message[HV_SYNIC_SINT_COUNT];
806} __packed;
807
808/* Define timer message payload structure. */
809struct hv_timer_message_payload {
810 u32 timer_index;
811 u32 reserved;
812 u64 expiration_time; /* When the timer expired */
813 u64 delivery_time; /* When the message was delivered */
814} __packed;
815
816struct hv_x64_segment_register {
817 u64 base;
818 u32 limit;
819 u16 selector;
820 union {
821 struct {
822 u16 segment_type : 4;
823 u16 non_system_segment : 1;
824 u16 descriptor_privilege_level : 2;
825 u16 present : 1;
826 u16 reserved : 4;
827 u16 available : 1;
828 u16 _long : 1;
829 u16 _default : 1;
830 u16 granularity : 1;
831 } __packed;
832 u16 attributes;
833 };
834} __packed;
835
836struct hv_x64_table_register {
837 u16 pad[3];
838 u16 limit;
839 u64 base;
840} __packed;
841
842#define HV_NORMAL_VTL 0
843
844union hv_input_vtl {
845 u8 as_uint8;
846 struct {
847 u8 target_vtl : 4;
848 u8 use_target_vtl : 1;
849 u8 reserved_z : 3;
850 };
851} __packed;
852
853struct hv_init_vp_context {
854 u64 rip;
855 u64 rsp;
856 u64 rflags;
857
858 struct hv_x64_segment_register cs;
859 struct hv_x64_segment_register ds;
860 struct hv_x64_segment_register es;
861 struct hv_x64_segment_register fs;
862 struct hv_x64_segment_register gs;
863 struct hv_x64_segment_register ss;
864 struct hv_x64_segment_register tr;
865 struct hv_x64_segment_register ldtr;
866
867 struct hv_x64_table_register idtr;
868 struct hv_x64_table_register gdtr;
869
870 u64 efer;
871 u64 cr0;
872 u64 cr3;
873 u64 cr4;
874 u64 msr_cr_pat;
875} __packed;
876
877struct hv_enable_vp_vtl {
878 u64 partition_id;
879 u32 vp_index;
880 union hv_input_vtl target_vtl;
881 u8 mbz0;
882 u16 mbz1;
883 struct hv_init_vp_context vp_context;
884} __packed;
885
886struct hv_get_vp_from_apic_id_in {
887 u64 partition_id;
888 union hv_input_vtl target_vtl;
889 u8 res[7];
890 u32 apic_ids[];
891} __packed;
892
893union hv_register_vsm_partition_config {
894 u64 as_uint64;
895 struct {
896 u64 enable_vtl_protection : 1;
897 u64 default_vtl_protection_mask : 4;
898 u64 zero_memory_on_reset : 1;
899 u64 deny_lower_vtl_startup : 1;
900 u64 intercept_acceptance : 1;
901 u64 intercept_enable_vtl_protection : 1;
902 u64 intercept_vp_startup : 1;
903 u64 intercept_cpuid_unimplemented : 1;
904 u64 intercept_unrecoverable_exception : 1;
905 u64 intercept_page : 1;
906 u64 mbz : 51;
907 } __packed;
908};
909
910union hv_register_vsm_capabilities {
911 u64 as_uint64;
912 struct {
913 u64 dr6_shared: 1;
914 u64 mbec_vtl_mask: 16;
915 u64 deny_lower_vtl_startup: 1;
916 u64 supervisor_shadow_stack: 1;
917 u64 hardware_hvpt_available: 1;
918 u64 software_hvpt_available: 1;
919 u64 hardware_hvpt_range_bits: 6;
920 u64 intercept_page_available: 1;
921 u64 return_action_available: 1;
922 u64 reserved: 35;
923 } __packed;
924};
925
926union hv_register_vsm_page_offsets {
927 struct {
928 u64 vtl_call_offset : 12;
929 u64 vtl_return_offset : 12;
930 u64 reserved_mbz : 40;
931 } __packed;
932 u64 as_uint64;
933};
934
935struct hv_nested_enlightenments_control {
936 struct {
937 u32 directhypercall : 1;
938 u32 reserved : 31;
939 } __packed features;
940 struct {
941 u32 inter_partition_comm : 1;
942 u32 reserved : 31;
943 } __packed hypercall_controls;
944} __packed;
945
946/* Define virtual processor assist page structure. */
947struct hv_vp_assist_page {
948 u32 apic_assist;
949 u32 reserved1;
950 u32 vtl_entry_reason;
951 u32 vtl_reserved;
952 u64 vtl_ret_x64rax;
953 u64 vtl_ret_x64rcx;
954 struct hv_nested_enlightenments_control nested_control;
955 u8 enlighten_vmentry;
956 u8 reserved2[7];
957 u64 current_nested_vmcs;
958 u8 synthetic_time_unhalted_timer_expired;
959 u8 reserved3[7];
960 u8 virtualization_fault_information[40];
961 u8 reserved4[8];
962 u8 intercept_message[256];
963 u8 vtl_ret_actions[256];
964} __packed;
965
966enum hv_register_name {
967 /* Suspend Registers */
968 HV_REGISTER_EXPLICIT_SUSPEND = 0x00000000,
969 HV_REGISTER_INTERCEPT_SUSPEND = 0x00000001,
970 HV_REGISTER_DISPATCH_SUSPEND = 0x00000003,
971
972 /* Version - 128-bit result same as CPUID 0x40000002 */
973 HV_REGISTER_HYPERVISOR_VERSION = 0x00000100,
974
975 /* Feature Access (registers are 128 bits) - same as CPUID 0x40000003 - 0x4000000B */
976 HV_REGISTER_PRIVILEGES_AND_FEATURES_INFO = 0x00000200,
977 HV_REGISTER_FEATURES_INFO = 0x00000201,
978 HV_REGISTER_IMPLEMENTATION_LIMITS_INFO = 0x00000202,
979 HV_REGISTER_HARDWARE_FEATURES_INFO = 0x00000203,
980 HV_REGISTER_CPU_MANAGEMENT_FEATURES_INFO = 0x00000204,
981 HV_REGISTER_SVM_FEATURES_INFO = 0x00000205,
982 HV_REGISTER_SKIP_LEVEL_FEATURES_INFO = 0x00000206,
983 HV_REGISTER_NESTED_VIRT_FEATURES_INFO = 0x00000207,
984 HV_REGISTER_IPT_FEATURES_INFO = 0x00000208,
985
986 /* Guest Crash Registers */
987 HV_REGISTER_GUEST_CRASH_P0 = 0x00000210,
988 HV_REGISTER_GUEST_CRASH_P1 = 0x00000211,
989 HV_REGISTER_GUEST_CRASH_P2 = 0x00000212,
990 HV_REGISTER_GUEST_CRASH_P3 = 0x00000213,
991 HV_REGISTER_GUEST_CRASH_P4 = 0x00000214,
992 HV_REGISTER_GUEST_CRASH_CTL = 0x00000215,
993
994 /* Misc */
995 HV_REGISTER_VP_RUNTIME = 0x00090000,
996 HV_REGISTER_GUEST_OS_ID = 0x00090002,
997 HV_REGISTER_VP_INDEX = 0x00090003,
998 HV_REGISTER_TIME_REF_COUNT = 0x00090004,
999 HV_REGISTER_CPU_MANAGEMENT_VERSION = 0x00090007,
1000 HV_REGISTER_VP_ASSIST_PAGE = 0x00090013,
1001 HV_REGISTER_VP_ROOT_SIGNAL_COUNT = 0x00090014,
1002 HV_REGISTER_REFERENCE_TSC = 0x00090017,
1003
1004 /* Hypervisor-defined Registers (Synic) */
1005 HV_REGISTER_SINT0 = 0x000A0000,
1006 HV_REGISTER_SINT1 = 0x000A0001,
1007 HV_REGISTER_SINT2 = 0x000A0002,
1008 HV_REGISTER_SINT3 = 0x000A0003,
1009 HV_REGISTER_SINT4 = 0x000A0004,
1010 HV_REGISTER_SINT5 = 0x000A0005,
1011 HV_REGISTER_SINT6 = 0x000A0006,
1012 HV_REGISTER_SINT7 = 0x000A0007,
1013 HV_REGISTER_SINT8 = 0x000A0008,
1014 HV_REGISTER_SINT9 = 0x000A0009,
1015 HV_REGISTER_SINT10 = 0x000A000A,
1016 HV_REGISTER_SINT11 = 0x000A000B,
1017 HV_REGISTER_SINT12 = 0x000A000C,
1018 HV_REGISTER_SINT13 = 0x000A000D,
1019 HV_REGISTER_SINT14 = 0x000A000E,
1020 HV_REGISTER_SINT15 = 0x000A000F,
1021 HV_REGISTER_SCONTROL = 0x000A0010,
1022 HV_REGISTER_SVERSION = 0x000A0011,
1023 HV_REGISTER_SIEFP = 0x000A0012,
1024 HV_REGISTER_SIMP = 0x000A0013,
1025 HV_REGISTER_EOM = 0x000A0014,
1026 HV_REGISTER_SIRBP = 0x000A0015,
1027
1028 HV_REGISTER_NESTED_SINT0 = 0x000A1000,
1029 HV_REGISTER_NESTED_SINT1 = 0x000A1001,
1030 HV_REGISTER_NESTED_SINT2 = 0x000A1002,
1031 HV_REGISTER_NESTED_SINT3 = 0x000A1003,
1032 HV_REGISTER_NESTED_SINT4 = 0x000A1004,
1033 HV_REGISTER_NESTED_SINT5 = 0x000A1005,
1034 HV_REGISTER_NESTED_SINT6 = 0x000A1006,
1035 HV_REGISTER_NESTED_SINT7 = 0x000A1007,
1036 HV_REGISTER_NESTED_SINT8 = 0x000A1008,
1037 HV_REGISTER_NESTED_SINT9 = 0x000A1009,
1038 HV_REGISTER_NESTED_SINT10 = 0x000A100A,
1039 HV_REGISTER_NESTED_SINT11 = 0x000A100B,
1040 HV_REGISTER_NESTED_SINT12 = 0x000A100C,
1041 HV_REGISTER_NESTED_SINT13 = 0x000A100D,
1042 HV_REGISTER_NESTED_SINT14 = 0x000A100E,
1043 HV_REGISTER_NESTED_SINT15 = 0x000A100F,
1044 HV_REGISTER_NESTED_SCONTROL = 0x000A1010,
1045 HV_REGISTER_NESTED_SVERSION = 0x000A1011,
1046 HV_REGISTER_NESTED_SIFP = 0x000A1012,
1047 HV_REGISTER_NESTED_SIPP = 0x000A1013,
1048 HV_REGISTER_NESTED_EOM = 0x000A1014,
1049 HV_REGISTER_NESTED_SIRBP = 0x000a1015,
1050
1051 /* Hypervisor-defined Registers (Synthetic Timers) */
1052 HV_REGISTER_STIMER0_CONFIG = 0x000B0000,
1053 HV_REGISTER_STIMER0_COUNT = 0x000B0001,
1054
1055 /* VSM */
1056 HV_REGISTER_VSM_VP_STATUS = 0x000D0003,
1057
1058 /* Synthetic VSM registers */
1059 HV_REGISTER_VSM_CODE_PAGE_OFFSETS = 0x000D0002,
1060 HV_REGISTER_VSM_CAPABILITIES = 0x000D0006,
1061 HV_REGISTER_VSM_PARTITION_CONFIG = 0x000D0007,
1062
1063#if defined(CONFIG_X86)
1064 /* X64 Debug Registers */
1065 HV_X64_REGISTER_DR0 = 0x00050000,
1066 HV_X64_REGISTER_DR1 = 0x00050001,
1067 HV_X64_REGISTER_DR2 = 0x00050002,
1068 HV_X64_REGISTER_DR3 = 0x00050003,
1069 HV_X64_REGISTER_DR6 = 0x00050004,
1070 HV_X64_REGISTER_DR7 = 0x00050005,
1071
1072 /* X64 Cache control MSRs */
1073 HV_X64_REGISTER_MSR_MTRR_CAP = 0x0008000D,
1074 HV_X64_REGISTER_MSR_MTRR_DEF_TYPE = 0x0008000E,
1075 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE0 = 0x00080010,
1076 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE1 = 0x00080011,
1077 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE2 = 0x00080012,
1078 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE3 = 0x00080013,
1079 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE4 = 0x00080014,
1080 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE5 = 0x00080015,
1081 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE6 = 0x00080016,
1082 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE7 = 0x00080017,
1083 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE8 = 0x00080018,
1084 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE9 = 0x00080019,
1085 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEA = 0x0008001A,
1086 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEB = 0x0008001B,
1087 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEC = 0x0008001C,
1088 HV_X64_REGISTER_MSR_MTRR_PHYS_BASED = 0x0008001D,
1089 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEE = 0x0008001E,
1090 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEF = 0x0008001F,
1091 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK0 = 0x00080040,
1092 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK1 = 0x00080041,
1093 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK2 = 0x00080042,
1094 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK3 = 0x00080043,
1095 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK4 = 0x00080044,
1096 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK5 = 0x00080045,
1097 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK6 = 0x00080046,
1098 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK7 = 0x00080047,
1099 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK8 = 0x00080048,
1100 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK9 = 0x00080049,
1101 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKA = 0x0008004A,
1102 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKB = 0x0008004B,
1103 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKC = 0x0008004C,
1104 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKD = 0x0008004D,
1105 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKE = 0x0008004E,
1106 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKF = 0x0008004F,
1107 HV_X64_REGISTER_MSR_MTRR_FIX64K00000 = 0x00080070,
1108 HV_X64_REGISTER_MSR_MTRR_FIX16K80000 = 0x00080071,
1109 HV_X64_REGISTER_MSR_MTRR_FIX16KA0000 = 0x00080072,
1110 HV_X64_REGISTER_MSR_MTRR_FIX4KC0000 = 0x00080073,
1111 HV_X64_REGISTER_MSR_MTRR_FIX4KC8000 = 0x00080074,
1112 HV_X64_REGISTER_MSR_MTRR_FIX4KD0000 = 0x00080075,
1113 HV_X64_REGISTER_MSR_MTRR_FIX4KD8000 = 0x00080076,
1114 HV_X64_REGISTER_MSR_MTRR_FIX4KE0000 = 0x00080077,
1115 HV_X64_REGISTER_MSR_MTRR_FIX4KE8000 = 0x00080078,
1116 HV_X64_REGISTER_MSR_MTRR_FIX4KF0000 = 0x00080079,
1117 HV_X64_REGISTER_MSR_MTRR_FIX4KF8000 = 0x0008007A,
1118
1119 HV_X64_REGISTER_REG_PAGE = 0x0009001C,
1120#endif
1121};
1122
1123/*
1124 * Arch compatibility regs for use with hv_set/get_register
1125 */
1126#if defined(CONFIG_X86)
1127
1128/*
1129 * To support arch-generic code calling hv_set/get_register:
1130 * - On x86, HV_MSR_ indicates an MSR accessed via rdmsrq/wrmsrq
1131 * - On ARM, HV_MSR_ indicates a VP register accessed via hypercall
1132 */
1133#define HV_MSR_CRASH_P0 (HV_X64_MSR_CRASH_P0)
1134#define HV_MSR_CRASH_P1 (HV_X64_MSR_CRASH_P1)
1135#define HV_MSR_CRASH_P2 (HV_X64_MSR_CRASH_P2)
1136#define HV_MSR_CRASH_P3 (HV_X64_MSR_CRASH_P3)
1137#define HV_MSR_CRASH_P4 (HV_X64_MSR_CRASH_P4)
1138#define HV_MSR_CRASH_CTL (HV_X64_MSR_CRASH_CTL)
1139
1140#define HV_MSR_VP_INDEX (HV_X64_MSR_VP_INDEX)
1141#define HV_MSR_TIME_REF_COUNT (HV_X64_MSR_TIME_REF_COUNT)
1142#define HV_MSR_REFERENCE_TSC (HV_X64_MSR_REFERENCE_TSC)
1143
1144#define HV_MSR_SINT0 (HV_X64_MSR_SINT0)
1145#define HV_MSR_SVERSION (HV_X64_MSR_SVERSION)
1146#define HV_MSR_SCONTROL (HV_X64_MSR_SCONTROL)
1147#define HV_MSR_SIEFP (HV_X64_MSR_SIEFP)
1148#define HV_MSR_SIMP (HV_X64_MSR_SIMP)
1149#define HV_MSR_EOM (HV_X64_MSR_EOM)
1150#define HV_MSR_SIRBP (HV_X64_MSR_SIRBP)
1151
1152#define HV_MSR_NESTED_SCONTROL (HV_X64_MSR_NESTED_SCONTROL)
1153#define HV_MSR_NESTED_SVERSION (HV_X64_MSR_NESTED_SVERSION)
1154#define HV_MSR_NESTED_SIEFP (HV_X64_MSR_NESTED_SIEFP)
1155#define HV_MSR_NESTED_SIMP (HV_X64_MSR_NESTED_SIMP)
1156#define HV_MSR_NESTED_EOM (HV_X64_MSR_NESTED_EOM)
1157#define HV_MSR_NESTED_SINT0 (HV_X64_MSR_NESTED_SINT0)
1158
1159#define HV_MSR_STIMER0_CONFIG (HV_X64_MSR_STIMER0_CONFIG)
1160#define HV_MSR_STIMER0_COUNT (HV_X64_MSR_STIMER0_COUNT)
1161
1162#elif defined(CONFIG_ARM64) /* CONFIG_X86 */
1163
1164#define HV_MSR_CRASH_P0 (HV_REGISTER_GUEST_CRASH_P0)
1165#define HV_MSR_CRASH_P1 (HV_REGISTER_GUEST_CRASH_P1)
1166#define HV_MSR_CRASH_P2 (HV_REGISTER_GUEST_CRASH_P2)
1167#define HV_MSR_CRASH_P3 (HV_REGISTER_GUEST_CRASH_P3)
1168#define HV_MSR_CRASH_P4 (HV_REGISTER_GUEST_CRASH_P4)
1169#define HV_MSR_CRASH_CTL (HV_REGISTER_GUEST_CRASH_CTL)
1170
1171#define HV_MSR_VP_INDEX (HV_REGISTER_VP_INDEX)
1172#define HV_MSR_TIME_REF_COUNT (HV_REGISTER_TIME_REF_COUNT)
1173#define HV_MSR_REFERENCE_TSC (HV_REGISTER_REFERENCE_TSC)
1174
1175#define HV_MSR_SINT0 (HV_REGISTER_SINT0)
1176#define HV_MSR_SCONTROL (HV_REGISTER_SCONTROL)
1177#define HV_MSR_SIEFP (HV_REGISTER_SIEFP)
1178#define HV_MSR_SIMP (HV_REGISTER_SIMP)
1179#define HV_MSR_EOM (HV_REGISTER_EOM)
1180#define HV_MSR_SIRBP (HV_REGISTER_SIRBP)
1181
1182#define HV_MSR_STIMER0_CONFIG (HV_REGISTER_STIMER0_CONFIG)
1183#define HV_MSR_STIMER0_COUNT (HV_REGISTER_STIMER0_COUNT)
1184
1185#endif /* CONFIG_ARM64 */
1186
1187union hv_explicit_suspend_register {
1188 u64 as_uint64;
1189 struct {
1190 u64 suspended : 1;
1191 u64 reserved : 63;
1192 } __packed;
1193};
1194
1195union hv_intercept_suspend_register {
1196 u64 as_uint64;
1197 struct {
1198 u64 suspended : 1;
1199 u64 reserved : 63;
1200 } __packed;
1201};
1202
1203union hv_dispatch_suspend_register {
1204 u64 as_uint64;
1205 struct {
1206 u64 suspended : 1;
1207 u64 reserved : 63;
1208 } __packed;
1209};
1210
1211union hv_arm64_pending_interruption_register {
1212 u64 as_uint64;
1213 struct {
1214 u64 interruption_pending : 1;
1215 u64 interruption_type: 1;
1216 u64 reserved : 30;
1217 u64 error_code : 32;
1218 } __packed;
1219};
1220
1221union hv_arm64_interrupt_state_register {
1222 u64 as_uint64;
1223 struct {
1224 u64 interrupt_shadow : 1;
1225 u64 reserved : 63;
1226 } __packed;
1227};
1228
1229union hv_arm64_pending_synthetic_exception_event {
1230 u64 as_uint64[2];
1231 struct {
1232 u8 event_pending : 1;
1233 u8 event_type : 3;
1234 u8 reserved : 4;
1235 u8 rsvd[3];
1236 u32 exception_type;
1237 u64 context;
1238 } __packed;
1239};
1240
1241union hv_x64_interrupt_state_register {
1242 u64 as_uint64;
1243 struct {
1244 u64 interrupt_shadow : 1;
1245 u64 nmi_masked : 1;
1246 u64 reserved : 62;
1247 } __packed;
1248};
1249
1250union hv_x64_pending_interruption_register {
1251 u64 as_uint64;
1252 struct {
1253 u32 interruption_pending : 1;
1254 u32 interruption_type : 3;
1255 u32 deliver_error_code : 1;
1256 u32 instruction_length : 4;
1257 u32 nested_event : 1;
1258 u32 reserved : 6;
1259 u32 interruption_vector : 16;
1260 u32 error_code;
1261 } __packed;
1262};
1263
1264union hv_register_value {
1265 struct hv_u128 reg128;
1266 u64 reg64;
1267 u32 reg32;
1268 u16 reg16;
1269 u8 reg8;
1270
1271 struct hv_x64_segment_register segment;
1272 struct hv_x64_table_register table;
1273 union hv_explicit_suspend_register explicit_suspend;
1274 union hv_intercept_suspend_register intercept_suspend;
1275 union hv_dispatch_suspend_register dispatch_suspend;
1276#ifdef CONFIG_ARM64
1277 union hv_arm64_interrupt_state_register interrupt_state;
1278 union hv_arm64_pending_interruption_register pending_interruption;
1279#endif
1280#ifdef CONFIG_X86
1281 union hv_x64_interrupt_state_register interrupt_state;
1282 union hv_x64_pending_interruption_register pending_interruption;
1283#endif
1284 union hv_arm64_pending_synthetic_exception_event pending_synthetic_exception_event;
1285};
1286
1287/* NOTE: Linux helper struct - NOT from Hyper-V code. */
1288struct hv_output_get_vp_registers {
1289 DECLARE_FLEX_ARRAY(union hv_register_value, values);
1290};
1291
1292#if defined(CONFIG_ARM64)
1293/* HvGetVpRegisters returns an array of these output elements */
1294struct hv_get_vp_registers_output {
1295 union {
1296 struct {
1297 u32 a;
1298 u32 b;
1299 u32 c;
1300 u32 d;
1301 } as32 __packed;
1302 struct {
1303 u64 low;
1304 u64 high;
1305 } as64 __packed;
1306 };
1307};
1308
1309#endif /* CONFIG_ARM64 */
1310
1311struct hv_register_assoc {
1312 u32 name; /* enum hv_register_name */
1313 u32 reserved1;
1314 u64 reserved2;
1315 union hv_register_value value;
1316} __packed;
1317
1318struct hv_input_get_vp_registers {
1319 u64 partition_id;
1320 u32 vp_index;
1321 union hv_input_vtl input_vtl;
1322 u8 rsvd_z8;
1323 u16 rsvd_z16;
1324 u32 names[];
1325} __packed;
1326
1327struct hv_input_set_vp_registers {
1328 u64 partition_id;
1329 u32 vp_index;
1330 union hv_input_vtl input_vtl;
1331 u8 rsvd_z8;
1332 u16 rsvd_z16;
1333 struct hv_register_assoc elements[];
1334} __packed;
1335
1336#define HV_UNMAP_GPA_LARGE_PAGE 0x2
1337
1338/* HvCallSendSyntheticClusterIpi hypercall */
1339struct hv_send_ipi { /* HV_INPUT_SEND_SYNTHETIC_CLUSTER_IPI */
1340 u32 vector;
1341 u32 reserved;
1342 u64 cpu_mask;
1343} __packed;
1344
1345#define HV_VTL_MASK GENMASK(3, 0)
1346
1347/* Hyper-V memory host visibility */
1348enum hv_mem_host_visibility {
1349 VMBUS_PAGE_NOT_VISIBLE = 0,
1350 VMBUS_PAGE_VISIBLE_READ_ONLY = 1,
1351 VMBUS_PAGE_VISIBLE_READ_WRITE = 3
1352};
1353
1354/* HvCallModifySparseGpaPageHostVisibility hypercall */
1355#define HV_MAX_MODIFY_GPA_REP_COUNT ((HV_HYP_PAGE_SIZE / sizeof(u64)) - 2)
1356struct hv_gpa_range_for_visibility {
1357 u64 partition_id;
1358 u32 host_visibility : 2;
1359 u32 reserved0 : 30;
1360 u32 reserved1;
1361 u64 gpa_page_list[HV_MAX_MODIFY_GPA_REP_COUNT];
1362} __packed;
1363
1364#if defined(CONFIG_X86)
1365union hv_msi_address_register { /* HV_MSI_ADDRESS */
1366 u32 as_uint32;
1367 struct {
1368 u32 reserved1 : 2;
1369 u32 destination_mode : 1;
1370 u32 redirection_hint : 1;
1371 u32 reserved2 : 8;
1372 u32 destination_id : 8;
1373 u32 msi_base : 12;
1374 };
1375} __packed;
1376
1377union hv_msi_data_register { /* HV_MSI_ENTRY.Data */
1378 u32 as_uint32;
1379 struct {
1380 u32 vector : 8;
1381 u32 delivery_mode : 3;
1382 u32 reserved1 : 3;
1383 u32 level_assert : 1;
1384 u32 trigger_mode : 1;
1385 u32 reserved2 : 16;
1386 };
1387} __packed;
1388
1389union hv_msi_entry { /* HV_MSI_ENTRY */
1390
1391 u64 as_uint64;
1392 struct {
1393 union hv_msi_address_register address;
1394 union hv_msi_data_register data;
1395 } __packed;
1396};
1397
1398#elif defined(CONFIG_ARM64) /* CONFIG_X86 */
1399
1400union hv_msi_entry {
1401 u64 as_uint64[2];
1402 struct {
1403 u64 address;
1404 u32 data;
1405 u32 reserved;
1406 } __packed;
1407};
1408#endif /* CONFIG_ARM64 */
1409
1410union hv_ioapic_rte {
1411 u64 as_uint64;
1412
1413 struct {
1414 u32 vector : 8;
1415 u32 delivery_mode : 3;
1416 u32 destination_mode : 1;
1417 u32 delivery_status : 1;
1418 u32 interrupt_polarity : 1;
1419 u32 remote_irr : 1;
1420 u32 trigger_mode : 1;
1421 u32 interrupt_mask : 1;
1422 u32 reserved1 : 15;
1423
1424 u32 reserved2 : 24;
1425 u32 destination_id : 8;
1426 };
1427
1428 struct {
1429 u32 low_uint32;
1430 u32 high_uint32;
1431 };
1432} __packed;
1433
1434enum hv_interrupt_source { /* HV_INTERRUPT_SOURCE */
1435 HV_INTERRUPT_SOURCE_MSI = 1, /* MSI and MSI-X */
1436 HV_INTERRUPT_SOURCE_IOAPIC,
1437};
1438
1439struct hv_interrupt_entry { /* HV_INTERRUPT_ENTRY */
1440 u32 source;
1441 u32 reserved1;
1442 union {
1443 union hv_msi_entry msi_entry;
1444 union hv_ioapic_rte ioapic_rte;
1445 };
1446} __packed;
1447
1448#define HV_DEVICE_INTERRUPT_TARGET_MULTICAST 1
1449#define HV_DEVICE_INTERRUPT_TARGET_PROCESSOR_SET 2
1450
1451struct hv_device_interrupt_target { /* HV_DEVICE_INTERRUPT_TARGET */
1452 u32 vector;
1453 u32 flags; /* HV_DEVICE_INTERRUPT_TARGET_* above */
1454 union {
1455 u64 vp_mask;
1456 struct hv_vpset vp_set;
1457 };
1458} __packed;
1459
1460struct hv_retarget_device_interrupt { /* HV_INPUT_RETARGET_DEVICE_INTERRUPT */
1461 u64 partition_id; /* use "self" */
1462 u64 device_id;
1463 struct hv_interrupt_entry int_entry;
1464 u64 reserved2;
1465 struct hv_device_interrupt_target int_target;
1466} __packed __aligned(8);
1467
1468enum hv_intercept_type {
1469#if defined(CONFIG_X86)
1470 HV_INTERCEPT_TYPE_X64_IO_PORT = 0x00000000,
1471 HV_INTERCEPT_TYPE_X64_MSR = 0x00000001,
1472 HV_INTERCEPT_TYPE_X64_CPUID = 0x00000002,
1473#endif
1474 HV_INTERCEPT_TYPE_EXCEPTION = 0x00000003,
1475 /* Used to be HV_INTERCEPT_TYPE_REGISTER */
1476 HV_INTERCEPT_TYPE_RESERVED0 = 0x00000004,
1477 HV_INTERCEPT_TYPE_MMIO = 0x00000005,
1478#if defined(CONFIG_X86)
1479 HV_INTERCEPT_TYPE_X64_GLOBAL_CPUID = 0x00000006,
1480 HV_INTERCEPT_TYPE_X64_APIC_SMI = 0x00000007,
1481#endif
1482 HV_INTERCEPT_TYPE_HYPERCALL = 0x00000008,
1483#if defined(CONFIG_X86)
1484 HV_INTERCEPT_TYPE_X64_APIC_INIT_SIPI = 0x00000009,
1485 HV_INTERCEPT_MC_UPDATE_PATCH_LEVEL_MSR_READ = 0x0000000A,
1486 HV_INTERCEPT_TYPE_X64_APIC_WRITE = 0x0000000B,
1487 HV_INTERCEPT_TYPE_X64_MSR_INDEX = 0x0000000C,
1488#endif
1489 HV_INTERCEPT_TYPE_MAX,
1490 HV_INTERCEPT_TYPE_INVALID = 0xFFFFFFFF,
1491};
1492
1493union hv_intercept_parameters {
1494 /* HV_INTERCEPT_PARAMETERS is defined to be an 8-byte field. */
1495 u64 as_uint64;
1496#if defined(CONFIG_X86)
1497 /* HV_INTERCEPT_TYPE_X64_IO_PORT */
1498 u16 io_port;
1499 /* HV_INTERCEPT_TYPE_X64_CPUID */
1500 u32 cpuid_index;
1501 /* HV_INTERCEPT_TYPE_X64_APIC_WRITE */
1502 u32 apic_write_mask;
1503 /* HV_INTERCEPT_TYPE_EXCEPTION */
1504 u16 exception_vector;
1505 /* HV_INTERCEPT_TYPE_X64_MSR_INDEX */
1506 u32 msr_index;
1507#endif
1508 /* N.B. Other intercept types do not have any parameters. */
1509};
1510
1511/* Data structures for HVCALL_MMIO_READ and HVCALL_MMIO_WRITE */
1512#define HV_HYPERCALL_MMIO_MAX_DATA_LENGTH 64
1513
1514struct hv_mmio_read_input { /* HV_INPUT_MEMORY_MAPPED_IO_READ */
1515 u64 gpa;
1516 u32 size;
1517 u32 reserved;
1518} __packed;
1519
1520struct hv_mmio_read_output {
1521 u8 data[HV_HYPERCALL_MMIO_MAX_DATA_LENGTH];
1522} __packed;
1523
1524struct hv_mmio_write_input {
1525 u64 gpa;
1526 u32 size;
1527 u32 reserved;
1528 u8 data[HV_HYPERCALL_MMIO_MAX_DATA_LENGTH];
1529} __packed;
1530
1531#endif /* _HV_HVGDK_MINI_H */
1532

source code of linux/include/hyperv/hvgdk_mini.h