1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
5 */
6
7/* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */
8#define __DISABLE_TRACE_MMIO__
9
10#include <linux/acpi.h>
11#include <linux/bitfield.h>
12#include <linux/clk.h>
13#include <linux/firmware.h>
14#include <linux/slab.h>
15#include <linux/dma-mapping.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_platform.h>
20#include <linux/pinctrl/consumer.h>
21#include <linux/platform_device.h>
22#include <linux/soc/qcom/geni-se.h>
23
24/**
25 * DOC: Overview
26 *
27 * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced
28 * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper
29 * controller. QUP Wrapper is designed to support various serial bus protocols
30 * like UART, SPI, I2C, I3C, etc.
31 */
32
33/**
34 * DOC: Hardware description
35 *
36 * GENI based QUP is a highly-flexible and programmable module for supporting
37 * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single
38 * QUP module can provide upto 8 serial interfaces, using its internal
39 * serial engines. The actual configuration is determined by the target
40 * platform configuration. The protocol supported by each interface is
41 * determined by the firmware loaded to the serial engine. Each SE consists
42 * of a DMA Engine and GENI sub modules which enable serial engines to
43 * support FIFO and DMA modes of operation.
44 *
45 *
46 * +-----------------------------------------+
47 * |QUP Wrapper |
48 * | +----------------------------+ |
49 * --QUP & SE Clocks--> | Serial Engine N | +-IO------>
50 * | | ... | | Interface
51 * <---Clock Perf.----+ +----+-----------------------+ | |
52 * State Interface | | Serial Engine 1 | | |
53 * | | | | |
54 * | | | | |
55 * <--------AHB-------> | | | |
56 * | | +----+ |
57 * | | | |
58 * | | | |
59 * <------SE IRQ------+ +----------------------------+ |
60 * | |
61 * +-----------------------------------------+
62 *
63 * Figure 1: GENI based QUP Wrapper
64 *
65 * The GENI submodules include primary and secondary sequencers which are
66 * used to drive TX & RX operations. On serial interfaces that operate using
67 * master-slave model, primary sequencer drives both TX & RX operations. On
68 * serial interfaces that operate using peer-to-peer model, primary sequencer
69 * drives TX operation and secondary sequencer drives RX operation.
70 */
71
72/**
73 * DOC: Software description
74 *
75 * GENI SE Wrapper driver is structured into 2 parts:
76 *
77 * geni_wrapper represents QUP Wrapper controller. This part of the driver
78 * manages QUP Wrapper information such as hardware version, clock
79 * performance table that is common to all the internal serial engines.
80 *
81 * geni_se represents serial engine. This part of the driver manages serial
82 * engine information such as clocks, containing QUP Wrapper, etc. This part
83 * of driver also supports operations (eg. initialize the concerned serial
84 * engine, select between FIFO and DMA mode of operation etc.) that are
85 * common to all the serial engines and are independent of serial interfaces.
86 */
87
88#define MAX_CLK_PERF_LEVEL 32
89#define MAX_CLKS 2
90
91/**
92 * struct geni_wrapper - Data structure to represent the QUP Wrapper Core
93 * @dev: Device pointer of the QUP wrapper core
94 * @base: Base address of this instance of QUP wrapper core
95 * @clks: Handle to the primary & optional secondary AHB clocks
96 * @num_clks: Count of clocks
97 */
98struct geni_wrapper {
99 struct device *dev;
100 void __iomem *base;
101 struct clk_bulk_data clks[MAX_CLKS];
102 unsigned int num_clks;
103};
104
105/**
106 * struct geni_se_desc - Data structure to represent the QUP Wrapper resources
107 * @clks: Name of the primary & optional secondary AHB clocks
108 * @num_clks: Count of clock names
109 */
110struct geni_se_desc {
111 unsigned int num_clks;
112 const char * const *clks;
113};
114
115static const char * const icc_path_names[] = {"qup-core", "qup-config",
116 "qup-memory"};
117
118static const char * const protocol_name[] = { "None", "SPI", "UART", "I2C", "I3C", "SPI SLAVE" };
119
120/**
121 * struct se_fw_hdr - Serial Engine firmware configuration header
122 *
123 * This structure defines the SE firmware header, which together with the
124 * firmware payload is stored in individual ELF segments.
125 *
126 * @magic: Set to 'SEFW'.
127 * @version: Structure version number.
128 * @core_version: QUPV3 hardware version.
129 * @serial_protocol: Encoded in GENI_FW_REVISION.
130 * @fw_version: Firmware version, from GENI_FW_REVISION.
131 * @cfg_version: Configuration version, from GENI_INIT_CFG_REVISION.
132 * @fw_size_in_items: Number of 32-bit words in GENI_FW_RAM.
133 * @fw_offset: Byte offset to GENI_FW_RAM array.
134 * @cfg_size_in_items: Number of GENI_FW_CFG index/value pairs.
135 * @cfg_idx_offset: Byte offset to GENI_FW_CFG index array.
136 * @cfg_val_offset: Byte offset to GENI_FW_CFG values array.
137 */
138struct se_fw_hdr {
139 __le32 magic;
140 __le32 version;
141 __le32 core_version;
142 __le16 serial_protocol;
143 __le16 fw_version;
144 __le16 cfg_version;
145 __le16 fw_size_in_items;
146 __le16 fw_offset;
147 __le16 cfg_size_in_items;
148 __le16 cfg_idx_offset;
149 __le16 cfg_val_offset;
150};
151
152/*Magic numbers*/
153#define SE_MAGIC_NUM 0x57464553
154
155#define MAX_GENI_CFG_RAMn_CNT 455
156
157#define MI_PBT_NON_PAGED_SEGMENT 0x0
158#define MI_PBT_HASH_SEGMENT 0x2
159#define MI_PBT_NOTUSED_SEGMENT 0x3
160#define MI_PBT_SHARED_SEGMENT 0x4
161
162#define MI_PBT_FLAG_PAGE_MODE BIT(20)
163#define MI_PBT_FLAG_SEGMENT_TYPE GENMASK(26, 24)
164#define MI_PBT_FLAG_ACCESS_TYPE GENMASK(23, 21)
165
166#define MI_PBT_PAGE_MODE_VALUE(x) FIELD_GET(MI_PBT_FLAG_PAGE_MODE, x)
167
168#define MI_PBT_SEGMENT_TYPE_VALUE(x) FIELD_GET(MI_PBT_FLAG_SEGMENT_TYPE, x)
169
170#define MI_PBT_ACCESS_TYPE_VALUE(x) FIELD_GET(MI_PBT_FLAG_ACCESS_TYPE, x)
171
172#define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \
173 M_IO_DATA_DEASSERT_EN | \
174 M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \
175 M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \
176 M_TX_FIFO_WR_ERR_EN)
177
178/* Common QUPV3 registers */
179#define QUPV3_HW_VER_REG 0x4
180#define QUPV3_SE_AHB_M_CFG 0x118
181#define QUPV3_COMMON_CFG 0x120
182#define QUPV3_COMMON_CGC_CTRL 0x21c
183
184/* QUPV3_COMMON_CFG fields */
185#define FAST_SWITCH_TO_HIGH_DISABLE BIT(0)
186
187/* QUPV3_SE_AHB_M_CFG fields */
188#define AHB_M_CLK_CGC_ON BIT(0)
189
190/* QUPV3_COMMON_CGC_CTRL fields */
191#define COMMON_CSR_SLV_CLK_CGC_ON BIT(0)
192
193/* Common SE registers */
194#define SE_GENI_INIT_CFG_REVISION 0x0
195#define SE_GENI_S_INIT_CFG_REVISION 0x4
196#define SE_GENI_CGC_CTRL 0x28
197#define SE_GENI_CLK_CTRL_RO 0x60
198#define SE_GENI_FW_S_REVISION_RO 0x6c
199#define SE_GENI_CFG_REG0 0x100
200#define SE_GENI_BYTE_GRAN 0x254
201#define SE_GENI_TX_PACKING_CFG0 0x260
202#define SE_GENI_TX_PACKING_CFG1 0x264
203#define SE_GENI_RX_PACKING_CFG0 0x284
204#define SE_GENI_RX_PACKING_CFG1 0x288
205#define SE_GENI_S_IRQ_ENABLE 0x644
206#define SE_DMA_TX_PTR_L 0xc30
207#define SE_DMA_TX_PTR_H 0xc34
208#define SE_DMA_TX_ATTR 0xc38
209#define SE_DMA_TX_LEN 0xc3c
210#define SE_DMA_TX_IRQ_EN 0xc48
211#define SE_DMA_TX_IRQ_EN_SET 0xc4c
212#define SE_DMA_TX_IRQ_EN_CLR 0xc50
213#define SE_DMA_TX_LEN_IN 0xc54
214#define SE_DMA_TX_MAX_BURST 0xc5c
215#define SE_DMA_RX_PTR_L 0xd30
216#define SE_DMA_RX_PTR_H 0xd34
217#define SE_DMA_RX_ATTR 0xd38
218#define SE_DMA_RX_LEN 0xd3c
219#define SE_DMA_RX_IRQ_EN 0xd48
220#define SE_DMA_RX_IRQ_EN_SET 0xd4c
221#define SE_DMA_RX_IRQ_EN_CLR 0xd50
222#define SE_DMA_RX_MAX_BURST 0xd5c
223#define SE_DMA_RX_FLUSH 0xd60
224#define SE_GSI_EVENT_EN 0xe18
225#define SE_IRQ_EN 0xe1c
226#define SE_DMA_GENERAL_CFG 0xe30
227#define SE_GENI_FW_REVISION 0x1000
228#define SE_GENI_S_FW_REVISION 0x1004
229#define SE_GENI_CFG_RAMN 0x1010
230#define SE_GENI_CLK_CTRL 0x2000
231#define SE_DMA_IF_EN 0x2004
232#define SE_FIFO_IF_DISABLE 0x2008
233
234/* GENI_FW_REVISION_RO fields */
235#define FW_REV_VERSION_MSK GENMASK(7, 0)
236
237/* GENI_OUTPUT_CTRL fields */
238#define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0)
239
240/* GENI_CGC_CTRL fields */
241#define CFG_AHB_CLK_CGC_ON BIT(0)
242#define CFG_AHB_WR_ACLK_CGC_ON BIT(1)
243#define DATA_AHB_CLK_CGC_ON BIT(2)
244#define SCLK_CGC_ON BIT(3)
245#define TX_CLK_CGC_ON BIT(4)
246#define RX_CLK_CGC_ON BIT(5)
247#define EXT_CLK_CGC_ON BIT(6)
248#define PROG_RAM_HCLK_OFF BIT(8)
249#define PROG_RAM_SCLK_OFF BIT(9)
250#define DEFAULT_CGC_EN GENMASK(6, 0)
251
252/* SE_GSI_EVENT_EN fields */
253#define DMA_RX_EVENT_EN BIT(0)
254#define DMA_TX_EVENT_EN BIT(1)
255#define GENI_M_EVENT_EN BIT(2)
256#define GENI_S_EVENT_EN BIT(3)
257
258/* SE_IRQ_EN fields */
259#define DMA_RX_IRQ_EN BIT(0)
260#define DMA_TX_IRQ_EN BIT(1)
261#define GENI_M_IRQ_EN BIT(2)
262#define GENI_S_IRQ_EN BIT(3)
263
264/* SE_DMA_GENERAL_CFG */
265#define DMA_RX_CLK_CGC_ON BIT(0)
266#define DMA_TX_CLK_CGC_ON BIT(1)
267#define DMA_AHB_SLV_CLK_CGC_ON BIT(2)
268#define AHB_SEC_SLV_CLK_CGC_ON BIT(3)
269#define DUMMY_RX_NON_BUFFERABLE BIT(4)
270#define RX_DMA_ZERO_PADDING_EN BIT(5)
271#define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6)
272#define RX_DMA_IRQ_DELAY_SHFT 6
273
274/* GENI_CLK_CTRL fields */
275#define SER_CLK_SEL BIT(0)
276
277/* GENI_DMA_IF_EN fields */
278#define DMA_IF_EN BIT(0)
279
280#define geni_setbits32(_addr, _v) writel(readl(_addr) | (_v), _addr)
281#define geni_clrbits32(_addr, _v) writel(readl(_addr) & ~(_v), _addr)
282
283/**
284 * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version
285 * @se: Pointer to the corresponding serial engine.
286 *
287 * Return: Hardware Version of the wrapper.
288 */
289u32 geni_se_get_qup_hw_version(struct geni_se *se)
290{
291 struct geni_wrapper *wrapper = se->wrapper;
292
293 return readl_relaxed(wrapper->base + QUPV3_HW_VER_REG);
294}
295EXPORT_SYMBOL_GPL(geni_se_get_qup_hw_version);
296
297static void geni_se_io_set_mode(void __iomem *base)
298{
299 u32 val;
300
301 val = readl_relaxed(base + SE_IRQ_EN);
302 val |= GENI_M_IRQ_EN | GENI_S_IRQ_EN;
303 val |= DMA_TX_IRQ_EN | DMA_RX_IRQ_EN;
304 writel_relaxed(val, base + SE_IRQ_EN);
305
306 val = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
307 val &= ~GENI_DMA_MODE_EN;
308 writel_relaxed(val, base + SE_GENI_DMA_MODE_EN);
309
310 writel_relaxed(0, base + SE_GSI_EVENT_EN);
311}
312
313static void geni_se_io_init(void __iomem *base)
314{
315 u32 val;
316
317 val = readl_relaxed(base + SE_GENI_CGC_CTRL);
318 val |= DEFAULT_CGC_EN;
319 writel_relaxed(val, base + SE_GENI_CGC_CTRL);
320
321 val = readl_relaxed(base + SE_DMA_GENERAL_CFG);
322 val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CLK_CGC_ON;
323 val |= DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON;
324 writel_relaxed(val, base + SE_DMA_GENERAL_CFG);
325
326 writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL);
327 writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG);
328}
329
330static void geni_se_irq_clear(struct geni_se *se)
331{
332 writel_relaxed(0, se->base + SE_GSI_EVENT_EN);
333 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);
334 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR);
335 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR);
336 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR);
337 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN);
338}
339
340/**
341 * geni_se_init() - Initialize the GENI serial engine
342 * @se: Pointer to the concerned serial engine.
343 * @rx_wm: Receive watermark, in units of FIFO words.
344 * @rx_rfr: Ready-for-receive watermark, in units of FIFO words.
345 *
346 * This function is used to initialize the GENI serial engine, configure
347 * receive watermark and ready-for-receive watermarks.
348 */
349void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr)
350{
351 u32 val;
352
353 geni_se_irq_clear(se);
354 geni_se_io_init(base: se->base);
355 geni_se_io_set_mode(base: se->base);
356
357 writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG);
358 writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG);
359
360 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
361 val |= M_COMMON_GENI_M_IRQ_EN;
362 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
363
364 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
365 val |= S_COMMON_GENI_S_IRQ_EN;
366 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
367}
368EXPORT_SYMBOL_GPL(geni_se_init);
369
370static void geni_se_select_fifo_mode(struct geni_se *se)
371{
372 u32 proto = geni_se_read_proto(se);
373 u32 val, val_old;
374
375 geni_se_irq_clear(se);
376
377 /* UART driver manages enabling / disabling interrupts internally */
378 if (proto != GENI_SE_UART) {
379 /* Non-UART use only primary sequencer so dont bother about S_IRQ */
380 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
381 val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN;
382 val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
383 if (val != val_old)
384 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
385 }
386
387 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
388 val &= ~GENI_DMA_MODE_EN;
389 if (val != val_old)
390 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
391}
392
393static void geni_se_select_dma_mode(struct geni_se *se)
394{
395 u32 proto = geni_se_read_proto(se);
396 u32 val, val_old;
397
398 geni_se_irq_clear(se);
399
400 /* UART driver manages enabling / disabling interrupts internally */
401 if (proto != GENI_SE_UART) {
402 /* Non-UART use only primary sequencer so dont bother about S_IRQ */
403 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
404 val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
405 val &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
406 if (val != val_old)
407 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
408 }
409
410 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
411 val |= GENI_DMA_MODE_EN;
412 if (val != val_old)
413 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
414}
415
416static void geni_se_select_gpi_mode(struct geni_se *se)
417{
418 u32 val;
419
420 geni_se_irq_clear(se);
421
422 writel(val: 0, addr: se->base + SE_IRQ_EN);
423
424 val = readl(addr: se->base + SE_GENI_M_IRQ_EN);
425 val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN |
426 M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
427 writel(val, addr: se->base + SE_GENI_M_IRQ_EN);
428
429 writel(GENI_DMA_MODE_EN, addr: se->base + SE_GENI_DMA_MODE_EN);
430
431 val = readl(addr: se->base + SE_GSI_EVENT_EN);
432 val |= (DMA_RX_EVENT_EN | DMA_TX_EVENT_EN | GENI_M_EVENT_EN | GENI_S_EVENT_EN);
433 writel(val, addr: se->base + SE_GSI_EVENT_EN);
434}
435
436/**
437 * geni_se_select_mode() - Select the serial engine transfer mode
438 * @se: Pointer to the concerned serial engine.
439 * @mode: Transfer mode to be selected.
440 */
441void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode)
442{
443 WARN_ON(mode != GENI_SE_FIFO && mode != GENI_SE_DMA && mode != GENI_GPI_DMA);
444
445 switch (mode) {
446 case GENI_SE_FIFO:
447 geni_se_select_fifo_mode(se);
448 break;
449 case GENI_SE_DMA:
450 geni_se_select_dma_mode(se);
451 break;
452 case GENI_GPI_DMA:
453 geni_se_select_gpi_mode(se);
454 break;
455 case GENI_SE_INVALID:
456 default:
457 break;
458 }
459}
460EXPORT_SYMBOL_GPL(geni_se_select_mode);
461
462/**
463 * DOC: Overview
464 *
465 * GENI FIFO packing is highly configurable. TX/RX packing/unpacking consist
466 * of up to 4 operations, each operation represented by 4 configuration vectors
467 * of 10 bits programmed in GENI_TX_PACKING_CFG0 and GENI_TX_PACKING_CFG1 for
468 * TX FIFO and in GENI_RX_PACKING_CFG0 and GENI_RX_PACKING_CFG1 for RX FIFO.
469 * Refer to below examples for detailed bit-field description.
470 *
471 * Example 1: word_size = 7, packing_mode = 4 x 8, msb_to_lsb = 1
472 *
473 * +-----------+-------+-------+-------+-------+
474 * | | vec_0 | vec_1 | vec_2 | vec_3 |
475 * +-----------+-------+-------+-------+-------+
476 * | start | 0x6 | 0xe | 0x16 | 0x1e |
477 * | direction | 1 | 1 | 1 | 1 |
478 * | length | 6 | 6 | 6 | 6 |
479 * | stop | 0 | 0 | 0 | 1 |
480 * +-----------+-------+-------+-------+-------+
481 *
482 * Example 2: word_size = 15, packing_mode = 2 x 16, msb_to_lsb = 0
483 *
484 * +-----------+-------+-------+-------+-------+
485 * | | vec_0 | vec_1 | vec_2 | vec_3 |
486 * +-----------+-------+-------+-------+-------+
487 * | start | 0x0 | 0x8 | 0x10 | 0x18 |
488 * | direction | 0 | 0 | 0 | 0 |
489 * | length | 7 | 6 | 7 | 6 |
490 * | stop | 0 | 0 | 0 | 1 |
491 * +-----------+-------+-------+-------+-------+
492 *
493 * Example 3: word_size = 23, packing_mode = 1 x 32, msb_to_lsb = 1
494 *
495 * +-----------+-------+-------+-------+-------+
496 * | | vec_0 | vec_1 | vec_2 | vec_3 |
497 * +-----------+-------+-------+-------+-------+
498 * | start | 0x16 | 0xe | 0x6 | 0x0 |
499 * | direction | 1 | 1 | 1 | 1 |
500 * | length | 7 | 7 | 6 | 0 |
501 * | stop | 0 | 0 | 1 | 0 |
502 * +-----------+-------+-------+-------+-------+
503 *
504 */
505
506#define NUM_PACKING_VECTORS 4
507#define PACKING_START_SHIFT 5
508#define PACKING_DIR_SHIFT 4
509#define PACKING_LEN_SHIFT 1
510#define PACKING_STOP_BIT BIT(0)
511#define PACKING_VECTOR_SHIFT 10
512/**
513 * geni_se_config_packing() - Packing configuration of the serial engine
514 * @se: Pointer to the concerned serial engine
515 * @bpw: Bits of data per transfer word.
516 * @pack_words: Number of words per fifo element.
517 * @msb_to_lsb: Transfer from MSB to LSB or vice-versa.
518 * @tx_cfg: Flag to configure the TX Packing.
519 * @rx_cfg: Flag to configure the RX Packing.
520 *
521 * This function is used to configure the packing rules for the current
522 * transfer.
523 */
524void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,
525 bool msb_to_lsb, bool tx_cfg, bool rx_cfg)
526{
527 u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0};
528 int len;
529 int temp_bpw = bpw;
530 int idx_start = msb_to_lsb ? bpw - 1 : 0;
531 int idx = idx_start;
532 int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE;
533 int ceil_bpw = ALIGN(bpw, BITS_PER_BYTE);
534 int iter = (ceil_bpw * pack_words) / BITS_PER_BYTE;
535 int i;
536
537 if (iter <= 0 || iter > NUM_PACKING_VECTORS)
538 return;
539
540 for (i = 0; i < iter; i++) {
541 len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1;
542 cfg[i] = idx << PACKING_START_SHIFT;
543 cfg[i] |= msb_to_lsb << PACKING_DIR_SHIFT;
544 cfg[i] |= len << PACKING_LEN_SHIFT;
545
546 if (temp_bpw <= BITS_PER_BYTE) {
547 idx = ((i + 1) * BITS_PER_BYTE) + idx_start;
548 temp_bpw = bpw;
549 } else {
550 idx = idx + idx_delta;
551 temp_bpw = temp_bpw - BITS_PER_BYTE;
552 }
553 }
554 cfg[iter - 1] |= PACKING_STOP_BIT;
555 cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT);
556 cfg1 = cfg[2] | (cfg[3] << PACKING_VECTOR_SHIFT);
557
558 if (tx_cfg) {
559 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0);
560 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1);
561 }
562 if (rx_cfg) {
563 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0);
564 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1);
565 }
566
567 /*
568 * Number of protocol words in each FIFO entry
569 * 0 - 4x8, four words in each entry, max word size of 8 bits
570 * 1 - 2x16, two words in each entry, max word size of 16 bits
571 * 2 - 1x32, one word in each entry, max word size of 32 bits
572 * 3 - undefined
573 */
574 if (pack_words || bpw == 32)
575 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN);
576}
577EXPORT_SYMBOL_GPL(geni_se_config_packing);
578
579static void geni_se_clks_off(struct geni_se *se)
580{
581 struct geni_wrapper *wrapper = se->wrapper;
582
583 clk_disable_unprepare(clk: se->clk);
584 clk_bulk_disable_unprepare(num_clks: wrapper->num_clks, clks: wrapper->clks);
585}
586
587/**
588 * geni_se_resources_off() - Turn off resources associated with the serial
589 * engine
590 * @se: Pointer to the concerned serial engine.
591 *
592 * Return: 0 on success, standard Linux error codes on failure/error.
593 */
594int geni_se_resources_off(struct geni_se *se)
595{
596 int ret;
597
598 if (has_acpi_companion(dev: se->dev))
599 return 0;
600
601 ret = pinctrl_pm_select_sleep_state(dev: se->dev);
602 if (ret)
603 return ret;
604
605 geni_se_clks_off(se);
606 return 0;
607}
608EXPORT_SYMBOL_GPL(geni_se_resources_off);
609
610static int geni_se_clks_on(struct geni_se *se)
611{
612 int ret;
613 struct geni_wrapper *wrapper = se->wrapper;
614
615 ret = clk_bulk_prepare_enable(num_clks: wrapper->num_clks, clks: wrapper->clks);
616 if (ret)
617 return ret;
618
619 ret = clk_prepare_enable(clk: se->clk);
620 if (ret)
621 clk_bulk_disable_unprepare(num_clks: wrapper->num_clks, clks: wrapper->clks);
622 return ret;
623}
624
625/**
626 * geni_se_resources_on() - Turn on resources associated with the serial
627 * engine
628 * @se: Pointer to the concerned serial engine.
629 *
630 * Return: 0 on success, standard Linux error codes on failure/error.
631 */
632int geni_se_resources_on(struct geni_se *se)
633{
634 int ret;
635
636 if (has_acpi_companion(dev: se->dev))
637 return 0;
638
639 ret = geni_se_clks_on(se);
640 if (ret)
641 return ret;
642
643 ret = pinctrl_pm_select_default_state(dev: se->dev);
644 if (ret)
645 geni_se_clks_off(se);
646
647 return ret;
648}
649EXPORT_SYMBOL_GPL(geni_se_resources_on);
650
651/**
652 * geni_se_clk_tbl_get() - Get the clock table to program DFS
653 * @se: Pointer to the concerned serial engine.
654 * @tbl: Table in which the output is returned.
655 *
656 * This function is called by the protocol drivers to determine the different
657 * clock frequencies supported by serial engine core clock. The protocol
658 * drivers use the output to determine the clock frequency index to be
659 * programmed into DFS.
660 *
661 * Return: number of valid performance levels in the table on success,
662 * standard Linux error codes on failure.
663 */
664int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl)
665{
666 long freq = 0;
667 int i;
668
669 if (se->clk_perf_tbl) {
670 *tbl = se->clk_perf_tbl;
671 return se->num_clk_levels;
672 }
673
674 se->clk_perf_tbl = devm_kcalloc(dev: se->dev, MAX_CLK_PERF_LEVEL,
675 size: sizeof(*se->clk_perf_tbl),
676 GFP_KERNEL);
677 if (!se->clk_perf_tbl)
678 return -ENOMEM;
679
680 for (i = 0; i < MAX_CLK_PERF_LEVEL; i++) {
681 freq = clk_round_rate(clk: se->clk, rate: freq + 1);
682 if (freq <= 0 ||
683 (i > 0 && freq == se->clk_perf_tbl[i - 1]))
684 break;
685 se->clk_perf_tbl[i] = freq;
686 }
687 se->num_clk_levels = i;
688 *tbl = se->clk_perf_tbl;
689 return se->num_clk_levels;
690}
691EXPORT_SYMBOL_GPL(geni_se_clk_tbl_get);
692
693/**
694 * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency
695 * @se: Pointer to the concerned serial engine.
696 * @req_freq: Requested clock frequency.
697 * @index: Index of the resultant frequency in the table.
698 * @res_freq: Resultant frequency of the source clock.
699 * @exact: Flag to indicate exact multiple requirement of the requested
700 * frequency.
701 *
702 * This function is called by the protocol drivers to determine the best match
703 * of the requested frequency as provided by the serial engine clock in order
704 * to meet the performance requirements.
705 *
706 * If we return success:
707 * - if @exact is true then @res_freq / <an_integer> == @req_freq
708 * - if @exact is false then @res_freq / <an_integer> <= @req_freq
709 *
710 * Return: 0 on success, standard Linux error codes on failure.
711 */
712int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,
713 unsigned int *index, unsigned long *res_freq,
714 bool exact)
715{
716 unsigned long *tbl;
717 int num_clk_levels;
718 int i;
719 unsigned long best_delta;
720 unsigned long new_delta;
721 unsigned int divider;
722
723 num_clk_levels = geni_se_clk_tbl_get(se, &tbl);
724 if (num_clk_levels < 0)
725 return num_clk_levels;
726
727 if (num_clk_levels == 0)
728 return -EINVAL;
729
730 best_delta = ULONG_MAX;
731 for (i = 0; i < num_clk_levels; i++) {
732 divider = DIV_ROUND_UP(tbl[i], req_freq);
733 new_delta = req_freq - tbl[i] / divider;
734 if (new_delta < best_delta) {
735 /* We have a new best! */
736 *index = i;
737 *res_freq = tbl[i];
738
739 /* If the new best is exact then we're done */
740 if (new_delta == 0)
741 return 0;
742
743 /* Record how close we got */
744 best_delta = new_delta;
745 }
746 }
747
748 if (exact)
749 return -EINVAL;
750
751 return 0;
752}
753EXPORT_SYMBOL_GPL(geni_se_clk_freq_match);
754
755#define GENI_SE_DMA_DONE_EN BIT(0)
756#define GENI_SE_DMA_EOT_EN BIT(1)
757#define GENI_SE_DMA_AHB_ERR_EN BIT(2)
758#define GENI_SE_DMA_RESET_DONE_EN BIT(3)
759#define GENI_SE_DMA_FLUSH_DONE BIT(4)
760
761#define GENI_SE_DMA_EOT_BUF BIT(0)
762
763/**
764 * geni_se_tx_init_dma() - Initiate TX DMA transfer on the serial engine
765 * @se: Pointer to the concerned serial engine.
766 * @iova: Mapped DMA address.
767 * @len: Length of the TX buffer.
768 *
769 * This function is used to initiate DMA TX transfer.
770 */
771void geni_se_tx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len)
772{
773 u32 val;
774
775 val = GENI_SE_DMA_DONE_EN;
776 val |= GENI_SE_DMA_EOT_EN;
777 val |= GENI_SE_DMA_AHB_ERR_EN;
778 writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET);
779 writel_relaxed(lower_32_bits(iova), se->base + SE_DMA_TX_PTR_L);
780 writel_relaxed(upper_32_bits(iova), se->base + SE_DMA_TX_PTR_H);
781 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR);
782 writel(val: len, addr: se->base + SE_DMA_TX_LEN);
783}
784EXPORT_SYMBOL_GPL(geni_se_tx_init_dma);
785
786/**
787 * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer
788 * @se: Pointer to the concerned serial engine.
789 * @buf: Pointer to the TX buffer.
790 * @len: Length of the TX buffer.
791 * @iova: Pointer to store the mapped DMA address.
792 *
793 * This function is used to prepare the buffers for DMA TX.
794 *
795 * Return: 0 on success, standard Linux error codes on failure.
796 */
797int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len,
798 dma_addr_t *iova)
799{
800 struct geni_wrapper *wrapper = se->wrapper;
801
802 if (!wrapper)
803 return -EINVAL;
804
805 *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE);
806 if (dma_mapping_error(dev: wrapper->dev, dma_addr: *iova))
807 return -EIO;
808
809 geni_se_tx_init_dma(se, *iova, len);
810 return 0;
811}
812EXPORT_SYMBOL_GPL(geni_se_tx_dma_prep);
813
814/**
815 * geni_se_rx_init_dma() - Initiate RX DMA transfer on the serial engine
816 * @se: Pointer to the concerned serial engine.
817 * @iova: Mapped DMA address.
818 * @len: Length of the RX buffer.
819 *
820 * This function is used to initiate DMA RX transfer.
821 */
822void geni_se_rx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len)
823{
824 u32 val;
825
826 val = GENI_SE_DMA_DONE_EN;
827 val |= GENI_SE_DMA_EOT_EN;
828 val |= GENI_SE_DMA_AHB_ERR_EN;
829 writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET);
830 writel_relaxed(lower_32_bits(iova), se->base + SE_DMA_RX_PTR_L);
831 writel_relaxed(upper_32_bits(iova), se->base + SE_DMA_RX_PTR_H);
832 /* RX does not have EOT buffer type bit. So just reset RX_ATTR */
833 writel_relaxed(0, se->base + SE_DMA_RX_ATTR);
834 writel(val: len, addr: se->base + SE_DMA_RX_LEN);
835}
836EXPORT_SYMBOL_GPL(geni_se_rx_init_dma);
837
838/**
839 * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer
840 * @se: Pointer to the concerned serial engine.
841 * @buf: Pointer to the RX buffer.
842 * @len: Length of the RX buffer.
843 * @iova: Pointer to store the mapped DMA address.
844 *
845 * This function is used to prepare the buffers for DMA RX.
846 *
847 * Return: 0 on success, standard Linux error codes on failure.
848 */
849int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
850 dma_addr_t *iova)
851{
852 struct geni_wrapper *wrapper = se->wrapper;
853
854 if (!wrapper)
855 return -EINVAL;
856
857 *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE);
858 if (dma_mapping_error(dev: wrapper->dev, dma_addr: *iova))
859 return -EIO;
860
861 geni_se_rx_init_dma(se, *iova, len);
862 return 0;
863}
864EXPORT_SYMBOL_GPL(geni_se_rx_dma_prep);
865
866/**
867 * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer
868 * @se: Pointer to the concerned serial engine.
869 * @iova: DMA address of the TX buffer.
870 * @len: Length of the TX buffer.
871 *
872 * This function is used to unprepare the DMA buffers after DMA TX.
873 */
874void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
875{
876 struct geni_wrapper *wrapper = se->wrapper;
877
878 if (!dma_mapping_error(dev: wrapper->dev, dma_addr: iova))
879 dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE);
880}
881EXPORT_SYMBOL_GPL(geni_se_tx_dma_unprep);
882
883/**
884 * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer
885 * @se: Pointer to the concerned serial engine.
886 * @iova: DMA address of the RX buffer.
887 * @len: Length of the RX buffer.
888 *
889 * This function is used to unprepare the DMA buffers after DMA RX.
890 */
891void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
892{
893 struct geni_wrapper *wrapper = se->wrapper;
894
895 if (!dma_mapping_error(dev: wrapper->dev, dma_addr: iova))
896 dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE);
897}
898EXPORT_SYMBOL_GPL(geni_se_rx_dma_unprep);
899
900int geni_icc_get(struct geni_se *se, const char *icc_ddr)
901{
902 int i, err;
903 const char *icc_names[] = {"qup-core", "qup-config", icc_ddr};
904
905 if (has_acpi_companion(dev: se->dev))
906 return 0;
907
908 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
909 if (!icc_names[i])
910 continue;
911
912 se->icc_paths[i].path = devm_of_icc_get(dev: se->dev, name: icc_names[i]);
913 if (IS_ERR(ptr: se->icc_paths[i].path))
914 goto err;
915 }
916
917 return 0;
918
919err:
920 err = PTR_ERR(ptr: se->icc_paths[i].path);
921 if (err != -EPROBE_DEFER)
922 dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n",
923 icc_names[i], err);
924 return err;
925
926}
927EXPORT_SYMBOL_GPL(geni_icc_get);
928
929int geni_icc_set_bw(struct geni_se *se)
930{
931 int i, ret;
932
933 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
934 ret = icc_set_bw(path: se->icc_paths[i].path,
935 avg_bw: se->icc_paths[i].avg_bw, peak_bw: se->icc_paths[i].avg_bw);
936 if (ret) {
937 dev_err_ratelimited(se->dev, "ICC BW voting failed on path '%s': %d\n",
938 icc_path_names[i], ret);
939 return ret;
940 }
941 }
942
943 return 0;
944}
945EXPORT_SYMBOL_GPL(geni_icc_set_bw);
946
947void geni_icc_set_tag(struct geni_se *se, u32 tag)
948{
949 int i;
950
951 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++)
952 icc_set_tag(path: se->icc_paths[i].path, tag);
953}
954EXPORT_SYMBOL_GPL(geni_icc_set_tag);
955
956/* To do: Replace this by icc_bulk_enable once it's implemented in ICC core */
957int geni_icc_enable(struct geni_se *se)
958{
959 int i, ret;
960
961 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
962 ret = icc_enable(path: se->icc_paths[i].path);
963 if (ret) {
964 dev_err_ratelimited(se->dev, "ICC enable failed on path '%s': %d\n",
965 icc_path_names[i], ret);
966 return ret;
967 }
968 }
969
970 return 0;
971}
972EXPORT_SYMBOL_GPL(geni_icc_enable);
973
974int geni_icc_disable(struct geni_se *se)
975{
976 int i, ret;
977
978 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
979 ret = icc_disable(path: se->icc_paths[i].path);
980 if (ret) {
981 dev_err_ratelimited(se->dev, "ICC disable failed on path '%s': %d\n",
982 icc_path_names[i], ret);
983 return ret;
984 }
985 }
986
987 return 0;
988}
989EXPORT_SYMBOL_GPL(geni_icc_disable);
990
991/**
992 * geni_find_protocol_fw() - Locate and validate SE firmware for a protocol.
993 * @dev: Pointer to the device structure.
994 * @fw: Pointer to the firmware image.
995 * @protocol: Expected serial engine protocol type.
996 *
997 * Identifies the appropriate firmware image or configuration required for a
998 * specific communication protocol instance running on a Qualcomm GENI
999 * controller.
1000 *
1001 * Return: pointer to a valid 'struct se_fw_hdr' if found, or NULL otherwise.
1002 */
1003static struct se_fw_hdr *geni_find_protocol_fw(struct device *dev, const struct firmware *fw,
1004 enum geni_se_protocol_type protocol)
1005{
1006 const struct elf32_hdr *ehdr;
1007 const struct elf32_phdr *phdrs;
1008 const struct elf32_phdr *phdr;
1009 struct se_fw_hdr *sefw;
1010 u32 fw_end, cfg_idx_end, cfg_val_end;
1011 u16 fw_size;
1012 int i;
1013
1014 if (!fw || fw->size < sizeof(struct elf32_hdr))
1015 return NULL;
1016
1017 ehdr = (const struct elf32_hdr *)fw->data;
1018 phdrs = (const struct elf32_phdr *)(fw->data + ehdr->e_phoff);
1019
1020 /*
1021 * The firmware is expected to have at least two program headers (segments).
1022 * One for metadata and the other for the actual protocol-specific firmware.
1023 */
1024 if (ehdr->e_phnum < 2) {
1025 dev_err(dev, "Invalid firmware: less than 2 program headers\n");
1026 return NULL;
1027 }
1028
1029 for (i = 0; i < ehdr->e_phnum; i++) {
1030 phdr = &phdrs[i];
1031
1032 if (fw->size < phdr->p_offset + phdr->p_filesz) {
1033 dev_err(dev, "Firmware size (%zu) < expected offset (%u) + size (%u)\n",
1034 fw->size, phdr->p_offset, phdr->p_filesz);
1035 return NULL;
1036 }
1037
1038 if (phdr->p_type != PT_LOAD || !phdr->p_memsz)
1039 continue;
1040
1041 if (MI_PBT_PAGE_MODE_VALUE(phdr->p_flags) != MI_PBT_NON_PAGED_SEGMENT ||
1042 MI_PBT_SEGMENT_TYPE_VALUE(phdr->p_flags) == MI_PBT_HASH_SEGMENT ||
1043 MI_PBT_ACCESS_TYPE_VALUE(phdr->p_flags) == MI_PBT_NOTUSED_SEGMENT ||
1044 MI_PBT_ACCESS_TYPE_VALUE(phdr->p_flags) == MI_PBT_SHARED_SEGMENT)
1045 continue;
1046
1047 if (phdr->p_filesz < sizeof(struct se_fw_hdr))
1048 continue;
1049
1050 sefw = (struct se_fw_hdr *)(fw->data + phdr->p_offset);
1051 fw_size = le16_to_cpu(sefw->fw_size_in_items);
1052 fw_end = le16_to_cpu(sefw->fw_offset) + fw_size * sizeof(u32);
1053 cfg_idx_end = le16_to_cpu(sefw->cfg_idx_offset) +
1054 le16_to_cpu(sefw->cfg_size_in_items) * sizeof(u8);
1055 cfg_val_end = le16_to_cpu(sefw->cfg_val_offset) +
1056 le16_to_cpu(sefw->cfg_size_in_items) * sizeof(u32);
1057
1058 if (le32_to_cpu(sefw->magic) != SE_MAGIC_NUM || le32_to_cpu(sefw->version) != 1)
1059 continue;
1060
1061 if (le32_to_cpu(sefw->serial_protocol) != protocol)
1062 continue;
1063
1064 if (fw_size % 2 != 0) {
1065 fw_size++;
1066 sefw->fw_size_in_items = cpu_to_le16(fw_size);
1067 }
1068
1069 if (fw_size >= MAX_GENI_CFG_RAMn_CNT) {
1070 dev_err(dev,
1071 "Firmware size (%u) exceeds max allowed RAMn count (%u)\n",
1072 fw_size, MAX_GENI_CFG_RAMn_CNT);
1073 continue;
1074 }
1075
1076 if (fw_end > phdr->p_filesz || cfg_idx_end > phdr->p_filesz ||
1077 cfg_val_end > phdr->p_filesz) {
1078 dev_err(dev, "Truncated or corrupt SE FW segment found at index %d\n", i);
1079 continue;
1080 }
1081
1082 return sefw;
1083 }
1084
1085 dev_err(dev, "Failed to get %s protocol firmware\n", protocol_name[protocol]);
1086 return NULL;
1087}
1088
1089/**
1090 * geni_configure_xfer_mode() - Set the transfer mode.
1091 * @se: Pointer to the concerned serial engine.
1092 * @mode: SE data transfer mode.
1093 *
1094 * Set the transfer mode to either FIFO or DMA according to the mode specified
1095 * by the protocol driver.
1096 *
1097 * Return: 0 if successful, otherwise return an error value.
1098 */
1099static int geni_configure_xfer_mode(struct geni_se *se, enum geni_se_xfer_mode mode)
1100{
1101 /* Configure SE FIFO, DMA or GSI mode. */
1102 switch (mode) {
1103 case GENI_GPI_DMA:
1104 geni_setbits32(se->base + SE_GENI_DMA_MODE_EN, GENI_DMA_MODE_EN);
1105 writel(val: 0x0, addr: se->base + SE_IRQ_EN);
1106 writel(DMA_RX_EVENT_EN | DMA_TX_EVENT_EN | GENI_M_EVENT_EN | GENI_S_EVENT_EN,
1107 addr: se->base + SE_GSI_EVENT_EN);
1108 break;
1109
1110 case GENI_SE_FIFO:
1111 geni_clrbits32(se->base + SE_GENI_DMA_MODE_EN, GENI_DMA_MODE_EN);
1112 writel(DMA_RX_IRQ_EN | DMA_TX_IRQ_EN | GENI_M_IRQ_EN | GENI_S_IRQ_EN,
1113 addr: se->base + SE_IRQ_EN);
1114 writel(val: 0x0, addr: se->base + SE_GSI_EVENT_EN);
1115 break;
1116
1117 case GENI_SE_DMA:
1118 geni_setbits32(se->base + SE_GENI_DMA_MODE_EN, GENI_DMA_MODE_EN);
1119 writel(DMA_RX_IRQ_EN | DMA_TX_IRQ_EN | GENI_M_IRQ_EN | GENI_S_IRQ_EN,
1120 addr: se->base + SE_IRQ_EN);
1121 writel(val: 0x0, addr: se->base + SE_GSI_EVENT_EN);
1122 break;
1123
1124 default:
1125 dev_err(se->dev, "Invalid geni-se transfer mode: %d\n", mode);
1126 return -EINVAL;
1127 }
1128 return 0;
1129}
1130
1131/**
1132 * geni_enable_interrupts() - Enable interrupts.
1133 * @se: Pointer to the concerned serial engine.
1134 *
1135 * Enable the required interrupts during the firmware load process.
1136 */
1137static void geni_enable_interrupts(struct geni_se *se)
1138{
1139 u32 val;
1140
1141 /* Enable required interrupts. */
1142 writel(M_COMMON_GENI_M_IRQ_EN, addr: se->base + SE_GENI_M_IRQ_EN);
1143
1144 val = S_CMD_OVERRUN_EN | S_ILLEGAL_CMD_EN | S_CMD_CANCEL_EN | S_CMD_ABORT_EN |
1145 S_GP_IRQ_0_EN | S_GP_IRQ_1_EN | S_GP_IRQ_2_EN | S_GP_IRQ_3_EN |
1146 S_RX_FIFO_WR_ERR_EN | S_RX_FIFO_RD_ERR_EN;
1147 writel(val, addr: se->base + SE_GENI_S_IRQ_ENABLE);
1148
1149 /* DMA mode configuration. */
1150 val = GENI_SE_DMA_RESET_DONE_EN | GENI_SE_DMA_AHB_ERR_EN | GENI_SE_DMA_DONE_EN;
1151 writel(val, addr: se->base + SE_DMA_TX_IRQ_EN_SET);
1152 val = GENI_SE_DMA_FLUSH_DONE | GENI_SE_DMA_RESET_DONE_EN | GENI_SE_DMA_AHB_ERR_EN |
1153 GENI_SE_DMA_DONE_EN;
1154 writel(val, addr: se->base + SE_DMA_RX_IRQ_EN_SET);
1155}
1156
1157/**
1158 * geni_write_fw_revision() - Write the firmware revision.
1159 * @se: Pointer to the concerned serial engine.
1160 * @serial_protocol: serial protocol type.
1161 * @fw_version: QUP firmware version.
1162 *
1163 * Write the firmware revision and protocol into the respective register.
1164 */
1165static void geni_write_fw_revision(struct geni_se *se, u16 serial_protocol, u16 fw_version)
1166{
1167 u32 reg;
1168
1169 reg = FIELD_PREP(FW_REV_PROTOCOL_MSK, serial_protocol);
1170 reg |= FIELD_PREP(FW_REV_VERSION_MSK, fw_version);
1171
1172 writel(val: reg, addr: se->base + SE_GENI_FW_REVISION);
1173 writel(val: reg, addr: se->base + SE_GENI_S_FW_REVISION);
1174}
1175
1176/**
1177 * geni_load_se_fw() - Load Serial Engine specific firmware.
1178 * @se: Pointer to the concerned serial engine.
1179 * @fw: Pointer to the firmware structure.
1180 * @mode: SE data transfer mode.
1181 * @protocol: Protocol type to be used with the SE (e.g., UART, SPI, I2C).
1182 *
1183 * Load the protocol firmware into the IRAM of the Serial Engine.
1184 *
1185 * Return: 0 if successful, otherwise return an error value.
1186 */
1187static int geni_load_se_fw(struct geni_se *se, const struct firmware *fw,
1188 enum geni_se_xfer_mode mode, enum geni_se_protocol_type protocol)
1189{
1190 const u32 *fw_data, *cfg_val_arr;
1191 const u8 *cfg_idx_arr;
1192 u32 i, reg_value;
1193 int ret;
1194 struct se_fw_hdr *hdr;
1195
1196 hdr = geni_find_protocol_fw(dev: se->dev, fw, protocol);
1197 if (!hdr)
1198 return -EINVAL;
1199
1200 fw_data = (const u32 *)((u8 *)hdr + le16_to_cpu(hdr->fw_offset));
1201 cfg_idx_arr = (const u8 *)hdr + le16_to_cpu(hdr->cfg_idx_offset);
1202 cfg_val_arr = (const u32 *)((u8 *)hdr + le16_to_cpu(hdr->cfg_val_offset));
1203
1204 ret = geni_icc_set_bw(se);
1205 if (ret)
1206 return ret;
1207
1208 ret = geni_icc_enable(se);
1209 if (ret)
1210 return ret;
1211
1212 ret = geni_se_resources_on(se);
1213 if (ret)
1214 goto out_icc_disable;
1215
1216 /*
1217 * Disable high-priority interrupts until all currently executing
1218 * low-priority interrupts have been fully handled.
1219 */
1220 geni_setbits32(se->wrapper->base + QUPV3_COMMON_CFG, FAST_SWITCH_TO_HIGH_DISABLE);
1221
1222 /* Set AHB_M_CLK_CGC_ON to indicate hardware controls se-wrapper cgc clock. */
1223 geni_setbits32(se->wrapper->base + QUPV3_SE_AHB_M_CFG, AHB_M_CLK_CGC_ON);
1224
1225 /* Let hardware to control common cgc. */
1226 geni_setbits32(se->wrapper->base + QUPV3_COMMON_CGC_CTRL, COMMON_CSR_SLV_CLK_CGC_ON);
1227
1228 /*
1229 * Setting individual bits in GENI_OUTPUT_CTRL activates corresponding output lines,
1230 * allowing the hardware to drive data as configured.
1231 */
1232 writel(val: 0x0, addr: se->base + GENI_OUTPUT_CTRL);
1233
1234 /* Set SCLK and HCLK to program RAM */
1235 geni_setbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_HCLK_OFF);
1236 writel(val: 0x0, addr: se->base + SE_GENI_CLK_CTRL);
1237 geni_clrbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_HCLK_OFF);
1238
1239 /* Enable required clocks for DMA CSR, TX and RX. */
1240 reg_value = AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CLK_CGC_ON |
1241 DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON;
1242 geni_setbits32(se->base + SE_DMA_GENERAL_CFG, reg_value);
1243
1244 /* Let hardware control CGC by default. */
1245 writel(DEFAULT_CGC_EN, addr: se->base + SE_GENI_CGC_CTRL);
1246
1247 /* Set version of the configuration register part of firmware. */
1248 writel(le16_to_cpu(hdr->cfg_version), addr: se->base + SE_GENI_INIT_CFG_REVISION);
1249 writel(le16_to_cpu(hdr->cfg_version), addr: se->base + SE_GENI_S_INIT_CFG_REVISION);
1250
1251 /* Configure GENI primitive table. */
1252 for (i = 0; i < le16_to_cpu(hdr->cfg_size_in_items); i++)
1253 writel(val: cfg_val_arr[i],
1254 addr: se->base + SE_GENI_CFG_REG0 + (cfg_idx_arr[i] * sizeof(u32)));
1255
1256 /* Configure condition for assertion of RX_RFR_WATERMARK condition. */
1257 reg_value = geni_se_get_rx_fifo_depth(se);
1258 writel(val: reg_value - 2, addr: se->base + SE_GENI_RX_RFR_WATERMARK_REG);
1259
1260 /* Let hardware control CGC */
1261 geni_setbits32(se->base + GENI_OUTPUT_CTRL, DEFAULT_IO_OUTPUT_CTRL_MSK);
1262
1263 ret = geni_configure_xfer_mode(se, mode);
1264 if (ret)
1265 goto out_resources_off;
1266
1267 geni_enable_interrupts(se);
1268
1269 geni_write_fw_revision(se, le16_to_cpu(hdr->serial_protocol), le16_to_cpu(hdr->fw_version));
1270
1271 /* Program RAM address space. */
1272 memcpy_toio(se->base + SE_GENI_CFG_RAMN, fw_data,
1273 le16_to_cpu(hdr->fw_size_in_items) * sizeof(u32));
1274
1275 /* Put default values on GENI's output pads. */
1276 writel_relaxed(0x1, se->base + GENI_FORCE_DEFAULT_REG);
1277
1278 /* Toggle SCLK/HCLK from high to low to finalize RAM programming and apply config. */
1279 geni_setbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_HCLK_OFF);
1280 geni_setbits32(se->base + SE_GENI_CLK_CTRL, SER_CLK_SEL);
1281 geni_clrbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_HCLK_OFF);
1282
1283 /* Serial engine DMA interface is enabled. */
1284 geni_setbits32(se->base + SE_DMA_IF_EN, DMA_IF_EN);
1285
1286 /* Enable or disable FIFO interface of the serial engine. */
1287 if (mode == GENI_SE_FIFO)
1288 geni_clrbits32(se->base + SE_FIFO_IF_DISABLE, FIFO_IF_DISABLE);
1289 else
1290 geni_setbits32(se->base + SE_FIFO_IF_DISABLE, FIFO_IF_DISABLE);
1291
1292out_resources_off:
1293 geni_se_resources_off(se);
1294
1295out_icc_disable:
1296 geni_icc_disable(se);
1297 return ret;
1298}
1299
1300/**
1301 * geni_load_se_firmware() - Load firmware for SE based on protocol
1302 * @se: Pointer to the concerned serial engine.
1303 * @protocol: Protocol type to be used with the SE (e.g., UART, SPI, I2C).
1304 *
1305 * Retrieves the firmware name from device properties and sets the transfer mode
1306 * (FIFO or GSI DMA) based on device tree configuration. Enforces FIFO mode for
1307 * UART protocol due to lack of GSI DMA support. Requests the firmware and loads
1308 * it into the SE.
1309 *
1310 * Return: 0 on success, negative error code on failure.
1311 */
1312int geni_load_se_firmware(struct geni_se *se, enum geni_se_protocol_type protocol)
1313{
1314 const char *fw_name;
1315 const struct firmware *fw;
1316 enum geni_se_xfer_mode mode = GENI_SE_FIFO;
1317 int ret;
1318
1319 if (protocol >= ARRAY_SIZE(protocol_name)) {
1320 dev_err(se->dev, "Invalid geni-se protocol: %d", protocol);
1321 return -EINVAL;
1322 }
1323
1324 ret = device_property_read_string(dev: se->wrapper->dev, propname: "firmware-name", val: &fw_name);
1325 if (ret) {
1326 dev_err(se->dev, "Failed to read firmware-name property: %d\n", ret);
1327 return -EINVAL;
1328 }
1329
1330 if (of_property_read_bool(np: se->dev->of_node, propname: "qcom,enable-gsi-dma"))
1331 mode = GENI_GPI_DMA;
1332
1333 /* GSI mode is not supported by the UART driver; therefore, setting FIFO mode */
1334 if (protocol == GENI_SE_UART)
1335 mode = GENI_SE_FIFO;
1336
1337 ret = request_firmware(fw: &fw, name: fw_name, device: se->dev);
1338 if (ret) {
1339 if (ret == -ENOENT)
1340 return -EPROBE_DEFER;
1341
1342 dev_err(se->dev, "Failed to request firmware '%s' for protocol %d: ret: %d\n",
1343 fw_name, protocol, ret);
1344 return ret;
1345 }
1346
1347 ret = geni_load_se_fw(se, fw, mode, protocol);
1348 release_firmware(fw);
1349
1350 if (ret) {
1351 dev_err(se->dev, "Failed to load SE firmware for protocol %d: ret: %d\n",
1352 protocol, ret);
1353 return ret;
1354 }
1355
1356 dev_dbg(se->dev, "Firmware load for %s protocol is successful for xfer mode: %d\n",
1357 protocol_name[protocol], mode);
1358 return 0;
1359}
1360EXPORT_SYMBOL_GPL(geni_load_se_firmware);
1361
1362static int geni_se_probe(struct platform_device *pdev)
1363{
1364 struct device *dev = &pdev->dev;
1365 struct geni_wrapper *wrapper;
1366 const struct geni_se_desc *desc;
1367 int ret;
1368
1369 wrapper = devm_kzalloc(dev, size: sizeof(*wrapper), GFP_KERNEL);
1370 if (!wrapper)
1371 return -ENOMEM;
1372
1373 wrapper->dev = dev;
1374 wrapper->base = devm_platform_ioremap_resource(pdev, index: 0);
1375 if (IS_ERR(ptr: wrapper->base))
1376 return PTR_ERR(ptr: wrapper->base);
1377
1378 desc = device_get_match_data(dev: &pdev->dev);
1379
1380 if (!has_acpi_companion(dev: &pdev->dev) && desc->num_clks) {
1381 int i;
1382
1383 wrapper->num_clks = min_t(unsigned int, desc->num_clks, MAX_CLKS);
1384
1385 for (i = 0; i < wrapper->num_clks; ++i)
1386 wrapper->clks[i].id = desc->clks[i];
1387
1388 ret = of_count_phandle_with_args(np: dev->of_node, list_name: "clocks", cells_name: "#clock-cells");
1389 if (ret < 0) {
1390 dev_err(dev, "invalid clocks property at %pOF\n", dev->of_node);
1391 return ret;
1392 }
1393
1394 if (ret < wrapper->num_clks) {
1395 dev_err(dev, "invalid clocks count at %pOF, expected %d entries\n",
1396 dev->of_node, wrapper->num_clks);
1397 return -EINVAL;
1398 }
1399
1400 ret = devm_clk_bulk_get(dev, num_clks: wrapper->num_clks, clks: wrapper->clks);
1401 if (ret) {
1402 dev_err(dev, "Err getting clks %d\n", ret);
1403 return ret;
1404 }
1405 }
1406
1407 dev_set_drvdata(dev, data: wrapper);
1408 dev_dbg(dev, "GENI SE Driver probed\n");
1409 return devm_of_platform_populate(dev);
1410}
1411
1412static const char * const qup_clks[] = {
1413 "m-ahb",
1414 "s-ahb",
1415};
1416
1417static const struct geni_se_desc qup_desc = {
1418 .clks = qup_clks,
1419 .num_clks = ARRAY_SIZE(qup_clks),
1420};
1421
1422static const struct geni_se_desc sa8255p_qup_desc = {};
1423
1424static const char * const i2c_master_hub_clks[] = {
1425 "s-ahb",
1426};
1427
1428static const struct geni_se_desc i2c_master_hub_desc = {
1429 .clks = i2c_master_hub_clks,
1430 .num_clks = ARRAY_SIZE(i2c_master_hub_clks),
1431};
1432
1433static const struct of_device_id geni_se_dt_match[] = {
1434 { .compatible = "qcom,geni-se-qup", .data = &qup_desc },
1435 { .compatible = "qcom,geni-se-i2c-master-hub", .data = &i2c_master_hub_desc },
1436 { .compatible = "qcom,sa8255p-geni-se-qup", .data = &sa8255p_qup_desc },
1437 {}
1438};
1439MODULE_DEVICE_TABLE(of, geni_se_dt_match);
1440
1441static struct platform_driver geni_se_driver = {
1442 .driver = {
1443 .name = "geni_se_qup",
1444 .of_match_table = geni_se_dt_match,
1445 },
1446 .probe = geni_se_probe,
1447};
1448module_platform_driver(geni_se_driver);
1449
1450MODULE_DESCRIPTION("GENI Serial Engine Driver");
1451MODULE_LICENSE("GPL v2");
1452

source code of linux/drivers/soc/qcom/qcom-geni-se.c