1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4	*/
5
6	#include <linux/signal.h>
7	#include <linux/slab.h>
8	#include <linux/module.h>
9	#include <linux/netdevice.h>
10	#include <linux/etherdevice.h>
11	#include <linux/mii.h>
12	#include <linux/ethtool.h>
13	#include <linux/phy.h>
14	#include <linux/usb.h>
15	#include <linux/crc32.h>
16	#include <linux/if_vlan.h>
17	#include <linux/uaccess.h>
18	#include <linux/list.h>
19	#include <linux/ip.h>
20	#include <linux/ipv6.h>
21	#include <net/ip6_checksum.h>
22	#include <uapi/linux/mdio.h>
23	#include <linux/mdio.h>
24	#include <linux/usb/cdc.h>
25	#include <linux/suspend.h>
26	#include <linux/atomic.h>
27	#include <linux/acpi.h>
28	#include <linux/firmware.h>
29	#include <crypto/sha2.h>
30	#include <linux/usb/r8152.h>
31	#include <net/gso.h>
32
33	/* Information for net-next */
34	#define NETNEXT_VERSION "12"
35
36	/* Information for net */
37	#define NET_VERSION "13"
38
39	#define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
40	#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
41	#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
42	#define MODULENAME "r8152"
43
44	#define R8152_PHY_ID 32
45
46	#define PLA_IDR 0xc000
47	#define PLA_RCR 0xc010
48	#define PLA_RCR1 0xc012
49	#define PLA_RMS 0xc016
50	#define PLA_RXFIFO_CTRL0 0xc0a0
51	#define PLA_RXFIFO_FULL 0xc0a2
52	#define PLA_RXFIFO_CTRL1 0xc0a4
53	#define PLA_RX_FIFO_FULL 0xc0a6
54	#define PLA_RXFIFO_CTRL2 0xc0a8
55	#define PLA_RX_FIFO_EMPTY 0xc0aa
56	#define PLA_DMY_REG0 0xc0b0
57	#define PLA_FMC 0xc0b4
58	#define PLA_CFG_WOL 0xc0b6
59	#define PLA_TEREDO_CFG 0xc0bc
60	#define PLA_TEREDO_WAKE_BASE 0xc0c4
61	#define PLA_MAR 0xcd00
62	#define PLA_BACKUP 0xd000
63	#define PLA_BDC_CR 0xd1a0
64	#define PLA_TEREDO_TIMER 0xd2cc
65	#define PLA_REALWOW_TIMER 0xd2e8
66	#define PLA_UPHY_TIMER 0xd388
67	#define PLA_SUSPEND_FLAG 0xd38a
68	#define PLA_INDICATE_FALG 0xd38c
69	#define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
70	#define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
71	#define PLA_EXTRA_STATUS 0xd398
72	#define PLA_GPHY_CTRL 0xd3ae
73	#define PLA_POL_GPIO_CTRL 0xdc6a
74	#define PLA_EFUSE_DATA 0xdd00
75	#define PLA_EFUSE_CMD 0xdd02
76	#define PLA_LEDSEL 0xdd90
77	#define PLA_LED_FEATURE 0xdd92
78	#define PLA_PHYAR 0xde00
79	#define PLA_BOOT_CTRL 0xe004
80	#define PLA_LWAKE_CTRL_REG 0xe007
81	#define PLA_GPHY_INTR_IMR 0xe022
82	#define PLA_EEE_CR 0xe040
83	#define PLA_EEE_TXTWSYS 0xe04c
84	#define PLA_EEE_TXTWSYS_2P5G 0xe058
85	#define PLA_EEEP_CR 0xe080
86	#define PLA_MAC_PWR_CTRL 0xe0c0
87	#define PLA_MAC_PWR_CTRL2 0xe0ca
88	#define PLA_MAC_PWR_CTRL3 0xe0cc
89	#define PLA_MAC_PWR_CTRL4 0xe0ce
90	#define PLA_WDT6_CTRL 0xe428
91	#define PLA_TCR0 0xe610
92	#define PLA_TCR1 0xe612
93	#define PLA_MTPS 0xe615
94	#define PLA_TXFIFO_CTRL 0xe618
95	#define PLA_TXFIFO_FULL 0xe61a
96	#define PLA_RSTTALLY 0xe800
97	#define PLA_CR 0xe813
98	#define PLA_CRWECR 0xe81c
99	#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
100	#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
101	#define PLA_CONFIG5 0xe822
102	#define PLA_PHY_PWR 0xe84c
103	#define PLA_OOB_CTRL 0xe84f
104	#define PLA_CPCR 0xe854
105	#define PLA_MISC_0 0xe858
106	#define PLA_MISC_1 0xe85a
107	#define PLA_OCP_GPHY_BASE 0xe86c
108	#define PLA_TALLYCNT 0xe890
109	#define PLA_SFF_STS_7 0xe8de
110	#define PLA_PHYSTATUS 0xe908
111	#define PLA_CONFIG6 0xe90a /* CONFIG6 */
112	#define PLA_USB_CFG 0xe952
113	#define PLA_BP_BA 0xfc26
114	#define PLA_BP_0 0xfc28
115	#define PLA_BP_1 0xfc2a
116	#define PLA_BP_2 0xfc2c
117	#define PLA_BP_3 0xfc2e
118	#define PLA_BP_4 0xfc30
119	#define PLA_BP_5 0xfc32
120	#define PLA_BP_6 0xfc34
121	#define PLA_BP_7 0xfc36
122	#define PLA_BP_EN 0xfc38
123
124	#define USB_USB2PHY 0xb41e
125	#define USB_SSPHYLINK1 0xb426
126	#define USB_SSPHYLINK2 0xb428
127	#define USB_L1_CTRL 0xb45e
128	#define USB_U2P3_CTRL 0xb460
129	#define USB_CSR_DUMMY1 0xb464
130	#define USB_CSR_DUMMY2 0xb466
131	#define USB_DEV_STAT 0xb808
132	#define USB_CONNECT_TIMER 0xcbf8
133	#define USB_MSC_TIMER 0xcbfc
134	#define USB_BURST_SIZE 0xcfc0
135	#define USB_FW_FIX_EN0 0xcfca
136	#define USB_FW_FIX_EN1 0xcfcc
137	#define USB_LPM_CONFIG 0xcfd8
138	#define USB_ECM_OPTION 0xcfee
139	#define USB_CSTMR 0xcfef /* RTL8153A */
140	#define USB_MISC_2 0xcfff
141	#define USB_ECM_OP 0xd26b
142	#define USB_GPHY_CTRL 0xd284
143	#define USB_SPEED_OPTION 0xd32a
144	#define USB_FW_CTRL 0xd334 /* RTL8153B */
145	#define USB_FC_TIMER 0xd340
146	#define USB_USB_CTRL 0xd406
147	#define USB_PHY_CTRL 0xd408
148	#define USB_TX_AGG 0xd40a
149	#define USB_RX_BUF_TH 0xd40c
150	#define USB_USB_TIMER 0xd428
151	#define USB_RX_EARLY_TIMEOUT 0xd42c
152	#define USB_RX_EARLY_SIZE 0xd42e
153	#define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
154	#define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
155	#define USB_TX_DMA 0xd434
156	#define USB_UPT_RXDMA_OWN 0xd437
157	#define USB_UPHY3_MDCMDIO 0xd480
158	#define USB_TOLERANCE 0xd490
159	#define USB_LPM_CTRL 0xd41a
160	#define USB_BMU_RESET 0xd4b0
161	#define USB_BMU_CONFIG 0xd4b4
162	#define USB_U1U2_TIMER 0xd4da
163	#define USB_FW_TASK 0xd4e8 /* RTL8153B */
164	#define USB_RX_AGGR_NUM 0xd4ee
165	#define USB_UPS_CTRL 0xd800
166	#define USB_POWER_CUT 0xd80a
167	#define USB_MISC_0 0xd81a
168	#define USB_MISC_1 0xd81f
169	#define USB_AFE_CTRL2 0xd824
170	#define USB_UPHY_XTAL 0xd826
171	#define USB_UPS_CFG 0xd842
172	#define USB_UPS_FLAGS 0xd848
173	#define USB_WDT1_CTRL 0xe404
174	#define USB_WDT11_CTRL 0xe43c
175	#define USB_BP_BA PLA_BP_BA
176	#define USB_BP_0 PLA_BP_0
177	#define USB_BP_1 PLA_BP_1
178	#define USB_BP_2 PLA_BP_2
179	#define USB_BP_3 PLA_BP_3
180	#define USB_BP_4 PLA_BP_4
181	#define USB_BP_5 PLA_BP_5
182	#define USB_BP_6 PLA_BP_6
183	#define USB_BP_7 PLA_BP_7
184	#define USB_BP_EN PLA_BP_EN /* RTL8153A */
185	#define USB_BP_8 0xfc38 /* RTL8153B */
186	#define USB_BP_9 0xfc3a
187	#define USB_BP_10 0xfc3c
188	#define USB_BP_11 0xfc3e
189	#define USB_BP_12 0xfc40
190	#define USB_BP_13 0xfc42
191	#define USB_BP_14 0xfc44
192	#define USB_BP_15 0xfc46
193	#define USB_BP2_EN 0xfc48
194
195	/* OCP Registers */
196	#define OCP_ALDPS_CONFIG 0x2010
197	#define OCP_EEE_CONFIG1 0x2080
198	#define OCP_EEE_CONFIG2 0x2092
199	#define OCP_EEE_CONFIG3 0x2094
200	#define OCP_BASE_MII 0xa400
201	#define OCP_EEE_AR 0xa41a
202	#define OCP_EEE_DATA 0xa41c
203	#define OCP_PHY_STATUS 0xa420
204	#define OCP_INTR_EN 0xa424
205	#define OCP_NCTL_CFG 0xa42c
206	#define OCP_POWER_CFG 0xa430
207	#define OCP_EEE_CFG 0xa432
208	#define OCP_SRAM_ADDR 0xa436
209	#define OCP_SRAM_DATA 0xa438
210	#define OCP_DOWN_SPEED 0xa442
211	#define OCP_EEE_ABLE 0xa5c4
212	#define OCP_EEE_ADV 0xa5d0
213	#define OCP_EEE_LPABLE 0xa5d2
214	#define OCP_10GBT_CTRL 0xa5d4
215	#define OCP_10GBT_STAT 0xa5d6
216	#define OCP_EEE_ADV2 0xa6d4
217	#define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
218	#define OCP_PHY_PATCH_STAT 0xb800
219	#define OCP_PHY_PATCH_CMD 0xb820
220	#define OCP_PHY_LOCK 0xb82e
221	#define OCP_ADC_IOFFSET 0xbcfc
222	#define OCP_ADC_CFG 0xbc06
223	#define OCP_SYSCLK_CFG 0xc416
224
225	/* SRAM Register */
226	#define SRAM_GREEN_CFG 0x8011
227	#define SRAM_LPF_CFG 0x8012
228	#define SRAM_GPHY_FW_VER 0x801e
229	#define SRAM_10M_AMP1 0x8080
230	#define SRAM_10M_AMP2 0x8082
231	#define SRAM_IMPEDANCE 0x8084
232	#define SRAM_PHY_LOCK 0xb82e
233
234	/* PLA_RCR */
235	#define RCR_AAP 0x00000001
236	#define RCR_APM 0x00000002
237	#define RCR_AM 0x00000004
238	#define RCR_AB 0x00000008
239	#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
240	#define SLOT_EN BIT(11)
241
242	/* PLA_RCR1 */
243	#define OUTER_VLAN BIT(7)
244	#define INNER_VLAN BIT(6)
245
246	/* PLA_RXFIFO_CTRL0 */
247	#define RXFIFO_THR1_NORMAL 0x00080002
248	#define RXFIFO_THR1_OOB 0x01800003
249
250	/* PLA_RXFIFO_FULL */
251	#define RXFIFO_FULL_MASK 0xfff
252
253	/* PLA_RXFIFO_CTRL1 */
254	#define RXFIFO_THR2_FULL 0x00000060
255	#define RXFIFO_THR2_HIGH 0x00000038
256	#define RXFIFO_THR2_OOB 0x0000004a
257	#define RXFIFO_THR2_NORMAL 0x00a0
258
259	/* PLA_RXFIFO_CTRL2 */
260	#define RXFIFO_THR3_FULL 0x00000078
261	#define RXFIFO_THR3_HIGH 0x00000048
262	#define RXFIFO_THR3_OOB 0x0000005a
263	#define RXFIFO_THR3_NORMAL 0x0110
264
265	/* PLA_TXFIFO_CTRL */
266	#define TXFIFO_THR_NORMAL 0x00400008
267	#define TXFIFO_THR_NORMAL2 0x01000008
268
269	/* PLA_DMY_REG0 */
270	#define ECM_ALDPS 0x0002
271
272	/* PLA_FMC */
273	#define FMC_FCR_MCU_EN 0x0001
274
275	/* PLA_EEEP_CR */
276	#define EEEP_CR_EEEP_TX 0x0002
277
278	/* PLA_WDT6_CTRL */
279	#define WDT6_SET_MODE 0x0010
280
281	/* PLA_TCR0 */
282	#define TCR0_TX_EMPTY 0x0800
283	#define TCR0_AUTO_FIFO 0x0080
284
285	/* PLA_TCR1 */
286	#define VERSION_MASK 0x7cf0
287	#define IFG_MASK (BIT(3) | BIT(9) | BIT(8))
288	#define IFG_144NS BIT(9)
289	#define IFG_96NS (BIT(9) | BIT(8))
290
291	/* PLA_MTPS */
292	#define MTPS_JUMBO (12 * 1024 / 64)
293	#define MTPS_DEFAULT (6 * 1024 / 64)
294
295	/* PLA_RSTTALLY */
296	#define TALLY_RESET 0x0001
297
298	/* PLA_CR */
299	#define CR_RST 0x10
300	#define CR_RE 0x08
301	#define CR_TE 0x04
302
303	/* PLA_CRWECR */
304	#define CRWECR_NORAML 0x00
305	#define CRWECR_CONFIG 0xc0
306
307	/* PLA_OOB_CTRL */
308	#define NOW_IS_OOB 0x80
309	#define TXFIFO_EMPTY 0x20
310	#define RXFIFO_EMPTY 0x10
311	#define LINK_LIST_READY 0x02
312	#define DIS_MCU_CLROOB 0x01
313	#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
314
315	/* PLA_MISC_1 */
316	#define RXDY_GATED_EN 0x0008
317
318	/* PLA_SFF_STS_7 */
319	#define RE_INIT_LL 0x8000
320	#define MCU_BORW_EN 0x4000
321
322	/* PLA_CPCR */
323	#define FLOW_CTRL_EN BIT(0)
324	#define CPCR_RX_VLAN 0x0040
325
326	/* PLA_CFG_WOL */
327	#define MAGIC_EN 0x0001
328
329	/* PLA_TEREDO_CFG */
330	#define TEREDO_SEL 0x8000
331	#define TEREDO_WAKE_MASK 0x7f00
332	#define TEREDO_RS_EVENT_MASK 0x00fe
333	#define OOB_TEREDO_EN 0x0001
334
335	/* PLA_BDC_CR */
336	#define ALDPS_PROXY_MODE 0x0001
337
338	/* PLA_EFUSE_CMD */
339	#define EFUSE_READ_CMD BIT(15)
340	#define EFUSE_DATA_BIT16 BIT(7)
341
342	/* PLA_CONFIG34 */
343	#define LINK_ON_WAKE_EN 0x0010
344	#define LINK_OFF_WAKE_EN 0x0008
345
346	/* PLA_CONFIG6 */
347	#define LANWAKE_CLR_EN BIT(0)
348
349	/* PLA_USB_CFG */
350	#define EN_XG_LIP BIT(1)
351	#define EN_G_LIP BIT(2)
352
353	/* PLA_CONFIG5 */
354	#define BWF_EN 0x0040
355	#define MWF_EN 0x0020
356	#define UWF_EN 0x0010
357	#define LAN_WAKE_EN 0x0002
358
359	/* PLA_LED_FEATURE */
360	#define LED_MODE_MASK 0x0700
361
362	/* PLA_PHY_PWR */
363	#define TX_10M_IDLE_EN 0x0080
364	#define PFM_PWM_SWITCH 0x0040
365	#define TEST_IO_OFF BIT(4)
366
367	/* PLA_MAC_PWR_CTRL */
368	#define D3_CLK_GATED_EN 0x00004000
369	#define MCU_CLK_RATIO 0x07010f07
370	#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
371	#define ALDPS_SPDWN_RATIO 0x0f87
372
373	/* PLA_MAC_PWR_CTRL2 */
374	#define EEE_SPDWN_RATIO 0x8007
375	#define MAC_CLK_SPDWN_EN BIT(15)
376	#define EEE_SPDWN_RATIO_MASK 0xff
377
378	/* PLA_MAC_PWR_CTRL3 */
379	#define PLA_MCU_SPDWN_EN BIT(14)
380	#define PKT_AVAIL_SPDWN_EN 0x0100
381	#define SUSPEND_SPDWN_EN 0x0004
382	#define U1U2_SPDWN_EN 0x0002
383	#define L1_SPDWN_EN 0x0001
384
385	/* PLA_MAC_PWR_CTRL4 */
386	#define PWRSAVE_SPDWN_EN 0x1000
387	#define RXDV_SPDWN_EN 0x0800
388	#define TX10MIDLE_EN 0x0100
389	#define IDLE_SPDWN_EN BIT(6)
390	#define TP100_SPDWN_EN 0x0020
391	#define TP500_SPDWN_EN 0x0010
392	#define TP1000_SPDWN_EN 0x0008
393	#define EEE_SPDWN_EN 0x0001
394
395	/* PLA_GPHY_INTR_IMR */
396	#define GPHY_STS_MSK 0x0001
397	#define SPEED_DOWN_MSK 0x0002
398	#define SPDWN_RXDV_MSK 0x0004
399	#define SPDWN_LINKCHG_MSK 0x0008
400
401	/* PLA_PHYAR */
402	#define PHYAR_FLAG 0x80000000
403
404	/* PLA_EEE_CR */
405	#define EEE_RX_EN 0x0001
406	#define EEE_TX_EN 0x0002
407
408	/* PLA_BOOT_CTRL */
409	#define AUTOLOAD_DONE 0x0002
410
411	/* PLA_LWAKE_CTRL_REG */
412	#define LANWAKE_PIN BIT(7)
413
414	/* PLA_SUSPEND_FLAG */
415	#define LINK_CHG_EVENT BIT(0)
416
417	/* PLA_INDICATE_FALG */
418	#define UPCOMING_RUNTIME_D3 BIT(0)
419
420	/* PLA_MACDBG_PRE and PLA_MACDBG_POST */
421	#define DEBUG_OE BIT(0)
422	#define DEBUG_LTSSM 0x0082
423
424	/* PLA_EXTRA_STATUS */
425	#define CUR_LINK_OK BIT(15)
426	#define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */
427	#define LINK_CHANGE_FLAG BIT(8)
428	#define POLL_LINK_CHG BIT(0)
429
430	/* PLA_GPHY_CTRL */
431	#define GPHY_FLASH BIT(1)
432
433	/* PLA_POL_GPIO_CTRL */
434	#define DACK_DET_EN BIT(15)
435	#define POL_GPHY_PATCH BIT(4)
436
437	/* USB_USB2PHY */
438	#define USB2PHY_SUSPEND 0x0001
439	#define USB2PHY_L1 0x0002
440
441	/* USB_SSPHYLINK1 */
442	#define DELAY_PHY_PWR_CHG BIT(1)
443
444	/* USB_SSPHYLINK2 */
445	#define pwd_dn_scale_mask 0x3ffe
446	#define pwd_dn_scale(x) ((x) << 1)
447
448	/* USB_CSR_DUMMY1 */
449	#define DYNAMIC_BURST 0x0001
450
451	/* USB_CSR_DUMMY2 */
452	#define EP4_FULL_FC 0x0001
453
454	/* USB_DEV_STAT */
455	#define STAT_SPEED_MASK 0x0006
456	#define STAT_SPEED_HIGH 0x0000
457	#define STAT_SPEED_FULL 0x0002
458
459	/* USB_FW_FIX_EN0 */
460	#define FW_FIX_SUSPEND BIT(14)
461
462	/* USB_FW_FIX_EN1 */
463	#define FW_IP_RESET_EN BIT(9)
464
465	/* USB_LPM_CONFIG */
466	#define LPM_U1U2_EN BIT(0)
467
468	/* USB_TX_AGG */
469	#define TX_AGG_MAX_THRESHOLD 0x03
470
471	/* USB_RX_BUF_TH */
472	#define RX_THR_SUPPER 0x0c350180
473	#define RX_THR_HIGH 0x7a120180
474	#define RX_THR_SLOW 0xffff0180
475	#define RX_THR_B 0x00010001
476
477	/* USB_TX_DMA */
478	#define TEST_MODE_DISABLE 0x00000001
479	#define TX_SIZE_ADJUST1 0x00000100
480
481	/* USB_BMU_RESET */
482	#define BMU_RESET_EP_IN 0x01
483	#define BMU_RESET_EP_OUT 0x02
484
485	/* USB_BMU_CONFIG */
486	#define ACT_ODMA BIT(1)
487
488	/* USB_UPT_RXDMA_OWN */
489	#define OWN_UPDATE BIT(0)
490	#define OWN_CLEAR BIT(1)
491
492	/* USB_FW_TASK */
493	#define FC_PATCH_TASK BIT(1)
494
495	/* USB_RX_AGGR_NUM */
496	#define RX_AGGR_NUM_MASK 0x1ff
497
498	/* USB_UPS_CTRL */
499	#define POWER_CUT 0x0100
500
501	/* USB_PM_CTRL_STATUS */
502	#define RESUME_INDICATE 0x0001
503
504	/* USB_ECM_OPTION */
505	#define BYPASS_MAC_RESET BIT(5)
506
507	/* USB_CSTMR */
508	#define FORCE_SUPER BIT(0)
509
510	/* USB_MISC_2 */
511	#define UPS_FORCE_PWR_DOWN BIT(0)
512
513	/* USB_ECM_OP */
514	#define EN_ALL_SPEED BIT(0)
515
516	/* USB_GPHY_CTRL */
517	#define GPHY_PATCH_DONE BIT(2)
518	#define BYPASS_FLASH BIT(5)
519	#define BACKUP_RESTRORE BIT(6)
520
521	/* USB_SPEED_OPTION */
522	#define RG_PWRDN_EN BIT(8)
523	#define ALL_SPEED_OFF BIT(9)
524
525	/* USB_FW_CTRL */
526	#define FLOW_CTRL_PATCH_OPT BIT(1)
527	#define AUTO_SPEEDUP BIT(3)
528	#define FLOW_CTRL_PATCH_2 BIT(8)
529
530	/* USB_FC_TIMER */
531	#define CTRL_TIMER_EN BIT(15)
532
533	/* USB_USB_CTRL */
534	#define CDC_ECM_EN BIT(3)
535	#define RX_AGG_DISABLE 0x0010
536	#define RX_ZERO_EN 0x0080
537
538	/* USB_U2P3_CTRL */
539	#define U2P3_ENABLE 0x0001
540	#define RX_DETECT8 BIT(3)
541
542	/* USB_POWER_CUT */
543	#define PWR_EN 0x0001
544	#define PHASE2_EN 0x0008
545	#define UPS_EN BIT(4)
546	#define USP_PREWAKE BIT(5)
547
548	/* USB_MISC_0 */
549	#define PCUT_STATUS 0x0001
550
551	/* USB_RX_EARLY_TIMEOUT */
552	#define COALESCE_SUPER 85000U
553	#define COALESCE_HIGH 250000U
554	#define COALESCE_SLOW 524280U
555
556	/* USB_WDT1_CTRL */
557	#define WTD1_EN BIT(0)
558
559	/* USB_WDT11_CTRL */
560	#define TIMER11_EN 0x0001
561
562	/* USB_LPM_CTRL */
563	/* bit 4 ~ 5: fifo empty boundary */
564	#define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
565	/* bit 2 ~ 3: LMP timer */
566	#define LPM_TIMER_MASK 0x0c
567	#define LPM_TIMER_500MS 0x04 /* 500 ms */
568	#define LPM_TIMER_500US 0x0c /* 500 us */
569	#define ROK_EXIT_LPM 0x02
570
571	/* USB_AFE_CTRL2 */
572	#define SEN_VAL_MASK 0xf800
573	#define SEN_VAL_NORMAL 0xa000
574	#define SEL_RXIDLE 0x0100
575
576	/* USB_UPHY_XTAL */
577	#define OOBS_POLLING BIT(8)
578
579	/* USB_UPS_CFG */
580	#define SAW_CNT_1MS_MASK 0x0fff
581	#define MID_REVERSE BIT(5) /* RTL8156A */
582
583	/* USB_UPS_FLAGS */
584	#define UPS_FLAGS_R_TUNE BIT(0)
585	#define UPS_FLAGS_EN_10M_CKDIV BIT(1)
586	#define UPS_FLAGS_250M_CKDIV BIT(2)
587	#define UPS_FLAGS_EN_ALDPS BIT(3)
588	#define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
589	#define UPS_FLAGS_SPEED_MASK (0xf << 16)
590	#define ups_flags_speed(x) ((x) << 16)
591	#define UPS_FLAGS_EN_EEE BIT(20)
592	#define UPS_FLAGS_EN_500M_EEE BIT(21)
593	#define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
594	#define UPS_FLAGS_EEE_PLLOFF_100 BIT(23)
595	#define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
596	#define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
597	#define UPS_FLAGS_EN_GREEN BIT(26)
598	#define UPS_FLAGS_EN_FLOW_CTR BIT(27)
599
600	enum spd_duplex {
601	NWAY_10M_HALF,
602	NWAY_10M_FULL,
603	NWAY_100M_HALF,
604	NWAY_100M_FULL,
605	NWAY_1000M_FULL,
606	FORCE_10M_HALF,
607	FORCE_10M_FULL,
608	FORCE_100M_HALF,
609	FORCE_100M_FULL,
610	FORCE_1000M_FULL,
611	NWAY_2500M_FULL,
612	};
613
614	/* OCP_ALDPS_CONFIG */
615	#define ENPWRSAVE 0x8000
616	#define ENPDNPS 0x0200
617	#define LINKENA 0x0100
618	#define DIS_SDSAVE 0x0010
619
620	/* OCP_PHY_STATUS */
621	#define PHY_STAT_MASK 0x0007
622	#define PHY_STAT_EXT_INIT 2
623	#define PHY_STAT_LAN_ON 3
624	#define PHY_STAT_PWRDN 5
625
626	/* OCP_INTR_EN */
627	#define INTR_SPEED_FORCE BIT(3)
628
629	/* OCP_NCTL_CFG */
630	#define PGA_RETURN_EN BIT(1)
631
632	/* OCP_POWER_CFG */
633	#define EEE_CLKDIV_EN 0x8000
634	#define EN_ALDPS 0x0004
635	#define EN_10M_PLLOFF 0x0001
636
637	/* OCP_EEE_CONFIG1 */
638	#define RG_TXLPI_MSK_HFDUP 0x8000
639	#define RG_MATCLR_EN 0x4000
640	#define EEE_10_CAP 0x2000
641	#define EEE_NWAY_EN 0x1000
642	#define TX_QUIET_EN 0x0200
643	#define RX_QUIET_EN 0x0100
644	#define sd_rise_time_mask 0x0070
645	#define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
646	#define RG_RXLPI_MSK_HFDUP 0x0008
647	#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
648
649	/* OCP_EEE_CONFIG2 */
650	#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
651	#define RG_DACQUIET_EN 0x0400
652	#define RG_LDVQUIET_EN 0x0200
653	#define RG_CKRSEL 0x0020
654	#define RG_EEEPRG_EN 0x0010
655
656	/* OCP_EEE_CONFIG3 */
657	#define fast_snr_mask 0xff80
658	#define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
659	#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
660	#define MSK_PH 0x0006 /* bit 0 ~ 3 */
661
662	/* OCP_EEE_AR */
663	/* bit[15:14] function */
664	#define FUN_ADDR 0x0000
665	#define FUN_DATA 0x4000
666	/* bit[4:0] device addr */
667
668	/* OCP_EEE_CFG */
669	#define CTAP_SHORT_EN 0x0040
670	#define EEE10_EN 0x0010
671
672	/* OCP_DOWN_SPEED */
673	#define EN_EEE_CMODE BIT(14)
674	#define EN_EEE_1000 BIT(13)
675	#define EN_EEE_100 BIT(12)
676	#define EN_10M_CLKDIV BIT(11)
677	#define EN_10M_BGOFF 0x0080
678
679	/* OCP_10GBT_CTRL */
680	#define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */
681
682	/* OCP_PHY_STATE */
683	#define TXDIS_STATE 0x01
684	#define ABD_STATE 0x02
685
686	/* OCP_PHY_PATCH_STAT */
687	#define PATCH_READY BIT(6)
688
689	/* OCP_PHY_PATCH_CMD */
690	#define PATCH_REQUEST BIT(4)
691
692	/* OCP_PHY_LOCK */
693	#define PATCH_LOCK BIT(0)
694
695	/* OCP_ADC_CFG */
696	#define CKADSEL_L 0x0100
697	#define ADC_EN 0x0080
698	#define EN_EMI_L 0x0040
699
700	/* OCP_SYSCLK_CFG */
701	#define sysclk_div_expo(x) (min(x, 5) << 8)
702	#define clk_div_expo(x) (min(x, 5) << 4)
703
704	/* SRAM_GREEN_CFG */
705	#define GREEN_ETH_EN BIT(15)
706	#define R_TUNE_EN BIT(11)
707
708	/* SRAM_LPF_CFG */
709	#define LPF_AUTO_TUNE 0x8000
710
711	/* SRAM_10M_AMP1 */
712	#define GDAC_IB_UPALL 0x0008
713
714	/* SRAM_10M_AMP2 */
715	#define AMP_DN 0x0200
716
717	/* SRAM_IMPEDANCE */
718	#define RX_DRIVING_MASK 0x6000
719
720	/* SRAM_PHY_LOCK */
721	#define PHY_PATCH_LOCK 0x0001
722
723	/* MAC PASSTHRU */
724	#define AD_MASK 0xfee0
725	#define BND_MASK 0x0004
726	#define BD_MASK 0x0001
727	#define EFUSE 0xcfdb
728	#define PASS_THRU_MASK 0x1
729
730	#define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
731
732	enum rtl_register_content {
733	_2500bps = BIT(10),
734	_1250bps = BIT(9),
735	_500bps = BIT(8),
736	_tx_flow = BIT(6),
737	_rx_flow = BIT(5),
738	_1000bps = 0x10,
739	_100bps = 0x08,
740	_10bps = 0x04,
741	LINK_STATUS = 0x02,
742	FULL_DUP = 0x01,
743	};
744
745	#define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS))
746	#define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow))
747
748	#define RTL8152_MAX_TX 4
749	#define RTL8152_MAX_RX 10
750	#define INTBUFSIZE 2
751	#define TX_ALIGN 4
752	#define RX_ALIGN 8
753
754	#define RTL8152_RX_MAX_PENDING 4096
755	#define RTL8152_RXFG_HEADSZ 256
756
757	#define INTR_LINK 0x0004
758
759	#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
760	#define RTL8153_RMS RTL8153_MAX_PACKET
761	#define RTL8152_TX_TIMEOUT (5 * HZ)
762	#define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)
763	#define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN)
764	#define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)
765
766	/* rtl8152 flags */
767	enum rtl8152_flags {
768	RTL8152_INACCESSIBLE = 0,
769	RTL8152_SET_RX_MODE,
770	WORK_ENABLE,
771	RTL8152_LINK_CHG,
772	SELECTIVE_SUSPEND,
773	PHY_RESET,
774	SCHEDULE_TASKLET,
775	GREEN_ETHERNET,
776	RX_EPROTO,
777	IN_PRE_RESET,
778	PROBED_WITH_NO_ERRORS,
779	PROBE_SHOULD_RETRY,
780	};
781
782	#define DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB 0x721e
783	#define DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK 0x3054
784	#define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082
785	#define DEVICE_ID_THINKPAD_USB_C_DONGLE 0x720c
786	#define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387
787	#define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3 0x3062
788	#define DEVICE_ID_THINKPAD_HYBRID_USB_C_DOCK 0xa359
789
790	struct tally_counter {
791	__le64 tx_packets;
792	__le64 rx_packets;
793	__le64 tx_errors;
794	__le32 rx_errors;
795	__le16 rx_missed;
796	__le16 align_errors;
797	__le32 tx_one_collision;
798	__le32 tx_multi_collision;
799	__le64 rx_unicast;
800	__le64 rx_broadcast;
801	__le32 rx_multicast;
802	__le16 tx_aborted;
803	__le16 tx_underrun;
804	};
805
806	struct rx_desc {
807	__le32 opts1;
808	#define RX_LEN_MASK 0x7fff
809
810	__le32 opts2;
811	#define RD_UDP_CS BIT(23)
812	#define RD_TCP_CS BIT(22)
813	#define RD_IPV6_CS BIT(20)
814	#define RD_IPV4_CS BIT(19)
815
816	__le32 opts3;
817	#define IPF BIT(23) /* IP checksum fail */
818	#define UDPF BIT(22) /* UDP checksum fail */
819	#define TCPF BIT(21) /* TCP checksum fail */
820	#define RX_VLAN_TAG BIT(16)
821
822	__le32 opts4;
823	__le32 opts5;
824	__le32 opts6;
825	};
826
827	struct tx_desc {
828	__le32 opts1;
829	#define TX_FS BIT(31) /* First segment of a packet */
830	#define TX_LS BIT(30) /* Final segment of a packet */
831	#define GTSENDV4 BIT(28)
832	#define GTSENDV6 BIT(27)
833	#define GTTCPHO_SHIFT 18
834	#define GTTCPHO_MAX 0x7fU
835	#define TX_LEN_MAX 0x3ffffU
836
837	__le32 opts2;
838	#define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
839	#define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
840	#define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
841	#define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
842	#define MSS_SHIFT 17
843	#define MSS_MAX 0x7ffU
844	#define TCPHO_SHIFT 17
845	#define TCPHO_MAX 0x7ffU
846	#define TX_VLAN_TAG BIT(16)
847	};
848
849	struct r8152;
850
851	struct rx_agg {
852	struct list_head list, info_list;
853	struct urb *urb;
854	struct r8152 *context;
855	struct page *page;
856	void *buffer;
857	};
858
859	struct tx_agg {
860	struct list_head list;
861	struct urb *urb;
862	struct r8152 *context;
863	void *buffer;
864	void *head;
865	u32 skb_num;
866	u32 skb_len;
867	};
868
869	struct r8152 {
870	unsigned long flags;
871	struct usb_device *udev;
872	struct napi_struct napi;
873	struct usb_interface *intf;
874	struct net_device *netdev;
875	struct urb *intr_urb;
876	struct tx_agg tx_info[RTL8152_MAX_TX];
877	struct list_head rx_info, rx_used;
878	struct list_head rx_done, tx_free;
879	struct sk_buff_head tx_queue, rx_queue;
880	spinlock_t rx_lock, tx_lock;
881	struct delayed_work schedule, hw_phy_work;
882	struct mii_if_info mii;
883	struct mutex control; /* use for hw setting */
884	#ifdef CONFIG_PM_SLEEP
885	struct notifier_block pm_notifier;
886	#endif
887	struct tasklet_struct tx_tl;
888
889	struct rtl_ops {
890	void (*init)(struct r8152 *tp);
891	int (*enable)(struct r8152 *tp);
892	void (*disable)(struct r8152 *tp);
893	void (*up)(struct r8152 *tp);
894	void (*down)(struct r8152 *tp);
895	void (*unload)(struct r8152 *tp);
896	int (*eee_get)(struct r8152 *tp, struct ethtool_keee *eee);
897	int (*eee_set)(struct r8152 *tp, struct ethtool_keee *eee);
898	bool (*in_nway)(struct r8152 *tp);
899	void (*hw_phy_cfg)(struct r8152 *tp);
900	void (*autosuspend_en)(struct r8152 *tp, bool enable);
901	void (*change_mtu)(struct r8152 *tp);
902	} rtl_ops;
903
904	struct ups_info {
905	u32 r_tune:1;
906	u32 _10m_ckdiv:1;
907	u32 _250m_ckdiv:1;
908	u32 aldps:1;
909	u32 lite_mode:2;
910	u32 speed_duplex:4;
911	u32 eee:1;
912	u32 eee_lite:1;
913	u32 eee_ckdiv:1;
914	u32 eee_plloff_100:1;
915	u32 eee_plloff_giga:1;
916	u32 eee_cmod_lv:1;
917	u32 green:1;
918	u32 flow_control:1;
919	u32 ctap_short_off:1;
920	} ups_info;
921
922	#define RTL_VER_SIZE 32
923
924	struct rtl_fw {
925	const char *fw_name;
926	const struct firmware *fw;
927
928	char version[RTL_VER_SIZE];
929	int (*pre_fw)(struct r8152 *tp);
930	int (*post_fw)(struct r8152 *tp);
931
932	bool retry;
933	} rtl_fw;
934
935	atomic_t rx_count;
936
937	bool eee_en;
938	int intr_interval;
939	u32 saved_wolopts;
940	u32 msg_enable;
941	u32 tx_qlen;
942	u32 coalesce;
943	u32 advertising;
944	u32 rx_buf_sz;
945	u32 rx_copybreak;
946	u32 rx_pending;
947	u32 fc_pause_on, fc_pause_off;
948
949	unsigned int pipe_in, pipe_out, pipe_intr, pipe_ctrl_in, pipe_ctrl_out;
950
951	u32 support_2500full:1;
952	u32 lenovo_macpassthru:1;
953	u32 dell_tb_rx_agg_bug:1;
954	u16 ocp_base;
955	u16 speed;
956	u16 eee_adv;
957	u8 *intr_buff;
958	u8 version;
959	u8 duplex;
960	u8 autoneg;
961
962	unsigned int reg_access_reset_count;
963	};
964
965	/**
966	* struct fw_block - block type and total length
967	* @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
968	* RTL_FW_USB and so on.
969	* @length: total length of the current block.
970	*/
971	struct fw_block {
972	__le32 type;
973	__le32 length;
974	} __packed;
975
976	/**
977	* struct fw_header - header of the firmware file
978	* @checksum: checksum of sha256 which is calculated from the whole file
979	* except the checksum field of the file. That is, calculate sha256
980	* from the version field to the end of the file.
981	* @version: version of this firmware.
982	* @blocks: the first firmware block of the file
983	*/
984	struct fw_header {
985	u8 checksum[32];
986	char version[RTL_VER_SIZE];
987	struct fw_block blocks[];
988	} __packed;
989
990	enum rtl8152_fw_flags {
991	FW_FLAGS_USB = 0,
992	FW_FLAGS_PLA,
993	FW_FLAGS_START,
994	FW_FLAGS_STOP,
995	FW_FLAGS_NC,
996	FW_FLAGS_NC1,
997	FW_FLAGS_NC2,
998	FW_FLAGS_UC2,
999	FW_FLAGS_UC,
1000	FW_FLAGS_SPEED_UP,
1001	FW_FLAGS_VER,
1002	};
1003
1004	enum rtl8152_fw_fixup_cmd {
1005	FW_FIXUP_AND = 0,
1006	FW_FIXUP_OR,
1007	FW_FIXUP_NOT,
1008	FW_FIXUP_XOR,
1009	};
1010
1011	struct fw_phy_set {
1012	__le16 addr;
1013	__le16 data;
1014	} __packed;
1015
1016	struct fw_phy_speed_up {
1017	struct fw_block blk_hdr;
1018	__le16 fw_offset;
1019	__le16 version;
1020	__le16 fw_reg;
1021	__le16 reserved;
1022	char info[];
1023	} __packed;
1024
1025	struct fw_phy_ver {
1026	struct fw_block blk_hdr;
1027	struct fw_phy_set ver;
1028	__le32 reserved;
1029	} __packed;
1030
1031	struct fw_phy_fixup {
1032	struct fw_block blk_hdr;
1033	struct fw_phy_set setting;
1034	__le16 bit_cmd;
1035	__le16 reserved;
1036	} __packed;
1037
1038	struct fw_phy_union {
1039	struct fw_block blk_hdr;
1040	__le16 fw_offset;
1041	__le16 fw_reg;
1042	struct fw_phy_set pre_set[2];
1043	struct fw_phy_set bp[8];
1044	struct fw_phy_set bp_en;
1045	u8 pre_num;
1046	u8 bp_num;
1047	char info[];
1048	} __packed;
1049
1050	/**
1051	* struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
1052	* The layout of the firmware block is:
1053	* <struct fw_mac> + <info> + <firmware data>.
1054	* @blk_hdr: firmware descriptor (type, length)
1055	* @fw_offset: offset of the firmware binary data. The start address of
1056	* the data would be the address of struct fw_mac + @fw_offset.
1057	* @fw_reg: the register to load the firmware. Depends on chip.
1058	* @bp_ba_addr: the register to write break point base address. Depends on
1059	* chip.
1060	* @bp_ba_value: break point base address. Depends on chip.
1061	* @bp_en_addr: the register to write break point enabled mask. Depends
1062	* on chip.
1063	* @bp_en_value: break point enabled mask. Depends on the firmware.
1064	* @bp_start: the start register of break points. Depends on chip.
1065	* @bp_num: the break point number which needs to be set for this firmware.
1066	* Depends on the firmware.
1067	* @bp: break points. Depends on firmware.
1068	* @reserved: reserved space (unused)
1069	* @fw_ver_reg: the register to store the fw version.
1070	* @fw_ver_data: the firmware version of the current type.
1071	* @info: additional information for debugging, and is followed by the
1072	* binary data of firmware.
1073	*/
1074	struct fw_mac {
1075	struct fw_block blk_hdr;
1076	__le16 fw_offset;
1077	__le16 fw_reg;
1078	__le16 bp_ba_addr;
1079	__le16 bp_ba_value;
1080	__le16 bp_en_addr;
1081	__le16 bp_en_value;
1082	__le16 bp_start;
1083	__le16 bp_num;
1084	__le16 bp[16]; /* any value determined by firmware */
1085	__le32 reserved;
1086	__le16 fw_ver_reg;
1087	u8 fw_ver_data;
1088	char info[];
1089	} __packed;
1090
1091	/**
1092	* struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
1093	* This is used to set patch key when loading the firmware of PHY.
1094	* @blk_hdr: firmware descriptor (type, length)
1095	* @key_reg: the register to write the patch key.
1096	* @key_data: patch key.
1097	* @reserved: reserved space (unused)
1098	*/
1099	struct fw_phy_patch_key {
1100	struct fw_block blk_hdr;
1101	__le16 key_reg;
1102	__le16 key_data;
1103	__le32 reserved;
1104	} __packed;
1105
1106	/**
1107	* struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
1108	* The layout of the firmware block is:
1109	* <struct fw_phy_nc> + <info> + <firmware data>.
1110	* @blk_hdr: firmware descriptor (type, length)
1111	* @fw_offset: offset of the firmware binary data. The start address of
1112	* the data would be the address of struct fw_phy_nc + @fw_offset.
1113	* @fw_reg: the register to load the firmware. Depends on chip.
1114	* @ba_reg: the register to write the base address. Depends on chip.
1115	* @ba_data: base address. Depends on chip.
1116	* @patch_en_addr: the register of enabling patch mode. Depends on chip.
1117	* @patch_en_value: patch mode enabled mask. Depends on the firmware.
1118	* @mode_reg: the regitster of switching the mode.
1119	* @mode_pre: the mode needing to be set before loading the firmware.
1120	* @mode_post: the mode to be set when finishing to load the firmware.
1121	* @reserved: reserved space (unused)
1122	* @bp_start: the start register of break points. Depends on chip.
1123	* @bp_num: the break point number which needs to be set for this firmware.
1124	* Depends on the firmware.
1125	* @bp: break points. Depends on firmware.
1126	* @info: additional information for debugging, and is followed by the
1127	* binary data of firmware.
1128	*/
1129	struct fw_phy_nc {
1130	struct fw_block blk_hdr;
1131	__le16 fw_offset;
1132	__le16 fw_reg;
1133	__le16 ba_reg;
1134	__le16 ba_data;
1135	__le16 patch_en_addr;
1136	__le16 patch_en_value;
1137	__le16 mode_reg;
1138	__le16 mode_pre;
1139	__le16 mode_post;
1140	__le16 reserved;
1141	__le16 bp_start;
1142	__le16 bp_num;
1143	__le16 bp[4];
1144	char info[];
1145	} __packed;
1146
1147	enum rtl_fw_type {
1148	RTL_FW_END = 0,
1149	RTL_FW_PLA,
1150	RTL_FW_USB,
1151	RTL_FW_PHY_START,
1152	RTL_FW_PHY_STOP,
1153	RTL_FW_PHY_NC,
1154	RTL_FW_PHY_FIXUP,
1155	RTL_FW_PHY_UNION_NC,
1156	RTL_FW_PHY_UNION_NC1,
1157	RTL_FW_PHY_UNION_NC2,
1158	RTL_FW_PHY_UNION_UC2,
1159	RTL_FW_PHY_UNION_UC,
1160	RTL_FW_PHY_UNION_MISC,
1161	RTL_FW_PHY_SPEED_UP,
1162	RTL_FW_PHY_VER,
1163	};
1164
1165	enum rtl_version {
1166	RTL_VER_UNKNOWN = 0,
1167	RTL_VER_01,
1168	RTL_VER_02,
1169	RTL_VER_03,
1170	RTL_VER_04,
1171	RTL_VER_05,
1172	RTL_VER_06,
1173	RTL_VER_07,
1174	RTL_VER_08,
1175	RTL_VER_09,
1176
1177	RTL_TEST_01,
1178	RTL_VER_10,
1179	RTL_VER_11,
1180	RTL_VER_12,
1181	RTL_VER_13,
1182	RTL_VER_14,
1183	RTL_VER_15,
1184
1185	RTL_VER_MAX
1186	};
1187
1188	enum tx_csum_stat {
1189	TX_CSUM_SUCCESS = 0,
1190	TX_CSUM_TSO,
1191	TX_CSUM_NONE
1192	};
1193
1194	#define RTL_ADVERTISED_10_HALF BIT(0)
1195	#define RTL_ADVERTISED_10_FULL BIT(1)
1196	#define RTL_ADVERTISED_100_HALF BIT(2)
1197	#define RTL_ADVERTISED_100_FULL BIT(3)
1198	#define RTL_ADVERTISED_1000_HALF BIT(4)
1199	#define RTL_ADVERTISED_1000_FULL BIT(5)
1200	#define RTL_ADVERTISED_2500_FULL BIT(6)
1201
1202	/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1203	* The RTL chips use a 64 element hash table based on the Ethernet CRC.
1204	*/
1205	static const int multicast_filter_limit = 32;
1206	static unsigned int agg_buf_sz = 16384;
1207
1208	#define RTL_LIMITED_TSO_SIZE (size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc))
1209
1210	/* If register access fails then we block access and issue a reset. If this
1211	* happens too many times in a row without a successful access then we stop
1212	* trying to reset and just leave access blocked.
1213	*/
1214	#define REGISTER_ACCESS_MAX_RESETS 3
1215
1216	static void rtl_set_inaccessible(struct r8152 *tp)
1217	{
1218	set_bit(nr: RTL8152_INACCESSIBLE, addr: &tp->flags);
1219	smp_mb__after_atomic();
1220	}
1221
1222	static void rtl_set_accessible(struct r8152 *tp)
1223	{
1224	clear_bit(nr: RTL8152_INACCESSIBLE, addr: &tp->flags);
1225	smp_mb__after_atomic();
1226	}
1227
1228	static
1229	int r8152_control_msg(struct r8152 *tp, unsigned int pipe, __u8 request,
1230	__u8 requesttype, __u16 value, __u16 index, void *data,
1231	__u16 size, const char *msg_tag)
1232	{
1233	struct usb_device *udev = tp->udev;
1234	int ret;
1235
1236	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1237	return -ENODEV;
1238
1239	ret = usb_control_msg(dev: udev, pipe, request, requesttype,
1240	value, index, data, size,
1241	USB_CTRL_GET_TIMEOUT);
1242
1243	/* No need to issue a reset to report an error if the USB device got
1244	* unplugged; just return immediately.
1245	*/
1246	if (ret == -ENODEV)
1247	return ret;
1248
1249	/* If the write was successful then we're done */
1250	if (ret >= 0) {
1251	tp->reg_access_reset_count = 0;
1252	return ret;
1253	}
1254
1255	dev_err(&udev->dev,
1256	"Failed to %s %d bytes at %#06x/%#06x (%d)\n",
1257	msg_tag, size, value, index, ret);
1258
1259	/* Block all future register access until we reset. Much of the code
1260	* in the driver doesn't check for errors. Notably, many parts of the
1261	* driver do a read/modify/write of a register value without
1262	* confirming that the read succeeded. Writing back modified garbage
1263	* like this can fully wedge the adapter, requiring a power cycle.
1264	*/
1265	rtl_set_inaccessible(tp);
1266
1267	/* If probe hasn't yet finished, then we'll request a retry of the
1268	* whole probe routine if we get any control transfer errors. We
1269	* never have to clear this bit since we free/reallocate the whole "tp"
1270	* structure if we retry probe.
1271	*/
1272	if (!test_bit(PROBED_WITH_NO_ERRORS, &tp->flags)) {
1273	set_bit(nr: PROBE_SHOULD_RETRY, addr: &tp->flags);
1274	return ret;
1275	}
1276
1277	/* Failing to access registers in pre-reset is not surprising since we
1278	* wouldn't be resetting if things were behaving normally. The register
1279	* access we do in pre-reset isn't truly mandatory--we're just reusing
1280	* the disable() function and trying to be nice by powering the
1281	* adapter down before resetting it. Thus, if we're in pre-reset,
1282	* we'll return right away and not try to queue up yet another reset.
1283	* We know the post-reset is already coming.
1284	*/
1285	if (test_bit(IN_PRE_RESET, &tp->flags))
1286	return ret;
1287
1288	if (tp->reg_access_reset_count < REGISTER_ACCESS_MAX_RESETS) {
1289	usb_queue_reset_device(dev: tp->intf);
1290	tp->reg_access_reset_count++;
1291	} else if (tp->reg_access_reset_count == REGISTER_ACCESS_MAX_RESETS) {
1292	dev_err(&udev->dev,
1293	"Tried to reset %d times; giving up.\n",
1294	REGISTER_ACCESS_MAX_RESETS);
1295	}
1296
1297	return ret;
1298	}
1299
1300	static
1301	int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1302	{
1303	int ret;
1304	void *tmp;
1305
1306	tmp = kmalloc(size, GFP_KERNEL);
1307	if (!tmp)
1308	return -ENOMEM;
1309
1310	ret = r8152_control_msg(tp, pipe: tp->pipe_ctrl_in,
1311	RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1312	value, index, data: tmp, size, msg_tag: "read");
1313
1314	if (ret < 0)
1315	memset(data, 0xff, size);
1316	else
1317	memcpy(data, tmp, size);
1318
1319	kfree(objp: tmp);
1320
1321	return ret;
1322	}
1323
1324	static
1325	int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1326	{
1327	int ret;
1328	void *tmp;
1329
1330	tmp = kmemdup(data, size, GFP_KERNEL);
1331	if (!tmp)
1332	return -ENOMEM;
1333
1334	ret = r8152_control_msg(tp, pipe: tp->pipe_ctrl_out,
1335	RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1336	value, index, data: tmp, size, msg_tag: "write");
1337
1338	kfree(objp: tmp);
1339
1340	return ret;
1341	}
1342
1343	static void rtl_set_unplug(struct r8152 *tp)
1344	{
1345	if (tp->udev->state == USB_STATE_NOTATTACHED)
1346	rtl_set_inaccessible(tp);
1347	}
1348
1349	static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1350	void *data, u16 type)
1351	{
1352	u16 limit = 64;
1353	int ret = 0;
1354
1355	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1356	return -ENODEV;
1357
1358	/* both size and indix must be 4 bytes align */
1359	if ((size & 3) || !size || (index & 3) || !data)
1360	return -EPERM;
1361
1362	if ((u32)index + (u32)size > 0xffff)
1363	return -EPERM;
1364
1365	while (size) {
1366	if (size > limit) {
1367	ret = get_registers(tp, value: index, index: type, size: limit, data);
1368	if (ret < 0)
1369	break;
1370
1371	index += limit;
1372	data += limit;
1373	size -= limit;
1374	} else {
1375	ret = get_registers(tp, value: index, index: type, size, data);
1376	if (ret < 0)
1377	break;
1378
1379	index += size;
1380	data += size;
1381	size = 0;
1382	break;
1383	}
1384	}
1385
1386	if (ret == -ENODEV)
1387	rtl_set_unplug(tp);
1388
1389	return ret;
1390	}
1391
1392	static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1393	u16 size, void *data, u16 type)
1394	{
1395	int ret;
1396	u16 byteen_start, byteen_end, byen;
1397	u16 limit = 512;
1398
1399	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1400	return -ENODEV;
1401
1402	/* both size and indix must be 4 bytes align */
1403	if ((size & 3) || !size || (index & 3) || !data)
1404	return -EPERM;
1405
1406	if ((u32)index + (u32)size > 0xffff)
1407	return -EPERM;
1408
1409	byteen_start = byteen & BYTE_EN_START_MASK;
1410	byteen_end = byteen & BYTE_EN_END_MASK;
1411
1412	byen = byteen_start | (byteen_start << 4);
1413
1414	/* Split the first DWORD if the byte_en is not 0xff */
1415	if (byen != BYTE_EN_DWORD) {
1416	ret = set_registers(tp, value: index, index: type | byen, size: 4, data);
1417	if (ret < 0)
1418	goto error1;
1419
1420	index += 4;
1421	data += 4;
1422	size -= 4;
1423	}
1424
1425	if (size) {
1426	byen = byteen_end | (byteen_end >> 4);
1427
1428	/* Split the last DWORD if the byte_en is not 0xff */
1429	if (byen != BYTE_EN_DWORD)
1430	size -= 4;
1431
1432	while (size) {
1433	if (size > limit) {
1434	ret = set_registers(tp, value: index,
1435	index: type | BYTE_EN_DWORD,
1436	size: limit, data);
1437	if (ret < 0)
1438	goto error1;
1439
1440	index += limit;
1441	data += limit;
1442	size -= limit;
1443	} else {
1444	ret = set_registers(tp, value: index,
1445	index: type | BYTE_EN_DWORD,
1446	size, data);
1447	if (ret < 0)
1448	goto error1;
1449
1450	index += size;
1451	data += size;
1452	size = 0;
1453	break;
1454	}
1455	}
1456
1457	/* Set the last DWORD */
1458	if (byen != BYTE_EN_DWORD)
1459	ret = set_registers(tp, value: index, index: type | byen, size: 4, data);
1460	}
1461
1462	error1:
1463	if (ret == -ENODEV)
1464	rtl_set_unplug(tp);
1465
1466	return ret;
1467	}
1468
1469	static inline
1470	int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1471	{
1472	return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1473	}
1474
1475	static inline
1476	int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1477	{
1478	return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1479	}
1480
1481	static inline
1482	int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1483	{
1484	return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1485	}
1486
1487	static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1488	{
1489	__le32 data;
1490
1491	generic_ocp_read(tp, index, size: sizeof(data), data: &data, type);
1492
1493	return __le32_to_cpu(data);
1494	}
1495
1496	static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1497	{
1498	__le32 tmp = __cpu_to_le32(data);
1499
1500	generic_ocp_write(tp, index, BYTE_EN_DWORD, size: sizeof(tmp), data: &tmp, type);
1501	}
1502
1503	static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1504	{
1505	u32 data;
1506	__le32 tmp;
1507	u16 byen = BYTE_EN_WORD;
1508	u8 shift = index & 2;
1509
1510	index &= ~3;
1511	byen <<= shift;
1512
1513	generic_ocp_read(tp, index, size: sizeof(tmp), data: &tmp, type: type | byen);
1514
1515	data = __le32_to_cpu(tmp);
1516	data >>= (shift * 8);
1517	data &= 0xffff;
1518
1519	return (u16)data;
1520	}
1521
1522	static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1523	{
1524	u32 mask = 0xffff;
1525	__le32 tmp;
1526	u16 byen = BYTE_EN_WORD;
1527	u8 shift = index & 2;
1528
1529	data &= mask;
1530
1531	if (index & 2) {
1532	byen <<= shift;
1533	mask <<= (shift * 8);
1534	data <<= (shift * 8);
1535	index &= ~3;
1536	}
1537
1538	tmp = __cpu_to_le32(data);
1539
1540	generic_ocp_write(tp, index, byteen: byen, size: sizeof(tmp), data: &tmp, type);
1541	}
1542
1543	static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1544	{
1545	u32 data;
1546	__le32 tmp;
1547	u8 shift = index & 3;
1548
1549	index &= ~3;
1550
1551	generic_ocp_read(tp, index, size: sizeof(tmp), data: &tmp, type);
1552
1553	data = __le32_to_cpu(tmp);
1554	data >>= (shift * 8);
1555	data &= 0xff;
1556
1557	return (u8)data;
1558	}
1559
1560	static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1561	{
1562	u32 mask = 0xff;
1563	__le32 tmp;
1564	u16 byen = BYTE_EN_BYTE;
1565	u8 shift = index & 3;
1566
1567	data &= mask;
1568
1569	if (index & 3) {
1570	byen <<= shift;
1571	mask <<= (shift * 8);
1572	data <<= (shift * 8);
1573	index &= ~3;
1574	}
1575
1576	tmp = __cpu_to_le32(data);
1577
1578	generic_ocp_write(tp, index, byteen: byen, size: sizeof(tmp), data: &tmp, type);
1579	}
1580
1581	static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1582	{
1583	u16 ocp_base, ocp_index;
1584
1585	ocp_base = addr & 0xf000;
1586	if (ocp_base != tp->ocp_base) {
1587	ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, data: ocp_base);
1588	tp->ocp_base = ocp_base;
1589	}
1590
1591	ocp_index = (addr & 0x0fff) | 0xb000;
1592	return ocp_read_word(tp, MCU_TYPE_PLA, index: ocp_index);
1593	}
1594
1595	static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1596	{
1597	u16 ocp_base, ocp_index;
1598
1599	ocp_base = addr & 0xf000;
1600	if (ocp_base != tp->ocp_base) {
1601	ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, data: ocp_base);
1602	tp->ocp_base = ocp_base;
1603	}
1604
1605	ocp_index = (addr & 0x0fff) | 0xb000;
1606	ocp_write_word(tp, MCU_TYPE_PLA, index: ocp_index, data);
1607	}
1608
1609	static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1610	{
1611	ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, data: value);
1612	}
1613
1614	static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1615	{
1616	return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1617	}
1618
1619	static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1620	{
1621	ocp_reg_write(tp, OCP_SRAM_ADDR, data: addr);
1622	ocp_reg_write(tp, OCP_SRAM_DATA, data);
1623	}
1624
1625	static u16 sram_read(struct r8152 *tp, u16 addr)
1626	{
1627	ocp_reg_write(tp, OCP_SRAM_ADDR, data: addr);
1628	return ocp_reg_read(tp, OCP_SRAM_DATA);
1629	}
1630
1631	static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1632	{
1633	struct r8152 *tp = netdev_priv(dev: netdev);
1634	int ret;
1635
1636	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1637	return -ENODEV;
1638
1639	if (phy_id != R8152_PHY_ID)
1640	return -EINVAL;
1641
1642	ret = r8152_mdio_read(tp, reg_addr: reg);
1643
1644	return ret;
1645	}
1646
1647	static
1648	void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1649	{
1650	struct r8152 *tp = netdev_priv(dev: netdev);
1651
1652	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1653	return;
1654
1655	if (phy_id != R8152_PHY_ID)
1656	return;
1657
1658	r8152_mdio_write(tp, reg_addr: reg, value: val);
1659	}
1660
1661	static int
1662	r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1663
1664	static int
1665	rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
1666	u32 advertising);
1667
1668	static int __rtl8152_set_mac_address(struct net_device *netdev,
1669	struct sockaddr_storage *addr,
1670	bool in_resume)
1671	{
1672	struct r8152 *tp = netdev_priv(dev: netdev);
1673	int ret = -EADDRNOTAVAIL;
1674
1675	if (!is_valid_ether_addr(addr: addr->__data))
1676	goto out1;
1677
1678	if (!in_resume) {
1679	ret = usb_autopm_get_interface(intf: tp->intf);
1680	if (ret < 0)
1681	goto out1;
1682	}
1683
1684	mutex_lock(&tp->control);
1685
1686	eth_hw_addr_set(dev: netdev, addr: addr->__data);
1687
1688	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1689	pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, size: 8, data: addr->__data);
1690	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1691
1692	mutex_unlock(lock: &tp->control);
1693
1694	if (!in_resume)
1695	usb_autopm_put_interface(intf: tp->intf);
1696	out1:
1697	return ret;
1698	}
1699
1700	static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1701	{
1702	return __rtl8152_set_mac_address(netdev, addr: p, in_resume: false);
1703	}
1704
1705	/* Devices containing proper chips can support a persistent
1706	* host system provided MAC address.
1707	* Examples of this are Dell TB15 and Dell WD15 docks
1708	*/
1709	static int vendor_mac_passthru_addr_read(struct r8152 *tp,
1710	struct sockaddr_storage *ss)
1711	{
1712	acpi_status status;
1713	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1714	union acpi_object *obj;
1715	int ret = -EINVAL;
1716	u32 ocp_data;
1717	unsigned char buf[6];
1718	char *mac_obj_name;
1719	acpi_object_type mac_obj_type;
1720	int mac_strlen;
1721
1722	if (tp->lenovo_macpassthru) {
1723	mac_obj_name = "\\MACA";
1724	mac_obj_type = ACPI_TYPE_STRING;
1725	mac_strlen = 0x16;
1726	} else {
1727	/* test for -AD variant of RTL8153 */
1728	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1729	if ((ocp_data & AD_MASK) == 0x1000) {
1730	/* test for MAC address pass-through bit */
1731	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1732	if ((ocp_data & PASS_THRU_MASK) != 1) {
1733	netif_dbg(tp, probe, tp->netdev,
1734	"No efuse for RTL8153-AD MAC pass through\n");
1735	return -ENODEV;
1736	}
1737	} else {
1738	/* test for RTL8153-BND and RTL8153-BD */
1739	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1740	if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1741	netif_dbg(tp, probe, tp->netdev,
1742	"Invalid variant for MAC pass through\n");
1743	return -ENODEV;
1744	}
1745	}
1746
1747	mac_obj_name = "\\_SB.AMAC";
1748	mac_obj_type = ACPI_TYPE_BUFFER;
1749	mac_strlen = 0x17;
1750	}
1751
1752	/* returns _AUXMAC_#AABBCCDDEEFF# */
1753	status = acpi_evaluate_object(NULL, pathname: mac_obj_name, NULL, return_object_buffer: &buffer);
1754	obj = (union acpi_object *)buffer.pointer;
1755	if (!ACPI_SUCCESS(status))
1756	return -ENODEV;
1757	if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1758	netif_warn(tp, probe, tp->netdev,
1759	"Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1760	obj->type, obj->string.length);
1761	goto amacout;
1762	}
1763
1764	if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1765	strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1766	netif_warn(tp, probe, tp->netdev,
1767	"Invalid header when reading pass-thru MAC addr\n");
1768	goto amacout;
1769	}
1770	ret = hex2bin(dst: buf, src: obj->string.pointer + 9, count: 6);
1771	if (!(ret == 0 && is_valid_ether_addr(addr: buf))) {
1772	netif_warn(tp, probe, tp->netdev,
1773	"Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1774	ret, buf);
1775	ret = -EINVAL;
1776	goto amacout;
1777	}
1778	memcpy(ss->__data, buf, 6);
1779	tp->netdev->addr_assign_type = NET_ADDR_STOLEN;
1780	netif_info(tp, probe, tp->netdev,
1781	"Using pass-thru MAC addr %pM\n", ss->__data);
1782
1783	amacout:
1784	kfree(objp: obj);
1785	return ret;
1786	}
1787
1788	static int determine_ethernet_addr(struct r8152 *tp,
1789	struct sockaddr_storage *ss)
1790	{
1791	struct net_device *dev = tp->netdev;
1792	int ret;
1793
1794	ss->ss_family = dev->type;
1795
1796	ret = eth_platform_get_mac_address(dev: &tp->udev->dev, mac_addr: ss->__data);
1797	if (ret < 0) {
1798	if (tp->version == RTL_VER_01) {
1799	ret = pla_ocp_read(tp, PLA_IDR, size: 8, data: ss->__data);
1800	} else {
1801	/* if device doesn't support MAC pass through this will
1802	* be expected to be non-zero
1803	*/
1804	ret = vendor_mac_passthru_addr_read(tp, ss);
1805	if (ret < 0)
1806	ret = pla_ocp_read(tp, PLA_BACKUP, size: 8,
1807	data: ss->__data);
1808	}
1809	}
1810
1811	if (ret < 0) {
1812	netif_err(tp, probe, dev, "Get ether addr fail\n");
1813	} else if (!is_valid_ether_addr(addr: ss->__data)) {
1814	netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1815	ss->__data);
1816	eth_hw_addr_random(dev);
1817	ether_addr_copy(dst: ss->__data, src: dev->dev_addr);
1818	netif_info(tp, probe, dev, "Random ether addr %pM\n",
1819	ss->__data);
1820	return 0;
1821	}
1822
1823	return ret;
1824	}
1825
1826	static int set_ethernet_addr(struct r8152 *tp, bool in_resume)
1827	{
1828	struct net_device *dev = tp->netdev;
1829	struct sockaddr_storage ss;
1830	int ret;
1831
1832	ret = determine_ethernet_addr(tp, ss: &ss);
1833	if (ret < 0)
1834	return ret;
1835
1836	if (tp->version == RTL_VER_01)
1837	eth_hw_addr_set(dev, addr: ss.__data);
1838	else
1839	ret = __rtl8152_set_mac_address(netdev: dev, addr: &ss, in_resume);
1840
1841	return ret;
1842	}
1843
1844	static void read_bulk_callback(struct urb *urb)
1845	{
1846	struct net_device *netdev;
1847	int status = urb->status;
1848	struct rx_agg *agg;
1849	struct r8152 *tp;
1850	unsigned long flags;
1851
1852	agg = urb->context;
1853	if (!agg)
1854	return;
1855
1856	tp = agg->context;
1857	if (!tp)
1858	return;
1859
1860	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1861	return;
1862
1863	if (!test_bit(WORK_ENABLE, &tp->flags))
1864	return;
1865
1866	netdev = tp->netdev;
1867
1868	/* When link down, the driver would cancel all bulks. */
1869	/* This avoid the re-submitting bulk */
1870	if (!netif_carrier_ok(dev: netdev))
1871	return;
1872
1873	usb_mark_last_busy(udev: tp->udev);
1874
1875	switch (status) {
1876	case 0:
1877	if (urb->actual_length < ETH_ZLEN)
1878	break;
1879
1880	spin_lock_irqsave(&tp->rx_lock, flags);
1881	list_add_tail(new: &agg->list, head: &tp->rx_done);
1882	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
1883	napi_schedule(n: &tp->napi);
1884	return;
1885	case -ESHUTDOWN:
1886	rtl_set_unplug(tp);
1887	netif_device_detach(dev: tp->netdev);
1888	return;
1889	case -EPROTO:
1890	urb->actual_length = 0;
1891	spin_lock_irqsave(&tp->rx_lock, flags);
1892	list_add_tail(new: &agg->list, head: &tp->rx_done);
1893	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
1894	set_bit(nr: RX_EPROTO, addr: &tp->flags);
1895	schedule_delayed_work(dwork: &tp->schedule, delay: 1);
1896	return;
1897	case -ENOENT:
1898	return; /* the urb is in unlink state */
1899	case -ETIME:
1900	if (net_ratelimit())
1901	netdev_warn(dev: netdev, format: "maybe reset is needed?\n");
1902	break;
1903	default:
1904	if (net_ratelimit())
1905	netdev_warn(dev: netdev, format: "Rx status %d\n", status);
1906	break;
1907	}
1908
1909	r8152_submit_rx(tp, agg, GFP_ATOMIC);
1910	}
1911
1912	static void write_bulk_callback(struct urb *urb)
1913	{
1914	struct net_device_stats *stats;
1915	struct net_device *netdev;
1916	struct tx_agg *agg;
1917	struct r8152 *tp;
1918	unsigned long flags;
1919	int status = urb->status;
1920
1921	agg = urb->context;
1922	if (!agg)
1923	return;
1924
1925	tp = agg->context;
1926	if (!tp)
1927	return;
1928
1929	netdev = tp->netdev;
1930	stats = &netdev->stats;
1931	if (status) {
1932	if (net_ratelimit())
1933	netdev_warn(dev: netdev, format: "Tx status %d\n", status);
1934	stats->tx_errors += agg->skb_num;
1935	} else {
1936	stats->tx_packets += agg->skb_num;
1937	stats->tx_bytes += agg->skb_len;
1938	}
1939
1940	spin_lock_irqsave(&tp->tx_lock, flags);
1941	list_add_tail(new: &agg->list, head: &tp->tx_free);
1942	spin_unlock_irqrestore(lock: &tp->tx_lock, flags);
1943
1944	usb_autopm_put_interface_async(intf: tp->intf);
1945
1946	if (!netif_carrier_ok(dev: netdev))
1947	return;
1948
1949	if (!test_bit(WORK_ENABLE, &tp->flags))
1950	return;
1951
1952	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1953	return;
1954
1955	if (!skb_queue_empty(list: &tp->tx_queue))
1956	tasklet_schedule(t: &tp->tx_tl);
1957	}
1958
1959	static void intr_callback(struct urb *urb)
1960	{
1961	struct r8152 *tp;
1962	__le16 *d;
1963	int status = urb->status;
1964	int res;
1965
1966	tp = urb->context;
1967	if (!tp)
1968	return;
1969
1970	if (!test_bit(WORK_ENABLE, &tp->flags))
1971	return;
1972
1973	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
1974	return;
1975
1976	switch (status) {
1977	case 0: /* success */
1978	break;
1979	case -ECONNRESET: /* unlink */
1980	case -ESHUTDOWN:
1981	netif_device_detach(dev: tp->netdev);
1982	fallthrough;
1983	case -ENOENT:
1984	case -EPROTO:
1985	netif_info(tp, intr, tp->netdev,
1986	"Stop submitting intr, status %d\n", status);
1987	return;
1988	case -EOVERFLOW:
1989	if (net_ratelimit())
1990	netif_info(tp, intr, tp->netdev,
1991	"intr status -EOVERFLOW\n");
1992	goto resubmit;
1993	/* -EPIPE: should clear the halt */
1994	default:
1995	netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1996	goto resubmit;
1997	}
1998
1999	d = urb->transfer_buffer;
2000	if (INTR_LINK & __le16_to_cpu(d[0])) {
2001	if (!netif_carrier_ok(dev: tp->netdev)) {
2002	set_bit(nr: RTL8152_LINK_CHG, addr: &tp->flags);
2003	schedule_delayed_work(dwork: &tp->schedule, delay: 0);
2004	}
2005	} else {
2006	if (netif_carrier_ok(dev: tp->netdev)) {
2007	netif_stop_queue(dev: tp->netdev);
2008	set_bit(nr: RTL8152_LINK_CHG, addr: &tp->flags);
2009	schedule_delayed_work(dwork: &tp->schedule, delay: 0);
2010	}
2011	}
2012
2013	resubmit:
2014	res = usb_submit_urb(urb, GFP_ATOMIC);
2015	if (res == -ENODEV) {
2016	rtl_set_unplug(tp);
2017	netif_device_detach(dev: tp->netdev);
2018	} else if (res) {
2019	netif_err(tp, intr, tp->netdev,
2020	"can't resubmit intr, status %d\n", res);
2021	}
2022	}
2023
2024	static inline void *rx_agg_align(void *data)
2025	{
2026	return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
2027	}
2028
2029	static inline void *tx_agg_align(void *data)
2030	{
2031	return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
2032	}
2033
2034	static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
2035	{
2036	list_del(entry: &agg->info_list);
2037
2038	usb_free_urb(urb: agg->urb);
2039	put_page(page: agg->page);
2040	kfree(objp: agg);
2041
2042	atomic_dec(v: &tp->rx_count);
2043	}
2044
2045	static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
2046	{
2047	struct net_device *netdev = tp->netdev;
2048	int node = netdev->dev.parent ? dev_to_node(dev: netdev->dev.parent) : -1;
2049	unsigned int order = get_order(size: tp->rx_buf_sz);
2050	struct rx_agg *rx_agg;
2051	unsigned long flags;
2052
2053	rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
2054	if (!rx_agg)
2055	return NULL;
2056
2057	rx_agg->page = alloc_pages(mflags | __GFP_COMP | __GFP_NOWARN, order);
2058	if (!rx_agg->page)
2059	goto free_rx;
2060
2061	rx_agg->buffer = page_address(rx_agg->page);
2062
2063	rx_agg->urb = usb_alloc_urb(iso_packets: 0, mem_flags: mflags);
2064	if (!rx_agg->urb)
2065	goto free_buf;
2066
2067	rx_agg->context = tp;
2068
2069	INIT_LIST_HEAD(list: &rx_agg->list);
2070	INIT_LIST_HEAD(list: &rx_agg->info_list);
2071	spin_lock_irqsave(&tp->rx_lock, flags);
2072	list_add_tail(new: &rx_agg->info_list, head: &tp->rx_info);
2073	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
2074
2075	atomic_inc(v: &tp->rx_count);
2076
2077	return rx_agg;
2078
2079	free_buf:
2080	__free_pages(page: rx_agg->page, order);
2081	free_rx:
2082	kfree(objp: rx_agg);
2083	return NULL;
2084	}
2085
2086	static void free_all_mem(struct r8152 *tp)
2087	{
2088	struct rx_agg *agg, *agg_next;
2089	unsigned long flags;
2090	int i;
2091
2092	spin_lock_irqsave(&tp->rx_lock, flags);
2093
2094	list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
2095	free_rx_agg(tp, agg);
2096
2097	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
2098
2099	WARN_ON(atomic_read(&tp->rx_count));
2100
2101	for (i = 0; i < RTL8152_MAX_TX; i++) {
2102	usb_free_urb(urb: tp->tx_info[i].urb);
2103	tp->tx_info[i].urb = NULL;
2104
2105	kfree(objp: tp->tx_info[i].buffer);
2106	tp->tx_info[i].buffer = NULL;
2107	tp->tx_info[i].head = NULL;
2108	}
2109
2110	usb_free_urb(urb: tp->intr_urb);
2111	tp->intr_urb = NULL;
2112
2113	kfree(objp: tp->intr_buff);
2114	tp->intr_buff = NULL;
2115	}
2116
2117	static int alloc_all_mem(struct r8152 *tp)
2118	{
2119	struct net_device *netdev = tp->netdev;
2120	struct usb_interface *intf = tp->intf;
2121	struct usb_host_interface *alt = intf->cur_altsetting;
2122	struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
2123	int node, i;
2124
2125	node = netdev->dev.parent ? dev_to_node(dev: netdev->dev.parent) : -1;
2126
2127	spin_lock_init(&tp->rx_lock);
2128	spin_lock_init(&tp->tx_lock);
2129	INIT_LIST_HEAD(list: &tp->rx_info);
2130	INIT_LIST_HEAD(list: &tp->tx_free);
2131	INIT_LIST_HEAD(list: &tp->rx_done);
2132	skb_queue_head_init(list: &tp->tx_queue);
2133	skb_queue_head_init(list: &tp->rx_queue);
2134	atomic_set(v: &tp->rx_count, i: 0);
2135
2136	for (i = 0; i < RTL8152_MAX_RX; i++) {
2137	if (!alloc_rx_agg(tp, GFP_KERNEL))
2138	goto err1;
2139	}
2140
2141	for (i = 0; i < RTL8152_MAX_TX; i++) {
2142	struct urb *urb;
2143	u8 *buf;
2144
2145	buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
2146	if (!buf)
2147	goto err1;
2148
2149	if (buf != tx_agg_align(data: buf)) {
2150	kfree(objp: buf);
2151	buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
2152	node);
2153	if (!buf)
2154	goto err1;
2155	}
2156
2157	urb = usb_alloc_urb(iso_packets: 0, GFP_KERNEL);
2158	if (!urb) {
2159	kfree(objp: buf);
2160	goto err1;
2161	}
2162
2163	INIT_LIST_HEAD(list: &tp->tx_info[i].list);
2164	tp->tx_info[i].context = tp;
2165	tp->tx_info[i].urb = urb;
2166	tp->tx_info[i].buffer = buf;
2167	tp->tx_info[i].head = tx_agg_align(data: buf);
2168
2169	list_add_tail(new: &tp->tx_info[i].list, head: &tp->tx_free);
2170	}
2171
2172	tp->intr_urb = usb_alloc_urb(iso_packets: 0, GFP_KERNEL);
2173	if (!tp->intr_urb)
2174	goto err1;
2175
2176	tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
2177	if (!tp->intr_buff)
2178	goto err1;
2179
2180	tp->intr_interval = (int)ep_intr->desc.bInterval;
2181	usb_fill_int_urb(urb: tp->intr_urb, dev: tp->udev, pipe: tp->pipe_intr,
2182	transfer_buffer: tp->intr_buff, INTBUFSIZE, complete_fn: intr_callback,
2183	context: tp, interval: tp->intr_interval);
2184
2185	return 0;
2186
2187	err1:
2188	free_all_mem(tp);
2189	return -ENOMEM;
2190	}
2191
2192	static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
2193	{
2194	struct tx_agg *agg = NULL;
2195	unsigned long flags;
2196
2197	if (list_empty(head: &tp->tx_free))
2198	return NULL;
2199
2200	spin_lock_irqsave(&tp->tx_lock, flags);
2201	if (!list_empty(head: &tp->tx_free)) {
2202	struct list_head *cursor;
2203
2204	cursor = tp->tx_free.next;
2205	list_del_init(entry: cursor);
2206	agg = list_entry(cursor, struct tx_agg, list);
2207	}
2208	spin_unlock_irqrestore(lock: &tp->tx_lock, flags);
2209
2210	return agg;
2211	}
2212
2213	/* r8152_csum_workaround()
2214	* The hw limits the value of the transport offset. When the offset is out of
2215	* range, calculate the checksum by sw.
2216	*/
2217	static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
2218	struct sk_buff_head *list)
2219	{
2220	if (skb_shinfo(skb)->gso_size) {
2221	netdev_features_t features = tp->netdev->features;
2222	struct sk_buff *segs, *seg, *next;
2223	struct sk_buff_head seg_list;
2224
2225	features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
2226	segs = skb_gso_segment(skb, features);
2227	if (IS_ERR(ptr: segs) || !segs)
2228	goto drop;
2229
2230	__skb_queue_head_init(list: &seg_list);
2231
2232	skb_list_walk_safe(segs, seg, next) {
2233	skb_mark_not_on_list(skb: seg);
2234	__skb_queue_tail(list: &seg_list, newsk: seg);
2235	}
2236
2237	skb_queue_splice(list: &seg_list, head: list);
2238	dev_kfree_skb(skb);
2239	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2240	if (skb_checksum_help(skb) < 0)
2241	goto drop;
2242
2243	__skb_queue_head(list, newsk: skb);
2244	} else {
2245	struct net_device_stats *stats;
2246
2247	drop:
2248	stats = &tp->netdev->stats;
2249	stats->tx_dropped++;
2250	dev_kfree_skb(skb);
2251	}
2252	}
2253
2254	static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
2255	{
2256	if (skb_vlan_tag_present(skb)) {
2257	u32 opts2;
2258
2259	opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
2260	desc->opts2 |= cpu_to_le32(opts2);
2261	}
2262	}
2263
2264	static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
2265	{
2266	u32 opts2 = le32_to_cpu(desc->opts2);
2267
2268	if (opts2 & RX_VLAN_TAG)
2269	__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2270	swab16(opts2 & 0xffff));
2271	}
2272
2273	static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
2274	struct sk_buff *skb, u32 len)
2275	{
2276	u32 mss = skb_shinfo(skb)->gso_size;
2277	u32 opts1, opts2 = 0;
2278	int ret = TX_CSUM_SUCCESS;
2279
2280	WARN_ON_ONCE(len > TX_LEN_MAX);
2281
2282	opts1 = len | TX_FS | TX_LS;
2283
2284	if (mss) {
2285	u32 transport_offset = (u32)skb_transport_offset(skb);
2286
2287	if (transport_offset > GTTCPHO_MAX) {
2288	netif_warn(tp, tx_err, tp->netdev,
2289	"Invalid transport offset 0x%x for TSO\n",
2290	transport_offset);
2291	ret = TX_CSUM_TSO;
2292	goto unavailable;
2293	}
2294
2295	switch (vlan_get_protocol(skb)) {
2296	case htons(ETH_P_IP):
2297	opts1 |= GTSENDV4;
2298	break;
2299
2300	case htons(ETH_P_IPV6):
2301	if (skb_cow_head(skb, headroom: 0)) {
2302	ret = TX_CSUM_TSO;
2303	goto unavailable;
2304	}
2305	tcp_v6_gso_csum_prep(skb);
2306	opts1 |= GTSENDV6;
2307	break;
2308
2309	default:
2310	WARN_ON_ONCE(1);
2311	break;
2312	}
2313
2314	opts1 |= transport_offset << GTTCPHO_SHIFT;
2315	opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
2316	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2317	u32 transport_offset = (u32)skb_transport_offset(skb);
2318	u8 ip_protocol;
2319
2320	if (transport_offset > TCPHO_MAX) {
2321	netif_warn(tp, tx_err, tp->netdev,
2322	"Invalid transport offset 0x%x\n",
2323	transport_offset);
2324	ret = TX_CSUM_NONE;
2325	goto unavailable;
2326	}
2327
2328	switch (vlan_get_protocol(skb)) {
2329	case htons(ETH_P_IP):
2330	opts2 |= IPV4_CS;
2331	ip_protocol = ip_hdr(skb)->protocol;
2332	break;
2333
2334	case htons(ETH_P_IPV6):
2335	opts2 |= IPV6_CS;
2336	ip_protocol = ipv6_hdr(skb)->nexthdr;
2337	break;
2338
2339	default:
2340	ip_protocol = IPPROTO_RAW;
2341	break;
2342	}
2343
2344	if (ip_protocol == IPPROTO_TCP)
2345	opts2 |= TCP_CS;
2346	else if (ip_protocol == IPPROTO_UDP)
2347	opts2 |= UDP_CS;
2348	else
2349	WARN_ON_ONCE(1);
2350
2351	opts2 |= transport_offset << TCPHO_SHIFT;
2352	}
2353
2354	desc->opts2 = cpu_to_le32(opts2);
2355	desc->opts1 = cpu_to_le32(opts1);
2356
2357	unavailable:
2358	return ret;
2359	}
2360
2361	static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2362	{
2363	struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2364	int remain, ret;
2365	u8 *tx_data;
2366
2367	__skb_queue_head_init(list: &skb_head);
2368	spin_lock(lock: &tx_queue->lock);
2369	skb_queue_splice_init(list: tx_queue, head: &skb_head);
2370	spin_unlock(lock: &tx_queue->lock);
2371
2372	tx_data = agg->head;
2373	agg->skb_num = 0;
2374	agg->skb_len = 0;
2375	remain = agg_buf_sz;
2376
2377	while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2378	struct tx_desc *tx_desc;
2379	struct sk_buff *skb;
2380	unsigned int len;
2381
2382	skb = __skb_dequeue(list: &skb_head);
2383	if (!skb)
2384	break;
2385
2386	len = skb->len + sizeof(*tx_desc);
2387
2388	if (len > remain) {
2389	__skb_queue_head(list: &skb_head, newsk: skb);
2390	break;
2391	}
2392
2393	tx_data = tx_agg_align(data: tx_data);
2394	tx_desc = (struct tx_desc *)tx_data;
2395
2396	if (r8152_tx_csum(tp, desc: tx_desc, skb, len: skb->len)) {
2397	r8152_csum_workaround(tp, skb, list: &skb_head);
2398	continue;
2399	}
2400
2401	rtl_tx_vlan_tag(desc: tx_desc, skb);
2402
2403	tx_data += sizeof(*tx_desc);
2404
2405	len = skb->len;
2406	if (skb_copy_bits(skb, offset: 0, to: tx_data, len) < 0) {
2407	struct net_device_stats *stats = &tp->netdev->stats;
2408
2409	stats->tx_dropped++;
2410	dev_kfree_skb_any(skb);
2411	tx_data -= sizeof(*tx_desc);
2412	continue;
2413	}
2414
2415	tx_data += len;
2416	agg->skb_len += len;
2417	agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2418
2419	dev_kfree_skb_any(skb);
2420
2421	remain = agg_buf_sz - (int)(tx_agg_align(data: tx_data) - agg->head);
2422
2423	if (tp->dell_tb_rx_agg_bug)
2424	break;
2425	}
2426
2427	if (!skb_queue_empty(list: &skb_head)) {
2428	spin_lock(lock: &tx_queue->lock);
2429	skb_queue_splice(list: &skb_head, head: tx_queue);
2430	spin_unlock(lock: &tx_queue->lock);
2431	}
2432
2433	netif_tx_lock(dev: tp->netdev);
2434
2435	if (netif_queue_stopped(dev: tp->netdev) &&
2436	skb_queue_len(list_: &tp->tx_queue) < tp->tx_qlen)
2437	netif_wake_queue(dev: tp->netdev);
2438
2439	netif_tx_unlock(dev: tp->netdev);
2440
2441	ret = usb_autopm_get_interface_async(intf: tp->intf);
2442	if (ret < 0)
2443	goto out_tx_fill;
2444
2445	usb_fill_bulk_urb(urb: agg->urb, dev: tp->udev, pipe: tp->pipe_out,
2446	transfer_buffer: agg->head, buffer_length: (int)(tx_data - (u8 *)agg->head),
2447	complete_fn: (usb_complete_t)write_bulk_callback, context: agg);
2448
2449	ret = usb_submit_urb(urb: agg->urb, GFP_ATOMIC);
2450	if (ret < 0)
2451	usb_autopm_put_interface_async(intf: tp->intf);
2452
2453	out_tx_fill:
2454	return ret;
2455	}
2456
2457	static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2458	{
2459	u8 checksum = CHECKSUM_NONE;
2460	u32 opts2, opts3;
2461
2462	if (!(tp->netdev->features & NETIF_F_RXCSUM))
2463	goto return_result;
2464
2465	opts2 = le32_to_cpu(rx_desc->opts2);
2466	opts3 = le32_to_cpu(rx_desc->opts3);
2467
2468	if (opts2 & RD_IPV4_CS) {
2469	if (opts3 & IPF)
2470	checksum = CHECKSUM_NONE;
2471	else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2472	checksum = CHECKSUM_UNNECESSARY;
2473	else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2474	checksum = CHECKSUM_UNNECESSARY;
2475	} else if (opts2 & RD_IPV6_CS) {
2476	if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2477	checksum = CHECKSUM_UNNECESSARY;
2478	else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2479	checksum = CHECKSUM_UNNECESSARY;
2480	}
2481
2482	return_result:
2483	return checksum;
2484	}
2485
2486	static inline bool rx_count_exceed(struct r8152 *tp)
2487	{
2488	return atomic_read(v: &tp->rx_count) > RTL8152_MAX_RX;
2489	}
2490
2491	static inline int agg_offset(struct rx_agg *agg, void *addr)
2492	{
2493	return (int)(addr - agg->buffer);
2494	}
2495
2496	static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2497	{
2498	struct rx_agg *agg, *agg_next, *agg_free = NULL;
2499	unsigned long flags;
2500
2501	spin_lock_irqsave(&tp->rx_lock, flags);
2502
2503	list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2504	if (page_count(page: agg->page) == 1) {
2505	if (!agg_free) {
2506	list_del_init(entry: &agg->list);
2507	agg_free = agg;
2508	continue;
2509	}
2510	if (rx_count_exceed(tp)) {
2511	list_del_init(entry: &agg->list);
2512	free_rx_agg(tp, agg);
2513	}
2514	break;
2515	}
2516	}
2517
2518	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
2519
2520	if (!agg_free && atomic_read(v: &tp->rx_count) < tp->rx_pending)
2521	agg_free = alloc_rx_agg(tp, mflags);
2522
2523	return agg_free;
2524	}
2525
2526	static int rx_bottom(struct r8152 *tp, int budget)
2527	{
2528	unsigned long flags;
2529	struct list_head *cursor, *next, rx_queue;
2530	int ret = 0, work_done = 0;
2531	struct napi_struct *napi = &tp->napi;
2532
2533	if (!skb_queue_empty(list: &tp->rx_queue)) {
2534	while (work_done < budget) {
2535	struct sk_buff *skb = __skb_dequeue(list: &tp->rx_queue);
2536	struct net_device *netdev = tp->netdev;
2537	struct net_device_stats *stats = &netdev->stats;
2538	unsigned int pkt_len;
2539
2540	if (!skb)
2541	break;
2542
2543	pkt_len = skb->len;
2544	napi_gro_receive(napi, skb);
2545	work_done++;
2546	stats->rx_packets++;
2547	stats->rx_bytes += pkt_len;
2548	}
2549	}
2550
2551	if (list_empty(head: &tp->rx_done) || work_done >= budget)
2552	goto out1;
2553
2554	clear_bit(nr: RX_EPROTO, addr: &tp->flags);
2555	INIT_LIST_HEAD(list: &rx_queue);
2556	spin_lock_irqsave(&tp->rx_lock, flags);
2557	list_splice_init(list: &tp->rx_done, head: &rx_queue);
2558	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
2559
2560	list_for_each_safe(cursor, next, &rx_queue) {
2561	struct rx_desc *rx_desc;
2562	struct rx_agg *agg, *agg_free;
2563	int len_used = 0;
2564	struct urb *urb;
2565	u8 *rx_data;
2566
2567	/* A bulk transfer of USB may contain may packets, so the
2568	* total packets may more than the budget. Deal with all
2569	* packets in current bulk transfer, and stop to handle the
2570	* next bulk transfer until next schedule, if budget is
2571	* exhausted.
2572	*/
2573	if (work_done >= budget)
2574	break;
2575
2576	list_del_init(entry: cursor);
2577
2578	agg = list_entry(cursor, struct rx_agg, list);
2579	urb = agg->urb;
2580	if (urb->status != 0 || urb->actual_length < ETH_ZLEN)
2581	goto submit;
2582
2583	agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2584
2585	rx_desc = agg->buffer;
2586	rx_data = agg->buffer;
2587	len_used += sizeof(struct rx_desc);
2588
2589	while (urb->actual_length > len_used) {
2590	struct net_device *netdev = tp->netdev;
2591	struct net_device_stats *stats = &netdev->stats;
2592	unsigned int pkt_len, rx_frag_head_sz, len;
2593	struct sk_buff *skb;
2594	bool use_frags;
2595
2596	WARN_ON_ONCE(skb_queue_len(&tp->rx_queue) >= 1000);
2597
2598	pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2599	if (pkt_len < ETH_ZLEN)
2600	break;
2601
2602	len_used += pkt_len;
2603	if (urb->actual_length < len_used)
2604	break;
2605
2606	pkt_len -= ETH_FCS_LEN;
2607	len = pkt_len;
2608	rx_data += sizeof(struct rx_desc);
2609
2610	if (!agg_free || tp->rx_copybreak > len)
2611	use_frags = false;
2612	else
2613	use_frags = true;
2614
2615	if (use_frags) {
2616	/* If the budget is exhausted, the packet
2617	* would be queued in the driver. That is,
2618	* napi_gro_frags() wouldn't be called, so
2619	* we couldn't use napi_get_frags().
2620	*/
2621	if (work_done >= budget) {
2622	rx_frag_head_sz = tp->rx_copybreak;
2623	skb = napi_alloc_skb(napi,
2624	length: rx_frag_head_sz);
2625	} else {
2626	rx_frag_head_sz = 0;
2627	skb = napi_get_frags(napi);
2628	}
2629	} else {
2630	rx_frag_head_sz = 0;
2631	skb = napi_alloc_skb(napi, length: len);
2632	}
2633
2634	if (!skb) {
2635	stats->rx_dropped++;
2636	goto find_next_rx;
2637	}
2638
2639	skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2640	rtl_rx_vlan_tag(desc: rx_desc, skb);
2641
2642	if (use_frags) {
2643	if (rx_frag_head_sz) {
2644	memcpy(skb->data, rx_data,
2645	rx_frag_head_sz);
2646	skb_put(skb, len: rx_frag_head_sz);
2647	len -= rx_frag_head_sz;
2648	rx_data += rx_frag_head_sz;
2649	skb->protocol = eth_type_trans(skb,
2650	dev: netdev);
2651	}
2652
2653	skb_add_rx_frag(skb, i: 0, page: agg->page,
2654	off: agg_offset(agg, addr: rx_data),
2655	size: len, SKB_DATA_ALIGN(len));
2656	get_page(page: agg->page);
2657	} else {
2658	memcpy(skb->data, rx_data, len);
2659	skb_put(skb, len);
2660	skb->protocol = eth_type_trans(skb, dev: netdev);
2661	}
2662
2663	if (work_done < budget) {
2664	if (use_frags)
2665	napi_gro_frags(napi);
2666	else
2667	napi_gro_receive(napi, skb);
2668
2669	work_done++;
2670	stats->rx_packets++;
2671	stats->rx_bytes += pkt_len;
2672	} else {
2673	__skb_queue_tail(list: &tp->rx_queue, newsk: skb);
2674	}
2675
2676	find_next_rx:
2677	rx_data = rx_agg_align(data: rx_data + len + ETH_FCS_LEN);
2678	rx_desc = (struct rx_desc *)rx_data;
2679	len_used = agg_offset(agg, addr: rx_data);
2680	len_used += sizeof(struct rx_desc);
2681	}
2682
2683	WARN_ON(!agg_free && page_count(agg->page) > 1);
2684
2685	if (agg_free) {
2686	spin_lock_irqsave(&tp->rx_lock, flags);
2687	if (page_count(page: agg->page) == 1) {
2688	list_add(new: &agg_free->list, head: &tp->rx_used);
2689	} else {
2690	list_add_tail(new: &agg->list, head: &tp->rx_used);
2691	agg = agg_free;
2692	urb = agg->urb;
2693	}
2694	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
2695	}
2696
2697	submit:
2698	if (!ret) {
2699	ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2700	} else {
2701	urb->actual_length = 0;
2702	list_add_tail(new: &agg->list, head: next);
2703	}
2704	}
2705
2706	/* Splice the remained list back to rx_done for next schedule */
2707	if (!list_empty(head: &rx_queue)) {
2708	spin_lock_irqsave(&tp->rx_lock, flags);
2709	list_splice(list: &rx_queue, head: &tp->rx_done);
2710	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
2711	}
2712
2713	out1:
2714	return work_done;
2715	}
2716
2717	static void tx_bottom(struct r8152 *tp)
2718	{
2719	int res;
2720
2721	do {
2722	struct net_device *netdev = tp->netdev;
2723	struct tx_agg *agg;
2724
2725	if (skb_queue_empty(list: &tp->tx_queue))
2726	break;
2727
2728	agg = r8152_get_tx_agg(tp);
2729	if (!agg)
2730	break;
2731
2732	res = r8152_tx_agg_fill(tp, agg);
2733	if (!res)
2734	continue;
2735
2736	if (res == -ENODEV) {
2737	rtl_set_unplug(tp);
2738	netif_device_detach(dev: netdev);
2739	} else {
2740	struct net_device_stats *stats = &netdev->stats;
2741	unsigned long flags;
2742
2743	netif_warn(tp, tx_err, netdev,
2744	"failed tx_urb %d\n", res);
2745	stats->tx_dropped += agg->skb_num;
2746
2747	spin_lock_irqsave(&tp->tx_lock, flags);
2748	list_add_tail(new: &agg->list, head: &tp->tx_free);
2749	spin_unlock_irqrestore(lock: &tp->tx_lock, flags);
2750	}
2751	} while (res == 0);
2752	}
2753
2754	static void bottom_half(struct tasklet_struct *t)
2755	{
2756	struct r8152 *tp = from_tasklet(tp, t, tx_tl);
2757
2758	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
2759	return;
2760
2761	if (!test_bit(WORK_ENABLE, &tp->flags))
2762	return;
2763
2764	/* When link down, the driver would cancel all bulks. */
2765	/* This avoid the re-submitting bulk */
2766	if (!netif_carrier_ok(dev: tp->netdev))
2767	return;
2768
2769	clear_bit(nr: SCHEDULE_TASKLET, addr: &tp->flags);
2770
2771	tx_bottom(tp);
2772	}
2773
2774	static int r8152_poll(struct napi_struct *napi, int budget)
2775	{
2776	struct r8152 *tp = container_of(napi, struct r8152, napi);
2777	int work_done;
2778
2779	if (!budget)
2780	return 0;
2781
2782	work_done = rx_bottom(tp, budget);
2783
2784	if (work_done < budget) {
2785	if (!napi_complete_done(n: napi, work_done))
2786	goto out;
2787	if (!list_empty(head: &tp->rx_done))
2788	napi_schedule(n: napi);
2789	}
2790
2791	out:
2792	return work_done;
2793	}
2794
2795	static
2796	int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2797	{
2798	int ret;
2799
2800	/* The rx would be stopped, so skip submitting */
2801	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) ||
2802	!test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(dev: tp->netdev))
2803	return 0;
2804
2805	usb_fill_bulk_urb(urb: agg->urb, dev: tp->udev, pipe: tp->pipe_in,
2806	transfer_buffer: agg->buffer, buffer_length: tp->rx_buf_sz,
2807	complete_fn: (usb_complete_t)read_bulk_callback, context: agg);
2808
2809	ret = usb_submit_urb(urb: agg->urb, mem_flags);
2810	if (ret == -ENODEV) {
2811	rtl_set_unplug(tp);
2812	netif_device_detach(dev: tp->netdev);
2813	} else if (ret) {
2814	struct urb *urb = agg->urb;
2815	unsigned long flags;
2816
2817	urb->actual_length = 0;
2818	spin_lock_irqsave(&tp->rx_lock, flags);
2819	list_add_tail(new: &agg->list, head: &tp->rx_done);
2820	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
2821
2822	netif_err(tp, rx_err, tp->netdev,
2823	"Couldn't submit rx[%p], ret = %d\n", agg, ret);
2824
2825	napi_schedule(n: &tp->napi);
2826	}
2827
2828	return ret;
2829	}
2830
2831	static void rtl_drop_queued_tx(struct r8152 *tp)
2832	{
2833	struct net_device_stats *stats = &tp->netdev->stats;
2834	struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2835	struct sk_buff *skb;
2836
2837	if (skb_queue_empty(list: tx_queue))
2838	return;
2839
2840	__skb_queue_head_init(list: &skb_head);
2841	spin_lock_bh(lock: &tx_queue->lock);
2842	skb_queue_splice_init(list: tx_queue, head: &skb_head);
2843	spin_unlock_bh(lock: &tx_queue->lock);
2844
2845	while ((skb = __skb_dequeue(list: &skb_head))) {
2846	dev_kfree_skb(skb);
2847	stats->tx_dropped++;
2848	}
2849	}
2850
2851	static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2852	{
2853	struct r8152 *tp = netdev_priv(dev: netdev);
2854
2855	netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2856
2857	usb_queue_reset_device(dev: tp->intf);
2858	}
2859
2860	static void rtl8152_set_rx_mode(struct net_device *netdev)
2861	{
2862	struct r8152 *tp = netdev_priv(dev: netdev);
2863
2864	if (netif_carrier_ok(dev: netdev)) {
2865	set_bit(nr: RTL8152_SET_RX_MODE, addr: &tp->flags);
2866	schedule_delayed_work(dwork: &tp->schedule, delay: 0);
2867	}
2868	}
2869
2870	static void _rtl8152_set_rx_mode(struct net_device *netdev)
2871	{
2872	struct r8152 *tp = netdev_priv(dev: netdev);
2873	u32 mc_filter[2]; /* Multicast hash filter */
2874	__le32 tmp[2];
2875	u32 ocp_data;
2876
2877	netif_stop_queue(dev: netdev);
2878	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2879	ocp_data &= ~RCR_ACPT_ALL;
2880	ocp_data |= RCR_AB | RCR_APM;
2881
2882	if (netdev->flags & IFF_PROMISC) {
2883	/* Unconditionally log net taps. */
2884	netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2885	ocp_data |= RCR_AM | RCR_AAP;
2886	mc_filter[1] = 0xffffffff;
2887	mc_filter[0] = 0xffffffff;
2888	} else if ((netdev->flags & IFF_MULTICAST &&
2889	netdev_mc_count(netdev) > multicast_filter_limit) ||
2890	(netdev->flags & IFF_ALLMULTI)) {
2891	/* Too many to filter perfectly -- accept all multicasts. */
2892	ocp_data |= RCR_AM;
2893	mc_filter[1] = 0xffffffff;
2894	mc_filter[0] = 0xffffffff;
2895	} else {
2896	mc_filter[1] = 0;
2897	mc_filter[0] = 0;
2898
2899	if (netdev->flags & IFF_MULTICAST) {
2900	struct netdev_hw_addr *ha;
2901
2902	netdev_for_each_mc_addr(ha, netdev) {
2903	int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2904
2905	mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2906	ocp_data |= RCR_AM;
2907	}
2908	}
2909	}
2910
2911	tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2912	tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2913
2914	pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, size: sizeof(tmp), data: tmp);
2915	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
2916	netif_wake_queue(dev: netdev);
2917	}
2918
2919	static netdev_features_t
2920	rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2921	netdev_features_t features)
2922	{
2923	u32 mss = skb_shinfo(skb)->gso_size;
2924	int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2925
2926	if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) &&
2927	skb_transport_offset(skb) > max_offset)
2928	features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2929	else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2930	features &= ~NETIF_F_GSO_MASK;
2931
2932	return features;
2933	}
2934
2935	static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2936	struct net_device *netdev)
2937	{
2938	struct r8152 *tp = netdev_priv(dev: netdev);
2939
2940	skb_tx_timestamp(skb);
2941
2942	skb_queue_tail(list: &tp->tx_queue, newsk: skb);
2943
2944	if (!list_empty(head: &tp->tx_free)) {
2945	if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2946	set_bit(nr: SCHEDULE_TASKLET, addr: &tp->flags);
2947	schedule_delayed_work(dwork: &tp->schedule, delay: 0);
2948	} else {
2949	usb_mark_last_busy(udev: tp->udev);
2950	tasklet_schedule(t: &tp->tx_tl);
2951	}
2952	} else if (skb_queue_len(list_: &tp->tx_queue) > tp->tx_qlen) {
2953	netif_stop_queue(dev: netdev);
2954	}
2955
2956	return NETDEV_TX_OK;
2957	}
2958
2959	static void r8152b_reset_packet_filter(struct r8152 *tp)
2960	{
2961	u32 ocp_data;
2962
2963	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2964	ocp_data &= ~FMC_FCR_MCU_EN;
2965	ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, data: ocp_data);
2966	ocp_data |= FMC_FCR_MCU_EN;
2967	ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, data: ocp_data);
2968	}
2969
2970	static void rtl8152_nic_reset(struct r8152 *tp)
2971	{
2972	u32 ocp_data;
2973	int i;
2974
2975	switch (tp->version) {
2976	case RTL_TEST_01:
2977	case RTL_VER_10:
2978	case RTL_VER_11:
2979	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2980	ocp_data &= ~CR_TE;
2981	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, data: ocp_data);
2982
2983	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2984	ocp_data &= ~BMU_RESET_EP_IN;
2985	ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, data: ocp_data);
2986
2987	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2988	ocp_data |= CDC_ECM_EN;
2989	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
2990
2991	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2992	ocp_data &= ~CR_RE;
2993	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, data: ocp_data);
2994
2995	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2996	ocp_data |= BMU_RESET_EP_IN;
2997	ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, data: ocp_data);
2998
2999	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
3000	ocp_data &= ~CDC_ECM_EN;
3001	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
3002	break;
3003
3004	default:
3005	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
3006
3007	for (i = 0; i < 1000; i++) {
3008	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3009	break;
3010	if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
3011	break;
3012	usleep_range(min: 100, max: 400);
3013	}
3014	break;
3015	}
3016	}
3017
3018	static void set_tx_qlen(struct r8152 *tp)
3019	{
3020	tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc));
3021	}
3022
3023	static inline u16 rtl8152_get_speed(struct r8152 *tp)
3024	{
3025	return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
3026	}
3027
3028	static void rtl_eee_plus_en(struct r8152 *tp, bool enable)
3029	{
3030	u32 ocp_data;
3031
3032	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
3033	if (enable)
3034	ocp_data |= EEEP_CR_EEEP_TX;
3035	else
3036	ocp_data &= ~EEEP_CR_EEEP_TX;
3037	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, data: ocp_data);
3038	}
3039
3040	static void rtl_set_eee_plus(struct r8152 *tp)
3041	{
3042	if (rtl8152_get_speed(tp) & _10bps)
3043	rtl_eee_plus_en(tp, enable: true);
3044	else
3045	rtl_eee_plus_en(tp, enable: false);
3046	}
3047
3048	static void rxdy_gated_en(struct r8152 *tp, bool enable)
3049	{
3050	u32 ocp_data;
3051
3052	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
3053	if (enable)
3054	ocp_data |= RXDY_GATED_EN;
3055	else
3056	ocp_data &= ~RXDY_GATED_EN;
3057	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, data: ocp_data);
3058	}
3059
3060	static int rtl_start_rx(struct r8152 *tp)
3061	{
3062	struct rx_agg *agg, *agg_next;
3063	struct list_head tmp_list;
3064	unsigned long flags;
3065	int ret = 0, i = 0;
3066
3067	INIT_LIST_HEAD(list: &tmp_list);
3068
3069	spin_lock_irqsave(&tp->rx_lock, flags);
3070
3071	INIT_LIST_HEAD(list: &tp->rx_done);
3072	INIT_LIST_HEAD(list: &tp->rx_used);
3073
3074	list_splice_init(list: &tp->rx_info, head: &tmp_list);
3075
3076	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
3077
3078	list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
3079	INIT_LIST_HEAD(list: &agg->list);
3080
3081	/* Only RTL8152_MAX_RX rx_agg need to be submitted. */
3082	if (++i > RTL8152_MAX_RX) {
3083	spin_lock_irqsave(&tp->rx_lock, flags);
3084	list_add_tail(new: &agg->list, head: &tp->rx_used);
3085	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
3086	} else if (unlikely(ret < 0)) {
3087	spin_lock_irqsave(&tp->rx_lock, flags);
3088	list_add_tail(new: &agg->list, head: &tp->rx_done);
3089	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
3090	} else {
3091	ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
3092	}
3093	}
3094
3095	spin_lock_irqsave(&tp->rx_lock, flags);
3096	WARN_ON(!list_empty(&tp->rx_info));
3097	list_splice(list: &tmp_list, head: &tp->rx_info);
3098	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
3099
3100	return ret;
3101	}
3102
3103	static int rtl_stop_rx(struct r8152 *tp)
3104	{
3105	struct rx_agg *agg, *agg_next;
3106	struct list_head tmp_list;
3107	unsigned long flags;
3108
3109	INIT_LIST_HEAD(list: &tmp_list);
3110
3111	/* The usb_kill_urb() couldn't be used in atomic.
3112	* Therefore, move the list of rx_info to a tmp one.
3113	* Then, list_for_each_entry_safe could be used without
3114	* spin lock.
3115	*/
3116
3117	spin_lock_irqsave(&tp->rx_lock, flags);
3118	list_splice_init(list: &tp->rx_info, head: &tmp_list);
3119	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
3120
3121	list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
3122	/* At least RTL8152_MAX_RX rx_agg have the page_count being
3123	* equal to 1, so the other ones could be freed safely.
3124	*/
3125	if (page_count(page: agg->page) > 1)
3126	free_rx_agg(tp, agg);
3127	else
3128	usb_kill_urb(urb: agg->urb);
3129	}
3130
3131	/* Move back the list of temp to the rx_info */
3132	spin_lock_irqsave(&tp->rx_lock, flags);
3133	WARN_ON(!list_empty(&tp->rx_info));
3134	list_splice(list: &tmp_list, head: &tp->rx_info);
3135	spin_unlock_irqrestore(lock: &tp->rx_lock, flags);
3136
3137	while (!skb_queue_empty(list: &tp->rx_queue))
3138	dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
3139
3140	return 0;
3141	}
3142
3143	static void rtl_set_ifg(struct r8152 *tp, u16 speed)
3144	{
3145	u32 ocp_data;
3146
3147	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3148	ocp_data &= ~IFG_MASK;
3149	if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) {
3150	ocp_data |= IFG_144NS;
3151	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, data: ocp_data);
3152
3153	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
3154	ocp_data &= ~TX10MIDLE_EN;
3155	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, data: ocp_data);
3156	} else {
3157	ocp_data |= IFG_96NS;
3158	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, data: ocp_data);
3159
3160	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
3161	ocp_data |= TX10MIDLE_EN;
3162	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, data: ocp_data);
3163	}
3164	}
3165
3166	static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
3167	{
3168	ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
3169	OWN_UPDATE | OWN_CLEAR);
3170	}
3171
3172	static int rtl_enable(struct r8152 *tp)
3173	{
3174	u32 ocp_data;
3175
3176	r8152b_reset_packet_filter(tp);
3177
3178	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
3179	ocp_data |= CR_RE | CR_TE;
3180	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, data: ocp_data);
3181
3182	switch (tp->version) {
3183	case RTL_VER_01:
3184	case RTL_VER_02:
3185	case RTL_VER_03:
3186	case RTL_VER_04:
3187	case RTL_VER_05:
3188	case RTL_VER_06:
3189	case RTL_VER_07:
3190	break;
3191	default:
3192	r8153b_rx_agg_chg_indicate(tp);
3193	break;
3194	}
3195
3196	rxdy_gated_en(tp, enable: false);
3197
3198	return 0;
3199	}
3200
3201	static int rtl8152_enable(struct r8152 *tp)
3202	{
3203	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3204	return -ENODEV;
3205
3206	set_tx_qlen(tp);
3207	rtl_set_eee_plus(tp);
3208
3209	return rtl_enable(tp);
3210	}
3211
3212	static void r8153_set_rx_early_timeout(struct r8152 *tp)
3213	{
3214	u32 ocp_data = tp->coalesce / 8;
3215
3216	switch (tp->version) {
3217	case RTL_VER_03:
3218	case RTL_VER_04:
3219	case RTL_VER_05:
3220	case RTL_VER_06:
3221	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3222	data: ocp_data);
3223	break;
3224
3225	case RTL_VER_08:
3226	case RTL_VER_09:
3227	case RTL_VER_14:
3228	/* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
3229	* primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
3230	*/
3231	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3232	data: 128 / 8);
3233	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3234	data: ocp_data);
3235	break;
3236
3237	case RTL_VER_10:
3238	case RTL_VER_11:
3239	case RTL_VER_12:
3240	case RTL_VER_13:
3241	case RTL_VER_15:
3242	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3243	data: 640 / 8);
3244	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3245	data: ocp_data);
3246	break;
3247
3248	default:
3249	break;
3250	}
3251	}
3252
3253	static void r8153_set_rx_early_size(struct r8152 *tp)
3254	{
3255	u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
3256
3257	switch (tp->version) {
3258	case RTL_VER_03:
3259	case RTL_VER_04:
3260	case RTL_VER_05:
3261	case RTL_VER_06:
3262	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3263	data: ocp_data / 4);
3264	break;
3265	case RTL_VER_08:
3266	case RTL_VER_09:
3267	case RTL_VER_14:
3268	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3269	data: ocp_data / 8);
3270	break;
3271	case RTL_TEST_01:
3272	case RTL_VER_10:
3273	case RTL_VER_11:
3274	case RTL_VER_12:
3275	case RTL_VER_13:
3276	case RTL_VER_15:
3277	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3278	data: ocp_data / 8);
3279	break;
3280	default:
3281	WARN_ON_ONCE(1);
3282	break;
3283	}
3284	}
3285
3286	static int rtl8153_enable(struct r8152 *tp)
3287	{
3288	u32 ocp_data;
3289
3290	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3291	return -ENODEV;
3292
3293	set_tx_qlen(tp);
3294	rtl_set_eee_plus(tp);
3295	r8153_set_rx_early_timeout(tp);
3296	r8153_set_rx_early_size(tp);
3297
3298	rtl_set_ifg(tp, speed: rtl8152_get_speed(tp));
3299
3300	switch (tp->version) {
3301	case RTL_VER_09:
3302	case RTL_VER_14:
3303	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
3304	ocp_data &= ~FC_PATCH_TASK;
3305	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
3306	usleep_range(min: 1000, max: 2000);
3307	ocp_data |= FC_PATCH_TASK;
3308	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
3309	break;
3310	default:
3311	break;
3312	}
3313
3314	return rtl_enable(tp);
3315	}
3316
3317	static void rtl_disable(struct r8152 *tp)
3318	{
3319	u32 ocp_data;
3320	int i;
3321
3322	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
3323	rtl_drop_queued_tx(tp);
3324	return;
3325	}
3326
3327	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3328	ocp_data &= ~RCR_ACPT_ALL;
3329	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
3330
3331	rtl_drop_queued_tx(tp);
3332
3333	for (i = 0; i < RTL8152_MAX_TX; i++)
3334	usb_kill_urb(urb: tp->tx_info[i].urb);
3335
3336	rxdy_gated_en(tp, enable: true);
3337
3338	for (i = 0; i < 1000; i++) {
3339	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3340	break;
3341	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3342	if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
3343	break;
3344	usleep_range(min: 1000, max: 2000);
3345	}
3346
3347	for (i = 0; i < 1000; i++) {
3348	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3349	break;
3350	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
3351	break;
3352	usleep_range(min: 1000, max: 2000);
3353	}
3354
3355	rtl_stop_rx(tp);
3356
3357	rtl8152_nic_reset(tp);
3358	}
3359
3360	static void r8152_power_cut_en(struct r8152 *tp, bool enable)
3361	{
3362	u32 ocp_data;
3363
3364	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
3365	if (enable)
3366	ocp_data |= POWER_CUT;
3367	else
3368	ocp_data &= ~POWER_CUT;
3369	ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, data: ocp_data);
3370
3371	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
3372	ocp_data &= ~RESUME_INDICATE;
3373	ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, data: ocp_data);
3374	}
3375
3376	static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
3377	{
3378	u32 ocp_data;
3379
3380	switch (tp->version) {
3381	case RTL_VER_01:
3382	case RTL_VER_02:
3383	case RTL_VER_03:
3384	case RTL_VER_04:
3385	case RTL_VER_05:
3386	case RTL_VER_06:
3387	case RTL_VER_07:
3388	case RTL_VER_08:
3389	case RTL_VER_09:
3390	case RTL_VER_14:
3391	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
3392	if (enable)
3393	ocp_data |= CPCR_RX_VLAN;
3394	else
3395	ocp_data &= ~CPCR_RX_VLAN;
3396	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, data: ocp_data);
3397	break;
3398
3399	case RTL_TEST_01:
3400	case RTL_VER_10:
3401	case RTL_VER_11:
3402	case RTL_VER_12:
3403	case RTL_VER_13:
3404	case RTL_VER_15:
3405	default:
3406	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1);
3407	if (enable)
3408	ocp_data |= OUTER_VLAN | INNER_VLAN;
3409	else
3410	ocp_data &= ~(OUTER_VLAN | INNER_VLAN);
3411	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, data: ocp_data);
3412	break;
3413	}
3414	}
3415
3416	static int rtl8152_set_features(struct net_device *dev,
3417	netdev_features_t features)
3418	{
3419	netdev_features_t changed = features ^ dev->features;
3420	struct r8152 *tp = netdev_priv(dev);
3421	int ret;
3422
3423	ret = usb_autopm_get_interface(intf: tp->intf);
3424	if (ret < 0)
3425	goto out;
3426
3427	mutex_lock(&tp->control);
3428
3429	if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
3430	if (features & NETIF_F_HW_VLAN_CTAG_RX)
3431	rtl_rx_vlan_en(tp, enable: true);
3432	else
3433	rtl_rx_vlan_en(tp, enable: false);
3434	}
3435
3436	mutex_unlock(lock: &tp->control);
3437
3438	usb_autopm_put_interface(intf: tp->intf);
3439
3440	out:
3441	return ret;
3442	}
3443
3444	#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
3445
3446	static u32 __rtl_get_wol(struct r8152 *tp)
3447	{
3448	u32 ocp_data;
3449	u32 wolopts = 0;
3450
3451	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3452	if (ocp_data & LINK_ON_WAKE_EN)
3453	wolopts |= WAKE_PHY;
3454
3455	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3456	if (ocp_data & UWF_EN)
3457	wolopts |= WAKE_UCAST;
3458	if (ocp_data & BWF_EN)
3459	wolopts |= WAKE_BCAST;
3460	if (ocp_data & MWF_EN)
3461	wolopts |= WAKE_MCAST;
3462
3463	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3464	if (ocp_data & MAGIC_EN)
3465	wolopts |= WAKE_MAGIC;
3466
3467	return wolopts;
3468	}
3469
3470	static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
3471	{
3472	u32 ocp_data;
3473
3474	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3475
3476	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3477	ocp_data &= ~LINK_ON_WAKE_EN;
3478	if (wolopts & WAKE_PHY)
3479	ocp_data |= LINK_ON_WAKE_EN;
3480	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, data: ocp_data);
3481
3482	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3483	ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
3484	if (wolopts & WAKE_UCAST)
3485	ocp_data |= UWF_EN;
3486	if (wolopts & WAKE_BCAST)
3487	ocp_data |= BWF_EN;
3488	if (wolopts & WAKE_MCAST)
3489	ocp_data |= MWF_EN;
3490	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, data: ocp_data);
3491
3492	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3493
3494	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3495	ocp_data &= ~MAGIC_EN;
3496	if (wolopts & WAKE_MAGIC)
3497	ocp_data |= MAGIC_EN;
3498	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, data: ocp_data);
3499
3500	if (wolopts & WAKE_ANY)
3501	device_set_wakeup_enable(dev: &tp->udev->dev, enable: true);
3502	else
3503	device_set_wakeup_enable(dev: &tp->udev->dev, enable: false);
3504	}
3505
3506	static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable)
3507	{
3508	u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3509
3510	/* MAC clock speed down */
3511	if (enable)
3512	ocp_data |= MAC_CLK_SPDWN_EN;
3513	else
3514	ocp_data &= ~MAC_CLK_SPDWN_EN;
3515
3516	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, data: ocp_data);
3517	}
3518
3519	static void r8156_mac_clk_spd(struct r8152 *tp, bool enable)
3520	{
3521	u32 ocp_data;
3522
3523	/* MAC clock speed down */
3524	if (enable) {
3525	/* aldps_spdwn_ratio, tp10_spdwn_ratio */
3526	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
3527	data: 0x0403);
3528
3529	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3530	ocp_data &= ~EEE_SPDWN_RATIO_MASK;
3531	ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */
3532	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, data: ocp_data);
3533	} else {
3534	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3535	ocp_data &= ~MAC_CLK_SPDWN_EN;
3536	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, data: ocp_data);
3537	}
3538	}
3539
3540	static void r8153_u1u2en(struct r8152 *tp, bool enable)
3541	{
3542	u8 u1u2[8];
3543
3544	if (enable)
3545	memset(u1u2, 0xff, sizeof(u1u2));
3546	else
3547	memset(u1u2, 0x00, sizeof(u1u2));
3548
3549	usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, size: sizeof(u1u2), data: u1u2);
3550	}
3551
3552	static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3553	{
3554	u32 ocp_data;
3555
3556	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3557	if (enable)
3558	ocp_data |= LPM_U1U2_EN;
3559	else
3560	ocp_data &= ~LPM_U1U2_EN;
3561
3562	ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, data: ocp_data);
3563	}
3564
3565	static void r8153_u2p3en(struct r8152 *tp, bool enable)
3566	{
3567	u32 ocp_data;
3568
3569	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3570	if (enable)
3571	ocp_data |= U2P3_ENABLE;
3572	else
3573	ocp_data &= ~U2P3_ENABLE;
3574	ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, data: ocp_data);
3575	}
3576
3577	static void r8153b_ups_flags(struct r8152 *tp)
3578	{
3579	u32 ups_flags = 0;
3580
3581	if (tp->ups_info.green)
3582	ups_flags |= UPS_FLAGS_EN_GREEN;
3583
3584	if (tp->ups_info.aldps)
3585	ups_flags |= UPS_FLAGS_EN_ALDPS;
3586
3587	if (tp->ups_info.eee)
3588	ups_flags |= UPS_FLAGS_EN_EEE;
3589
3590	if (tp->ups_info.flow_control)
3591	ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3592
3593	if (tp->ups_info.eee_ckdiv)
3594	ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3595
3596	if (tp->ups_info.eee_cmod_lv)
3597	ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3598
3599	if (tp->ups_info.r_tune)
3600	ups_flags |= UPS_FLAGS_R_TUNE;
3601
3602	if (tp->ups_info._10m_ckdiv)
3603	ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3604
3605	if (tp->ups_info.eee_plloff_100)
3606	ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3607
3608	if (tp->ups_info.eee_plloff_giga)
3609	ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3610
3611	if (tp->ups_info._250m_ckdiv)
3612	ups_flags |= UPS_FLAGS_250M_CKDIV;
3613
3614	if (tp->ups_info.ctap_short_off)
3615	ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3616
3617	switch (tp->ups_info.speed_duplex) {
3618	case NWAY_10M_HALF:
3619	ups_flags |= ups_flags_speed(1);
3620	break;
3621	case NWAY_10M_FULL:
3622	ups_flags |= ups_flags_speed(2);
3623	break;
3624	case NWAY_100M_HALF:
3625	ups_flags |= ups_flags_speed(3);
3626	break;
3627	case NWAY_100M_FULL:
3628	ups_flags |= ups_flags_speed(4);
3629	break;
3630	case NWAY_1000M_FULL:
3631	ups_flags |= ups_flags_speed(5);
3632	break;
3633	case FORCE_10M_HALF:
3634	ups_flags |= ups_flags_speed(6);
3635	break;
3636	case FORCE_10M_FULL:
3637	ups_flags |= ups_flags_speed(7);
3638	break;
3639	case FORCE_100M_HALF:
3640	ups_flags |= ups_flags_speed(8);
3641	break;
3642	case FORCE_100M_FULL:
3643	ups_flags |= ups_flags_speed(9);
3644	break;
3645	default:
3646	break;
3647	}
3648
3649	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, data: ups_flags);
3650	}
3651
3652	static void r8156_ups_flags(struct r8152 *tp)
3653	{
3654	u32 ups_flags = 0;
3655
3656	if (tp->ups_info.green)
3657	ups_flags |= UPS_FLAGS_EN_GREEN;
3658
3659	if (tp->ups_info.aldps)
3660	ups_flags |= UPS_FLAGS_EN_ALDPS;
3661
3662	if (tp->ups_info.eee)
3663	ups_flags |= UPS_FLAGS_EN_EEE;
3664
3665	if (tp->ups_info.flow_control)
3666	ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3667
3668	if (tp->ups_info.eee_ckdiv)
3669	ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3670
3671	if (tp->ups_info._10m_ckdiv)
3672	ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3673
3674	if (tp->ups_info.eee_plloff_100)
3675	ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3676
3677	if (tp->ups_info.eee_plloff_giga)
3678	ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3679
3680	if (tp->ups_info._250m_ckdiv)
3681	ups_flags |= UPS_FLAGS_250M_CKDIV;
3682
3683	switch (tp->ups_info.speed_duplex) {
3684	case FORCE_10M_HALF:
3685	ups_flags |= ups_flags_speed(0);
3686	break;
3687	case FORCE_10M_FULL:
3688	ups_flags |= ups_flags_speed(1);
3689	break;
3690	case FORCE_100M_HALF:
3691	ups_flags |= ups_flags_speed(2);
3692	break;
3693	case FORCE_100M_FULL:
3694	ups_flags |= ups_flags_speed(3);
3695	break;
3696	case NWAY_10M_HALF:
3697	ups_flags |= ups_flags_speed(4);
3698	break;
3699	case NWAY_10M_FULL:
3700	ups_flags |= ups_flags_speed(5);
3701	break;
3702	case NWAY_100M_HALF:
3703	ups_flags |= ups_flags_speed(6);
3704	break;
3705	case NWAY_100M_FULL:
3706	ups_flags |= ups_flags_speed(7);
3707	break;
3708	case NWAY_1000M_FULL:
3709	ups_flags |= ups_flags_speed(8);
3710	break;
3711	case NWAY_2500M_FULL:
3712	ups_flags |= ups_flags_speed(9);
3713	break;
3714	default:
3715	break;
3716	}
3717
3718	switch (tp->ups_info.lite_mode) {
3719	case 1:
3720	ups_flags |= 0 << 5;
3721	break;
3722	case 2:
3723	ups_flags |= 2 << 5;
3724	break;
3725	case 0:
3726	default:
3727	ups_flags |= 1 << 5;
3728	break;
3729	}
3730
3731	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, data: ups_flags);
3732	}
3733
3734	static void rtl_green_en(struct r8152 *tp, bool enable)
3735	{
3736	u16 data;
3737
3738	data = sram_read(tp, SRAM_GREEN_CFG);
3739	if (enable)
3740	data |= GREEN_ETH_EN;
3741	else
3742	data &= ~GREEN_ETH_EN;
3743	sram_write(tp, SRAM_GREEN_CFG, data);
3744
3745	tp->ups_info.green = enable;
3746	}
3747
3748	static void r8153b_green_en(struct r8152 *tp, bool enable)
3749	{
3750	if (enable) {
3751	sram_write(tp, addr: 0x8045, data: 0); /* 10M abiq&ldvbias */
3752	sram_write(tp, addr: 0x804d, data: 0x1222); /* 100M short abiq&ldvbias */
3753	sram_write(tp, addr: 0x805d, data: 0x0022); /* 1000M short abiq&ldvbias */
3754	} else {
3755	sram_write(tp, addr: 0x8045, data: 0x2444); /* 10M abiq&ldvbias */
3756	sram_write(tp, addr: 0x804d, data: 0x2444); /* 100M short abiq&ldvbias */
3757	sram_write(tp, addr: 0x805d, data: 0x2444); /* 1000M short abiq&ldvbias */
3758	}
3759
3760	rtl_green_en(tp, enable: true);
3761	}
3762
3763	static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3764	{
3765	u16 data;
3766	int i;
3767
3768	for (i = 0; i < 500; i++) {
3769	data = ocp_reg_read(tp, OCP_PHY_STATUS);
3770	data &= PHY_STAT_MASK;
3771	if (desired) {
3772	if (data == desired)
3773	break;
3774	} else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3775	data == PHY_STAT_EXT_INIT) {
3776	break;
3777	}
3778
3779	msleep(msecs: 20);
3780	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3781	break;
3782	}
3783
3784	return data;
3785	}
3786
3787	static void r8153b_ups_en(struct r8152 *tp, bool enable)
3788	{
3789	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3790
3791	if (enable) {
3792	r8153b_ups_flags(tp);
3793
3794	ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3795	ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3796
3797	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3798	ocp_data |= UPS_FORCE_PWR_DOWN;
3799	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, data: ocp_data);
3800	} else {
3801	ocp_data &= ~(UPS_EN | USP_PREWAKE);
3802	ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3803
3804	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3805	ocp_data &= ~UPS_FORCE_PWR_DOWN;
3806	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, data: ocp_data);
3807
3808	if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3809	int i;
3810
3811	for (i = 0; i < 500; i++) {
3812	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3813	return;
3814	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3815	AUTOLOAD_DONE)
3816	break;
3817	msleep(msecs: 20);
3818	}
3819
3820	tp->rtl_ops.hw_phy_cfg(tp);
3821
3822	rtl8152_set_speed(tp, autoneg: tp->autoneg, speed: tp->speed,
3823	duplex: tp->duplex, advertising: tp->advertising);
3824	}
3825	}
3826	}
3827
3828	static void r8153c_ups_en(struct r8152 *tp, bool enable)
3829	{
3830	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3831
3832	if (enable) {
3833	r8153b_ups_flags(tp);
3834
3835	ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3836	ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3837
3838	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3839	ocp_data |= UPS_FORCE_PWR_DOWN;
3840	ocp_data &= ~BIT(7);
3841	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, data: ocp_data);
3842	} else {
3843	ocp_data &= ~(UPS_EN | USP_PREWAKE);
3844	ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3845
3846	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3847	ocp_data &= ~UPS_FORCE_PWR_DOWN;
3848	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, data: ocp_data);
3849
3850	if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3851	int i;
3852
3853	for (i = 0; i < 500; i++) {
3854	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
3855	return;
3856	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3857	AUTOLOAD_DONE)
3858	break;
3859	msleep(msecs: 20);
3860	}
3861
3862	tp->rtl_ops.hw_phy_cfg(tp);
3863
3864	rtl8152_set_speed(tp, autoneg: tp->autoneg, speed: tp->speed,
3865	duplex: tp->duplex, advertising: tp->advertising);
3866	}
3867
3868	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3869
3870	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3871	ocp_data |= BIT(8);
3872	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, data: ocp_data);
3873
3874	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3875	}
3876	}
3877
3878	static void r8156_ups_en(struct r8152 *tp, bool enable)
3879	{
3880	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3881
3882	if (enable) {
3883	r8156_ups_flags(tp);
3884
3885	ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3886	ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3887
3888	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3889	ocp_data |= UPS_FORCE_PWR_DOWN;
3890	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, data: ocp_data);
3891
3892	switch (tp->version) {
3893	case RTL_VER_13:
3894	case RTL_VER_15:
3895	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL);
3896	ocp_data &= ~OOBS_POLLING;
3897	ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, data: ocp_data);
3898	break;
3899	default:
3900	break;
3901	}
3902	} else {
3903	ocp_data &= ~(UPS_EN | USP_PREWAKE);
3904	ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3905
3906	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3907	ocp_data &= ~UPS_FORCE_PWR_DOWN;
3908	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, data: ocp_data);
3909
3910	if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3911	tp->rtl_ops.hw_phy_cfg(tp);
3912
3913	rtl8152_set_speed(tp, autoneg: tp->autoneg, speed: tp->speed,
3914	duplex: tp->duplex, advertising: tp->advertising);
3915	}
3916	}
3917	}
3918
3919	static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3920	{
3921	u32 ocp_data;
3922
3923	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3924	if (enable)
3925	ocp_data |= PWR_EN | PHASE2_EN;
3926	else
3927	ocp_data &= ~(PWR_EN | PHASE2_EN);
3928	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3929
3930	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3931	ocp_data &= ~PCUT_STATUS;
3932	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, data: ocp_data);
3933	}
3934
3935	static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3936	{
3937	u32 ocp_data;
3938
3939	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3940	if (enable)
3941	ocp_data |= PWR_EN | PHASE2_EN;
3942	else
3943	ocp_data &= ~PWR_EN;
3944	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, data: ocp_data);
3945
3946	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3947	ocp_data &= ~PCUT_STATUS;
3948	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, data: ocp_data);
3949	}
3950
3951	static void r8153_queue_wake(struct r8152 *tp, bool enable)
3952	{
3953	u32 ocp_data;
3954
3955	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3956	if (enable)
3957	ocp_data |= UPCOMING_RUNTIME_D3;
3958	else
3959	ocp_data &= ~UPCOMING_RUNTIME_D3;
3960	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, data: ocp_data);
3961
3962	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3963	ocp_data &= ~LINK_CHG_EVENT;
3964	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, data: ocp_data);
3965
3966	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3967	ocp_data &= ~LINK_CHANGE_FLAG;
3968	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, data: ocp_data);
3969	}
3970
3971	static bool rtl_can_wakeup(struct r8152 *tp)
3972	{
3973	struct usb_device *udev = tp->udev;
3974
3975	return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3976	}
3977
3978	static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3979	{
3980	if (enable) {
3981	u32 ocp_data;
3982
3983	__rtl_set_wol(tp, WAKE_ANY);
3984
3985	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3986
3987	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3988	ocp_data |= LINK_OFF_WAKE_EN;
3989	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, data: ocp_data);
3990
3991	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3992	} else {
3993	u32 ocp_data;
3994
3995	__rtl_set_wol(tp, wolopts: tp->saved_wolopts);
3996
3997	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3998
3999	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
4000	ocp_data &= ~LINK_OFF_WAKE_EN;
4001	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, data: ocp_data);
4002
4003	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
4004	}
4005	}
4006
4007	static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
4008	{
4009	if (enable) {
4010	r8153_u1u2en(tp, enable: false);
4011	r8153_u2p3en(tp, enable: false);
4012	rtl_runtime_suspend_enable(tp, enable: true);
4013	} else {
4014	rtl_runtime_suspend_enable(tp, enable: false);
4015
4016	switch (tp->version) {
4017	case RTL_VER_03:
4018	case RTL_VER_04:
4019	break;
4020	case RTL_VER_05:
4021	case RTL_VER_06:
4022	default:
4023	r8153_u2p3en(tp, enable: true);
4024	break;
4025	}
4026
4027	r8153_u1u2en(tp, enable: true);
4028	}
4029	}
4030
4031	static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
4032	{
4033	if (enable) {
4034	r8153_queue_wake(tp, enable: true);
4035	r8153b_u1u2en(tp, enable: false);
4036	r8153_u2p3en(tp, enable: false);
4037	rtl_runtime_suspend_enable(tp, enable: true);
4038	r8153b_ups_en(tp, enable: true);
4039	} else {
4040	r8153b_ups_en(tp, enable: false);
4041	r8153_queue_wake(tp, enable: false);
4042	rtl_runtime_suspend_enable(tp, enable: false);
4043	if (tp->udev->speed >= USB_SPEED_SUPER)
4044	r8153b_u1u2en(tp, enable: true);
4045	}
4046	}
4047
4048	static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable)
4049	{
4050	if (enable) {
4051	r8153_queue_wake(tp, enable: true);
4052	r8153b_u1u2en(tp, enable: false);
4053	r8153_u2p3en(tp, enable: false);
4054	rtl_runtime_suspend_enable(tp, enable: true);
4055	r8153c_ups_en(tp, enable: true);
4056	} else {
4057	r8153c_ups_en(tp, enable: false);
4058	r8153_queue_wake(tp, enable: false);
4059	rtl_runtime_suspend_enable(tp, enable: false);
4060	r8153b_u1u2en(tp, enable: true);
4061	}
4062	}
4063
4064	static void rtl8156_runtime_enable(struct r8152 *tp, bool enable)
4065	{
4066	if (enable) {
4067	r8153_queue_wake(tp, enable: true);
4068	r8153b_u1u2en(tp, enable: false);
4069	r8153_u2p3en(tp, enable: false);
4070	rtl_runtime_suspend_enable(tp, enable: true);
4071	} else {
4072	r8153_queue_wake(tp, enable: false);
4073	rtl_runtime_suspend_enable(tp, enable: false);
4074	r8153_u2p3en(tp, enable: true);
4075	if (tp->udev->speed >= USB_SPEED_SUPER)
4076	r8153b_u1u2en(tp, enable: true);
4077	}
4078	}
4079
4080	static void r8153_teredo_off(struct r8152 *tp)
4081	{
4082	u32 ocp_data;
4083
4084	switch (tp->version) {
4085	case RTL_VER_01:
4086	case RTL_VER_02:
4087	case RTL_VER_03:
4088	case RTL_VER_04:
4089	case RTL_VER_05:
4090	case RTL_VER_06:
4091	case RTL_VER_07:
4092	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
4093	ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
4094	OOB_TEREDO_EN);
4095	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, data: ocp_data);
4096	break;
4097
4098	case RTL_VER_08:
4099	case RTL_VER_09:
4100	case RTL_TEST_01:
4101	case RTL_VER_10:
4102	case RTL_VER_11:
4103	case RTL_VER_12:
4104	case RTL_VER_13:
4105	case RTL_VER_14:
4106	case RTL_VER_15:
4107	default:
4108	/* The bit 0 ~ 7 are relative with teredo settings. They are
4109	* W1C (write 1 to clear), so set all 1 to disable it.
4110	*/
4111	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, data: 0xff);
4112	break;
4113	}
4114
4115	ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
4116	ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, data: 0);
4117	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, data: 0);
4118	}
4119
4120	static void rtl_reset_bmu(struct r8152 *tp)
4121	{
4122	u32 ocp_data;
4123
4124	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
4125	ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
4126	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, data: ocp_data);
4127	ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
4128	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, data: ocp_data);
4129	}
4130
4131	/* Clear the bp to stop the firmware before loading a new one */
4132	static void rtl_clear_bp(struct r8152 *tp, u16 type)
4133	{
4134	u16 bp[16] = {0};
4135	u16 bp_num;
4136
4137	switch (tp->version) {
4138	case RTL_VER_08:
4139	case RTL_VER_09:
4140	case RTL_VER_10:
4141	case RTL_VER_11:
4142	case RTL_VER_12:
4143	case RTL_VER_13:
4144	case RTL_VER_15:
4145	if (type == MCU_TYPE_USB) {
4146	ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, data: 0);
4147	bp_num = 16;
4148	break;
4149	}
4150	fallthrough;
4151	case RTL_VER_03:
4152	case RTL_VER_04:
4153	case RTL_VER_05:
4154	case RTL_VER_06:
4155	ocp_write_byte(tp, type, PLA_BP_EN, data: 0);
4156	fallthrough;
4157	case RTL_VER_01:
4158	case RTL_VER_02:
4159	case RTL_VER_07:
4160	bp_num = 8;
4161	break;
4162	case RTL_VER_14:
4163	default:
4164	ocp_write_word(tp, type, USB_BP2_EN, data: 0);
4165	bp_num = 16;
4166	break;
4167	}
4168
4169	generic_ocp_write(tp, PLA_BP_0, BYTE_EN_DWORD, size: bp_num << 1, data: bp, type);
4170
4171	/* wait 3 ms to make sure the firmware is stopped */
4172	usleep_range(min: 3000, max: 6000);
4173	ocp_write_word(tp, type, PLA_BP_BA, data: 0);
4174	}
4175
4176	static inline void rtl_reset_ocp_base(struct r8152 *tp)
4177	{
4178	tp->ocp_base = -1;
4179	}
4180
4181	static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait)
4182	{
4183	u16 data, check;
4184	int i;
4185
4186	data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
4187	if (request) {
4188	data |= PATCH_REQUEST;
4189	check = 0;
4190	} else {
4191	data &= ~PATCH_REQUEST;
4192	check = PATCH_READY;
4193	}
4194	ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
4195
4196	for (i = 0; wait && i < 5000; i++) {
4197	u32 ocp_data;
4198
4199	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
4200	return -ENODEV;
4201
4202	usleep_range(min: 1000, max: 2000);
4203	ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT);
4204	if ((ocp_data & PATCH_READY) ^ check)
4205	break;
4206	}
4207
4208	if (request && wait &&
4209	!(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
4210	dev_err(&tp->intf->dev, "PHY patch request fail\n");
4211	rtl_phy_patch_request(tp, request: false, wait: false);
4212	return -ETIME;
4213	} else {
4214	return 0;
4215	}
4216	}
4217
4218	static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key)
4219	{
4220	if (patch_key && key_addr) {
4221	sram_write(tp, addr: key_addr, data: patch_key);
4222	sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
4223	} else if (key_addr) {
4224	u16 data;
4225
4226	sram_write(tp, addr: 0x0000, data: 0x0000);
4227
4228	data = ocp_reg_read(tp, OCP_PHY_LOCK);
4229	data &= ~PATCH_LOCK;
4230	ocp_reg_write(tp, OCP_PHY_LOCK, data);
4231
4232	sram_write(tp, addr: key_addr, data: 0x0000);
4233	} else {
4234	WARN_ON_ONCE(1);
4235	}
4236	}
4237
4238	static int
4239	rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait)
4240	{
4241	if (rtl_phy_patch_request(tp, request: true, wait))
4242	return -ETIME;
4243
4244	rtl_patch_key_set(tp, key_addr, patch_key);
4245
4246	return 0;
4247	}
4248
4249	static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait)
4250	{
4251	rtl_patch_key_set(tp, key_addr, patch_key: 0);
4252
4253	rtl_phy_patch_request(tp, request: false, wait);
4254
4255	return 0;
4256	}
4257
4258	static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy)
4259	{
4260	u16 fw_offset;
4261	u32 length;
4262	bool rc = false;
4263
4264	switch (tp->version) {
4265	case RTL_VER_01:
4266	case RTL_VER_02:
4267	case RTL_VER_03:
4268	case RTL_VER_04:
4269	case RTL_VER_05:
4270	case RTL_VER_06:
4271	case RTL_VER_07:
4272	case RTL_VER_08:
4273	case RTL_VER_09:
4274	case RTL_VER_10:
4275	case RTL_VER_11:
4276	case RTL_VER_12:
4277	case RTL_VER_14:
4278	goto out;
4279	case RTL_VER_13:
4280	case RTL_VER_15:
4281	default:
4282	break;
4283	}
4284
4285	fw_offset = __le16_to_cpu(phy->fw_offset);
4286	length = __le32_to_cpu(phy->blk_hdr.length);
4287	if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4288	dev_err(&tp->intf->dev, "invalid fw_offset\n");
4289	goto out;
4290	}
4291
4292	length -= fw_offset;
4293	if (length & 3) {
4294	dev_err(&tp->intf->dev, "invalid block length\n");
4295	goto out;
4296	}
4297
4298	if (__le16_to_cpu(phy->fw_reg) != 0x9A00) {
4299	dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4300	goto out;
4301	}
4302
4303	rc = true;
4304	out:
4305	return rc;
4306	}
4307
4308	static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver)
4309	{
4310	bool rc = false;
4311
4312	switch (tp->version) {
4313	case RTL_VER_10:
4314	case RTL_VER_11:
4315	case RTL_VER_12:
4316	case RTL_VER_13:
4317	case RTL_VER_15:
4318	break;
4319	default:
4320	goto out;
4321	}
4322
4323	if (__le32_to_cpu(ver->blk_hdr.length) != sizeof(*ver)) {
4324	dev_err(&tp->intf->dev, "invalid block length\n");
4325	goto out;
4326	}
4327
4328	if (__le16_to_cpu(ver->ver.addr) != SRAM_GPHY_FW_VER) {
4329	dev_err(&tp->intf->dev, "invalid phy ver addr\n");
4330	goto out;
4331	}
4332
4333	rc = true;
4334	out:
4335	return rc;
4336	}
4337
4338	static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix)
4339	{
4340	bool rc = false;
4341
4342	switch (tp->version) {
4343	case RTL_VER_10:
4344	case RTL_VER_11:
4345	case RTL_VER_12:
4346	case RTL_VER_13:
4347	case RTL_VER_15:
4348	break;
4349	default:
4350	goto out;
4351	}
4352
4353	if (__le32_to_cpu(fix->blk_hdr.length) != sizeof(*fix)) {
4354	dev_err(&tp->intf->dev, "invalid block length\n");
4355	goto out;
4356	}
4357
4358	if (__le16_to_cpu(fix->setting.addr) != OCP_PHY_PATCH_CMD ||
4359	__le16_to_cpu(fix->setting.data) != BIT(7)) {
4360	dev_err(&tp->intf->dev, "invalid phy fixup\n");
4361	goto out;
4362	}
4363
4364	rc = true;
4365	out:
4366	return rc;
4367	}
4368
4369	static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy)
4370	{
4371	u16 fw_offset;
4372	u32 length;
4373	bool rc = false;
4374
4375	switch (tp->version) {
4376	case RTL_VER_10:
4377	case RTL_VER_11:
4378	case RTL_VER_12:
4379	case RTL_VER_13:
4380	case RTL_VER_15:
4381	break;
4382	default:
4383	goto out;
4384	}
4385
4386	fw_offset = __le16_to_cpu(phy->fw_offset);
4387	length = __le32_to_cpu(phy->blk_hdr.length);
4388	if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4389	dev_err(&tp->intf->dev, "invalid fw_offset\n");
4390	goto out;
4391	}
4392
4393	length -= fw_offset;
4394	if (length & 1) {
4395	dev_err(&tp->intf->dev, "invalid block length\n");
4396	goto out;
4397	}
4398
4399	if (phy->pre_num > 2) {
4400	dev_err(&tp->intf->dev, "invalid pre_num %d\n", phy->pre_num);
4401	goto out;
4402	}
4403
4404	if (phy->bp_num > 8) {
4405	dev_err(&tp->intf->dev, "invalid bp_num %d\n", phy->bp_num);
4406	goto out;
4407	}
4408
4409	rc = true;
4410	out:
4411	return rc;
4412	}
4413
4414	static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
4415	{
4416	u32 length;
4417	u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
4418	bool rc = false;
4419
4420	switch (tp->version) {
4421	case RTL_VER_04:
4422	case RTL_VER_05:
4423	case RTL_VER_06:
4424	fw_reg = 0xa014;
4425	ba_reg = 0xa012;
4426	patch_en_addr = 0xa01a;
4427	mode_reg = 0xb820;
4428	bp_start = 0xa000;
4429	break;
4430	default:
4431	goto out;
4432	}
4433
4434	fw_offset = __le16_to_cpu(phy->fw_offset);
4435	if (fw_offset < sizeof(*phy)) {
4436	dev_err(&tp->intf->dev, "fw_offset too small\n");
4437	goto out;
4438	}
4439
4440	length = __le32_to_cpu(phy->blk_hdr.length);
4441	if (length < fw_offset) {
4442	dev_err(&tp->intf->dev, "invalid fw_offset\n");
4443	goto out;
4444	}
4445
4446	length -= __le16_to_cpu(phy->fw_offset);
4447	if (!length || (length & 1)) {
4448	dev_err(&tp->intf->dev, "invalid block length\n");
4449	goto out;
4450	}
4451
4452	if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
4453	dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4454	goto out;
4455	}
4456
4457	if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
4458	dev_err(&tp->intf->dev, "invalid base address register\n");
4459	goto out;
4460	}
4461
4462	if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
4463	dev_err(&tp->intf->dev,
4464	"invalid patch mode enabled register\n");
4465	goto out;
4466	}
4467
4468	if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
4469	dev_err(&tp->intf->dev,
4470	"invalid register to switch the mode\n");
4471	goto out;
4472	}
4473
4474	if (__le16_to_cpu(phy->bp_start) != bp_start) {
4475	dev_err(&tp->intf->dev,
4476	"invalid start register of break point\n");
4477	goto out;
4478	}
4479
4480	if (__le16_to_cpu(phy->bp_num) > 4) {
4481	dev_err(&tp->intf->dev, "invalid break point number\n");
4482	goto out;
4483	}
4484
4485	rc = true;
4486	out:
4487	return rc;
4488	}
4489
4490	static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
4491	{
4492	u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
4493	bool rc = false;
4494	u32 length, type;
4495	int i, max_bp;
4496
4497	type = __le32_to_cpu(mac->blk_hdr.type);
4498	if (type == RTL_FW_PLA) {
4499	switch (tp->version) {
4500	case RTL_VER_01:
4501	case RTL_VER_02:
4502	case RTL_VER_07:
4503	fw_reg = 0xf800;
4504	bp_ba_addr = PLA_BP_BA;
4505	bp_en_addr = 0;
4506	bp_start = PLA_BP_0;
4507	max_bp = 8;
4508	break;
4509	case RTL_VER_03:
4510	case RTL_VER_04:
4511	case RTL_VER_05:
4512	case RTL_VER_06:
4513	case RTL_VER_08:
4514	case RTL_VER_09:
4515	case RTL_VER_11:
4516	case RTL_VER_12:
4517	case RTL_VER_13:
4518	case RTL_VER_15:
4519	fw_reg = 0xf800;
4520	bp_ba_addr = PLA_BP_BA;
4521	bp_en_addr = PLA_BP_EN;
4522	bp_start = PLA_BP_0;
4523	max_bp = 8;
4524	break;
4525	case RTL_VER_14:
4526	fw_reg = 0xf800;
4527	bp_ba_addr = PLA_BP_BA;
4528	bp_en_addr = USB_BP2_EN;
4529	bp_start = PLA_BP_0;
4530	max_bp = 16;
4531	break;
4532	default:
4533	goto out;
4534	}
4535	} else if (type == RTL_FW_USB) {
4536	switch (tp->version) {
4537	case RTL_VER_03:
4538	case RTL_VER_04:
4539	case RTL_VER_05:
4540	case RTL_VER_06:
4541	fw_reg = 0xf800;
4542	bp_ba_addr = USB_BP_BA;
4543	bp_en_addr = USB_BP_EN;
4544	bp_start = USB_BP_0;
4545	max_bp = 8;
4546	break;
4547	case RTL_VER_08:
4548	case RTL_VER_09:
4549	case RTL_VER_11:
4550	case RTL_VER_12:
4551	case RTL_VER_13:
4552	case RTL_VER_14:
4553	case RTL_VER_15:
4554	fw_reg = 0xe600;
4555	bp_ba_addr = USB_BP_BA;
4556	bp_en_addr = USB_BP2_EN;
4557	bp_start = USB_BP_0;
4558	max_bp = 16;
4559	break;
4560	case RTL_VER_01:
4561	case RTL_VER_02:
4562	case RTL_VER_07:
4563	default:
4564	goto out;
4565	}
4566	} else {
4567	goto out;
4568	}
4569
4570	fw_offset = __le16_to_cpu(mac->fw_offset);
4571	if (fw_offset < sizeof(*mac)) {
4572	dev_err(&tp->intf->dev, "fw_offset too small\n");
4573	goto out;
4574	}
4575
4576	length = __le32_to_cpu(mac->blk_hdr.length);
4577	if (length < fw_offset) {
4578	dev_err(&tp->intf->dev, "invalid fw_offset\n");
4579	goto out;
4580	}
4581
4582	length -= fw_offset;
4583	if (length < 4 || (length & 3)) {
4584	dev_err(&tp->intf->dev, "invalid block length\n");
4585	goto out;
4586	}
4587
4588	if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
4589	dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4590	goto out;
4591	}
4592
4593	if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
4594	dev_err(&tp->intf->dev, "invalid base address register\n");
4595	goto out;
4596	}
4597
4598	if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
4599	dev_err(&tp->intf->dev, "invalid enabled mask register\n");
4600	goto out;
4601	}
4602
4603	if (__le16_to_cpu(mac->bp_start) != bp_start) {
4604	dev_err(&tp->intf->dev,
4605	"invalid start register of break point\n");
4606	goto out;
4607	}
4608
4609	if (__le16_to_cpu(mac->bp_num) > max_bp) {
4610	dev_err(&tp->intf->dev, "invalid break point number\n");
4611	goto out;
4612	}
4613
4614	for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
4615	if (mac->bp[i]) {
4616	dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
4617	goto out;
4618	}
4619	}
4620
4621	rc = true;
4622	out:
4623	return rc;
4624	}
4625
4626	/* Verify the checksum for the firmware file. It is calculated from the version
4627	* field to the end of the file. Compare the result with the checksum field to
4628	* make sure the file is correct.
4629	*/
4630	static long rtl8152_fw_verify_checksum(struct r8152 *tp,
4631	struct fw_header *fw_hdr, size_t size)
4632	{
4633	u8 checksum[sizeof(fw_hdr->checksum)];
4634
4635	BUILD_BUG_ON(sizeof(checksum) != SHA256_DIGEST_SIZE);
4636	sha256(data: fw_hdr->version, len: size - sizeof(checksum), out: checksum);
4637
4638	if (memcmp(p: fw_hdr->checksum, q: checksum, size: sizeof(checksum))) {
4639	dev_err(&tp->intf->dev, "checksum fail\n");
4640	return -EFAULT;
4641	}
4642	return 0;
4643	}
4644
4645	static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
4646	{
4647	const struct firmware *fw = rtl_fw->fw;
4648	struct fw_header *fw_hdr = (struct fw_header *)fw->data;
4649	unsigned long fw_flags = 0;
4650	long ret = -EFAULT;
4651	int i;
4652
4653	if (fw->size < sizeof(*fw_hdr)) {
4654	dev_err(&tp->intf->dev, "file too small\n");
4655	goto fail;
4656	}
4657
4658	ret = rtl8152_fw_verify_checksum(tp, fw_hdr, size: fw->size);
4659	if (ret)
4660	goto fail;
4661
4662	ret = -EFAULT;
4663
4664	for (i = sizeof(*fw_hdr); i < fw->size;) {
4665	struct fw_block *block = (struct fw_block *)&fw->data[i];
4666	u32 type;
4667
4668	if ((i + sizeof(*block)) > fw->size)
4669	goto fail;
4670
4671	type = __le32_to_cpu(block->type);
4672	switch (type) {
4673	case RTL_FW_END:
4674	if (__le32_to_cpu(block->length) != sizeof(*block))
4675	goto fail;
4676	goto fw_end;
4677	case RTL_FW_PLA:
4678	if (test_bit(FW_FLAGS_PLA, &fw_flags)) {
4679	dev_err(&tp->intf->dev,
4680	"multiple PLA firmware encountered");
4681	goto fail;
4682	}
4683
4684	if (!rtl8152_is_fw_mac_ok(tp, mac: (struct fw_mac *)block)) {
4685	dev_err(&tp->intf->dev,
4686	"check PLA firmware failed\n");
4687	goto fail;
4688	}
4689	__set_bit(FW_FLAGS_PLA, &fw_flags);
4690	break;
4691	case RTL_FW_USB:
4692	if (test_bit(FW_FLAGS_USB, &fw_flags)) {
4693	dev_err(&tp->intf->dev,
4694	"multiple USB firmware encountered");
4695	goto fail;
4696	}
4697
4698	if (!rtl8152_is_fw_mac_ok(tp, mac: (struct fw_mac *)block)) {
4699	dev_err(&tp->intf->dev,
4700	"check USB firmware failed\n");
4701	goto fail;
4702	}
4703	__set_bit(FW_FLAGS_USB, &fw_flags);
4704	break;
4705	case RTL_FW_PHY_START:
4706	if (test_bit(FW_FLAGS_START, &fw_flags) ||
4707	test_bit(FW_FLAGS_NC, &fw_flags) ||
4708	test_bit(FW_FLAGS_NC1, &fw_flags) ||
4709	test_bit(FW_FLAGS_NC2, &fw_flags) ||
4710	test_bit(FW_FLAGS_UC2, &fw_flags) ||
4711	test_bit(FW_FLAGS_UC, &fw_flags) ||
4712	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4713	dev_err(&tp->intf->dev,
4714	"check PHY_START fail\n");
4715	goto fail;
4716	}
4717
4718	if (__le32_to_cpu(block->length) != sizeof(struct fw_phy_patch_key)) {
4719	dev_err(&tp->intf->dev,
4720	"Invalid length for PHY_START\n");
4721	goto fail;
4722	}
4723	__set_bit(FW_FLAGS_START, &fw_flags);
4724	break;
4725	case RTL_FW_PHY_STOP:
4726	if (test_bit(FW_FLAGS_STOP, &fw_flags) ||
4727	!test_bit(FW_FLAGS_START, &fw_flags)) {
4728	dev_err(&tp->intf->dev,
4729	"Check PHY_STOP fail\n");
4730	goto fail;
4731	}
4732
4733	if (__le32_to_cpu(block->length) != sizeof(*block)) {
4734	dev_err(&tp->intf->dev,
4735	"Invalid length for PHY_STOP\n");
4736	goto fail;
4737	}
4738	__set_bit(FW_FLAGS_STOP, &fw_flags);
4739	break;
4740	case RTL_FW_PHY_NC:
4741	if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4742	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4743	dev_err(&tp->intf->dev,
4744	"check PHY_NC fail\n");
4745	goto fail;
4746	}
4747
4748	if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4749	dev_err(&tp->intf->dev,
4750	"multiple PHY NC encountered\n");
4751	goto fail;
4752	}
4753
4754	if (!rtl8152_is_fw_phy_nc_ok(tp, phy: (struct fw_phy_nc *)block)) {
4755	dev_err(&tp->intf->dev,
4756	"check PHY NC firmware failed\n");
4757	goto fail;
4758	}
4759	__set_bit(FW_FLAGS_NC, &fw_flags);
4760	break;
4761	case RTL_FW_PHY_UNION_NC:
4762	if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4763	test_bit(FW_FLAGS_NC1, &fw_flags) ||
4764	test_bit(FW_FLAGS_NC2, &fw_flags) ||
4765	test_bit(FW_FLAGS_UC2, &fw_flags) ||
4766	test_bit(FW_FLAGS_UC, &fw_flags) ||
4767	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4768	dev_err(&tp->intf->dev, "PHY_UNION_NC out of order\n");
4769	goto fail;
4770	}
4771
4772	if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4773	dev_err(&tp->intf->dev, "multiple PHY_UNION_NC encountered\n");
4774	goto fail;
4775	}
4776
4777	if (!rtl8152_is_fw_phy_union_ok(tp, phy: (struct fw_phy_union *)block)) {
4778	dev_err(&tp->intf->dev, "check PHY_UNION_NC failed\n");
4779	goto fail;
4780	}
4781	__set_bit(FW_FLAGS_NC, &fw_flags);
4782	break;
4783	case RTL_FW_PHY_UNION_NC1:
4784	if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4785	test_bit(FW_FLAGS_NC2, &fw_flags) ||
4786	test_bit(FW_FLAGS_UC2, &fw_flags) ||
4787	test_bit(FW_FLAGS_UC, &fw_flags) ||
4788	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4789	dev_err(&tp->intf->dev, "PHY_UNION_NC1 out of order\n");
4790	goto fail;
4791	}
4792
4793	if (test_bit(FW_FLAGS_NC1, &fw_flags)) {
4794	dev_err(&tp->intf->dev, "multiple PHY NC1 encountered\n");
4795	goto fail;
4796	}
4797
4798	if (!rtl8152_is_fw_phy_union_ok(tp, phy: (struct fw_phy_union *)block)) {
4799	dev_err(&tp->intf->dev, "check PHY_UNION_NC1 failed\n");
4800	goto fail;
4801	}
4802	__set_bit(FW_FLAGS_NC1, &fw_flags);
4803	break;
4804	case RTL_FW_PHY_UNION_NC2:
4805	if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4806	test_bit(FW_FLAGS_UC2, &fw_flags) ||
4807	test_bit(FW_FLAGS_UC, &fw_flags) ||
4808	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4809	dev_err(&tp->intf->dev, "PHY_UNION_NC2 out of order\n");
4810	goto fail;
4811	}
4812
4813	if (test_bit(FW_FLAGS_NC2, &fw_flags)) {
4814	dev_err(&tp->intf->dev, "multiple PHY NC2 encountered\n");
4815	goto fail;
4816	}
4817
4818	if (!rtl8152_is_fw_phy_union_ok(tp, phy: (struct fw_phy_union *)block)) {
4819	dev_err(&tp->intf->dev, "check PHY_UNION_NC2 failed\n");
4820	goto fail;
4821	}
4822	__set_bit(FW_FLAGS_NC2, &fw_flags);
4823	break;
4824	case RTL_FW_PHY_UNION_UC2:
4825	if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4826	test_bit(FW_FLAGS_UC, &fw_flags) ||
4827	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4828	dev_err(&tp->intf->dev, "PHY_UNION_UC2 out of order\n");
4829	goto fail;
4830	}
4831
4832	if (test_bit(FW_FLAGS_UC2, &fw_flags)) {
4833	dev_err(&tp->intf->dev, "multiple PHY UC2 encountered\n");
4834	goto fail;
4835	}
4836
4837	if (!rtl8152_is_fw_phy_union_ok(tp, phy: (struct fw_phy_union *)block)) {
4838	dev_err(&tp->intf->dev, "check PHY_UNION_UC2 failed\n");
4839	goto fail;
4840	}
4841	__set_bit(FW_FLAGS_UC2, &fw_flags);
4842	break;
4843	case RTL_FW_PHY_UNION_UC:
4844	if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4845	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4846	dev_err(&tp->intf->dev, "PHY_UNION_UC out of order\n");
4847	goto fail;
4848	}
4849
4850	if (test_bit(FW_FLAGS_UC, &fw_flags)) {
4851	dev_err(&tp->intf->dev, "multiple PHY UC encountered\n");
4852	goto fail;
4853	}
4854
4855	if (!rtl8152_is_fw_phy_union_ok(tp, phy: (struct fw_phy_union *)block)) {
4856	dev_err(&tp->intf->dev, "check PHY_UNION_UC failed\n");
4857	goto fail;
4858	}
4859	__set_bit(FW_FLAGS_UC, &fw_flags);
4860	break;
4861	case RTL_FW_PHY_UNION_MISC:
4862	if (!rtl8152_is_fw_phy_union_ok(tp, phy: (struct fw_phy_union *)block)) {
4863	dev_err(&tp->intf->dev, "check RTL_FW_PHY_UNION_MISC failed\n");
4864	goto fail;
4865	}
4866	break;
4867	case RTL_FW_PHY_FIXUP:
4868	if (!rtl8152_is_fw_phy_fixup_ok(tp, fix: (struct fw_phy_fixup *)block)) {
4869	dev_err(&tp->intf->dev, "check PHY fixup failed\n");
4870	goto fail;
4871	}
4872	break;
4873	case RTL_FW_PHY_SPEED_UP:
4874	if (test_bit(FW_FLAGS_SPEED_UP, &fw_flags)) {
4875	dev_err(&tp->intf->dev, "multiple PHY firmware encountered");
4876	goto fail;
4877	}
4878
4879	if (!rtl8152_is_fw_phy_speed_up_ok(tp, phy: (struct fw_phy_speed_up *)block)) {
4880	dev_err(&tp->intf->dev, "check PHY speed up failed\n");
4881	goto fail;
4882	}
4883	__set_bit(FW_FLAGS_SPEED_UP, &fw_flags);
4884	break;
4885	case RTL_FW_PHY_VER:
4886	if (test_bit(FW_FLAGS_START, &fw_flags) ||
4887	test_bit(FW_FLAGS_NC, &fw_flags) ||
4888	test_bit(FW_FLAGS_NC1, &fw_flags) ||
4889	test_bit(FW_FLAGS_NC2, &fw_flags) ||
4890	test_bit(FW_FLAGS_UC2, &fw_flags) ||
4891	test_bit(FW_FLAGS_UC, &fw_flags) ||
4892	test_bit(FW_FLAGS_STOP, &fw_flags)) {
4893	dev_err(&tp->intf->dev, "Invalid order to set PHY version\n");
4894	goto fail;
4895	}
4896
4897	if (test_bit(FW_FLAGS_VER, &fw_flags)) {
4898	dev_err(&tp->intf->dev, "multiple PHY version encountered");
4899	goto fail;
4900	}
4901
4902	if (!rtl8152_is_fw_phy_ver_ok(tp, ver: (struct fw_phy_ver *)block)) {
4903	dev_err(&tp->intf->dev, "check PHY version failed\n");
4904	goto fail;
4905	}
4906	__set_bit(FW_FLAGS_VER, &fw_flags);
4907	break;
4908	default:
4909	dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
4910	type);
4911	break;
4912	}
4913
4914	/* next block */
4915	i += ALIGN(__le32_to_cpu(block->length), 8);
4916	}
4917
4918	fw_end:
4919	if (test_bit(FW_FLAGS_START, &fw_flags) && !test_bit(FW_FLAGS_STOP, &fw_flags)) {
4920	dev_err(&tp->intf->dev, "without PHY_STOP\n");
4921	goto fail;
4922	}
4923
4924	return 0;
4925	fail:
4926	return ret;
4927	}
4928
4929	static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait)
4930	{
4931	u32 len;
4932	u8 *data;
4933
4934	rtl_reset_ocp_base(tp);
4935
4936	if (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) {
4937	dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4938	return;
4939	}
4940
4941	len = __le32_to_cpu(phy->blk_hdr.length);
4942	len -= __le16_to_cpu(phy->fw_offset);
4943	data = (u8 *)phy + __le16_to_cpu(phy->fw_offset);
4944
4945	if (rtl_phy_patch_request(tp, request: true, wait))
4946	return;
4947
4948	while (len) {
4949	u32 ocp_data, size;
4950	int i;
4951
4952	if (len < 2048)
4953	size = len;
4954	else
4955	size = 2048;
4956
4957	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL);
4958	ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE;
4959	ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, data: ocp_data);
4960
4961	generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), byteen: 0xff, size, data, MCU_TYPE_USB);
4962
4963	data += size;
4964	len -= size;
4965
4966	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL);
4967	ocp_data |= POL_GPHY_PATCH;
4968	ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, data: ocp_data);
4969
4970	for (i = 0; i < 1000; i++) {
4971	if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH))
4972	break;
4973	}
4974
4975	if (i == 1000) {
4976	dev_err(&tp->intf->dev, "ram code speedup mode timeout\n");
4977	break;
4978	}
4979	}
4980
4981	rtl_reset_ocp_base(tp);
4982
4983	rtl_phy_patch_request(tp, request: false, wait);
4984
4985	if (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version))
4986	dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4987	else
4988	dev_err(&tp->intf->dev, "ram code speedup mode fail\n");
4989	}
4990
4991	static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver)
4992	{
4993	u16 ver_addr, ver;
4994
4995	ver_addr = __le16_to_cpu(phy_ver->ver.addr);
4996	ver = __le16_to_cpu(phy_ver->ver.data);
4997
4998	rtl_reset_ocp_base(tp);
4999
5000	if (sram_read(tp, addr: ver_addr) >= ver) {
5001	dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
5002	return 0;
5003	}
5004
5005	sram_write(tp, addr: ver_addr, data: ver);
5006
5007	dev_dbg(&tp->intf->dev, "PHY firmware version %x\n", ver);
5008
5009	return ver;
5010	}
5011
5012	static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix)
5013	{
5014	u16 addr, data;
5015
5016	rtl_reset_ocp_base(tp);
5017
5018	addr = __le16_to_cpu(fix->setting.addr);
5019	data = ocp_reg_read(tp, addr);
5020
5021	switch (__le16_to_cpu(fix->bit_cmd)) {
5022	case FW_FIXUP_AND:
5023	data &= __le16_to_cpu(fix->setting.data);
5024	break;
5025	case FW_FIXUP_OR:
5026	data |= __le16_to_cpu(fix->setting.data);
5027	break;
5028	case FW_FIXUP_NOT:
5029	data &= ~__le16_to_cpu(fix->setting.data);
5030	break;
5031	case FW_FIXUP_XOR:
5032	data ^= __le16_to_cpu(fix->setting.data);
5033	break;
5034	default:
5035	return;
5036	}
5037
5038	ocp_reg_write(tp, addr, data);
5039
5040	dev_dbg(&tp->intf->dev, "applied ocp %x %x\n", addr, data);
5041	}
5042
5043	static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy)
5044	{
5045	__le16 *data;
5046	u32 length;
5047	int i, num;
5048
5049	rtl_reset_ocp_base(tp);
5050
5051	num = phy->pre_num;
5052	for (i = 0; i < num; i++)
5053	sram_write(tp, __le16_to_cpu(phy->pre_set[i].addr),
5054	__le16_to_cpu(phy->pre_set[i].data));
5055
5056	length = __le32_to_cpu(phy->blk_hdr.length);
5057	length -= __le16_to_cpu(phy->fw_offset);
5058	num = length / 2;
5059	data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
5060
5061	ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
5062	for (i = 0; i < num; i++)
5063	ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
5064
5065	num = phy->bp_num;
5066	for (i = 0; i < num; i++)
5067	sram_write(tp, __le16_to_cpu(phy->bp[i].addr), __le16_to_cpu(phy->bp[i].data));
5068
5069	if (phy->bp_num && phy->bp_en.addr)
5070	sram_write(tp, __le16_to_cpu(phy->bp_en.addr), __le16_to_cpu(phy->bp_en.data));
5071
5072	dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
5073	}
5074
5075	static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
5076	{
5077	u16 mode_reg, bp_index;
5078	u32 length, i, num;
5079	__le16 *data;
5080
5081	rtl_reset_ocp_base(tp);
5082
5083	mode_reg = __le16_to_cpu(phy->mode_reg);
5084	sram_write(tp, addr: mode_reg, __le16_to_cpu(phy->mode_pre));
5085	sram_write(tp, __le16_to_cpu(phy->ba_reg),
5086	__le16_to_cpu(phy->ba_data));
5087
5088	length = __le32_to_cpu(phy->blk_hdr.length);
5089	length -= __le16_to_cpu(phy->fw_offset);
5090	num = length / 2;
5091	data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
5092
5093	ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
5094	for (i = 0; i < num; i++)
5095	ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
5096
5097	sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
5098	__le16_to_cpu(phy->patch_en_value));
5099
5100	bp_index = __le16_to_cpu(phy->bp_start);
5101	num = __le16_to_cpu(phy->bp_num);
5102	for (i = 0; i < num; i++) {
5103	sram_write(tp, addr: bp_index, __le16_to_cpu(phy->bp[i]));
5104	bp_index += 2;
5105	}
5106
5107	sram_write(tp, addr: mode_reg, __le16_to_cpu(phy->mode_post));
5108
5109	dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
5110	}
5111
5112	static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
5113	{
5114	u16 bp_en_addr, type, fw_ver_reg;
5115	u32 length;
5116	u8 *data;
5117
5118	switch (__le32_to_cpu(mac->blk_hdr.type)) {
5119	case RTL_FW_PLA:
5120	type = MCU_TYPE_PLA;
5121	break;
5122	case RTL_FW_USB:
5123	type = MCU_TYPE_USB;
5124	break;
5125	default:
5126	return;
5127	}
5128
5129	fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
5130	if (fw_ver_reg && ocp_read_byte(tp, MCU_TYPE_USB, index: fw_ver_reg) >= mac->fw_ver_data) {
5131	dev_dbg(&tp->intf->dev, "%s firmware has been the newest\n", type ? "PLA" : "USB");
5132	return;
5133	}
5134
5135	rtl_clear_bp(tp, type);
5136
5137	/* Enable backup/restore of MACDBG. This is required after clearing PLA
5138	* break points and before applying the PLA firmware.
5139	*/
5140	if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
5141	!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
5142	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
5143	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
5144	}
5145
5146	length = __le32_to_cpu(mac->blk_hdr.length);
5147	length -= __le16_to_cpu(mac->fw_offset);
5148
5149	data = (u8 *)mac;
5150	data += __le16_to_cpu(mac->fw_offset);
5151
5152	if (generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), byteen: 0xff, size: length,
5153	data, type) < 0) {
5154	dev_err(&tp->intf->dev, "Write %s fw fail\n",
5155	type ? "PLA" : "USB");
5156	return;
5157	}
5158
5159	ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
5160	__le16_to_cpu(mac->bp_ba_value));
5161
5162	if (generic_ocp_write(tp, __le16_to_cpu(mac->bp_start), BYTE_EN_DWORD,
5163	ALIGN(__le16_to_cpu(mac->bp_num) << 1, 4),
5164	data: mac->bp, type) < 0) {
5165	dev_err(&tp->intf->dev, "Write %s bp fail\n",
5166	type ? "PLA" : "USB");
5167	return;
5168	}
5169
5170	bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
5171	if (bp_en_addr)
5172	ocp_write_word(tp, type, index: bp_en_addr,
5173	__le16_to_cpu(mac->bp_en_value));
5174
5175	if (fw_ver_reg)
5176	ocp_write_byte(tp, MCU_TYPE_USB, index: fw_ver_reg,
5177	data: mac->fw_ver_data);
5178
5179	dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
5180	}
5181
5182	static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut)
5183	{
5184	struct rtl_fw *rtl_fw = &tp->rtl_fw;
5185	const struct firmware *fw;
5186	struct fw_header *fw_hdr;
5187	struct fw_phy_patch_key *key;
5188	u16 key_addr = 0;
5189	int i, patch_phy = 1;
5190
5191	if (IS_ERR_OR_NULL(ptr: rtl_fw->fw))
5192	return;
5193
5194	fw = rtl_fw->fw;
5195	fw_hdr = (struct fw_header *)fw->data;
5196
5197	if (rtl_fw->pre_fw)
5198	rtl_fw->pre_fw(tp);
5199
5200	for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
5201	struct fw_block *block = (struct fw_block *)&fw->data[i];
5202
5203	switch (__le32_to_cpu(block->type)) {
5204	case RTL_FW_END:
5205	goto post_fw;
5206	case RTL_FW_PLA:
5207	case RTL_FW_USB:
5208	rtl8152_fw_mac_apply(tp, mac: (struct fw_mac *)block);
5209	break;
5210	case RTL_FW_PHY_START:
5211	if (!patch_phy)
5212	break;
5213	key = (struct fw_phy_patch_key *)block;
5214	key_addr = __le16_to_cpu(key->key_reg);
5215	rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), wait: !power_cut);
5216	break;
5217	case RTL_FW_PHY_STOP:
5218	if (!patch_phy)
5219	break;
5220	WARN_ON(!key_addr);
5221	rtl_post_ram_code(tp, key_addr, wait: !power_cut);
5222	break;
5223	case RTL_FW_PHY_NC:
5224	rtl8152_fw_phy_nc_apply(tp, phy: (struct fw_phy_nc *)block);
5225	break;
5226	case RTL_FW_PHY_VER:
5227	patch_phy = rtl8152_fw_phy_ver(tp, phy_ver: (struct fw_phy_ver *)block);
5228	break;
5229	case RTL_FW_PHY_UNION_NC:
5230	case RTL_FW_PHY_UNION_NC1:
5231	case RTL_FW_PHY_UNION_NC2:
5232	case RTL_FW_PHY_UNION_UC2:
5233	case RTL_FW_PHY_UNION_UC:
5234	case RTL_FW_PHY_UNION_MISC:
5235	if (patch_phy)
5236	rtl8152_fw_phy_union_apply(tp, phy: (struct fw_phy_union *)block);
5237	break;
5238	case RTL_FW_PHY_FIXUP:
5239	if (patch_phy)
5240	rtl8152_fw_phy_fixup(tp, fix: (struct fw_phy_fixup *)block);
5241	break;
5242	case RTL_FW_PHY_SPEED_UP:
5243	rtl_ram_code_speed_up(tp, phy: (struct fw_phy_speed_up *)block, wait: !power_cut);
5244	break;
5245	default:
5246	break;
5247	}
5248
5249	i += ALIGN(__le32_to_cpu(block->length), 8);
5250	}
5251
5252	post_fw:
5253	if (rtl_fw->post_fw)
5254	rtl_fw->post_fw(tp);
5255
5256	rtl_reset_ocp_base(tp);
5257	strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
5258	dev_dbg(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
5259	}
5260
5261	static void rtl8152_release_firmware(struct r8152 *tp)
5262	{
5263	struct rtl_fw *rtl_fw = &tp->rtl_fw;
5264
5265	if (!IS_ERR_OR_NULL(ptr: rtl_fw->fw)) {
5266	release_firmware(fw: rtl_fw->fw);
5267	rtl_fw->fw = NULL;
5268	}
5269	}
5270
5271	static int rtl8152_request_firmware(struct r8152 *tp)
5272	{
5273	struct rtl_fw *rtl_fw = &tp->rtl_fw;
5274	long rc;
5275
5276	if (rtl_fw->fw || !rtl_fw->fw_name) {
5277	dev_info(&tp->intf->dev, "skip request firmware\n");
5278	rc = 0;
5279	goto result;
5280	}
5281
5282	rc = request_firmware(fw: &rtl_fw->fw, name: rtl_fw->fw_name, device: &tp->intf->dev);
5283	if (rc < 0)
5284	goto result;
5285
5286	rc = rtl8152_check_firmware(tp, rtl_fw);
5287	if (rc < 0)
5288	release_firmware(fw: rtl_fw->fw);
5289
5290	result:
5291	if (rc) {
5292	rtl_fw->fw = ERR_PTR(error: rc);
5293
5294	dev_warn(&tp->intf->dev,
5295	"unable to load firmware patch %s (%ld)\n",
5296	rtl_fw->fw_name, rc);
5297	}
5298
5299	return rc;
5300	}
5301
5302	static void r8152_aldps_en(struct r8152 *tp, bool enable)
5303	{
5304	if (enable) {
5305	ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
5306	LINKENA | DIS_SDSAVE);
5307	} else {
5308	ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
5309	DIS_SDSAVE);
5310	msleep(msecs: 20);
5311	}
5312	}
5313
5314	static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
5315	{
5316	ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
5317	ocp_reg_write(tp, OCP_EEE_DATA, data: reg);
5318	ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
5319	}
5320
5321	static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
5322	{
5323	u16 data;
5324
5325	r8152_mmd_indirect(tp, dev, reg);
5326	data = ocp_reg_read(tp, OCP_EEE_DATA);
5327	ocp_reg_write(tp, OCP_EEE_AR, data: 0x0000);
5328
5329	return data;
5330	}
5331
5332	static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
5333	{
5334	r8152_mmd_indirect(tp, dev, reg);
5335	ocp_reg_write(tp, OCP_EEE_DATA, data);
5336	ocp_reg_write(tp, OCP_EEE_AR, data: 0x0000);
5337	}
5338
5339	static void r8152_eee_en(struct r8152 *tp, bool enable)
5340	{
5341	u16 config1, config2, config3;
5342	u32 ocp_data;
5343
5344	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5345	config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
5346	config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
5347	config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
5348
5349	if (enable) {
5350	ocp_data |= EEE_RX_EN | EEE_TX_EN;
5351	config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
5352	config1 |= sd_rise_time(1);
5353	config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
5354	config3 |= fast_snr(42);
5355	} else {
5356	ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5357	config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
5358	RX_QUIET_EN);
5359	config1 |= sd_rise_time(7);
5360	config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
5361	config3 |= fast_snr(511);
5362	}
5363
5364	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, data: ocp_data);
5365	ocp_reg_write(tp, OCP_EEE_CONFIG1, data: config1);
5366	ocp_reg_write(tp, OCP_EEE_CONFIG2, data: config2);
5367	ocp_reg_write(tp, OCP_EEE_CONFIG3, data: config3);
5368	}
5369
5370	static void r8153_eee_en(struct r8152 *tp, bool enable)
5371	{
5372	u32 ocp_data;
5373	u16 config;
5374
5375	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5376	config = ocp_reg_read(tp, OCP_EEE_CFG);
5377
5378	if (enable) {
5379	ocp_data |= EEE_RX_EN | EEE_TX_EN;
5380	config |= EEE10_EN;
5381	} else {
5382	ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5383	config &= ~EEE10_EN;
5384	}
5385
5386	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, data: ocp_data);
5387	ocp_reg_write(tp, OCP_EEE_CFG, data: config);
5388
5389	tp->ups_info.eee = enable;
5390	}
5391
5392	static void r8156_eee_en(struct r8152 *tp, bool enable)
5393	{
5394	u16 config;
5395
5396	r8153_eee_en(tp, enable);
5397
5398	config = ocp_reg_read(tp, OCP_EEE_ADV2);
5399
5400	if (enable)
5401	config |= MDIO_EEE_2_5GT;
5402	else
5403	config &= ~MDIO_EEE_2_5GT;
5404
5405	ocp_reg_write(tp, OCP_EEE_ADV2, data: config);
5406	}
5407
5408	static void rtl_eee_enable(struct r8152 *tp, bool enable)
5409	{
5410	switch (tp->version) {
5411	case RTL_VER_01:
5412	case RTL_VER_02:
5413	case RTL_VER_07:
5414	if (enable) {
5415	r8152_eee_en(tp, enable: true);
5416	r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
5417	data: tp->eee_adv);
5418	} else {
5419	r8152_eee_en(tp, enable: false);
5420	r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, data: 0);
5421	}
5422	break;
5423	case RTL_VER_03:
5424	case RTL_VER_04:
5425	case RTL_VER_05:
5426	case RTL_VER_06:
5427	case RTL_VER_08:
5428	case RTL_VER_09:
5429	case RTL_VER_14:
5430	if (enable) {
5431	r8153_eee_en(tp, enable: true);
5432	ocp_reg_write(tp, OCP_EEE_ADV, data: tp->eee_adv);
5433	} else {
5434	r8153_eee_en(tp, enable: false);
5435	ocp_reg_write(tp, OCP_EEE_ADV, data: 0);
5436	}
5437	break;
5438	case RTL_VER_10:
5439	case RTL_VER_11:
5440	case RTL_VER_12:
5441	case RTL_VER_13:
5442	case RTL_VER_15:
5443	if (enable) {
5444	r8156_eee_en(tp, enable: true);
5445	ocp_reg_write(tp, OCP_EEE_ADV, data: tp->eee_adv);
5446	} else {
5447	r8156_eee_en(tp, enable: false);
5448	ocp_reg_write(tp, OCP_EEE_ADV, data: 0);
5449	}
5450	break;
5451	default:
5452	break;
5453	}
5454	}
5455
5456	static void r8152b_enable_fc(struct r8152 *tp)
5457	{
5458	u16 anar;
5459
5460	anar = r8152_mdio_read(tp, MII_ADVERTISE);
5461	anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
5462	r8152_mdio_write(tp, MII_ADVERTISE, value: anar);
5463
5464	tp->ups_info.flow_control = true;
5465	}
5466
5467	static void rtl8152_disable(struct r8152 *tp)
5468	{
5469	r8152_aldps_en(tp, enable: false);
5470	rtl_disable(tp);
5471	r8152_aldps_en(tp, enable: true);
5472	}
5473
5474	static void r8152b_hw_phy_cfg(struct r8152 *tp)
5475	{
5476	rtl8152_apply_firmware(tp, power_cut: false);
5477	rtl_eee_enable(tp, enable: tp->eee_en);
5478	r8152_aldps_en(tp, enable: true);
5479	r8152b_enable_fc(tp);
5480
5481	set_bit(nr: PHY_RESET, addr: &tp->flags);
5482	}
5483
5484	static void wait_oob_link_list_ready(struct r8152 *tp)
5485	{
5486	u32 ocp_data;
5487	int i;
5488
5489	for (i = 0; i < 1000; i++) {
5490	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
5491	break;
5492	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5493	if (ocp_data & LINK_LIST_READY)
5494	break;
5495	usleep_range(min: 1000, max: 2000);
5496	}
5497	}
5498
5499	static void r8156b_wait_loading_flash(struct r8152 *tp)
5500	{
5501	if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) &&
5502	!(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) {
5503	int i;
5504
5505	for (i = 0; i < 100; i++) {
5506	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
5507	break;
5508	if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE)
5509	break;
5510	usleep_range(min: 1000, max: 2000);
5511	}
5512	}
5513	}
5514
5515	static void r8152b_exit_oob(struct r8152 *tp)
5516	{
5517	u32 ocp_data;
5518
5519	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5520	ocp_data &= ~RCR_ACPT_ALL;
5521	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
5522
5523	rxdy_gated_en(tp, enable: true);
5524	r8153_teredo_off(tp);
5525	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
5526	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, data: 0x00);
5527
5528	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5529	ocp_data &= ~NOW_IS_OOB;
5530	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
5531
5532	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5533	ocp_data &= ~MCU_BORW_EN;
5534	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
5535
5536	wait_oob_link_list_ready(tp);
5537
5538	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5539	ocp_data |= RE_INIT_LL;
5540	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
5541
5542	wait_oob_link_list_ready(tp);
5543
5544	rtl8152_nic_reset(tp);
5545
5546	/* rx share fifo credit full threshold */
5547	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
5548
5549	if (tp->udev->speed == USB_SPEED_FULL ||
5550	tp->udev->speed == USB_SPEED_LOW) {
5551	/* rx share fifo credit near full threshold */
5552	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5553	RXFIFO_THR2_FULL);
5554	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5555	RXFIFO_THR3_FULL);
5556	} else {
5557	/* rx share fifo credit near full threshold */
5558	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5559	RXFIFO_THR2_HIGH);
5560	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5561	RXFIFO_THR3_HIGH);
5562	}
5563
5564	/* TX share fifo free credit full threshold */
5565	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
5566
5567	ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
5568	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
5569	ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
5570	TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
5571
5572	rtl_rx_vlan_en(tp, enable: tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
5573
5574	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5575
5576	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5577	ocp_data |= TCR0_AUTO_FIFO;
5578	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, data: ocp_data);
5579	}
5580
5581	static void r8152b_enter_oob(struct r8152 *tp)
5582	{
5583	u32 ocp_data;
5584
5585	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5586	ocp_data &= ~NOW_IS_OOB;
5587	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
5588
5589	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
5590	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
5591	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
5592
5593	rtl_disable(tp);
5594
5595	wait_oob_link_list_ready(tp);
5596
5597	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5598	ocp_data |= RE_INIT_LL;
5599	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
5600
5601	wait_oob_link_list_ready(tp);
5602
5603	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5604
5605	rtl_rx_vlan_en(tp, enable: true);
5606
5607	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
5608	ocp_data |= ALDPS_PROXY_MODE;
5609	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, data: ocp_data);
5610
5611	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5612	ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
5613	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
5614
5615	rxdy_gated_en(tp, enable: false);
5616
5617	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5618	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
5619	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
5620	}
5621
5622	static int r8153_pre_firmware_1(struct r8152 *tp)
5623	{
5624	int i;
5625
5626	/* Wait till the WTD timer is ready. It would take at most 104 ms. */
5627	for (i = 0; i < 104; i++) {
5628	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
5629
5630	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
5631	return -ENODEV;
5632	if (!(ocp_data & WTD1_EN))
5633	break;
5634	usleep_range(min: 1000, max: 2000);
5635	}
5636
5637	return 0;
5638	}
5639
5640	static int r8153_post_firmware_1(struct r8152 *tp)
5641	{
5642	/* set USB_BP_4 to support USB_SPEED_SUPER only */
5643	if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
5644	ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
5645
5646	/* reset UPHY timer to 36 ms */
5647	ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, data: 36000 / 16);
5648
5649	return 0;
5650	}
5651
5652	static int r8153_pre_firmware_2(struct r8152 *tp)
5653	{
5654	u32 ocp_data;
5655
5656	r8153_pre_firmware_1(tp);
5657
5658	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5659	ocp_data &= ~FW_FIX_SUSPEND;
5660	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, data: ocp_data);
5661
5662	return 0;
5663	}
5664
5665	static int r8153_post_firmware_2(struct r8152 *tp)
5666	{
5667	u32 ocp_data;
5668
5669	/* enable bp0 if support USB_SPEED_SUPER only */
5670	if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
5671	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5672	ocp_data |= BIT(0);
5673	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, data: ocp_data);
5674	}
5675
5676	/* reset UPHY timer to 36 ms */
5677	ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, data: 36000 / 16);
5678
5679	/* enable U3P3 check, set the counter to 4 */
5680	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
5681
5682	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5683	ocp_data |= FW_FIX_SUSPEND;
5684	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, data: ocp_data);
5685
5686	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5687	ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5688	ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, data: ocp_data);
5689
5690	return 0;
5691	}
5692
5693	static int r8153_post_firmware_3(struct r8152 *tp)
5694	{
5695	u32 ocp_data;
5696
5697	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5698	ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5699	ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, data: ocp_data);
5700
5701	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5702	ocp_data |= FW_IP_RESET_EN;
5703	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, data: ocp_data);
5704
5705	return 0;
5706	}
5707
5708	static int r8153b_pre_firmware_1(struct r8152 *tp)
5709	{
5710	/* enable fc timer and set timer to 1 second. */
5711	ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
5712	CTRL_TIMER_EN | (1000 / 8));
5713
5714	return 0;
5715	}
5716
5717	static int r8153b_post_firmware_1(struct r8152 *tp)
5718	{
5719	u32 ocp_data;
5720
5721	/* enable bp0 for RTL8153-BND */
5722	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
5723	if (ocp_data & BND_MASK) {
5724	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5725	ocp_data |= BIT(0);
5726	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, data: ocp_data);
5727	}
5728
5729	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5730	ocp_data |= FLOW_CTRL_PATCH_OPT;
5731	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, data: ocp_data);
5732
5733	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5734	ocp_data |= FC_PATCH_TASK;
5735	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
5736
5737	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5738	ocp_data |= FW_IP_RESET_EN;
5739	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, data: ocp_data);
5740
5741	return 0;
5742	}
5743
5744	static int r8153c_post_firmware_1(struct r8152 *tp)
5745	{
5746	u32 ocp_data;
5747
5748	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5749	ocp_data |= FLOW_CTRL_PATCH_2;
5750	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, data: ocp_data);
5751
5752	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5753	ocp_data |= FC_PATCH_TASK;
5754	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
5755
5756	return 0;
5757	}
5758
5759	static int r8156a_post_firmware_1(struct r8152 *tp)
5760	{
5761	u32 ocp_data;
5762
5763	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5764	ocp_data |= FW_IP_RESET_EN;
5765	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, data: ocp_data);
5766
5767	/* Modify U3PHY parameter for compatibility issue */
5768	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, data: 0x4026840e);
5769	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, data: 0x4001acc9);
5770
5771	return 0;
5772	}
5773
5774	static void r8153_aldps_en(struct r8152 *tp, bool enable)
5775	{
5776	u16 data;
5777
5778	data = ocp_reg_read(tp, OCP_POWER_CFG);
5779	if (enable) {
5780	data |= EN_ALDPS;
5781	ocp_reg_write(tp, OCP_POWER_CFG, data);
5782	} else {
5783	int i;
5784
5785	data &= ~EN_ALDPS;
5786	ocp_reg_write(tp, OCP_POWER_CFG, data);
5787	for (i = 0; i < 20; i++) {
5788	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
5789	return;
5790	usleep_range(min: 1000, max: 2000);
5791	if (ocp_read_word(tp, MCU_TYPE_PLA, index: 0xe000) & 0x0100)
5792	break;
5793	}
5794	}
5795
5796	tp->ups_info.aldps = enable;
5797	}
5798
5799	static void r8153_hw_phy_cfg(struct r8152 *tp)
5800	{
5801	u32 ocp_data;
5802	u16 data;
5803
5804	/* disable ALDPS before updating the PHY parameters */
5805	r8153_aldps_en(tp, enable: false);
5806
5807	/* disable EEE before updating the PHY parameters */
5808	rtl_eee_enable(tp, enable: false);
5809
5810	rtl8152_apply_firmware(tp, power_cut: false);
5811
5812	if (tp->version == RTL_VER_03) {
5813	data = ocp_reg_read(tp, OCP_EEE_CFG);
5814	data &= ~CTAP_SHORT_EN;
5815	ocp_reg_write(tp, OCP_EEE_CFG, data);
5816	}
5817
5818	data = ocp_reg_read(tp, OCP_POWER_CFG);
5819	data |= EEE_CLKDIV_EN;
5820	ocp_reg_write(tp, OCP_POWER_CFG, data);
5821
5822	data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5823	data |= EN_10M_BGOFF;
5824	ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5825	data = ocp_reg_read(tp, OCP_POWER_CFG);
5826	data |= EN_10M_PLLOFF;
5827	ocp_reg_write(tp, OCP_POWER_CFG, data);
5828	sram_write(tp, SRAM_IMPEDANCE, data: 0x0b13);
5829
5830	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5831	ocp_data |= PFM_PWM_SWITCH;
5832	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, data: ocp_data);
5833
5834	/* Enable LPF corner auto tune */
5835	sram_write(tp, SRAM_LPF_CFG, data: 0xf70f);
5836
5837	/* Adjust 10M Amplitude */
5838	sram_write(tp, SRAM_10M_AMP1, data: 0x00af);
5839	sram_write(tp, SRAM_10M_AMP2, data: 0x0208);
5840
5841	if (tp->eee_en)
5842	rtl_eee_enable(tp, enable: true);
5843
5844	r8153_aldps_en(tp, enable: true);
5845	r8152b_enable_fc(tp);
5846
5847	switch (tp->version) {
5848	case RTL_VER_03:
5849	case RTL_VER_04:
5850	break;
5851	case RTL_VER_05:
5852	case RTL_VER_06:
5853	default:
5854	r8153_u2p3en(tp, enable: true);
5855	break;
5856	}
5857
5858	set_bit(nr: PHY_RESET, addr: &tp->flags);
5859	}
5860
5861	static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
5862	{
5863	u32 ocp_data;
5864
5865	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
5866	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
5867	ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
5868	ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
5869
5870	return ocp_data;
5871	}
5872
5873	static void r8153b_hw_phy_cfg(struct r8152 *tp)
5874	{
5875	u32 ocp_data;
5876	u16 data;
5877
5878	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
5879	if (ocp_data & PCUT_STATUS) {
5880	ocp_data &= ~PCUT_STATUS;
5881	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, data: ocp_data);
5882	}
5883
5884	/* disable ALDPS before updating the PHY parameters */
5885	r8153_aldps_en(tp, enable: false);
5886
5887	/* disable EEE before updating the PHY parameters */
5888	rtl_eee_enable(tp, enable: false);
5889
5890	/* U1/U2/L1 idle timer. 500 us */
5891	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, data: 500);
5892
5893	data = r8153_phy_status(tp, desired: 0);
5894
5895	switch (data) {
5896	case PHY_STAT_PWRDN:
5897	case PHY_STAT_EXT_INIT:
5898	rtl8152_apply_firmware(tp, power_cut: true);
5899
5900	data = r8152_mdio_read(tp, MII_BMCR);
5901	data &= ~BMCR_PDOWN;
5902	r8152_mdio_write(tp, MII_BMCR, value: data);
5903	break;
5904	case PHY_STAT_LAN_ON:
5905	default:
5906	rtl8152_apply_firmware(tp, power_cut: false);
5907	break;
5908	}
5909
5910	r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
5911
5912	data = sram_read(tp, SRAM_GREEN_CFG);
5913	data |= R_TUNE_EN;
5914	sram_write(tp, SRAM_GREEN_CFG, data);
5915	data = ocp_reg_read(tp, OCP_NCTL_CFG);
5916	data |= PGA_RETURN_EN;
5917	ocp_reg_write(tp, OCP_NCTL_CFG, data);
5918
5919	/* ADC Bias Calibration:
5920	* read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
5921	* bit (bit3) to rebuild the real 16-bit data. Write the data to the
5922	* ADC ioffset.
5923	*/
5924	ocp_data = r8152_efuse_read(tp, addr: 0x7d);
5925	data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
5926	if (data != 0xffff)
5927	ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
5928
5929	/* ups mode tx-link-pulse timing adjustment:
5930	* rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
5931	* swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
5932	*/
5933	ocp_data = ocp_reg_read(tp, addr: 0xc426);
5934	ocp_data &= 0x3fff;
5935	if (ocp_data) {
5936	u32 swr_cnt_1ms_ini;
5937
5938	swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
5939	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
5940	ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
5941	ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, data: ocp_data);
5942	}
5943
5944	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5945	ocp_data |= PFM_PWM_SWITCH;
5946	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, data: ocp_data);
5947
5948	/* Advnace EEE */
5949	if (!rtl_phy_patch_request(tp, request: true, wait: true)) {
5950	data = ocp_reg_read(tp, OCP_POWER_CFG);
5951	data |= EEE_CLKDIV_EN;
5952	ocp_reg_write(tp, OCP_POWER_CFG, data);
5953	tp->ups_info.eee_ckdiv = true;
5954
5955	data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5956	data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
5957	ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5958	tp->ups_info.eee_cmod_lv = true;
5959	tp->ups_info._10m_ckdiv = true;
5960	tp->ups_info.eee_plloff_giga = true;
5961
5962	ocp_reg_write(tp, OCP_SYSCLK_CFG, data: 0);
5963	ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
5964	tp->ups_info._250m_ckdiv = true;
5965
5966	rtl_phy_patch_request(tp, request: false, wait: true);
5967	}
5968
5969	if (tp->eee_en)
5970	rtl_eee_enable(tp, enable: true);
5971
5972	r8153_aldps_en(tp, enable: true);
5973	r8152b_enable_fc(tp);
5974
5975	set_bit(nr: PHY_RESET, addr: &tp->flags);
5976	}
5977
5978	static void r8153c_hw_phy_cfg(struct r8152 *tp)
5979	{
5980	r8153b_hw_phy_cfg(tp);
5981
5982	tp->ups_info.r_tune = true;
5983	}
5984
5985	static void rtl8153_change_mtu(struct r8152 *tp)
5986	{
5987	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
5988	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
5989	}
5990
5991	static void r8153_first_init(struct r8152 *tp)
5992	{
5993	u32 ocp_data;
5994
5995	rxdy_gated_en(tp, enable: true);
5996	r8153_teredo_off(tp);
5997
5998	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5999	ocp_data &= ~RCR_ACPT_ALL;
6000	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
6001
6002	rtl8152_nic_reset(tp);
6003	rtl_reset_bmu(tp);
6004
6005	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6006	ocp_data &= ~NOW_IS_OOB;
6007	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
6008
6009	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6010	ocp_data &= ~MCU_BORW_EN;
6011	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6012
6013	wait_oob_link_list_ready(tp);
6014
6015	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6016	ocp_data |= RE_INIT_LL;
6017	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6018
6019	wait_oob_link_list_ready(tp);
6020
6021	rtl_rx_vlan_en(tp, enable: tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6022
6023	rtl8153_change_mtu(tp);
6024
6025	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
6026	ocp_data |= TCR0_AUTO_FIFO;
6027	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, data: ocp_data);
6028
6029	rtl8152_nic_reset(tp);
6030
6031	/* rx share fifo credit full threshold */
6032	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
6033	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
6034	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
6035	/* TX share fifo free credit full threshold */
6036	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
6037	}
6038
6039	static void r8153_enter_oob(struct r8152 *tp)
6040	{
6041	u32 ocp_data;
6042
6043	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6044	ocp_data &= ~NOW_IS_OOB;
6045	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
6046
6047	/* RX FIFO settings for OOB */
6048	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
6049	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
6050	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
6051
6052	rtl_disable(tp);
6053	rtl_reset_bmu(tp);
6054
6055	wait_oob_link_list_ready(tp);
6056
6057	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6058	ocp_data |= RE_INIT_LL;
6059	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6060
6061	wait_oob_link_list_ready(tp);
6062
6063	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, data: 1522);
6064	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT);
6065
6066	switch (tp->version) {
6067	case RTL_VER_03:
6068	case RTL_VER_04:
6069	case RTL_VER_05:
6070	case RTL_VER_06:
6071	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
6072	ocp_data &= ~TEREDO_WAKE_MASK;
6073	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, data: ocp_data);
6074	break;
6075
6076	case RTL_VER_08:
6077	case RTL_VER_09:
6078	case RTL_VER_14:
6079	/* Clear teredo wake event. bit[15:8] is the teredo wakeup
6080	* type. Set it to zero. bits[7:0] are the W1C bits about
6081	* the events. Set them to all 1 to clear them.
6082	*/
6083	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, data: 0x00ff);
6084	break;
6085
6086	default:
6087	break;
6088	}
6089
6090	rtl_rx_vlan_en(tp, enable: true);
6091
6092	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
6093	ocp_data |= ALDPS_PROXY_MODE;
6094	ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, data: ocp_data);
6095
6096	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6097	ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
6098	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
6099
6100	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6101	ocp_data |= MCU_BORW_EN;
6102	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6103
6104	rxdy_gated_en(tp, enable: false);
6105
6106	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6107	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
6108	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
6109	}
6110
6111	static void rtl8153_disable(struct r8152 *tp)
6112	{
6113	r8153_aldps_en(tp, enable: false);
6114	rtl_disable(tp);
6115	rtl_reset_bmu(tp);
6116	r8153_aldps_en(tp, enable: true);
6117	}
6118
6119	static u32 fc_pause_on_auto(struct r8152 *tp)
6120	{
6121	return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024);
6122	}
6123
6124	static u32 fc_pause_off_auto(struct r8152 *tp)
6125	{
6126	return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024);
6127	}
6128
6129	static void r8156_fc_parameter(struct r8152 *tp)
6130	{
6131	u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp);
6132	u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp);
6133
6134	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, data: pause_on / 16);
6135	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, data: pause_off / 16);
6136	}
6137
6138	static int rtl8156_enable(struct r8152 *tp)
6139	{
6140	u32 ocp_data;
6141	u16 speed;
6142
6143	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6144	return -ENODEV;
6145
6146	r8156_fc_parameter(tp);
6147	set_tx_qlen(tp);
6148	rtl_set_eee_plus(tp);
6149	r8153_set_rx_early_timeout(tp);
6150	r8153_set_rx_early_size(tp);
6151
6152	speed = rtl8152_get_speed(tp);
6153	rtl_set_ifg(tp, speed);
6154
6155	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
6156	if (speed & _2500bps)
6157	ocp_data &= ~IDLE_SPDWN_EN;
6158	else
6159	ocp_data |= IDLE_SPDWN_EN;
6160	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, data: ocp_data);
6161
6162	if (speed & _1000bps)
6163	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, data: 0x11);
6164	else if (speed & _500bps)
6165	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, data: 0x3d);
6166
6167	if (tp->udev->speed == USB_SPEED_HIGH) {
6168	/* USB 0xb45e[3:0] l1_nyet_hird */
6169	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
6170	ocp_data &= ~0xf;
6171	if (is_flow_control(speed))
6172	ocp_data |= 0xf;
6173	else
6174	ocp_data |= 0x1;
6175	ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, data: ocp_data);
6176	}
6177
6178	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
6179	ocp_data &= ~FC_PATCH_TASK;
6180	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
6181	usleep_range(min: 1000, max: 2000);
6182	ocp_data |= FC_PATCH_TASK;
6183	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
6184
6185	return rtl_enable(tp);
6186	}
6187
6188	static void rtl8156_disable(struct r8152 *tp)
6189	{
6190	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, data: 0);
6191	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, data: 0);
6192
6193	rtl8153_disable(tp);
6194	}
6195
6196	static int rtl8156b_enable(struct r8152 *tp)
6197	{
6198	u32 ocp_data;
6199	u16 speed;
6200
6201	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6202	return -ENODEV;
6203
6204	set_tx_qlen(tp);
6205	rtl_set_eee_plus(tp);
6206
6207	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM);
6208	ocp_data &= ~RX_AGGR_NUM_MASK;
6209	ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, data: ocp_data);
6210
6211	r8153_set_rx_early_timeout(tp);
6212	r8153_set_rx_early_size(tp);
6213
6214	speed = rtl8152_get_speed(tp);
6215	rtl_set_ifg(tp, speed);
6216
6217	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
6218	if (speed & _2500bps)
6219	ocp_data &= ~IDLE_SPDWN_EN;
6220	else
6221	ocp_data |= IDLE_SPDWN_EN;
6222	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, data: ocp_data);
6223
6224	if (tp->udev->speed == USB_SPEED_HIGH) {
6225	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
6226	ocp_data &= ~0xf;
6227	if (is_flow_control(speed))
6228	ocp_data |= 0xf;
6229	else
6230	ocp_data |= 0x1;
6231	ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, data: ocp_data);
6232	}
6233
6234	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
6235	ocp_data &= ~FC_PATCH_TASK;
6236	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
6237	usleep_range(min: 1000, max: 2000);
6238	ocp_data |= FC_PATCH_TASK;
6239	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
6240
6241	return rtl_enable(tp);
6242	}
6243
6244	static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
6245	u32 advertising)
6246	{
6247	u16 bmcr;
6248	int ret = 0;
6249
6250	if (autoneg == AUTONEG_DISABLE) {
6251	if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
6252	return -EINVAL;
6253
6254	switch (speed) {
6255	case SPEED_10:
6256	bmcr = BMCR_SPEED10;
6257	if (duplex == DUPLEX_FULL) {
6258	bmcr |= BMCR_FULLDPLX;
6259	tp->ups_info.speed_duplex = FORCE_10M_FULL;
6260	} else {
6261	tp->ups_info.speed_duplex = FORCE_10M_HALF;
6262	}
6263	break;
6264	case SPEED_100:
6265	bmcr = BMCR_SPEED100;
6266	if (duplex == DUPLEX_FULL) {
6267	bmcr |= BMCR_FULLDPLX;
6268	tp->ups_info.speed_duplex = FORCE_100M_FULL;
6269	} else {
6270	tp->ups_info.speed_duplex = FORCE_100M_HALF;
6271	}
6272	break;
6273	case SPEED_1000:
6274	if (tp->mii.supports_gmii) {
6275	bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
6276	tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6277	break;
6278	}
6279	fallthrough;
6280	default:
6281	ret = -EINVAL;
6282	goto out;
6283	}
6284
6285	if (duplex == DUPLEX_FULL)
6286	tp->mii.full_duplex = 1;
6287	else
6288	tp->mii.full_duplex = 0;
6289
6290	tp->mii.force_media = 1;
6291	} else {
6292	u16 orig, new1;
6293	u32 support;
6294
6295	support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6296	RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6297
6298	if (tp->mii.supports_gmii) {
6299	support |= RTL_ADVERTISED_1000_FULL;
6300
6301	if (tp->support_2500full)
6302	support |= RTL_ADVERTISED_2500_FULL;
6303	}
6304
6305	if (!(advertising & support))
6306	return -EINVAL;
6307
6308	orig = r8152_mdio_read(tp, MII_ADVERTISE);
6309	new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
6310	ADVERTISE_100HALF | ADVERTISE_100FULL);
6311	if (advertising & RTL_ADVERTISED_10_HALF) {
6312	new1 |= ADVERTISE_10HALF;
6313	tp->ups_info.speed_duplex = NWAY_10M_HALF;
6314	}
6315	if (advertising & RTL_ADVERTISED_10_FULL) {
6316	new1 |= ADVERTISE_10FULL;
6317	tp->ups_info.speed_duplex = NWAY_10M_FULL;
6318	}
6319
6320	if (advertising & RTL_ADVERTISED_100_HALF) {
6321	new1 |= ADVERTISE_100HALF;
6322	tp->ups_info.speed_duplex = NWAY_100M_HALF;
6323	}
6324	if (advertising & RTL_ADVERTISED_100_FULL) {
6325	new1 |= ADVERTISE_100FULL;
6326	tp->ups_info.speed_duplex = NWAY_100M_FULL;
6327	}
6328
6329	if (orig != new1) {
6330	r8152_mdio_write(tp, MII_ADVERTISE, value: new1);
6331	tp->mii.advertising = new1;
6332	}
6333
6334	if (tp->mii.supports_gmii) {
6335	orig = r8152_mdio_read(tp, MII_CTRL1000);
6336	new1 = orig & ~(ADVERTISE_1000FULL |
6337	ADVERTISE_1000HALF);
6338
6339	if (advertising & RTL_ADVERTISED_1000_FULL) {
6340	new1 |= ADVERTISE_1000FULL;
6341	tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6342	}
6343
6344	if (orig != new1)
6345	r8152_mdio_write(tp, MII_CTRL1000, value: new1);
6346	}
6347
6348	if (tp->support_2500full) {
6349	orig = ocp_reg_read(tp, OCP_10GBT_CTRL);
6350	new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G;
6351
6352	if (advertising & RTL_ADVERTISED_2500_FULL) {
6353	new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G;
6354	tp->ups_info.speed_duplex = NWAY_2500M_FULL;
6355	}
6356
6357	if (orig != new1)
6358	ocp_reg_write(tp, OCP_10GBT_CTRL, data: new1);
6359	}
6360
6361	bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
6362
6363	tp->mii.force_media = 0;
6364	}
6365
6366	if (test_and_clear_bit(nr: PHY_RESET, addr: &tp->flags))
6367	bmcr |= BMCR_RESET;
6368
6369	r8152_mdio_write(tp, MII_BMCR, value: bmcr);
6370
6371	if (bmcr & BMCR_RESET) {
6372	int i;
6373
6374	for (i = 0; i < 50; i++) {
6375	msleep(msecs: 20);
6376	if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
6377	break;
6378	}
6379	}
6380
6381	out:
6382	return ret;
6383	}
6384
6385	static void rtl8152_up(struct r8152 *tp)
6386	{
6387	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6388	return;
6389
6390	r8152_aldps_en(tp, enable: false);
6391	r8152b_exit_oob(tp);
6392	r8152_aldps_en(tp, enable: true);
6393	}
6394
6395	static void rtl8152_down(struct r8152 *tp)
6396	{
6397	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6398	rtl_drop_queued_tx(tp);
6399	return;
6400	}
6401
6402	r8152_power_cut_en(tp, enable: false);
6403	r8152_aldps_en(tp, enable: false);
6404	r8152b_enter_oob(tp);
6405	r8152_aldps_en(tp, enable: true);
6406	}
6407
6408	static void rtl8153_up(struct r8152 *tp)
6409	{
6410	u32 ocp_data;
6411
6412	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6413	return;
6414
6415	r8153_u1u2en(tp, enable: false);
6416	r8153_u2p3en(tp, enable: false);
6417	r8153_aldps_en(tp, enable: false);
6418	r8153_first_init(tp);
6419
6420	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6421	ocp_data |= LANWAKE_CLR_EN;
6422	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, data: ocp_data);
6423
6424	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
6425	ocp_data &= ~LANWAKE_PIN;
6426	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, data: ocp_data);
6427
6428	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
6429	ocp_data &= ~DELAY_PHY_PWR_CHG;
6430	ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, data: ocp_data);
6431
6432	r8153_aldps_en(tp, enable: true);
6433
6434	switch (tp->version) {
6435	case RTL_VER_03:
6436	case RTL_VER_04:
6437	break;
6438	case RTL_VER_05:
6439	case RTL_VER_06:
6440	default:
6441	r8153_u2p3en(tp, enable: true);
6442	break;
6443	}
6444
6445	r8153_u1u2en(tp, enable: true);
6446	}
6447
6448	static void rtl8153_down(struct r8152 *tp)
6449	{
6450	u32 ocp_data;
6451
6452	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6453	rtl_drop_queued_tx(tp);
6454	return;
6455	}
6456
6457	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6458	ocp_data &= ~LANWAKE_CLR_EN;
6459	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, data: ocp_data);
6460
6461	r8153_u1u2en(tp, enable: false);
6462	r8153_u2p3en(tp, enable: false);
6463	r8153_power_cut_en(tp, enable: false);
6464	r8153_aldps_en(tp, enable: false);
6465	r8153_enter_oob(tp);
6466	r8153_aldps_en(tp, enable: true);
6467	}
6468
6469	static void rtl8153b_up(struct r8152 *tp)
6470	{
6471	u32 ocp_data;
6472
6473	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6474	return;
6475
6476	r8153b_u1u2en(tp, enable: false);
6477	r8153_u2p3en(tp, enable: false);
6478	r8153_aldps_en(tp, enable: false);
6479
6480	r8153_first_init(tp);
6481	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6482
6483	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6484	ocp_data &= ~PLA_MCU_SPDWN_EN;
6485	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
6486
6487	r8153_aldps_en(tp, enable: true);
6488
6489	if (tp->udev->speed >= USB_SPEED_SUPER)
6490	r8153b_u1u2en(tp, enable: true);
6491	}
6492
6493	static void rtl8153b_down(struct r8152 *tp)
6494	{
6495	u32 ocp_data;
6496
6497	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6498	rtl_drop_queued_tx(tp);
6499	return;
6500	}
6501
6502	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6503	ocp_data |= PLA_MCU_SPDWN_EN;
6504	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
6505
6506	r8153b_u1u2en(tp, enable: false);
6507	r8153_u2p3en(tp, enable: false);
6508	r8153b_power_cut_en(tp, enable: false);
6509	r8153_aldps_en(tp, enable: false);
6510	r8153_enter_oob(tp);
6511	r8153_aldps_en(tp, enable: true);
6512	}
6513
6514	static void rtl8153c_change_mtu(struct r8152 *tp)
6515	{
6516	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
6517	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, data: 10 * 1024 / 64);
6518
6519	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, data: 512 / 64);
6520
6521	/* Adjust the tx fifo free credit full threshold, otherwise
6522	* the fifo would be too small to send a jumbo frame packet.
6523	*/
6524	if (tp->netdev->mtu < 8000)
6525	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, data: 2048 / 8);
6526	else
6527	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, data: 900 / 8);
6528	}
6529
6530	static void rtl8153c_up(struct r8152 *tp)
6531	{
6532	u32 ocp_data;
6533
6534	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6535	return;
6536
6537	r8153b_u1u2en(tp, enable: false);
6538	r8153_u2p3en(tp, enable: false);
6539	r8153_aldps_en(tp, enable: false);
6540
6541	rxdy_gated_en(tp, enable: true);
6542	r8153_teredo_off(tp);
6543
6544	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6545	ocp_data &= ~RCR_ACPT_ALL;
6546	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
6547
6548	rtl8152_nic_reset(tp);
6549	rtl_reset_bmu(tp);
6550
6551	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6552	ocp_data &= ~NOW_IS_OOB;
6553	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
6554
6555	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6556	ocp_data &= ~MCU_BORW_EN;
6557	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6558
6559	wait_oob_link_list_ready(tp);
6560
6561	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6562	ocp_data |= RE_INIT_LL;
6563	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6564
6565	wait_oob_link_list_ready(tp);
6566
6567	rtl_rx_vlan_en(tp, enable: tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6568
6569	rtl8153c_change_mtu(tp);
6570
6571	rtl8152_nic_reset(tp);
6572
6573	/* rx share fifo credit full threshold */
6574	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, data: 0x02);
6575	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, data: 0x08);
6576	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
6577	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
6578
6579	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6580
6581	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
6582
6583	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
6584	ocp_data |= BIT(8);
6585	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, data: ocp_data);
6586
6587	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
6588
6589	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6590	ocp_data &= ~PLA_MCU_SPDWN_EN;
6591	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
6592
6593	r8153_aldps_en(tp, enable: true);
6594	r8153b_u1u2en(tp, enable: true);
6595	}
6596
6597	static void rtl8156_change_mtu(struct r8152 *tp)
6598	{
6599	u32 rx_max_size = mtu_to_size(tp->netdev->mtu);
6600
6601	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, data: rx_max_size);
6602	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
6603	r8156_fc_parameter(tp);
6604
6605	/* TX share fifo free credit full threshold */
6606	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, data: 512 / 64);
6607	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL,
6608	ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16);
6609	}
6610
6611	static void rtl8156_up(struct r8152 *tp)
6612	{
6613	u32 ocp_data;
6614
6615	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6616	return;
6617
6618	r8153b_u1u2en(tp, enable: false);
6619	r8153_u2p3en(tp, enable: false);
6620	r8153_aldps_en(tp, enable: false);
6621
6622	rxdy_gated_en(tp, enable: true);
6623	r8153_teredo_off(tp);
6624
6625	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6626	ocp_data &= ~RCR_ACPT_ALL;
6627	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
6628
6629	rtl8152_nic_reset(tp);
6630	rtl_reset_bmu(tp);
6631
6632	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6633	ocp_data &= ~NOW_IS_OOB;
6634	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
6635
6636	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6637	ocp_data &= ~MCU_BORW_EN;
6638	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6639
6640	rtl_rx_vlan_en(tp, enable: tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6641
6642	rtl8156_change_mtu(tp);
6643
6644	switch (tp->version) {
6645	case RTL_TEST_01:
6646	case RTL_VER_10:
6647	case RTL_VER_11:
6648	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
6649	ocp_data |= ACT_ODMA;
6650	ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, data: ocp_data);
6651	break;
6652	default:
6653	break;
6654	}
6655
6656	/* share FIFO settings */
6657	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL);
6658	ocp_data &= ~RXFIFO_FULL_MASK;
6659	ocp_data |= 0x08;
6660	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, data: ocp_data);
6661
6662	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6663	ocp_data &= ~PLA_MCU_SPDWN_EN;
6664	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
6665
6666	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION);
6667	ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF);
6668	ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, data: ocp_data);
6669
6670	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, data: 0x00600400);
6671
6672	if (tp->saved_wolopts != __rtl_get_wol(tp)) {
6673	netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n");
6674	__rtl_set_wol(tp, wolopts: tp->saved_wolopts);
6675	}
6676
6677	r8153_aldps_en(tp, enable: true);
6678	r8153_u2p3en(tp, enable: true);
6679
6680	if (tp->udev->speed >= USB_SPEED_SUPER)
6681	r8153b_u1u2en(tp, enable: true);
6682	}
6683
6684	static void rtl8156_down(struct r8152 *tp)
6685	{
6686	u32 ocp_data;
6687
6688	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6689	rtl_drop_queued_tx(tp);
6690	return;
6691	}
6692
6693	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6694	ocp_data |= PLA_MCU_SPDWN_EN;
6695	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
6696
6697	r8153b_u1u2en(tp, enable: false);
6698	r8153_u2p3en(tp, enable: false);
6699	r8153b_power_cut_en(tp, enable: false);
6700	r8153_aldps_en(tp, enable: false);
6701
6702	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6703	ocp_data &= ~NOW_IS_OOB;
6704	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
6705
6706	/* RX FIFO settings for OOB */
6707	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, data: 64 / 16);
6708	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, data: 1024 / 16);
6709	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, data: 4096 / 16);
6710
6711	rtl_disable(tp);
6712	rtl_reset_bmu(tp);
6713
6714	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, data: 1522);
6715	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT);
6716
6717	/* Clear teredo wake event. bit[15:8] is the teredo wakeup
6718	* type. Set it to zero. bits[7:0] are the W1C bits about
6719	* the events. Set them to all 1 to clear them.
6720	*/
6721	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, data: 0x00ff);
6722
6723	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6724	ocp_data |= NOW_IS_OOB;
6725	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, data: ocp_data);
6726
6727	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6728	ocp_data |= MCU_BORW_EN;
6729	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, data: ocp_data);
6730
6731	rtl_rx_vlan_en(tp, enable: true);
6732	rxdy_gated_en(tp, enable: false);
6733
6734	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6735	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
6736	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
6737
6738	r8153_aldps_en(tp, enable: true);
6739	}
6740
6741	static bool rtl8152_in_nway(struct r8152 *tp)
6742	{
6743	u16 nway_state;
6744
6745	ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, data: 0x2000);
6746	tp->ocp_base = 0x2000;
6747	ocp_write_byte(tp, MCU_TYPE_PLA, index: 0xb014, data: 0x4c); /* phy state */
6748	nway_state = ocp_read_word(tp, MCU_TYPE_PLA, index: 0xb01a);
6749
6750	/* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
6751	if (nway_state & 0xc000)
6752	return false;
6753	else
6754	return true;
6755	}
6756
6757	static bool rtl8153_in_nway(struct r8152 *tp)
6758	{
6759	u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
6760
6761	if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
6762	return false;
6763	else
6764	return true;
6765	}
6766
6767	static void r8156_mdio_force_mode(struct r8152 *tp)
6768	{
6769	u16 data;
6770
6771	/* Select force mode through 0xa5b4 bit 15
6772	* 0: MDIO force mode
6773	* 1: MMD force mode
6774	*/
6775	data = ocp_reg_read(tp, addr: 0xa5b4);
6776	if (data & BIT(15)) {
6777	data &= ~BIT(15);
6778	ocp_reg_write(tp, addr: 0xa5b4, data);
6779	}
6780	}
6781
6782	static void set_carrier(struct r8152 *tp)
6783	{
6784	struct net_device *netdev = tp->netdev;
6785	struct napi_struct *napi = &tp->napi;
6786	u16 speed;
6787
6788	speed = rtl8152_get_speed(tp);
6789
6790	if (speed & LINK_STATUS) {
6791	if (!netif_carrier_ok(dev: netdev)) {
6792	tp->rtl_ops.enable(tp);
6793	netif_stop_queue(dev: netdev);
6794	napi_disable(n: napi);
6795	netif_carrier_on(dev: netdev);
6796	rtl_start_rx(tp);
6797	clear_bit(nr: RTL8152_SET_RX_MODE, addr: &tp->flags);
6798	_rtl8152_set_rx_mode(netdev);
6799	napi_enable(n: napi);
6800	netif_wake_queue(dev: netdev);
6801	netif_info(tp, link, netdev, "carrier on\n");
6802	} else if (netif_queue_stopped(dev: netdev) &&
6803	skb_queue_len(list_: &tp->tx_queue) < tp->tx_qlen) {
6804	netif_wake_queue(dev: netdev);
6805	}
6806	} else {
6807	if (netif_carrier_ok(dev: netdev)) {
6808	netif_carrier_off(dev: netdev);
6809	tasklet_disable(t: &tp->tx_tl);
6810	napi_disable(n: napi);
6811	tp->rtl_ops.disable(tp);
6812	napi_enable(n: napi);
6813	tasklet_enable(t: &tp->tx_tl);
6814	netif_info(tp, link, netdev, "carrier off\n");
6815	}
6816	}
6817	}
6818
6819	static void rtl_work_func_t(struct work_struct *work)
6820	{
6821	struct r8152 *tp = container_of(work, struct r8152, schedule.work);
6822
6823	/* If the device is unplugged or !netif_running(), the workqueue
6824	* doesn't need to wake the device, and could return directly.
6825	*/
6826	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) || !netif_running(dev: tp->netdev))
6827	return;
6828
6829	if (usb_autopm_get_interface(intf: tp->intf) < 0)
6830	return;
6831
6832	if (!test_bit(WORK_ENABLE, &tp->flags))
6833	goto out1;
6834
6835	if (!mutex_trylock(&tp->control)) {
6836	schedule_delayed_work(dwork: &tp->schedule, delay: 0);
6837	goto out1;
6838	}
6839
6840	if (test_and_clear_bit(nr: RTL8152_LINK_CHG, addr: &tp->flags))
6841	set_carrier(tp);
6842
6843	if (test_and_clear_bit(nr: RTL8152_SET_RX_MODE, addr: &tp->flags))
6844	_rtl8152_set_rx_mode(netdev: tp->netdev);
6845
6846	/* don't schedule tasket before linking */
6847	if (test_and_clear_bit(nr: SCHEDULE_TASKLET, addr: &tp->flags) &&
6848	netif_carrier_ok(dev: tp->netdev))
6849	tasklet_schedule(t: &tp->tx_tl);
6850
6851	if (test_and_clear_bit(nr: RX_EPROTO, addr: &tp->flags) &&
6852	!list_empty(head: &tp->rx_done))
6853	napi_schedule(n: &tp->napi);
6854
6855	mutex_unlock(lock: &tp->control);
6856
6857	out1:
6858	usb_autopm_put_interface(intf: tp->intf);
6859	}
6860
6861	static void rtl_hw_phy_work_func_t(struct work_struct *work)
6862	{
6863	struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
6864
6865	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
6866	return;
6867
6868	if (usb_autopm_get_interface(intf: tp->intf) < 0)
6869	return;
6870
6871	mutex_lock(&tp->control);
6872
6873	if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
6874	tp->rtl_fw.retry = false;
6875	tp->rtl_fw.fw = NULL;
6876
6877	/* Delay execution in case request_firmware() is not ready yet.
6878	*/
6879	queue_delayed_work(wq: system_long_wq, dwork: &tp->hw_phy_work, HZ * 10);
6880	goto ignore_once;
6881	}
6882
6883	tp->rtl_ops.hw_phy_cfg(tp);
6884
6885	rtl8152_set_speed(tp, autoneg: tp->autoneg, speed: tp->speed, duplex: tp->duplex,
6886	advertising: tp->advertising);
6887
6888	ignore_once:
6889	mutex_unlock(lock: &tp->control);
6890
6891	usb_autopm_put_interface(intf: tp->intf);
6892	}
6893
6894	#ifdef CONFIG_PM_SLEEP
6895	static int rtl_notifier(struct notifier_block *nb, unsigned long action,
6896	void *data)
6897	{
6898	struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
6899
6900	switch (action) {
6901	case PM_HIBERNATION_PREPARE:
6902	case PM_SUSPEND_PREPARE:
6903	usb_autopm_get_interface(intf: tp->intf);
6904	break;
6905
6906	case PM_POST_HIBERNATION:
6907	case PM_POST_SUSPEND:
6908	usb_autopm_put_interface(intf: tp->intf);
6909	break;
6910
6911	case PM_POST_RESTORE:
6912	case PM_RESTORE_PREPARE:
6913	default:
6914	break;
6915	}
6916
6917	return NOTIFY_DONE;
6918	}
6919	#endif
6920
6921	static int rtl8152_open(struct net_device *netdev)
6922	{
6923	struct r8152 *tp = netdev_priv(dev: netdev);
6924	int res = 0;
6925
6926	if (work_busy(work: &tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
6927	cancel_delayed_work_sync(dwork: &tp->hw_phy_work);
6928	rtl_hw_phy_work_func_t(work: &tp->hw_phy_work.work);
6929	}
6930
6931	res = alloc_all_mem(tp);
6932	if (res)
6933	goto out;
6934
6935	res = usb_autopm_get_interface(intf: tp->intf);
6936	if (res < 0)
6937	goto out_free;
6938
6939	mutex_lock(&tp->control);
6940
6941	tp->rtl_ops.up(tp);
6942
6943	netif_carrier_off(dev: netdev);
6944	netif_start_queue(dev: netdev);
6945	set_bit(nr: WORK_ENABLE, addr: &tp->flags);
6946
6947	res = usb_submit_urb(urb: tp->intr_urb, GFP_KERNEL);
6948	if (res) {
6949	if (res == -ENODEV)
6950	netif_device_detach(dev: tp->netdev);
6951	netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
6952	res);
6953	goto out_unlock;
6954	}
6955	napi_enable(n: &tp->napi);
6956	tasklet_enable(t: &tp->tx_tl);
6957
6958	mutex_unlock(lock: &tp->control);
6959
6960	usb_autopm_put_interface(intf: tp->intf);
6961	#ifdef CONFIG_PM_SLEEP
6962	tp->pm_notifier.notifier_call = rtl_notifier;
6963	register_pm_notifier(nb: &tp->pm_notifier);
6964	#endif
6965	return 0;
6966
6967	out_unlock:
6968	mutex_unlock(lock: &tp->control);
6969	usb_autopm_put_interface(intf: tp->intf);
6970	out_free:
6971	free_all_mem(tp);
6972	out:
6973	return res;
6974	}
6975
6976	static int rtl8152_close(struct net_device *netdev)
6977	{
6978	struct r8152 *tp = netdev_priv(dev: netdev);
6979	int res = 0;
6980
6981	#ifdef CONFIG_PM_SLEEP
6982	unregister_pm_notifier(nb: &tp->pm_notifier);
6983	#endif
6984	tasklet_disable(t: &tp->tx_tl);
6985	clear_bit(nr: WORK_ENABLE, addr: &tp->flags);
6986	usb_kill_urb(urb: tp->intr_urb);
6987	cancel_delayed_work_sync(dwork: &tp->schedule);
6988	napi_disable(n: &tp->napi);
6989	netif_stop_queue(dev: netdev);
6990
6991	res = usb_autopm_get_interface(intf: tp->intf);
6992	if (res < 0 || test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
6993	rtl_drop_queued_tx(tp);
6994	rtl_stop_rx(tp);
6995	} else {
6996	mutex_lock(&tp->control);
6997
6998	tp->rtl_ops.down(tp);
6999
7000	mutex_unlock(lock: &tp->control);
7001	}
7002
7003	if (!res)
7004	usb_autopm_put_interface(intf: tp->intf);
7005
7006	free_all_mem(tp);
7007
7008	return res;
7009	}
7010
7011	static void rtl_tally_reset(struct r8152 *tp)
7012	{
7013	u32 ocp_data;
7014
7015	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
7016	ocp_data |= TALLY_RESET;
7017	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, data: ocp_data);
7018	}
7019
7020	static void r8152b_init(struct r8152 *tp)
7021	{
7022	u32 ocp_data;
7023	u16 data;
7024
7025	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7026	return;
7027
7028	data = r8152_mdio_read(tp, MII_BMCR);
7029	if (data & BMCR_PDOWN) {
7030	data &= ~BMCR_PDOWN;
7031	r8152_mdio_write(tp, MII_BMCR, value: data);
7032	}
7033
7034	r8152_aldps_en(tp, enable: false);
7035
7036	if (tp->version == RTL_VER_01) {
7037	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
7038	ocp_data &= ~LED_MODE_MASK;
7039	ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, data: ocp_data);
7040	}
7041
7042	r8152_power_cut_en(tp, enable: false);
7043
7044	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7045	ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
7046	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, data: ocp_data);
7047	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
7048	ocp_data &= ~MCU_CLK_RATIO_MASK;
7049	ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
7050	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, data: ocp_data);
7051	ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
7052	SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
7053	ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, data: ocp_data);
7054
7055	rtl_tally_reset(tp);
7056
7057	/* enable rx aggregation */
7058	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7059	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7060	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
7061	}
7062
7063	static void r8153_init(struct r8152 *tp)
7064	{
7065	u32 ocp_data;
7066	u16 data;
7067	int i;
7068
7069	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7070	return;
7071
7072	r8153_u1u2en(tp, enable: false);
7073
7074	for (i = 0; i < 500; i++) {
7075	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7076	AUTOLOAD_DONE)
7077	break;
7078
7079	msleep(msecs: 20);
7080	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7081	break;
7082	}
7083
7084	data = r8153_phy_status(tp, desired: 0);
7085
7086	if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
7087	tp->version == RTL_VER_05)
7088	ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
7089
7090	data = r8152_mdio_read(tp, MII_BMCR);
7091	if (data & BMCR_PDOWN) {
7092	data &= ~BMCR_PDOWN;
7093	r8152_mdio_write(tp, MII_BMCR, value: data);
7094	}
7095
7096	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7097
7098	r8153_u2p3en(tp, enable: false);
7099
7100	if (tp->version == RTL_VER_04) {
7101	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
7102	ocp_data &= ~pwd_dn_scale_mask;
7103	ocp_data |= pwd_dn_scale(96);
7104	ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, data: ocp_data);
7105
7106	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
7107	ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
7108	ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, data: ocp_data);
7109	} else if (tp->version == RTL_VER_05) {
7110	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
7111	ocp_data &= ~ECM_ALDPS;
7112	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, data: ocp_data);
7113
7114	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
7115	if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
7116	ocp_data &= ~DYNAMIC_BURST;
7117	else
7118	ocp_data |= DYNAMIC_BURST;
7119	ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, data: ocp_data);
7120	} else if (tp->version == RTL_VER_06) {
7121	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
7122	if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
7123	ocp_data &= ~DYNAMIC_BURST;
7124	else
7125	ocp_data |= DYNAMIC_BURST;
7126	ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, data: ocp_data);
7127
7128	r8153_queue_wake(tp, enable: false);
7129
7130	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7131	if (rtl8152_get_speed(tp) & LINK_STATUS)
7132	ocp_data |= CUR_LINK_OK;
7133	else
7134	ocp_data &= ~CUR_LINK_OK;
7135	ocp_data |= POLL_LINK_CHG;
7136	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, data: ocp_data);
7137	}
7138
7139	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
7140	ocp_data |= EP4_FULL_FC;
7141	ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, data: ocp_data);
7142
7143	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
7144	ocp_data &= ~TIMER11_EN;
7145	ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, data: ocp_data);
7146
7147	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
7148	ocp_data &= ~LED_MODE_MASK;
7149	ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, data: ocp_data);
7150
7151	ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
7152	if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
7153	ocp_data |= LPM_TIMER_500MS;
7154	else
7155	ocp_data |= LPM_TIMER_500US;
7156	ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, data: ocp_data);
7157
7158	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
7159	ocp_data &= ~SEN_VAL_MASK;
7160	ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
7161	ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, data: ocp_data);
7162
7163	ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, data: 0x0001);
7164
7165	r8153_power_cut_en(tp, enable: false);
7166	rtl_runtime_suspend_enable(tp, enable: false);
7167	r8153_mac_clk_speed_down(tp, enable: false);
7168	r8153_u1u2en(tp, enable: true);
7169	usb_enable_lpm(udev: tp->udev);
7170
7171	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
7172	ocp_data |= LANWAKE_CLR_EN;
7173	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, data: ocp_data);
7174
7175	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
7176	ocp_data &= ~LANWAKE_PIN;
7177	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, data: ocp_data);
7178
7179	/* rx aggregation */
7180	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7181	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7182	if (tp->dell_tb_rx_agg_bug)
7183	ocp_data |= RX_AGG_DISABLE;
7184
7185	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
7186
7187	rtl_tally_reset(tp);
7188
7189	switch (tp->udev->speed) {
7190	case USB_SPEED_SUPER:
7191	case USB_SPEED_SUPER_PLUS:
7192	tp->coalesce = COALESCE_SUPER;
7193	break;
7194	case USB_SPEED_HIGH:
7195	tp->coalesce = COALESCE_HIGH;
7196	break;
7197	default:
7198	tp->coalesce = COALESCE_SLOW;
7199	break;
7200	}
7201	}
7202
7203	static void r8153b_init(struct r8152 *tp)
7204	{
7205	u32 ocp_data;
7206	u16 data;
7207	int i;
7208
7209	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7210	return;
7211
7212	r8153b_u1u2en(tp, enable: false);
7213
7214	for (i = 0; i < 500; i++) {
7215	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7216	AUTOLOAD_DONE)
7217	break;
7218
7219	msleep(msecs: 20);
7220	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7221	break;
7222	}
7223
7224	data = r8153_phy_status(tp, desired: 0);
7225
7226	data = r8152_mdio_read(tp, MII_BMCR);
7227	if (data & BMCR_PDOWN) {
7228	data &= ~BMCR_PDOWN;
7229	r8152_mdio_write(tp, MII_BMCR, value: data);
7230	}
7231
7232	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7233
7234	r8153_u2p3en(tp, enable: false);
7235
7236	/* MSC timer = 0xfff * 8ms = 32760 ms */
7237	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, data: 0x0fff);
7238
7239	r8153b_power_cut_en(tp, enable: false);
7240	r8153b_ups_en(tp, enable: false);
7241	r8153_queue_wake(tp, enable: false);
7242	rtl_runtime_suspend_enable(tp, enable: false);
7243
7244	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7245	if (rtl8152_get_speed(tp) & LINK_STATUS)
7246	ocp_data |= CUR_LINK_OK;
7247	else
7248	ocp_data &= ~CUR_LINK_OK;
7249	ocp_data |= POLL_LINK_CHG;
7250	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, data: ocp_data);
7251
7252	if (tp->udev->speed >= USB_SPEED_SUPER)
7253	r8153b_u1u2en(tp, enable: true);
7254
7255	usb_enable_lpm(udev: tp->udev);
7256
7257	/* MAC clock speed down */
7258	r8153_mac_clk_speed_down(tp, enable: true);
7259
7260	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
7261	ocp_data &= ~PLA_MCU_SPDWN_EN;
7262	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
7263
7264	if (tp->version == RTL_VER_09) {
7265	/* Disable Test IO for 32QFN */
7266	if (ocp_read_byte(tp, MCU_TYPE_PLA, index: 0xdc00) & BIT(5)) {
7267	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7268	ocp_data |= TEST_IO_OFF;
7269	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, data: ocp_data);
7270	}
7271	}
7272
7273	set_bit(nr: GREEN_ETHERNET, addr: &tp->flags);
7274
7275	/* rx aggregation */
7276	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7277	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7278	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
7279
7280	rtl_tally_reset(tp);
7281
7282	tp->coalesce = 15000; /* 15 us */
7283	}
7284
7285	static void r8153c_init(struct r8152 *tp)
7286	{
7287	u32 ocp_data;
7288	u16 data;
7289	int i;
7290
7291	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7292	return;
7293
7294	r8153b_u1u2en(tp, enable: false);
7295
7296	/* Disable spi_en */
7297	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
7298	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
7299	ocp_data &= ~BIT(3);
7300	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, data: ocp_data);
7301	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, index: 0xcbf0);
7302	ocp_data |= BIT(1);
7303	ocp_write_word(tp, MCU_TYPE_USB, index: 0xcbf0, data: ocp_data);
7304
7305	for (i = 0; i < 500; i++) {
7306	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7307	AUTOLOAD_DONE)
7308	break;
7309
7310	msleep(msecs: 20);
7311	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
7312	return;
7313	}
7314
7315	data = r8153_phy_status(tp, desired: 0);
7316
7317	data = r8152_mdio_read(tp, MII_BMCR);
7318	if (data & BMCR_PDOWN) {
7319	data &= ~BMCR_PDOWN;
7320	r8152_mdio_write(tp, MII_BMCR, value: data);
7321	}
7322
7323	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7324
7325	r8153_u2p3en(tp, enable: false);
7326
7327	/* MSC timer = 0xfff * 8ms = 32760 ms */
7328	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, data: 0x0fff);
7329
7330	r8153b_power_cut_en(tp, enable: false);
7331	r8153c_ups_en(tp, enable: false);
7332	r8153_queue_wake(tp, enable: false);
7333	rtl_runtime_suspend_enable(tp, enable: false);
7334
7335	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7336	if (rtl8152_get_speed(tp) & LINK_STATUS)
7337	ocp_data |= CUR_LINK_OK;
7338	else
7339	ocp_data &= ~CUR_LINK_OK;
7340
7341	ocp_data |= POLL_LINK_CHG;
7342	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, data: ocp_data);
7343
7344	r8153b_u1u2en(tp, enable: true);
7345
7346	usb_enable_lpm(udev: tp->udev);
7347
7348	/* MAC clock speed down */
7349	r8153_mac_clk_speed_down(tp, enable: true);
7350
7351	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
7352	ocp_data &= ~BIT(7);
7353	ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, data: ocp_data);
7354
7355	set_bit(nr: GREEN_ETHERNET, addr: &tp->flags);
7356
7357	/* rx aggregation */
7358	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7359	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7360	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
7361
7362	rtl_tally_reset(tp);
7363
7364	tp->coalesce = 15000; /* 15 us */
7365	}
7366
7367	static void r8156_hw_phy_cfg(struct r8152 *tp)
7368	{
7369	u32 ocp_data;
7370	u16 data;
7371
7372	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7373	if (ocp_data & PCUT_STATUS) {
7374	ocp_data &= ~PCUT_STATUS;
7375	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, data: ocp_data);
7376	}
7377
7378	data = r8153_phy_status(tp, desired: 0);
7379	switch (data) {
7380	case PHY_STAT_EXT_INIT:
7381	rtl8152_apply_firmware(tp, power_cut: true);
7382
7383	data = ocp_reg_read(tp, addr: 0xa468);
7384	data &= ~(BIT(3) | BIT(1));
7385	ocp_reg_write(tp, addr: 0xa468, data);
7386	break;
7387	case PHY_STAT_LAN_ON:
7388	case PHY_STAT_PWRDN:
7389	default:
7390	rtl8152_apply_firmware(tp, power_cut: false);
7391	break;
7392	}
7393
7394	/* disable ALDPS before updating the PHY parameters */
7395	r8153_aldps_en(tp, enable: false);
7396
7397	/* disable EEE before updating the PHY parameters */
7398	rtl_eee_enable(tp, enable: false);
7399
7400	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7401	WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7402
7403	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7404	ocp_data |= PFM_PWM_SWITCH;
7405	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, data: ocp_data);
7406
7407	switch (tp->version) {
7408	case RTL_VER_10:
7409	data = ocp_reg_read(tp, addr: 0xad40);
7410	data &= ~0x3ff;
7411	data |= BIT(7) | BIT(2);
7412	ocp_reg_write(tp, addr: 0xad40, data);
7413
7414	data = ocp_reg_read(tp, addr: 0xad4e);
7415	data |= BIT(4);
7416	ocp_reg_write(tp, addr: 0xad4e, data);
7417	data = ocp_reg_read(tp, addr: 0xad16);
7418	data &= ~0x3ff;
7419	data |= 0x6;
7420	ocp_reg_write(tp, addr: 0xad16, data);
7421	data = ocp_reg_read(tp, addr: 0xad32);
7422	data &= ~0x3f;
7423	data |= 6;
7424	ocp_reg_write(tp, addr: 0xad32, data);
7425	data = ocp_reg_read(tp, addr: 0xac08);
7426	data &= ~(BIT(12) | BIT(8));
7427	ocp_reg_write(tp, addr: 0xac08, data);
7428	data = ocp_reg_read(tp, addr: 0xac8a);
7429	data |= BIT(12) | BIT(13) | BIT(14);
7430	data &= ~BIT(15);
7431	ocp_reg_write(tp, addr: 0xac8a, data);
7432	data = ocp_reg_read(tp, addr: 0xad18);
7433	data |= BIT(10);
7434	ocp_reg_write(tp, addr: 0xad18, data);
7435	data = ocp_reg_read(tp, addr: 0xad1a);
7436	data |= 0x3ff;
7437	ocp_reg_write(tp, addr: 0xad1a, data);
7438	data = ocp_reg_read(tp, addr: 0xad1c);
7439	data |= 0x3ff;
7440	ocp_reg_write(tp, addr: 0xad1c, data);
7441
7442	data = sram_read(tp, addr: 0x80ea);
7443	data &= ~0xff00;
7444	data |= 0xc400;
7445	sram_write(tp, addr: 0x80ea, data);
7446	data = sram_read(tp, addr: 0x80eb);
7447	data &= ~0x0700;
7448	data |= 0x0300;
7449	sram_write(tp, addr: 0x80eb, data);
7450	data = sram_read(tp, addr: 0x80f8);
7451	data &= ~0xff00;
7452	data |= 0x1c00;
7453	sram_write(tp, addr: 0x80f8, data);
7454	data = sram_read(tp, addr: 0x80f1);
7455	data &= ~0xff00;
7456	data |= 0x3000;
7457	sram_write(tp, addr: 0x80f1, data);
7458
7459	data = sram_read(tp, addr: 0x80fe);
7460	data &= ~0xff00;
7461	data |= 0xa500;
7462	sram_write(tp, addr: 0x80fe, data);
7463	data = sram_read(tp, addr: 0x8102);
7464	data &= ~0xff00;
7465	data |= 0x5000;
7466	sram_write(tp, addr: 0x8102, data);
7467	data = sram_read(tp, addr: 0x8015);
7468	data &= ~0xff00;
7469	data |= 0x3300;
7470	sram_write(tp, addr: 0x8015, data);
7471	data = sram_read(tp, addr: 0x8100);
7472	data &= ~0xff00;
7473	data |= 0x7000;
7474	sram_write(tp, addr: 0x8100, data);
7475	data = sram_read(tp, addr: 0x8014);
7476	data &= ~0xff00;
7477	data |= 0xf000;
7478	sram_write(tp, addr: 0x8014, data);
7479	data = sram_read(tp, addr: 0x8016);
7480	data &= ~0xff00;
7481	data |= 0x6500;
7482	sram_write(tp, addr: 0x8016, data);
7483	data = sram_read(tp, addr: 0x80dc);
7484	data &= ~0xff00;
7485	data |= 0xed00;
7486	sram_write(tp, addr: 0x80dc, data);
7487	data = sram_read(tp, addr: 0x80df);
7488	data |= BIT(8);
7489	sram_write(tp, addr: 0x80df, data);
7490	data = sram_read(tp, addr: 0x80e1);
7491	data &= ~BIT(8);
7492	sram_write(tp, addr: 0x80e1, data);
7493
7494	data = ocp_reg_read(tp, addr: 0xbf06);
7495	data &= ~0x003f;
7496	data |= 0x0038;
7497	ocp_reg_write(tp, addr: 0xbf06, data);
7498
7499	sram_write(tp, addr: 0x819f, data: 0xddb6);
7500
7501	ocp_reg_write(tp, addr: 0xbc34, data: 0x5555);
7502	data = ocp_reg_read(tp, addr: 0xbf0a);
7503	data &= ~0x0e00;
7504	data |= 0x0a00;
7505	ocp_reg_write(tp, addr: 0xbf0a, data);
7506
7507	data = ocp_reg_read(tp, addr: 0xbd2c);
7508	data &= ~BIT(13);
7509	ocp_reg_write(tp, addr: 0xbd2c, data);
7510	break;
7511	case RTL_VER_11:
7512	data = ocp_reg_read(tp, addr: 0xad16);
7513	data |= 0x3ff;
7514	ocp_reg_write(tp, addr: 0xad16, data);
7515	data = ocp_reg_read(tp, addr: 0xad32);
7516	data &= ~0x3f;
7517	data |= 6;
7518	ocp_reg_write(tp, addr: 0xad32, data);
7519	data = ocp_reg_read(tp, addr: 0xac08);
7520	data &= ~(BIT(12) | BIT(8));
7521	ocp_reg_write(tp, addr: 0xac08, data);
7522	data = ocp_reg_read(tp, addr: 0xacc0);
7523	data &= ~0x3;
7524	data |= BIT(1);
7525	ocp_reg_write(tp, addr: 0xacc0, data);
7526	data = ocp_reg_read(tp, addr: 0xad40);
7527	data &= ~0xe7;
7528	data |= BIT(6) | BIT(2);
7529	ocp_reg_write(tp, addr: 0xad40, data);
7530	data = ocp_reg_read(tp, addr: 0xac14);
7531	data &= ~BIT(7);
7532	ocp_reg_write(tp, addr: 0xac14, data);
7533	data = ocp_reg_read(tp, addr: 0xac80);
7534	data &= ~(BIT(8) | BIT(9));
7535	ocp_reg_write(tp, addr: 0xac80, data);
7536	data = ocp_reg_read(tp, addr: 0xac5e);
7537	data &= ~0x7;
7538	data |= BIT(1);
7539	ocp_reg_write(tp, addr: 0xac5e, data);
7540	ocp_reg_write(tp, addr: 0xad4c, data: 0x00a8);
7541	ocp_reg_write(tp, addr: 0xac5c, data: 0x01ff);
7542	data = ocp_reg_read(tp, addr: 0xac8a);
7543	data &= ~0xf0;
7544	data |= BIT(4) | BIT(5);
7545	ocp_reg_write(tp, addr: 0xac8a, data);
7546	ocp_reg_write(tp, addr: 0xb87c, data: 0x8157);
7547	data = ocp_reg_read(tp, addr: 0xb87e);
7548	data &= ~0xff00;
7549	data |= 0x0500;
7550	ocp_reg_write(tp, addr: 0xb87e, data);
7551	ocp_reg_write(tp, addr: 0xb87c, data: 0x8159);
7552	data = ocp_reg_read(tp, addr: 0xb87e);
7553	data &= ~0xff00;
7554	data |= 0x0700;
7555	ocp_reg_write(tp, addr: 0xb87e, data);
7556
7557	/* AAGC */
7558	ocp_reg_write(tp, addr: 0xb87c, data: 0x80a2);
7559	ocp_reg_write(tp, addr: 0xb87e, data: 0x0153);
7560	ocp_reg_write(tp, addr: 0xb87c, data: 0x809c);
7561	ocp_reg_write(tp, addr: 0xb87e, data: 0x0153);
7562
7563	/* EEE parameter */
7564	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, data: 0x0056);
7565
7566	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7567	ocp_data |= EN_XG_LIP | EN_G_LIP;
7568	ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, data: ocp_data);
7569
7570	sram_write(tp, addr: 0x8257, data: 0x020f); /* XG PLL */
7571	sram_write(tp, addr: 0x80ea, data: 0x7843); /* GIGA Master */
7572
7573	if (rtl_phy_patch_request(tp, request: true, wait: true))
7574	return;
7575
7576	/* Advance EEE */
7577	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
7578	ocp_data |= EEE_SPDWN_EN;
7579	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, data: ocp_data);
7580
7581	data = ocp_reg_read(tp, OCP_DOWN_SPEED);
7582	data &= ~(EN_EEE_100 | EN_EEE_1000);
7583	data |= EN_10M_CLKDIV;
7584	ocp_reg_write(tp, OCP_DOWN_SPEED, data);
7585	tp->ups_info._10m_ckdiv = true;
7586	tp->ups_info.eee_plloff_100 = false;
7587	tp->ups_info.eee_plloff_giga = false;
7588
7589	data = ocp_reg_read(tp, OCP_POWER_CFG);
7590	data &= ~EEE_CLKDIV_EN;
7591	ocp_reg_write(tp, OCP_POWER_CFG, data);
7592	tp->ups_info.eee_ckdiv = false;
7593
7594	ocp_reg_write(tp, OCP_SYSCLK_CFG, data: 0);
7595	ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5));
7596	tp->ups_info._250m_ckdiv = false;
7597
7598	rtl_phy_patch_request(tp, request: false, wait: true);
7599
7600	/* enable ADC Ibias Cal */
7601	data = ocp_reg_read(tp, addr: 0xd068);
7602	data |= BIT(13);
7603	ocp_reg_write(tp, addr: 0xd068, data);
7604
7605	/* enable Thermal Sensor */
7606	data = sram_read(tp, addr: 0x81a2);
7607	data &= ~BIT(8);
7608	sram_write(tp, addr: 0x81a2, data);
7609	data = ocp_reg_read(tp, addr: 0xb54c);
7610	data &= ~0xff00;
7611	data |= 0xdb00;
7612	ocp_reg_write(tp, addr: 0xb54c, data);
7613
7614	/* Nway 2.5G Lite */
7615	data = ocp_reg_read(tp, addr: 0xa454);
7616	data &= ~BIT(0);
7617	ocp_reg_write(tp, addr: 0xa454, data);
7618
7619	/* CS DSP solution */
7620	data = ocp_reg_read(tp, OCP_10GBT_CTRL);
7621	data |= RTL_ADV2_5G_F_R;
7622	ocp_reg_write(tp, OCP_10GBT_CTRL, data);
7623	data = ocp_reg_read(tp, addr: 0xad4e);
7624	data &= ~BIT(4);
7625	ocp_reg_write(tp, addr: 0xad4e, data);
7626	data = ocp_reg_read(tp, addr: 0xa86a);
7627	data &= ~BIT(0);
7628	ocp_reg_write(tp, addr: 0xa86a, data);
7629
7630	/* MDI SWAP */
7631	if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) &&
7632	(ocp_reg_read(tp, addr: 0xd068) & BIT(1))) {
7633	u16 swap_a, swap_b;
7634
7635	data = ocp_reg_read(tp, addr: 0xd068);
7636	data &= ~0x1f;
7637	data |= 0x1; /* p0 */
7638	ocp_reg_write(tp, addr: 0xd068, data);
7639	swap_a = ocp_reg_read(tp, addr: 0xd06a);
7640	data &= ~0x18;
7641	data |= 0x18; /* p3 */
7642	ocp_reg_write(tp, addr: 0xd068, data);
7643	swap_b = ocp_reg_read(tp, addr: 0xd06a);
7644	data &= ~0x18; /* p0 */
7645	ocp_reg_write(tp, addr: 0xd068, data);
7646	ocp_reg_write(tp, addr: 0xd06a,
7647	data: (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7648	data |= 0x18; /* p3 */
7649	ocp_reg_write(tp, addr: 0xd068, data);
7650	ocp_reg_write(tp, addr: 0xd06a,
7651	data: (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7652	data &= ~0x18;
7653	data |= 0x08; /* p1 */
7654	ocp_reg_write(tp, addr: 0xd068, data);
7655	swap_a = ocp_reg_read(tp, addr: 0xd06a);
7656	data &= ~0x18;
7657	data |= 0x10; /* p2 */
7658	ocp_reg_write(tp, addr: 0xd068, data);
7659	swap_b = ocp_reg_read(tp, addr: 0xd06a);
7660	data &= ~0x18;
7661	data |= 0x08; /* p1 */
7662	ocp_reg_write(tp, addr: 0xd068, data);
7663	ocp_reg_write(tp, addr: 0xd06a,
7664	data: (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7665	data &= ~0x18;
7666	data |= 0x10; /* p2 */
7667	ocp_reg_write(tp, addr: 0xd068, data);
7668	ocp_reg_write(tp, addr: 0xd06a,
7669	data: (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7670	swap_a = ocp_reg_read(tp, addr: 0xbd5a);
7671	swap_b = ocp_reg_read(tp, addr: 0xbd5c);
7672	ocp_reg_write(tp, addr: 0xbd5a, data: (swap_a & ~0x1f1f) |
7673	((swap_b & 0x1f) << 8) |
7674	((swap_b >> 8) & 0x1f));
7675	ocp_reg_write(tp, addr: 0xbd5c, data: (swap_b & ~0x1f1f) |
7676	((swap_a & 0x1f) << 8) |
7677	((swap_a >> 8) & 0x1f));
7678	swap_a = ocp_reg_read(tp, addr: 0xbc18);
7679	swap_b = ocp_reg_read(tp, addr: 0xbc1a);
7680	ocp_reg_write(tp, addr: 0xbc18, data: (swap_a & ~0x1f1f) |
7681	((swap_b & 0x1f) << 8) |
7682	((swap_b >> 8) & 0x1f));
7683	ocp_reg_write(tp, addr: 0xbc1a, data: (swap_b & ~0x1f1f) |
7684	((swap_a & 0x1f) << 8) |
7685	((swap_a >> 8) & 0x1f));
7686	}
7687
7688	/* Notify the MAC when the speed is changed to force mode. */
7689	data = ocp_reg_read(tp, OCP_INTR_EN);
7690	data |= INTR_SPEED_FORCE;
7691	ocp_reg_write(tp, OCP_INTR_EN, data);
7692	break;
7693	default:
7694	break;
7695	}
7696
7697	rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
7698
7699	data = ocp_reg_read(tp, addr: 0xa428);
7700	data &= ~BIT(9);
7701	ocp_reg_write(tp, addr: 0xa428, data);
7702	data = ocp_reg_read(tp, addr: 0xa5ea);
7703	data &= ~BIT(0);
7704	ocp_reg_write(tp, addr: 0xa5ea, data);
7705	tp->ups_info.lite_mode = 0;
7706
7707	if (tp->eee_en)
7708	rtl_eee_enable(tp, enable: true);
7709
7710	r8153_aldps_en(tp, enable: true);
7711	r8152b_enable_fc(tp);
7712	r8153_u2p3en(tp, enable: true);
7713
7714	set_bit(nr: PHY_RESET, addr: &tp->flags);
7715	}
7716
7717	static void r8156b_hw_phy_cfg(struct r8152 *tp)
7718	{
7719	u32 ocp_data;
7720	u16 data;
7721
7722	switch (tp->version) {
7723	case RTL_VER_12:
7724	ocp_reg_write(tp, addr: 0xbf86, data: 0x9000);
7725	data = ocp_reg_read(tp, addr: 0xc402);
7726	data |= BIT(10);
7727	ocp_reg_write(tp, addr: 0xc402, data);
7728	data &= ~BIT(10);
7729	ocp_reg_write(tp, addr: 0xc402, data);
7730	ocp_reg_write(tp, addr: 0xbd86, data: 0x1010);
7731	ocp_reg_write(tp, addr: 0xbd88, data: 0x1010);
7732	data = ocp_reg_read(tp, addr: 0xbd4e);
7733	data &= ~(BIT(10) | BIT(11));
7734	data |= BIT(11);
7735	ocp_reg_write(tp, addr: 0xbd4e, data);
7736	data = ocp_reg_read(tp, addr: 0xbf46);
7737	data &= ~0xf00;
7738	data |= 0x700;
7739	ocp_reg_write(tp, addr: 0xbf46, data);
7740	break;
7741	case RTL_VER_13:
7742	case RTL_VER_15:
7743	r8156b_wait_loading_flash(tp);
7744	break;
7745	default:
7746	break;
7747	}
7748
7749	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7750	if (ocp_data & PCUT_STATUS) {
7751	ocp_data &= ~PCUT_STATUS;
7752	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, data: ocp_data);
7753	}
7754
7755	data = r8153_phy_status(tp, desired: 0);
7756	switch (data) {
7757	case PHY_STAT_EXT_INIT:
7758	rtl8152_apply_firmware(tp, power_cut: true);
7759
7760	data = ocp_reg_read(tp, addr: 0xa466);
7761	data &= ~BIT(0);
7762	ocp_reg_write(tp, addr: 0xa466, data);
7763
7764	data = ocp_reg_read(tp, addr: 0xa468);
7765	data &= ~(BIT(3) | BIT(1));
7766	ocp_reg_write(tp, addr: 0xa468, data);
7767	break;
7768	case PHY_STAT_LAN_ON:
7769	case PHY_STAT_PWRDN:
7770	default:
7771	rtl8152_apply_firmware(tp, power_cut: false);
7772	break;
7773	}
7774
7775	data = r8152_mdio_read(tp, MII_BMCR);
7776	if (data & BMCR_PDOWN) {
7777	data &= ~BMCR_PDOWN;
7778	r8152_mdio_write(tp, MII_BMCR, value: data);
7779	}
7780
7781	/* disable ALDPS before updating the PHY parameters */
7782	r8153_aldps_en(tp, enable: false);
7783
7784	/* disable EEE before updating the PHY parameters */
7785	rtl_eee_enable(tp, enable: false);
7786
7787	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7788	WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7789
7790	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7791	ocp_data |= PFM_PWM_SWITCH;
7792	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, data: ocp_data);
7793
7794	switch (tp->version) {
7795	case RTL_VER_12:
7796	data = ocp_reg_read(tp, addr: 0xbc08);
7797	data |= BIT(3) | BIT(2);
7798	ocp_reg_write(tp, addr: 0xbc08, data);
7799
7800	data = sram_read(tp, addr: 0x8fff);
7801	data &= ~0xff00;
7802	data |= 0x0400;
7803	sram_write(tp, addr: 0x8fff, data);
7804
7805	data = ocp_reg_read(tp, addr: 0xacda);
7806	data |= 0xff00;
7807	ocp_reg_write(tp, addr: 0xacda, data);
7808	data = ocp_reg_read(tp, addr: 0xacde);
7809	data |= 0xf000;
7810	ocp_reg_write(tp, addr: 0xacde, data);
7811	ocp_reg_write(tp, addr: 0xac8c, data: 0x0ffc);
7812	ocp_reg_write(tp, addr: 0xac46, data: 0xb7b4);
7813	ocp_reg_write(tp, addr: 0xac50, data: 0x0fbc);
7814	ocp_reg_write(tp, addr: 0xac3c, data: 0x9240);
7815	ocp_reg_write(tp, addr: 0xac4e, data: 0x0db4);
7816	ocp_reg_write(tp, addr: 0xacc6, data: 0x0707);
7817	ocp_reg_write(tp, addr: 0xacc8, data: 0xa0d3);
7818	ocp_reg_write(tp, addr: 0xad08, data: 0x0007);
7819
7820	ocp_reg_write(tp, addr: 0xb87c, data: 0x8560);
7821	ocp_reg_write(tp, addr: 0xb87e, data: 0x19cc);
7822	ocp_reg_write(tp, addr: 0xb87c, data: 0x8562);
7823	ocp_reg_write(tp, addr: 0xb87e, data: 0x19cc);
7824	ocp_reg_write(tp, addr: 0xb87c, data: 0x8564);
7825	ocp_reg_write(tp, addr: 0xb87e, data: 0x19cc);
7826	ocp_reg_write(tp, addr: 0xb87c, data: 0x8566);
7827	ocp_reg_write(tp, addr: 0xb87e, data: 0x147d);
7828	ocp_reg_write(tp, addr: 0xb87c, data: 0x8568);
7829	ocp_reg_write(tp, addr: 0xb87e, data: 0x147d);
7830	ocp_reg_write(tp, addr: 0xb87c, data: 0x856a);
7831	ocp_reg_write(tp, addr: 0xb87e, data: 0x147d);
7832	ocp_reg_write(tp, addr: 0xb87c, data: 0x8ffe);
7833	ocp_reg_write(tp, addr: 0xb87e, data: 0x0907);
7834	ocp_reg_write(tp, addr: 0xb87c, data: 0x80d6);
7835	ocp_reg_write(tp, addr: 0xb87e, data: 0x2801);
7836	ocp_reg_write(tp, addr: 0xb87c, data: 0x80f2);
7837	ocp_reg_write(tp, addr: 0xb87e, data: 0x2801);
7838	ocp_reg_write(tp, addr: 0xb87c, data: 0x80f4);
7839	ocp_reg_write(tp, addr: 0xb87e, data: 0x6077);
7840	ocp_reg_write(tp, addr: 0xb506, data: 0x01e7);
7841
7842	ocp_reg_write(tp, addr: 0xb87c, data: 0x8013);
7843	ocp_reg_write(tp, addr: 0xb87e, data: 0x0700);
7844	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fb9);
7845	ocp_reg_write(tp, addr: 0xb87e, data: 0x2801);
7846	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fba);
7847	ocp_reg_write(tp, addr: 0xb87e, data: 0x0100);
7848	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fbc);
7849	ocp_reg_write(tp, addr: 0xb87e, data: 0x1900);
7850	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fbe);
7851	ocp_reg_write(tp, addr: 0xb87e, data: 0xe100);
7852	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fc0);
7853	ocp_reg_write(tp, addr: 0xb87e, data: 0x0800);
7854	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fc2);
7855	ocp_reg_write(tp, addr: 0xb87e, data: 0xe500);
7856	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fc4);
7857	ocp_reg_write(tp, addr: 0xb87e, data: 0x0f00);
7858	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fc6);
7859	ocp_reg_write(tp, addr: 0xb87e, data: 0xf100);
7860	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fc8);
7861	ocp_reg_write(tp, addr: 0xb87e, data: 0x0400);
7862	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fca);
7863	ocp_reg_write(tp, addr: 0xb87e, data: 0xf300);
7864	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fcc);
7865	ocp_reg_write(tp, addr: 0xb87e, data: 0xfd00);
7866	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fce);
7867	ocp_reg_write(tp, addr: 0xb87e, data: 0xff00);
7868	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fd0);
7869	ocp_reg_write(tp, addr: 0xb87e, data: 0xfb00);
7870	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fd2);
7871	ocp_reg_write(tp, addr: 0xb87e, data: 0x0100);
7872	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fd4);
7873	ocp_reg_write(tp, addr: 0xb87e, data: 0xf400);
7874	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fd6);
7875	ocp_reg_write(tp, addr: 0xb87e, data: 0xff00);
7876	ocp_reg_write(tp, addr: 0xb87c, data: 0x8fd8);
7877	ocp_reg_write(tp, addr: 0xb87e, data: 0xf600);
7878
7879	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7880	ocp_data |= EN_XG_LIP | EN_G_LIP;
7881	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, data: ocp_data);
7882	ocp_reg_write(tp, addr: 0xb87c, data: 0x813d);
7883	ocp_reg_write(tp, addr: 0xb87e, data: 0x390e);
7884	ocp_reg_write(tp, addr: 0xb87c, data: 0x814f);
7885	ocp_reg_write(tp, addr: 0xb87e, data: 0x790e);
7886	ocp_reg_write(tp, addr: 0xb87c, data: 0x80b0);
7887	ocp_reg_write(tp, addr: 0xb87e, data: 0x0f31);
7888	data = ocp_reg_read(tp, addr: 0xbf4c);
7889	data |= BIT(1);
7890	ocp_reg_write(tp, addr: 0xbf4c, data);
7891	data = ocp_reg_read(tp, addr: 0xbcca);
7892	data |= BIT(9) | BIT(8);
7893	ocp_reg_write(tp, addr: 0xbcca, data);
7894	ocp_reg_write(tp, addr: 0xb87c, data: 0x8141);
7895	ocp_reg_write(tp, addr: 0xb87e, data: 0x320e);
7896	ocp_reg_write(tp, addr: 0xb87c, data: 0x8153);
7897	ocp_reg_write(tp, addr: 0xb87e, data: 0x720e);
7898	ocp_reg_write(tp, addr: 0xb87c, data: 0x8529);
7899	ocp_reg_write(tp, addr: 0xb87e, data: 0x050e);
7900	data = ocp_reg_read(tp, OCP_EEE_CFG);
7901	data &= ~CTAP_SHORT_EN;
7902	ocp_reg_write(tp, OCP_EEE_CFG, data);
7903
7904	sram_write(tp, addr: 0x816c, data: 0xc4a0);
7905	sram_write(tp, addr: 0x8170, data: 0xc4a0);
7906	sram_write(tp, addr: 0x8174, data: 0x04a0);
7907	sram_write(tp, addr: 0x8178, data: 0x04a0);
7908	sram_write(tp, addr: 0x817c, data: 0x0719);
7909	sram_write(tp, addr: 0x8ff4, data: 0x0400);
7910	sram_write(tp, addr: 0x8ff1, data: 0x0404);
7911
7912	ocp_reg_write(tp, addr: 0xbf4a, data: 0x001b);
7913	ocp_reg_write(tp, addr: 0xb87c, data: 0x8033);
7914	ocp_reg_write(tp, addr: 0xb87e, data: 0x7c13);
7915	ocp_reg_write(tp, addr: 0xb87c, data: 0x8037);
7916	ocp_reg_write(tp, addr: 0xb87e, data: 0x7c13);
7917	ocp_reg_write(tp, addr: 0xb87c, data: 0x803b);
7918	ocp_reg_write(tp, addr: 0xb87e, data: 0xfc32);
7919	ocp_reg_write(tp, addr: 0xb87c, data: 0x803f);
7920	ocp_reg_write(tp, addr: 0xb87e, data: 0x7c13);
7921	ocp_reg_write(tp, addr: 0xb87c, data: 0x8043);
7922	ocp_reg_write(tp, addr: 0xb87e, data: 0x7c13);
7923	ocp_reg_write(tp, addr: 0xb87c, data: 0x8047);
7924	ocp_reg_write(tp, addr: 0xb87e, data: 0x7c13);
7925
7926	ocp_reg_write(tp, addr: 0xb87c, data: 0x8145);
7927	ocp_reg_write(tp, addr: 0xb87e, data: 0x370e);
7928	ocp_reg_write(tp, addr: 0xb87c, data: 0x8157);
7929	ocp_reg_write(tp, addr: 0xb87e, data: 0x770e);
7930	ocp_reg_write(tp, addr: 0xb87c, data: 0x8169);
7931	ocp_reg_write(tp, addr: 0xb87e, data: 0x0d0a);
7932	ocp_reg_write(tp, addr: 0xb87c, data: 0x817b);
7933	ocp_reg_write(tp, addr: 0xb87e, data: 0x1d0a);
7934
7935	data = sram_read(tp, addr: 0x8217);
7936	data &= ~0xff00;
7937	data |= 0x5000;
7938	sram_write(tp, addr: 0x8217, data);
7939	data = sram_read(tp, addr: 0x821a);
7940	data &= ~0xff00;
7941	data |= 0x5000;
7942	sram_write(tp, addr: 0x821a, data);
7943	sram_write(tp, addr: 0x80da, data: 0x0403);
7944	data = sram_read(tp, addr: 0x80dc);
7945	data &= ~0xff00;
7946	data |= 0x1000;
7947	sram_write(tp, addr: 0x80dc, data);
7948	sram_write(tp, addr: 0x80b3, data: 0x0384);
7949	sram_write(tp, addr: 0x80b7, data: 0x2007);
7950	data = sram_read(tp, addr: 0x80ba);
7951	data &= ~0xff00;
7952	data |= 0x6c00;
7953	sram_write(tp, addr: 0x80ba, data);
7954	sram_write(tp, addr: 0x80b5, data: 0xf009);
7955	data = sram_read(tp, addr: 0x80bd);
7956	data &= ~0xff00;
7957	data |= 0x9f00;
7958	sram_write(tp, addr: 0x80bd, data);
7959	sram_write(tp, addr: 0x80c7, data: 0xf083);
7960	sram_write(tp, addr: 0x80dd, data: 0x03f0);
7961	data = sram_read(tp, addr: 0x80df);
7962	data &= ~0xff00;
7963	data |= 0x1000;
7964	sram_write(tp, addr: 0x80df, data);
7965	sram_write(tp, addr: 0x80cb, data: 0x2007);
7966	data = sram_read(tp, addr: 0x80ce);
7967	data &= ~0xff00;
7968	data |= 0x6c00;
7969	sram_write(tp, addr: 0x80ce, data);
7970	sram_write(tp, addr: 0x80c9, data: 0x8009);
7971	data = sram_read(tp, addr: 0x80d1);
7972	data &= ~0xff00;
7973	data |= 0x8000;
7974	sram_write(tp, addr: 0x80d1, data);
7975	sram_write(tp, addr: 0x80a3, data: 0x200a);
7976	sram_write(tp, addr: 0x80a5, data: 0xf0ad);
7977	sram_write(tp, addr: 0x809f, data: 0x6073);
7978	sram_write(tp, addr: 0x80a1, data: 0x000b);
7979	data = sram_read(tp, addr: 0x80a9);
7980	data &= ~0xff00;
7981	data |= 0xc000;
7982	sram_write(tp, addr: 0x80a9, data);
7983
7984	if (rtl_phy_patch_request(tp, request: true, wait: true))
7985	return;
7986
7987	data = ocp_reg_read(tp, addr: 0xb896);
7988	data &= ~BIT(0);
7989	ocp_reg_write(tp, addr: 0xb896, data);
7990	data = ocp_reg_read(tp, addr: 0xb892);
7991	data &= ~0xff00;
7992	ocp_reg_write(tp, addr: 0xb892, data);
7993	ocp_reg_write(tp, addr: 0xb88e, data: 0xc23e);
7994	ocp_reg_write(tp, addr: 0xb890, data: 0x0000);
7995	ocp_reg_write(tp, addr: 0xb88e, data: 0xc240);
7996	ocp_reg_write(tp, addr: 0xb890, data: 0x0103);
7997	ocp_reg_write(tp, addr: 0xb88e, data: 0xc242);
7998	ocp_reg_write(tp, addr: 0xb890, data: 0x0507);
7999	ocp_reg_write(tp, addr: 0xb88e, data: 0xc244);
8000	ocp_reg_write(tp, addr: 0xb890, data: 0x090b);
8001	ocp_reg_write(tp, addr: 0xb88e, data: 0xc246);
8002	ocp_reg_write(tp, addr: 0xb890, data: 0x0c0e);
8003	ocp_reg_write(tp, addr: 0xb88e, data: 0xc248);
8004	ocp_reg_write(tp, addr: 0xb890, data: 0x1012);
8005	ocp_reg_write(tp, addr: 0xb88e, data: 0xc24a);
8006	ocp_reg_write(tp, addr: 0xb890, data: 0x1416);
8007	data = ocp_reg_read(tp, addr: 0xb896);
8008	data |= BIT(0);
8009	ocp_reg_write(tp, addr: 0xb896, data);
8010
8011	rtl_phy_patch_request(tp, request: false, wait: true);
8012
8013	data = ocp_reg_read(tp, addr: 0xa86a);
8014	data |= BIT(0);
8015	ocp_reg_write(tp, addr: 0xa86a, data);
8016	data = ocp_reg_read(tp, addr: 0xa6f0);
8017	data |= BIT(0);
8018	ocp_reg_write(tp, addr: 0xa6f0, data);
8019
8020	ocp_reg_write(tp, addr: 0xbfa0, data: 0xd70d);
8021	ocp_reg_write(tp, addr: 0xbfa2, data: 0x4100);
8022	ocp_reg_write(tp, addr: 0xbfa4, data: 0xe868);
8023	ocp_reg_write(tp, addr: 0xbfa6, data: 0xdc59);
8024	ocp_reg_write(tp, addr: 0xb54c, data: 0x3c18);
8025	data = ocp_reg_read(tp, addr: 0xbfa4);
8026	data &= ~BIT(5);
8027	ocp_reg_write(tp, addr: 0xbfa4, data);
8028	data = sram_read(tp, addr: 0x817d);
8029	data |= BIT(12);
8030	sram_write(tp, addr: 0x817d, data);
8031	break;
8032	case RTL_VER_13:
8033	/* 2.5G INRX */
8034	data = ocp_reg_read(tp, addr: 0xac46);
8035	data &= ~0x00f0;
8036	data |= 0x0090;
8037	ocp_reg_write(tp, addr: 0xac46, data);
8038	data = ocp_reg_read(tp, addr: 0xad30);
8039	data &= ~0x0003;
8040	data |= 0x0001;
8041	ocp_reg_write(tp, addr: 0xad30, data);
8042	fallthrough;
8043	case RTL_VER_15:
8044	/* EEE parameter */
8045	ocp_reg_write(tp, addr: 0xb87c, data: 0x80f5);
8046	ocp_reg_write(tp, addr: 0xb87e, data: 0x760e);
8047	ocp_reg_write(tp, addr: 0xb87c, data: 0x8107);
8048	ocp_reg_write(tp, addr: 0xb87e, data: 0x360e);
8049	ocp_reg_write(tp, addr: 0xb87c, data: 0x8551);
8050	data = ocp_reg_read(tp, addr: 0xb87e);
8051	data &= ~0xff00;
8052	data |= 0x0800;
8053	ocp_reg_write(tp, addr: 0xb87e, data);
8054
8055	/* ADC_PGA parameter */
8056	data = ocp_reg_read(tp, addr: 0xbf00);
8057	data &= ~0xe000;
8058	data |= 0xa000;
8059	ocp_reg_write(tp, addr: 0xbf00, data);
8060	data = ocp_reg_read(tp, addr: 0xbf46);
8061	data &= ~0x0f00;
8062	data |= 0x0300;
8063	ocp_reg_write(tp, addr: 0xbf46, data);
8064
8065	/* Green Table-PGA, 1G full viterbi */
8066	sram_write(tp, addr: 0x8044, data: 0x2417);
8067	sram_write(tp, addr: 0x804a, data: 0x2417);
8068	sram_write(tp, addr: 0x8050, data: 0x2417);
8069	sram_write(tp, addr: 0x8056, data: 0x2417);
8070	sram_write(tp, addr: 0x805c, data: 0x2417);
8071	sram_write(tp, addr: 0x8062, data: 0x2417);
8072	sram_write(tp, addr: 0x8068, data: 0x2417);
8073	sram_write(tp, addr: 0x806e, data: 0x2417);
8074	sram_write(tp, addr: 0x8074, data: 0x2417);
8075	sram_write(tp, addr: 0x807a, data: 0x2417);
8076
8077	/* XG PLL */
8078	data = ocp_reg_read(tp, addr: 0xbf84);
8079	data &= ~0xe000;
8080	data |= 0xa000;
8081	ocp_reg_write(tp, addr: 0xbf84, data);
8082	break;
8083	default:
8084	break;
8085	}
8086
8087	/* Notify the MAC when the speed is changed to force mode. */
8088	data = ocp_reg_read(tp, OCP_INTR_EN);
8089	data |= INTR_SPEED_FORCE;
8090	ocp_reg_write(tp, OCP_INTR_EN, data);
8091
8092	if (rtl_phy_patch_request(tp, request: true, wait: true))
8093	return;
8094
8095	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
8096	ocp_data |= EEE_SPDWN_EN;
8097	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, data: ocp_data);
8098
8099	data = ocp_reg_read(tp, OCP_DOWN_SPEED);
8100	data &= ~(EN_EEE_100 | EN_EEE_1000);
8101	data |= EN_10M_CLKDIV;
8102	ocp_reg_write(tp, OCP_DOWN_SPEED, data);
8103	tp->ups_info._10m_ckdiv = true;
8104	tp->ups_info.eee_plloff_100 = false;
8105	tp->ups_info.eee_plloff_giga = false;
8106
8107	data = ocp_reg_read(tp, OCP_POWER_CFG);
8108	data &= ~EEE_CLKDIV_EN;
8109	ocp_reg_write(tp, OCP_POWER_CFG, data);
8110	tp->ups_info.eee_ckdiv = false;
8111
8112	rtl_phy_patch_request(tp, request: false, wait: true);
8113
8114	rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
8115
8116	data = ocp_reg_read(tp, addr: 0xa428);
8117	data &= ~BIT(9);
8118	ocp_reg_write(tp, addr: 0xa428, data);
8119	data = ocp_reg_read(tp, addr: 0xa5ea);
8120	data &= ~BIT(0);
8121	ocp_reg_write(tp, addr: 0xa5ea, data);
8122	tp->ups_info.lite_mode = 0;
8123
8124	if (tp->eee_en)
8125	rtl_eee_enable(tp, enable: true);
8126
8127	r8153_aldps_en(tp, enable: true);
8128	r8152b_enable_fc(tp);
8129	r8153_u2p3en(tp, enable: true);
8130
8131	set_bit(nr: PHY_RESET, addr: &tp->flags);
8132	}
8133
8134	static void r8156_init(struct r8152 *tp)
8135	{
8136	u32 ocp_data;
8137	u16 data;
8138	int i;
8139
8140	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8141	return;
8142
8143	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
8144	ocp_data &= ~EN_ALL_SPEED;
8145	ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, data: ocp_data);
8146
8147	ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, data: 0);
8148
8149	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
8150	ocp_data |= BYPASS_MAC_RESET;
8151	ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, data: ocp_data);
8152
8153	r8153b_u1u2en(tp, enable: false);
8154
8155	for (i = 0; i < 500; i++) {
8156	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
8157	AUTOLOAD_DONE)
8158	break;
8159
8160	msleep(msecs: 20);
8161	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8162	return;
8163	}
8164
8165	data = r8153_phy_status(tp, desired: 0);
8166	if (data == PHY_STAT_EXT_INIT) {
8167	data = ocp_reg_read(tp, addr: 0xa468);
8168	data &= ~(BIT(3) | BIT(1));
8169	ocp_reg_write(tp, addr: 0xa468, data);
8170	}
8171
8172	data = r8152_mdio_read(tp, MII_BMCR);
8173	if (data & BMCR_PDOWN) {
8174	data &= ~BMCR_PDOWN;
8175	r8152_mdio_write(tp, MII_BMCR, value: data);
8176	}
8177
8178	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
8179	WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
8180
8181	r8153_u2p3en(tp, enable: false);
8182
8183	/* MSC timer = 0xfff * 8ms = 32760 ms */
8184	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, data: 0x0fff);
8185
8186	/* U1/U2/L1 idle timer. 500 us */
8187	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, data: 500);
8188
8189	r8153b_power_cut_en(tp, enable: false);
8190	r8156_ups_en(tp, enable: false);
8191	r8153_queue_wake(tp, enable: false);
8192	rtl_runtime_suspend_enable(tp, enable: false);
8193
8194	if (tp->udev->speed >= USB_SPEED_SUPER)
8195	r8153b_u1u2en(tp, enable: true);
8196
8197	usb_enable_lpm(udev: tp->udev);
8198
8199	r8156_mac_clk_spd(tp, enable: true);
8200
8201	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
8202	ocp_data &= ~PLA_MCU_SPDWN_EN;
8203	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
8204
8205	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8206	if (rtl8152_get_speed(tp) & LINK_STATUS)
8207	ocp_data |= CUR_LINK_OK;
8208	else
8209	ocp_data &= ~CUR_LINK_OK;
8210	ocp_data |= POLL_LINK_CHG;
8211	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, data: ocp_data);
8212
8213	set_bit(nr: GREEN_ETHERNET, addr: &tp->flags);
8214
8215	/* rx aggregation */
8216	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8217	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8218	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
8219
8220	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
8221	ocp_data |= ACT_ODMA;
8222	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, data: ocp_data);
8223
8224	r8156_mdio_force_mode(tp);
8225	rtl_tally_reset(tp);
8226
8227	tp->coalesce = 15000; /* 15 us */
8228	}
8229
8230	static void r8156b_init(struct r8152 *tp)
8231	{
8232	u32 ocp_data;
8233	u16 data;
8234	int i;
8235
8236	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8237	return;
8238
8239	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
8240	ocp_data &= ~EN_ALL_SPEED;
8241	ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, data: ocp_data);
8242
8243	ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, data: 0);
8244
8245	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
8246	ocp_data |= BYPASS_MAC_RESET;
8247	ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, data: ocp_data);
8248
8249	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
8250	ocp_data |= RX_DETECT8;
8251	ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, data: ocp_data);
8252
8253	r8153b_u1u2en(tp, enable: false);
8254
8255	switch (tp->version) {
8256	case RTL_VER_13:
8257	case RTL_VER_15:
8258	r8156b_wait_loading_flash(tp);
8259	break;
8260	default:
8261	break;
8262	}
8263
8264	for (i = 0; i < 500; i++) {
8265	if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
8266	AUTOLOAD_DONE)
8267	break;
8268
8269	msleep(msecs: 20);
8270	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8271	return;
8272	}
8273
8274	data = r8153_phy_status(tp, desired: 0);
8275	if (data == PHY_STAT_EXT_INIT) {
8276	data = ocp_reg_read(tp, addr: 0xa468);
8277	data &= ~(BIT(3) | BIT(1));
8278	ocp_reg_write(tp, addr: 0xa468, data);
8279
8280	data = ocp_reg_read(tp, addr: 0xa466);
8281	data &= ~BIT(0);
8282	ocp_reg_write(tp, addr: 0xa466, data);
8283	}
8284
8285	data = r8152_mdio_read(tp, MII_BMCR);
8286	if (data & BMCR_PDOWN) {
8287	data &= ~BMCR_PDOWN;
8288	r8152_mdio_write(tp, MII_BMCR, value: data);
8289	}
8290
8291	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
8292
8293	r8153_u2p3en(tp, enable: false);
8294
8295	/* MSC timer = 0xfff * 8ms = 32760 ms */
8296	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, data: 0x0fff);
8297
8298	/* U1/U2/L1 idle timer. 500 us */
8299	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, data: 500);
8300
8301	r8153b_power_cut_en(tp, enable: false);
8302	r8156_ups_en(tp, enable: false);
8303	r8153_queue_wake(tp, enable: false);
8304	rtl_runtime_suspend_enable(tp, enable: false);
8305
8306	if (tp->udev->speed >= USB_SPEED_SUPER)
8307	r8153b_u1u2en(tp, enable: true);
8308
8309	usb_enable_lpm(udev: tp->udev);
8310
8311	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR);
8312	ocp_data &= ~SLOT_EN;
8313	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
8314
8315	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
8316	ocp_data |= FLOW_CTRL_EN;
8317	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, data: ocp_data);
8318
8319	/* enable fc timer and set timer to 600 ms. */
8320	ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
8321	CTRL_TIMER_EN | (600 / 8));
8322
8323	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
8324	if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN))
8325	ocp_data |= FLOW_CTRL_PATCH_2;
8326	ocp_data &= ~AUTO_SPEEDUP;
8327	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, data: ocp_data);
8328
8329	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
8330	ocp_data |= FC_PATCH_TASK;
8331	ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, data: ocp_data);
8332
8333	r8156_mac_clk_spd(tp, enable: true);
8334
8335	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
8336	ocp_data &= ~PLA_MCU_SPDWN_EN;
8337	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, data: ocp_data);
8338
8339	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8340	if (rtl8152_get_speed(tp) & LINK_STATUS)
8341	ocp_data |= CUR_LINK_OK;
8342	else
8343	ocp_data &= ~CUR_LINK_OK;
8344	ocp_data |= POLL_LINK_CHG;
8345	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, data: ocp_data);
8346
8347	set_bit(nr: GREEN_ETHERNET, addr: &tp->flags);
8348
8349	/* rx aggregation */
8350	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8351	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8352	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, data: ocp_data);
8353
8354	r8156_mdio_force_mode(tp);
8355	rtl_tally_reset(tp);
8356
8357	tp->coalesce = 15000; /* 15 us */
8358	}
8359
8360	static bool rtl_check_vendor_ok(struct usb_interface *intf)
8361	{
8362	struct usb_host_interface *alt = intf->cur_altsetting;
8363	struct usb_endpoint_descriptor *in, *out, *intr;
8364
8365	if (usb_find_common_endpoints(alt, bulk_in: &in, bulk_out: &out, int_in: &intr, NULL) < 0) {
8366	dev_err(&intf->dev, "Expected endpoints are not found\n");
8367	return false;
8368	}
8369
8370	/* Check Rx endpoint address */
8371	if (usb_endpoint_num(epd: in) != 1) {
8372	dev_err(&intf->dev, "Invalid Rx endpoint address\n");
8373	return false;
8374	}
8375
8376	/* Check Tx endpoint address */
8377	if (usb_endpoint_num(epd: out) != 2) {
8378	dev_err(&intf->dev, "Invalid Tx endpoint address\n");
8379	return false;
8380	}
8381
8382	/* Check interrupt endpoint address */
8383	if (usb_endpoint_num(epd: intr) != 3) {
8384	dev_err(&intf->dev, "Invalid interrupt endpoint address\n");
8385	return false;
8386	}
8387
8388	return true;
8389	}
8390
8391	static int rtl8152_pre_reset(struct usb_interface *intf)
8392	{
8393	struct r8152 *tp = usb_get_intfdata(intf);
8394	struct net_device *netdev;
8395
8396	rtnl_lock();
8397
8398	if (!tp || !test_bit(PROBED_WITH_NO_ERRORS, &tp->flags))
8399	return 0;
8400
8401	netdev = tp->netdev;
8402	if (!netif_running(dev: netdev))
8403	return 0;
8404
8405	netif_stop_queue(dev: netdev);
8406	tasklet_disable(t: &tp->tx_tl);
8407	clear_bit(nr: WORK_ENABLE, addr: &tp->flags);
8408	usb_kill_urb(urb: tp->intr_urb);
8409	cancel_delayed_work_sync(dwork: &tp->schedule);
8410	napi_disable(n: &tp->napi);
8411	if (netif_carrier_ok(dev: netdev)) {
8412	mutex_lock(&tp->control);
8413	set_bit(nr: IN_PRE_RESET, addr: &tp->flags);
8414	tp->rtl_ops.disable(tp);
8415	clear_bit(nr: IN_PRE_RESET, addr: &tp->flags);
8416	mutex_unlock(lock: &tp->control);
8417	}
8418
8419	return 0;
8420	}
8421
8422	static int rtl8152_post_reset(struct usb_interface *intf)
8423	{
8424	struct r8152 *tp = usb_get_intfdata(intf);
8425	struct net_device *netdev;
8426	struct sockaddr_storage ss;
8427
8428	if (!tp || !test_bit(PROBED_WITH_NO_ERRORS, &tp->flags))
8429	goto exit;
8430
8431	rtl_set_accessible(tp);
8432
8433	/* reset the MAC address in case of policy change */
8434	if (determine_ethernet_addr(tp, ss: &ss) >= 0)
8435	dev_set_mac_address(dev: tp->netdev, ss: &ss, NULL);
8436
8437	netdev = tp->netdev;
8438	if (!netif_running(dev: netdev))
8439	goto exit;
8440
8441	set_bit(nr: WORK_ENABLE, addr: &tp->flags);
8442	if (netif_carrier_ok(dev: netdev)) {
8443	mutex_lock(&tp->control);
8444	tp->rtl_ops.enable(tp);
8445	rtl_start_rx(tp);
8446	_rtl8152_set_rx_mode(netdev);
8447	mutex_unlock(lock: &tp->control);
8448	}
8449
8450	napi_enable(n: &tp->napi);
8451	tasklet_enable(t: &tp->tx_tl);
8452	netif_wake_queue(dev: netdev);
8453	usb_submit_urb(urb: tp->intr_urb, GFP_KERNEL);
8454
8455	if (!list_empty(head: &tp->rx_done))
8456	napi_schedule(n: &tp->napi);
8457
8458	exit:
8459	rtnl_unlock();
8460	return 0;
8461	}
8462
8463	static bool delay_autosuspend(struct r8152 *tp)
8464	{
8465	bool sw_linking = !!netif_carrier_ok(dev: tp->netdev);
8466	bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
8467
8468	/* This means a linking change occurs and the driver doesn't detect it,
8469	* yet. If the driver has disabled tx/rx and hw is linking on, the
8470	* device wouldn't wake up by receiving any packet.
8471	*/
8472	if (work_busy(work: &tp->schedule.work) || sw_linking != hw_linking)
8473	return true;
8474
8475	/* If the linking down is occurred by nway, the device may miss the
8476	* linking change event. And it wouldn't wake when linking on.
8477	*/
8478	if (!sw_linking && tp->rtl_ops.in_nway(tp))
8479	return true;
8480	else if (!skb_queue_empty(list: &tp->tx_queue))
8481	return true;
8482	else
8483	return false;
8484	}
8485
8486	static int rtl8152_runtime_resume(struct r8152 *tp)
8487	{
8488	struct net_device *netdev = tp->netdev;
8489
8490	if (netif_running(dev: netdev) && netdev->flags & IFF_UP) {
8491	struct napi_struct *napi = &tp->napi;
8492
8493	tp->rtl_ops.autosuspend_en(tp, false);
8494	napi_disable(n: napi);
8495	set_bit(nr: WORK_ENABLE, addr: &tp->flags);
8496
8497	if (netif_carrier_ok(dev: netdev)) {
8498	if (rtl8152_get_speed(tp) & LINK_STATUS) {
8499	rtl_start_rx(tp);
8500	} else {
8501	netif_carrier_off(dev: netdev);
8502	tp->rtl_ops.disable(tp);
8503	netif_info(tp, link, netdev, "linking down\n");
8504	}
8505	}
8506
8507	napi_enable(n: napi);
8508	clear_bit(nr: SELECTIVE_SUSPEND, addr: &tp->flags);
8509	smp_mb__after_atomic();
8510
8511	if (!list_empty(head: &tp->rx_done))
8512	napi_schedule(n: &tp->napi);
8513
8514	usb_submit_urb(urb: tp->intr_urb, GFP_NOIO);
8515	} else {
8516	if (netdev->flags & IFF_UP)
8517	tp->rtl_ops.autosuspend_en(tp, false);
8518
8519	clear_bit(nr: SELECTIVE_SUSPEND, addr: &tp->flags);
8520	}
8521
8522	return 0;
8523	}
8524
8525	static int rtl8152_system_resume(struct r8152 *tp)
8526	{
8527	struct net_device *netdev = tp->netdev;
8528
8529	netif_device_attach(dev: netdev);
8530
8531	if (netif_running(dev: netdev) && (netdev->flags & IFF_UP)) {
8532	tp->rtl_ops.up(tp);
8533	netif_carrier_off(dev: netdev);
8534	set_bit(nr: WORK_ENABLE, addr: &tp->flags);
8535	usb_submit_urb(urb: tp->intr_urb, GFP_NOIO);
8536	}
8537
8538	return 0;
8539	}
8540
8541	static int rtl8152_runtime_suspend(struct r8152 *tp)
8542	{
8543	struct net_device *netdev = tp->netdev;
8544	int ret = 0;
8545
8546	if (!tp->rtl_ops.autosuspend_en)
8547	return -EBUSY;
8548
8549	set_bit(nr: SELECTIVE_SUSPEND, addr: &tp->flags);
8550	smp_mb__after_atomic();
8551
8552	if (netif_running(dev: netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8553	u32 rcr = 0;
8554
8555	if (netif_carrier_ok(dev: netdev)) {
8556	u32 ocp_data;
8557
8558	rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
8559	ocp_data = rcr & ~RCR_ACPT_ALL;
8560	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: ocp_data);
8561	rxdy_gated_en(tp, enable: true);
8562	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
8563	PLA_OOB_CTRL);
8564	if (!(ocp_data & RXFIFO_EMPTY)) {
8565	rxdy_gated_en(tp, enable: false);
8566	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: rcr);
8567	clear_bit(nr: SELECTIVE_SUSPEND, addr: &tp->flags);
8568	smp_mb__after_atomic();
8569	ret = -EBUSY;
8570	goto out1;
8571	}
8572	}
8573
8574	clear_bit(nr: WORK_ENABLE, addr: &tp->flags);
8575	usb_kill_urb(urb: tp->intr_urb);
8576
8577	tp->rtl_ops.autosuspend_en(tp, true);
8578
8579	if (netif_carrier_ok(dev: netdev)) {
8580	struct napi_struct *napi = &tp->napi;
8581
8582	napi_disable(n: napi);
8583	rtl_stop_rx(tp);
8584	rxdy_gated_en(tp, enable: false);
8585	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, data: rcr);
8586	napi_enable(n: napi);
8587	}
8588
8589	if (delay_autosuspend(tp)) {
8590	rtl8152_runtime_resume(tp);
8591	ret = -EBUSY;
8592	}
8593	}
8594
8595	out1:
8596	return ret;
8597	}
8598
8599	static int rtl8152_system_suspend(struct r8152 *tp)
8600	{
8601	struct net_device *netdev = tp->netdev;
8602
8603	netif_device_detach(dev: netdev);
8604
8605	if (netif_running(dev: netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8606	struct napi_struct *napi = &tp->napi;
8607
8608	clear_bit(nr: WORK_ENABLE, addr: &tp->flags);
8609	usb_kill_urb(urb: tp->intr_urb);
8610	tasklet_disable(t: &tp->tx_tl);
8611	napi_disable(n: napi);
8612	cancel_delayed_work_sync(dwork: &tp->schedule);
8613	tp->rtl_ops.down(tp);
8614	napi_enable(n: napi);
8615	tasklet_enable(t: &tp->tx_tl);
8616	}
8617
8618	/* If we're inaccessible here then some of the work that we did to
8619	* get the adapter ready for suspend didn't work. Queue up a wakeup
8620	* event so we can try again.
8621	*/
8622	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8623	pm_wakeup_event(dev: &tp->udev->dev, msec: 0);
8624
8625	return 0;
8626	}
8627
8628	static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
8629	{
8630	struct r8152 *tp = usb_get_intfdata(intf);
8631	int ret;
8632
8633	mutex_lock(&tp->control);
8634
8635	if (PMSG_IS_AUTO(message))
8636	ret = rtl8152_runtime_suspend(tp);
8637	else
8638	ret = rtl8152_system_suspend(tp);
8639
8640	mutex_unlock(lock: &tp->control);
8641
8642	return ret;
8643	}
8644
8645	static int rtl8152_resume(struct usb_interface *intf)
8646	{
8647	struct r8152 *tp = usb_get_intfdata(intf);
8648	bool runtime_resume = test_bit(SELECTIVE_SUSPEND, &tp->flags);
8649	int ret;
8650
8651	mutex_lock(&tp->control);
8652
8653	rtl_reset_ocp_base(tp);
8654
8655	if (runtime_resume)
8656	ret = rtl8152_runtime_resume(tp);
8657	else
8658	ret = rtl8152_system_resume(tp);
8659
8660	mutex_unlock(lock: &tp->control);
8661
8662	/* If the device is RTL8152_INACCESSIBLE here then we should do a
8663	* reset. This is important because the usb_lock_device_for_reset()
8664	* that happens as a result of usb_queue_reset_device() will silently
8665	* fail if the device was suspended or if too much time passed.
8666	*
8667	* NOTE: The device is locked here so we can directly do the reset.
8668	* We don't need usb_lock_device_for_reset() because that's just a
8669	* wrapper over device_lock() and device_resume() (which calls us)
8670	* does that for us.
8671	*/
8672	if (!runtime_resume && test_bit(RTL8152_INACCESSIBLE, &tp->flags))
8673	usb_reset_device(dev: tp->udev);
8674
8675	return ret;
8676	}
8677
8678	static int rtl8152_reset_resume(struct usb_interface *intf)
8679	{
8680	struct r8152 *tp = usb_get_intfdata(intf);
8681
8682	clear_bit(nr: SELECTIVE_SUSPEND, addr: &tp->flags);
8683	rtl_reset_ocp_base(tp);
8684	tp->rtl_ops.init(tp);
8685	queue_delayed_work(wq: system_long_wq, dwork: &tp->hw_phy_work, delay: 0);
8686	set_ethernet_addr(tp, in_resume: true);
8687	return rtl8152_resume(intf);
8688	}
8689
8690	static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8691	{
8692	struct r8152 *tp = netdev_priv(dev);
8693
8694	if (usb_autopm_get_interface(intf: tp->intf) < 0)
8695	return;
8696
8697	if (!rtl_can_wakeup(tp)) {
8698	wol->supported = 0;
8699	wol->wolopts = 0;
8700	} else {
8701	mutex_lock(&tp->control);
8702	wol->supported = WAKE_ANY;
8703	wol->wolopts = __rtl_get_wol(tp);
8704	mutex_unlock(lock: &tp->control);
8705	}
8706
8707	usb_autopm_put_interface(intf: tp->intf);
8708	}
8709
8710	static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8711	{
8712	struct r8152 *tp = netdev_priv(dev);
8713	int ret;
8714
8715	if (!rtl_can_wakeup(tp))
8716	return -EOPNOTSUPP;
8717
8718	if (wol->wolopts & ~WAKE_ANY)
8719	return -EINVAL;
8720
8721	ret = usb_autopm_get_interface(intf: tp->intf);
8722	if (ret < 0)
8723	goto out_set_wol;
8724
8725	mutex_lock(&tp->control);
8726
8727	__rtl_set_wol(tp, wolopts: wol->wolopts);
8728	tp->saved_wolopts = wol->wolopts & WAKE_ANY;
8729
8730	mutex_unlock(lock: &tp->control);
8731
8732	usb_autopm_put_interface(intf: tp->intf);
8733
8734	out_set_wol:
8735	return ret;
8736	}
8737
8738	static u32 rtl8152_get_msglevel(struct net_device *dev)
8739	{
8740	struct r8152 *tp = netdev_priv(dev);
8741
8742	return tp->msg_enable;
8743	}
8744
8745	static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
8746	{
8747	struct r8152 *tp = netdev_priv(dev);
8748
8749	tp->msg_enable = value;
8750	}
8751
8752	static void rtl8152_get_drvinfo(struct net_device *netdev,
8753	struct ethtool_drvinfo *info)
8754	{
8755	struct r8152 *tp = netdev_priv(dev: netdev);
8756
8757	strscpy(info->driver, MODULENAME, sizeof(info->driver));
8758	strscpy(info->version, DRIVER_VERSION, sizeof(info->version));
8759	usb_make_path(dev: tp->udev, buf: info->bus_info, size: sizeof(info->bus_info));
8760	if (!IS_ERR_OR_NULL(ptr: tp->rtl_fw.fw))
8761	strscpy(info->fw_version, tp->rtl_fw.version,
8762	sizeof(info->fw_version));
8763	}
8764
8765	static
8766	int rtl8152_get_link_ksettings(struct net_device *netdev,
8767	struct ethtool_link_ksettings *cmd)
8768	{
8769	struct r8152 *tp = netdev_priv(dev: netdev);
8770	int ret;
8771
8772	if (!tp->mii.mdio_read)
8773	return -EOPNOTSUPP;
8774
8775	ret = usb_autopm_get_interface(intf: tp->intf);
8776	if (ret < 0)
8777	goto out;
8778
8779	mutex_lock(&tp->control);
8780
8781	mii_ethtool_get_link_ksettings(mii: &tp->mii, cmd);
8782
8783	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8784	cmd->link_modes.supported, tp->support_2500full);
8785
8786	if (tp->support_2500full) {
8787	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8788	cmd->link_modes.advertising,
8789	ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G);
8790
8791	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8792	cmd->link_modes.lp_advertising,
8793	ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G);
8794
8795	if (is_speed_2500(rtl8152_get_speed(tp)))
8796	cmd->base.speed = SPEED_2500;
8797	}
8798
8799	mutex_unlock(lock: &tp->control);
8800
8801	usb_autopm_put_interface(intf: tp->intf);
8802
8803	out:
8804	return ret;
8805	}
8806
8807	static int rtl8152_set_link_ksettings(struct net_device *dev,
8808	const struct ethtool_link_ksettings *cmd)
8809	{
8810	struct r8152 *tp = netdev_priv(dev);
8811	u32 advertising = 0;
8812	int ret;
8813
8814	ret = usb_autopm_get_interface(intf: tp->intf);
8815	if (ret < 0)
8816	goto out;
8817
8818	if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
8819	cmd->link_modes.advertising))
8820	advertising |= RTL_ADVERTISED_10_HALF;
8821
8822	if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
8823	cmd->link_modes.advertising))
8824	advertising |= RTL_ADVERTISED_10_FULL;
8825
8826	if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
8827	cmd->link_modes.advertising))
8828	advertising |= RTL_ADVERTISED_100_HALF;
8829
8830	if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
8831	cmd->link_modes.advertising))
8832	advertising |= RTL_ADVERTISED_100_FULL;
8833
8834	if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
8835	cmd->link_modes.advertising))
8836	advertising |= RTL_ADVERTISED_1000_HALF;
8837
8838	if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
8839	cmd->link_modes.advertising))
8840	advertising |= RTL_ADVERTISED_1000_FULL;
8841
8842	if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8843	cmd->link_modes.advertising))
8844	advertising |= RTL_ADVERTISED_2500_FULL;
8845
8846	mutex_lock(&tp->control);
8847
8848	ret = rtl8152_set_speed(tp, autoneg: cmd->base.autoneg, speed: cmd->base.speed,
8849	duplex: cmd->base.duplex, advertising);
8850	if (!ret) {
8851	tp->autoneg = cmd->base.autoneg;
8852	tp->speed = cmd->base.speed;
8853	tp->duplex = cmd->base.duplex;
8854	tp->advertising = advertising;
8855	}
8856
8857	mutex_unlock(lock: &tp->control);
8858
8859	usb_autopm_put_interface(intf: tp->intf);
8860
8861	out:
8862	return ret;
8863	}
8864
8865	static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
8866	"tx_packets",
8867	"rx_packets",
8868	"tx_errors",
8869	"rx_errors",
8870	"rx_missed",
8871	"align_errors",
8872	"tx_single_collisions",
8873	"tx_multi_collisions",
8874	"rx_unicast",
8875	"rx_broadcast",
8876	"rx_multicast",
8877	"tx_aborted",
8878	"tx_underrun",
8879	};
8880
8881	static int rtl8152_get_sset_count(struct net_device *dev, int sset)
8882	{
8883	switch (sset) {
8884	case ETH_SS_STATS:
8885	return ARRAY_SIZE(rtl8152_gstrings);
8886	default:
8887	return -EOPNOTSUPP;
8888	}
8889	}
8890
8891	static void rtl8152_get_ethtool_stats(struct net_device *dev,
8892	struct ethtool_stats *stats, u64 *data)
8893	{
8894	struct r8152 *tp = netdev_priv(dev);
8895	struct tally_counter tally;
8896
8897	if (usb_autopm_get_interface(intf: tp->intf) < 0)
8898	return;
8899
8900	generic_ocp_read(tp, PLA_TALLYCNT, size: sizeof(tally), data: &tally, MCU_TYPE_PLA);
8901
8902	usb_autopm_put_interface(intf: tp->intf);
8903
8904	data[0] = le64_to_cpu(tally.tx_packets);
8905	data[1] = le64_to_cpu(tally.rx_packets);
8906	data[2] = le64_to_cpu(tally.tx_errors);
8907	data[3] = le32_to_cpu(tally.rx_errors);
8908	data[4] = le16_to_cpu(tally.rx_missed);
8909	data[5] = le16_to_cpu(tally.align_errors);
8910	data[6] = le32_to_cpu(tally.tx_one_collision);
8911	data[7] = le32_to_cpu(tally.tx_multi_collision);
8912	data[8] = le64_to_cpu(tally.rx_unicast);
8913	data[9] = le64_to_cpu(tally.rx_broadcast);
8914	data[10] = le32_to_cpu(tally.rx_multicast);
8915	data[11] = le16_to_cpu(tally.tx_aborted);
8916	data[12] = le16_to_cpu(tally.tx_underrun);
8917	}
8918
8919	static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
8920	{
8921	switch (stringset) {
8922	case ETH_SS_STATS:
8923	memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
8924	break;
8925	}
8926	}
8927
8928	static int r8152_get_eee(struct r8152 *tp, struct ethtool_keee *eee)
8929	{
8930	__ETHTOOL_DECLARE_LINK_MODE_MASK(common);
8931	u16 val;
8932
8933	val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
8934	mii_eee_cap1_mod_linkmode_t(adv: eee->supported, val);
8935
8936	val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
8937	mii_eee_cap1_mod_linkmode_t(adv: eee->advertised, val);
8938
8939	val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
8940	mii_eee_cap1_mod_linkmode_t(adv: eee->lp_advertised, val);
8941
8942	eee->eee_enabled = tp->eee_en;
8943
8944	linkmode_and(dst: common, a: eee->advertised, b: eee->lp_advertised);
8945	eee->eee_active = phy_check_valid(speed: tp->speed, duplex: tp->duplex, features: common);
8946
8947	return 0;
8948	}
8949
8950	static int r8152_set_eee(struct r8152 *tp, struct ethtool_keee *eee)
8951	{
8952	u16 val = linkmode_to_mii_eee_cap1_t(adv: eee->advertised);
8953
8954	tp->eee_en = eee->eee_enabled;
8955	tp->eee_adv = val;
8956
8957	rtl_eee_enable(tp, enable: tp->eee_en);
8958
8959	return 0;
8960	}
8961
8962	static int r8153_get_eee(struct r8152 *tp, struct ethtool_keee *eee)
8963	{
8964	__ETHTOOL_DECLARE_LINK_MODE_MASK(common);
8965	u16 val;
8966
8967	val = ocp_reg_read(tp, OCP_EEE_ABLE);
8968	mii_eee_cap1_mod_linkmode_t(adv: eee->supported, val);
8969
8970	val = ocp_reg_read(tp, OCP_EEE_ADV);
8971	mii_eee_cap1_mod_linkmode_t(adv: eee->advertised, val);
8972
8973	val = ocp_reg_read(tp, OCP_EEE_LPABLE);
8974	mii_eee_cap1_mod_linkmode_t(adv: eee->lp_advertised, val);
8975
8976	eee->eee_enabled = tp->eee_en;
8977
8978	linkmode_and(dst: common, a: eee->advertised, b: eee->lp_advertised);
8979	eee->eee_active = phy_check_valid(speed: tp->speed, duplex: tp->duplex, features: common);
8980
8981	return 0;
8982	}
8983
8984	static int
8985	rtl_ethtool_get_eee(struct net_device *net, struct ethtool_keee *edata)
8986	{
8987	struct r8152 *tp = netdev_priv(dev: net);
8988	int ret;
8989
8990	if (!tp->rtl_ops.eee_get) {
8991	ret = -EOPNOTSUPP;
8992	goto out;
8993	}
8994
8995	ret = usb_autopm_get_interface(intf: tp->intf);
8996	if (ret < 0)
8997	goto out;
8998
8999	mutex_lock(&tp->control);
9000
9001	ret = tp->rtl_ops.eee_get(tp, edata);
9002
9003	mutex_unlock(lock: &tp->control);
9004
9005	usb_autopm_put_interface(intf: tp->intf);
9006
9007	out:
9008	return ret;
9009	}
9010
9011	static int
9012	rtl_ethtool_set_eee(struct net_device *net, struct ethtool_keee *edata)
9013	{
9014	struct r8152 *tp = netdev_priv(dev: net);
9015	int ret;
9016
9017	if (!tp->rtl_ops.eee_set) {
9018	ret = -EOPNOTSUPP;
9019	goto out;
9020	}
9021
9022	ret = usb_autopm_get_interface(intf: tp->intf);
9023	if (ret < 0)
9024	goto out;
9025
9026	mutex_lock(&tp->control);
9027
9028	ret = tp->rtl_ops.eee_set(tp, edata);
9029	if (!ret)
9030	ret = mii_nway_restart(mii: &tp->mii);
9031
9032	mutex_unlock(lock: &tp->control);
9033
9034	usb_autopm_put_interface(intf: tp->intf);
9035
9036	out:
9037	return ret;
9038	}
9039
9040	static int rtl8152_nway_reset(struct net_device *dev)
9041	{
9042	struct r8152 *tp = netdev_priv(dev);
9043	int ret;
9044
9045	ret = usb_autopm_get_interface(intf: tp->intf);
9046	if (ret < 0)
9047	goto out;
9048
9049	mutex_lock(&tp->control);
9050
9051	ret = mii_nway_restart(mii: &tp->mii);
9052
9053	mutex_unlock(lock: &tp->control);
9054
9055	usb_autopm_put_interface(intf: tp->intf);
9056
9057	out:
9058	return ret;
9059	}
9060
9061	static int rtl8152_get_coalesce(struct net_device *netdev,
9062	struct ethtool_coalesce *coalesce,
9063	struct kernel_ethtool_coalesce *kernel_coal,
9064	struct netlink_ext_ack *extack)
9065	{
9066	struct r8152 *tp = netdev_priv(dev: netdev);
9067
9068	switch (tp->version) {
9069	case RTL_VER_01:
9070	case RTL_VER_02:
9071	case RTL_VER_07:
9072	return -EOPNOTSUPP;
9073	default:
9074	break;
9075	}
9076
9077	coalesce->rx_coalesce_usecs = tp->coalesce;
9078
9079	return 0;
9080	}
9081
9082	static int rtl8152_set_coalesce(struct net_device *netdev,
9083	struct ethtool_coalesce *coalesce,
9084	struct kernel_ethtool_coalesce *kernel_coal,
9085	struct netlink_ext_ack *extack)
9086	{
9087	struct r8152 *tp = netdev_priv(dev: netdev);
9088	int ret;
9089
9090	switch (tp->version) {
9091	case RTL_VER_01:
9092	case RTL_VER_02:
9093	case RTL_VER_07:
9094	return -EOPNOTSUPP;
9095	default:
9096	break;
9097	}
9098
9099	if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
9100	return -EINVAL;
9101
9102	ret = usb_autopm_get_interface(intf: tp->intf);
9103	if (ret < 0)
9104	return ret;
9105
9106	mutex_lock(&tp->control);
9107
9108	if (tp->coalesce != coalesce->rx_coalesce_usecs) {
9109	tp->coalesce = coalesce->rx_coalesce_usecs;
9110
9111	if (netif_running(dev: netdev) && netif_carrier_ok(dev: netdev)) {
9112	netif_stop_queue(dev: netdev);
9113	napi_disable(n: &tp->napi);
9114	tp->rtl_ops.disable(tp);
9115	tp->rtl_ops.enable(tp);
9116	rtl_start_rx(tp);
9117	clear_bit(nr: RTL8152_SET_RX_MODE, addr: &tp->flags);
9118	_rtl8152_set_rx_mode(netdev);
9119	napi_enable(n: &tp->napi);
9120	netif_wake_queue(dev: netdev);
9121	}
9122	}
9123
9124	mutex_unlock(lock: &tp->control);
9125
9126	usb_autopm_put_interface(intf: tp->intf);
9127
9128	return ret;
9129	}
9130
9131	static int rtl8152_get_tunable(struct net_device *netdev,
9132	const struct ethtool_tunable *tunable, void *d)
9133	{
9134	struct r8152 *tp = netdev_priv(dev: netdev);
9135
9136	switch (tunable->id) {
9137	case ETHTOOL_RX_COPYBREAK:
9138	*(u32 *)d = tp->rx_copybreak;
9139	break;
9140	default:
9141	return -EOPNOTSUPP;
9142	}
9143
9144	return 0;
9145	}
9146
9147	static int rtl8152_set_tunable(struct net_device *netdev,
9148	const struct ethtool_tunable *tunable,
9149	const void *d)
9150	{
9151	struct r8152 *tp = netdev_priv(dev: netdev);
9152	u32 val;
9153
9154	switch (tunable->id) {
9155	case ETHTOOL_RX_COPYBREAK:
9156	val = *(u32 *)d;
9157	if (val < ETH_ZLEN) {
9158	netif_err(tp, rx_err, netdev,
9159	"Invalid rx copy break value\n");
9160	return -EINVAL;
9161	}
9162
9163	if (tp->rx_copybreak != val) {
9164	if (netdev->flags & IFF_UP) {
9165	mutex_lock(&tp->control);
9166	napi_disable(n: &tp->napi);
9167	tp->rx_copybreak = val;
9168	napi_enable(n: &tp->napi);
9169	mutex_unlock(lock: &tp->control);
9170	} else {
9171	tp->rx_copybreak = val;
9172	}
9173	}
9174	break;
9175	default:
9176	return -EOPNOTSUPP;
9177	}
9178
9179	return 0;
9180	}
9181
9182	static void rtl8152_get_ringparam(struct net_device *netdev,
9183	struct ethtool_ringparam *ring,
9184	struct kernel_ethtool_ringparam *kernel_ring,
9185	struct netlink_ext_ack *extack)
9186	{
9187	struct r8152 *tp = netdev_priv(dev: netdev);
9188
9189	ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
9190	ring->rx_pending = tp->rx_pending;
9191	}
9192
9193	static int rtl8152_set_ringparam(struct net_device *netdev,
9194	struct ethtool_ringparam *ring,
9195	struct kernel_ethtool_ringparam *kernel_ring,
9196	struct netlink_ext_ack *extack)
9197	{
9198	struct r8152 *tp = netdev_priv(dev: netdev);
9199
9200	if (ring->rx_pending < (RTL8152_MAX_RX * 2))
9201	return -EINVAL;
9202
9203	if (tp->rx_pending != ring->rx_pending) {
9204	if (netdev->flags & IFF_UP) {
9205	mutex_lock(&tp->control);
9206	napi_disable(n: &tp->napi);
9207	tp->rx_pending = ring->rx_pending;
9208	napi_enable(n: &tp->napi);
9209	mutex_unlock(lock: &tp->control);
9210	} else {
9211	tp->rx_pending = ring->rx_pending;
9212	}
9213	}
9214
9215	return 0;
9216	}
9217
9218	static void rtl8152_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9219	{
9220	struct r8152 *tp = netdev_priv(dev: netdev);
9221	u16 bmcr, lcladv, rmtadv;
9222	u8 cap;
9223
9224	if (usb_autopm_get_interface(intf: tp->intf) < 0)
9225	return;
9226
9227	mutex_lock(&tp->control);
9228
9229	bmcr = r8152_mdio_read(tp, MII_BMCR);
9230	lcladv = r8152_mdio_read(tp, MII_ADVERTISE);
9231	rmtadv = r8152_mdio_read(tp, MII_LPA);
9232
9233	mutex_unlock(lock: &tp->control);
9234
9235	usb_autopm_put_interface(intf: tp->intf);
9236
9237	if (!(bmcr & BMCR_ANENABLE)) {
9238	pause->autoneg = 0;
9239	pause->rx_pause = 0;
9240	pause->tx_pause = 0;
9241	return;
9242	}
9243
9244	pause->autoneg = 1;
9245
9246	cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
9247
9248	if (cap & FLOW_CTRL_RX)
9249	pause->rx_pause = 1;
9250
9251	if (cap & FLOW_CTRL_TX)
9252	pause->tx_pause = 1;
9253	}
9254
9255	static int rtl8152_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9256	{
9257	struct r8152 *tp = netdev_priv(dev: netdev);
9258	u16 old, new1;
9259	u8 cap = 0;
9260	int ret;
9261
9262	ret = usb_autopm_get_interface(intf: tp->intf);
9263	if (ret < 0)
9264	return ret;
9265
9266	mutex_lock(&tp->control);
9267
9268	if (pause->autoneg && !(r8152_mdio_read(tp, MII_BMCR) & BMCR_ANENABLE)) {
9269	ret = -EINVAL;
9270	goto out;
9271	}
9272
9273	if (pause->rx_pause)
9274	cap |= FLOW_CTRL_RX;
9275
9276	if (pause->tx_pause)
9277	cap |= FLOW_CTRL_TX;
9278
9279	old = r8152_mdio_read(tp, MII_ADVERTISE);
9280	new1 = (old & ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) | mii_advertise_flowctrl(cap);
9281	if (old != new1)
9282	r8152_mdio_write(tp, MII_ADVERTISE, value: new1);
9283
9284	out:
9285	mutex_unlock(lock: &tp->control);
9286	usb_autopm_put_interface(intf: tp->intf);
9287
9288	return ret;
9289	}
9290
9291	static const struct ethtool_ops ops = {
9292	.supported_coalesce_params = ETHTOOL_COALESCE_USECS,
9293	.get_drvinfo = rtl8152_get_drvinfo,
9294	.get_link = ethtool_op_get_link,
9295	.nway_reset = rtl8152_nway_reset,
9296	.get_msglevel = rtl8152_get_msglevel,
9297	.set_msglevel = rtl8152_set_msglevel,
9298	.get_wol = rtl8152_get_wol,
9299	.set_wol = rtl8152_set_wol,
9300	.get_strings = rtl8152_get_strings,
9301	.get_sset_count = rtl8152_get_sset_count,
9302	.get_ethtool_stats = rtl8152_get_ethtool_stats,
9303	.get_coalesce = rtl8152_get_coalesce,
9304	.set_coalesce = rtl8152_set_coalesce,
9305	.get_eee = rtl_ethtool_get_eee,
9306	.set_eee = rtl_ethtool_set_eee,
9307	.get_link_ksettings = rtl8152_get_link_ksettings,
9308	.set_link_ksettings = rtl8152_set_link_ksettings,
9309	.get_tunable = rtl8152_get_tunable,
9310	.set_tunable = rtl8152_set_tunable,
9311	.get_ringparam = rtl8152_get_ringparam,
9312	.set_ringparam = rtl8152_set_ringparam,
9313	.get_pauseparam = rtl8152_get_pauseparam,
9314	.set_pauseparam = rtl8152_set_pauseparam,
9315	.get_ts_info = ethtool_op_get_ts_info,
9316	};
9317
9318	static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
9319	{
9320	struct r8152 *tp = netdev_priv(dev: netdev);
9321	struct mii_ioctl_data *data = if_mii(rq);
9322	int res;
9323
9324	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9325	return -ENODEV;
9326
9327	res = usb_autopm_get_interface(intf: tp->intf);
9328	if (res < 0)
9329	goto out;
9330
9331	switch (cmd) {
9332	case SIOCGMIIPHY:
9333	data->phy_id = R8152_PHY_ID; /* Internal PHY */
9334	break;
9335
9336	case SIOCGMIIREG:
9337	mutex_lock(&tp->control);
9338	data->val_out = r8152_mdio_read(tp, reg_addr: data->reg_num);
9339	mutex_unlock(lock: &tp->control);
9340	break;
9341
9342	case SIOCSMIIREG:
9343	if (!capable(CAP_NET_ADMIN)) {
9344	res = -EPERM;
9345	break;
9346	}
9347	mutex_lock(&tp->control);
9348	r8152_mdio_write(tp, reg_addr: data->reg_num, value: data->val_in);
9349	mutex_unlock(lock: &tp->control);
9350	break;
9351
9352	default:
9353	res = -EOPNOTSUPP;
9354	}
9355
9356	usb_autopm_put_interface(intf: tp->intf);
9357
9358	out:
9359	return res;
9360	}
9361
9362	static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
9363	{
9364	struct r8152 *tp = netdev_priv(dev);
9365	int ret;
9366
9367	switch (tp->version) {
9368	case RTL_VER_01:
9369	case RTL_VER_02:
9370	case RTL_VER_07:
9371	WRITE_ONCE(dev->mtu, new_mtu);
9372	return 0;
9373	default:
9374	break;
9375	}
9376
9377	ret = usb_autopm_get_interface(intf: tp->intf);
9378	if (ret < 0)
9379	return ret;
9380
9381	mutex_lock(&tp->control);
9382
9383	WRITE_ONCE(dev->mtu, new_mtu);
9384
9385	if (netif_running(dev)) {
9386	if (tp->rtl_ops.change_mtu)
9387	tp->rtl_ops.change_mtu(tp);
9388
9389	if (netif_carrier_ok(dev)) {
9390	netif_stop_queue(dev);
9391	napi_disable(n: &tp->napi);
9392	tasklet_disable(t: &tp->tx_tl);
9393	tp->rtl_ops.disable(tp);
9394	tp->rtl_ops.enable(tp);
9395	rtl_start_rx(tp);
9396	tasklet_enable(t: &tp->tx_tl);
9397	napi_enable(n: &tp->napi);
9398	rtl8152_set_rx_mode(netdev: dev);
9399	netif_wake_queue(dev);
9400	}
9401	}
9402
9403	mutex_unlock(lock: &tp->control);
9404
9405	usb_autopm_put_interface(intf: tp->intf);
9406
9407	return ret;
9408	}
9409
9410	static const struct net_device_ops rtl8152_netdev_ops = {
9411	.ndo_open = rtl8152_open,
9412	.ndo_stop = rtl8152_close,
9413	.ndo_eth_ioctl = rtl8152_ioctl,
9414	.ndo_start_xmit = rtl8152_start_xmit,
9415	.ndo_tx_timeout = rtl8152_tx_timeout,
9416	.ndo_set_features = rtl8152_set_features,
9417	.ndo_set_rx_mode = rtl8152_set_rx_mode,
9418	.ndo_set_mac_address = rtl8152_set_mac_address,
9419	.ndo_change_mtu = rtl8152_change_mtu,
9420	.ndo_validate_addr = eth_validate_addr,
9421	.ndo_features_check = rtl8152_features_check,
9422	};
9423
9424	static void rtl8152_unload(struct r8152 *tp)
9425	{
9426	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9427	return;
9428
9429	if (tp->version != RTL_VER_01)
9430	r8152_power_cut_en(tp, enable: true);
9431	}
9432
9433	static void rtl8153_unload(struct r8152 *tp)
9434	{
9435	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9436	return;
9437
9438	r8153_power_cut_en(tp, enable: false);
9439	}
9440
9441	static void rtl8153b_unload(struct r8152 *tp)
9442	{
9443	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
9444	return;
9445
9446	r8153b_power_cut_en(tp, enable: false);
9447	}
9448
9449	static int rtl_ops_init(struct r8152 *tp)
9450	{
9451	struct rtl_ops *ops = &tp->rtl_ops;
9452	int ret = 0;
9453
9454	switch (tp->version) {
9455	case RTL_VER_01:
9456	case RTL_VER_02:
9457	case RTL_VER_07:
9458	ops->init = r8152b_init;
9459	ops->enable = rtl8152_enable;
9460	ops->disable = rtl8152_disable;
9461	ops->up = rtl8152_up;
9462	ops->down = rtl8152_down;
9463	ops->unload = rtl8152_unload;
9464	ops->eee_get = r8152_get_eee;
9465	ops->eee_set = r8152_set_eee;
9466	ops->in_nway = rtl8152_in_nway;
9467	ops->hw_phy_cfg = r8152b_hw_phy_cfg;
9468	ops->autosuspend_en = rtl_runtime_suspend_enable;
9469	tp->rx_buf_sz = 16 * 1024;
9470	tp->eee_en = true;
9471	tp->eee_adv = MDIO_EEE_100TX;
9472	break;
9473
9474	case RTL_VER_03:
9475	case RTL_VER_04:
9476	case RTL_VER_05:
9477	case RTL_VER_06:
9478	ops->init = r8153_init;
9479	ops->enable = rtl8153_enable;
9480	ops->disable = rtl8153_disable;
9481	ops->up = rtl8153_up;
9482	ops->down = rtl8153_down;
9483	ops->unload = rtl8153_unload;
9484	ops->eee_get = r8153_get_eee;
9485	ops->eee_set = r8152_set_eee;
9486	ops->in_nway = rtl8153_in_nway;
9487	ops->hw_phy_cfg = r8153_hw_phy_cfg;
9488	ops->autosuspend_en = rtl8153_runtime_enable;
9489	ops->change_mtu = rtl8153_change_mtu;
9490	if (tp->udev->speed < USB_SPEED_SUPER)
9491	tp->rx_buf_sz = 16 * 1024;
9492	else
9493	tp->rx_buf_sz = 32 * 1024;
9494	tp->eee_en = true;
9495	tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9496	break;
9497
9498	case RTL_VER_08:
9499	case RTL_VER_09:
9500	ops->init = r8153b_init;
9501	ops->enable = rtl8153_enable;
9502	ops->disable = rtl8153_disable;
9503	ops->up = rtl8153b_up;
9504	ops->down = rtl8153b_down;
9505	ops->unload = rtl8153b_unload;
9506	ops->eee_get = r8153_get_eee;
9507	ops->eee_set = r8152_set_eee;
9508	ops->in_nway = rtl8153_in_nway;
9509	ops->hw_phy_cfg = r8153b_hw_phy_cfg;
9510	ops->autosuspend_en = rtl8153b_runtime_enable;
9511	ops->change_mtu = rtl8153_change_mtu;
9512	tp->rx_buf_sz = 32 * 1024;
9513	tp->eee_en = true;
9514	tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9515	break;
9516
9517	case RTL_VER_11:
9518	tp->eee_en = true;
9519	tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9520	fallthrough;
9521	case RTL_VER_10:
9522	ops->init = r8156_init;
9523	ops->enable = rtl8156_enable;
9524	ops->disable = rtl8156_disable;
9525	ops->up = rtl8156_up;
9526	ops->down = rtl8156_down;
9527	ops->unload = rtl8153_unload;
9528	ops->eee_get = r8153_get_eee;
9529	ops->eee_set = r8152_set_eee;
9530	ops->in_nway = rtl8153_in_nway;
9531	ops->hw_phy_cfg = r8156_hw_phy_cfg;
9532	ops->autosuspend_en = rtl8156_runtime_enable;
9533	ops->change_mtu = rtl8156_change_mtu;
9534	tp->rx_buf_sz = 48 * 1024;
9535	tp->support_2500full = 1;
9536	break;
9537
9538	case RTL_VER_12:
9539	case RTL_VER_13:
9540	tp->support_2500full = 1;
9541	fallthrough;
9542	case RTL_VER_15:
9543	tp->eee_en = true;
9544	tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9545	ops->init = r8156b_init;
9546	ops->enable = rtl8156b_enable;
9547	ops->disable = rtl8153_disable;
9548	ops->up = rtl8156_up;
9549	ops->down = rtl8156_down;
9550	ops->unload = rtl8153_unload;
9551	ops->eee_get = r8153_get_eee;
9552	ops->eee_set = r8152_set_eee;
9553	ops->in_nway = rtl8153_in_nway;
9554	ops->hw_phy_cfg = r8156b_hw_phy_cfg;
9555	ops->autosuspend_en = rtl8156_runtime_enable;
9556	ops->change_mtu = rtl8156_change_mtu;
9557	tp->rx_buf_sz = 48 * 1024;
9558	break;
9559
9560	case RTL_VER_14:
9561	ops->init = r8153c_init;
9562	ops->enable = rtl8153_enable;
9563	ops->disable = rtl8153_disable;
9564	ops->up = rtl8153c_up;
9565	ops->down = rtl8153b_down;
9566	ops->unload = rtl8153_unload;
9567	ops->eee_get = r8153_get_eee;
9568	ops->eee_set = r8152_set_eee;
9569	ops->in_nway = rtl8153_in_nway;
9570	ops->hw_phy_cfg = r8153c_hw_phy_cfg;
9571	ops->autosuspend_en = rtl8153c_runtime_enable;
9572	ops->change_mtu = rtl8153c_change_mtu;
9573	tp->rx_buf_sz = 32 * 1024;
9574	tp->eee_en = true;
9575	tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9576	break;
9577
9578	default:
9579	ret = -ENODEV;
9580	dev_err(&tp->intf->dev, "Unknown Device\n");
9581	break;
9582	}
9583
9584	return ret;
9585	}
9586
9587	#define FIRMWARE_8153A_2 "rtl_nic/rtl8153a-2.fw"
9588	#define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw"
9589	#define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw"
9590	#define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw"
9591	#define FIRMWARE_8153C_1 "rtl_nic/rtl8153c-1.fw"
9592	#define FIRMWARE_8156A_2 "rtl_nic/rtl8156a-2.fw"
9593	#define FIRMWARE_8156B_2 "rtl_nic/rtl8156b-2.fw"
9594
9595	MODULE_FIRMWARE(FIRMWARE_8153A_2);
9596	MODULE_FIRMWARE(FIRMWARE_8153A_3);
9597	MODULE_FIRMWARE(FIRMWARE_8153A_4);
9598	MODULE_FIRMWARE(FIRMWARE_8153B_2);
9599	MODULE_FIRMWARE(FIRMWARE_8153C_1);
9600	MODULE_FIRMWARE(FIRMWARE_8156A_2);
9601	MODULE_FIRMWARE(FIRMWARE_8156B_2);
9602
9603	static int rtl_fw_init(struct r8152 *tp)
9604	{
9605	struct rtl_fw *rtl_fw = &tp->rtl_fw;
9606
9607	switch (tp->version) {
9608	case RTL_VER_04:
9609	rtl_fw->fw_name = FIRMWARE_8153A_2;
9610	rtl_fw->pre_fw = r8153_pre_firmware_1;
9611	rtl_fw->post_fw = r8153_post_firmware_1;
9612	break;
9613	case RTL_VER_05:
9614	rtl_fw->fw_name = FIRMWARE_8153A_3;
9615	rtl_fw->pre_fw = r8153_pre_firmware_2;
9616	rtl_fw->post_fw = r8153_post_firmware_2;
9617	break;
9618	case RTL_VER_06:
9619	rtl_fw->fw_name = FIRMWARE_8153A_4;
9620	rtl_fw->post_fw = r8153_post_firmware_3;
9621	break;
9622	case RTL_VER_09:
9623	rtl_fw->fw_name = FIRMWARE_8153B_2;
9624	rtl_fw->pre_fw = r8153b_pre_firmware_1;
9625	rtl_fw->post_fw = r8153b_post_firmware_1;
9626	break;
9627	case RTL_VER_11:
9628	rtl_fw->fw_name = FIRMWARE_8156A_2;
9629	rtl_fw->post_fw = r8156a_post_firmware_1;
9630	break;
9631	case RTL_VER_13:
9632	case RTL_VER_15:
9633	rtl_fw->fw_name = FIRMWARE_8156B_2;
9634	break;
9635	case RTL_VER_14:
9636	rtl_fw->fw_name = FIRMWARE_8153C_1;
9637	rtl_fw->pre_fw = r8153b_pre_firmware_1;
9638	rtl_fw->post_fw = r8153c_post_firmware_1;
9639	break;
9640	default:
9641	break;
9642	}
9643
9644	return 0;
9645	}
9646
9647	static u8 __rtl_get_hw_ver(struct usb_device *udev)
9648	{
9649	u32 ocp_data = 0;
9650	__le32 *tmp;
9651	u8 version;
9652	int ret;
9653	int i;
9654
9655	tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
9656	if (!tmp)
9657	return 0;
9658
9659	/* Retry up to 3 times in case there is a transitory error. We do this
9660	* since retrying a read of the version is always safe and this
9661	* function doesn't take advantage of r8152_control_msg().
9662	*/
9663	for (i = 0; i < 3; i++) {
9664	ret = usb_control_msg(dev: udev, usb_rcvctrlpipe(udev, 0),
9665	RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
9666	PLA_TCR0, MCU_TYPE_PLA, data: tmp, size: sizeof(*tmp),
9667	USB_CTRL_GET_TIMEOUT);
9668	if (ret > 0) {
9669	ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
9670	break;
9671	}
9672	}
9673
9674	if (i != 0 && ret > 0)
9675	dev_warn(&udev->dev, "Needed %d retries to read version\n", i);
9676
9677	kfree(objp: tmp);
9678
9679	switch (ocp_data) {
9680	case 0x4c00:
9681	version = RTL_VER_01;
9682	break;
9683	case 0x4c10:
9684	version = RTL_VER_02;
9685	break;
9686	case 0x5c00:
9687	version = RTL_VER_03;
9688	break;
9689	case 0x5c10:
9690	version = RTL_VER_04;
9691	break;
9692	case 0x5c20:
9693	version = RTL_VER_05;
9694	break;
9695	case 0x5c30:
9696	version = RTL_VER_06;
9697	break;
9698	case 0x4800:
9699	version = RTL_VER_07;
9700	break;
9701	case 0x6000:
9702	version = RTL_VER_08;
9703	break;
9704	case 0x6010:
9705	version = RTL_VER_09;
9706	break;
9707	case 0x7010:
9708	version = RTL_TEST_01;
9709	break;
9710	case 0x7020:
9711	version = RTL_VER_10;
9712	break;
9713	case 0x7030:
9714	version = RTL_VER_11;
9715	break;
9716	case 0x7400:
9717	version = RTL_VER_12;
9718	break;
9719	case 0x7410:
9720	version = RTL_VER_13;
9721	break;
9722	case 0x6400:
9723	version = RTL_VER_14;
9724	break;
9725	case 0x7420:
9726	version = RTL_VER_15;
9727	break;
9728	default:
9729	version = RTL_VER_UNKNOWN;
9730	dev_info(&udev->dev, "Unknown version 0x%04x\n", ocp_data);
9731	break;
9732	}
9733
9734	return version;
9735	}
9736
9737	u8 rtl8152_get_version(struct usb_interface *intf)
9738	{
9739	u8 version;
9740
9741	version = __rtl_get_hw_ver(interface_to_usbdev(intf));
9742
9743	dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
9744
9745	return version;
9746	}
9747	EXPORT_SYMBOL_GPL(rtl8152_get_version);
9748
9749	static bool rtl8152_supports_lenovo_macpassthru(struct usb_device *udev)
9750	{
9751	int parent_vendor_id = le16_to_cpu(udev->parent->descriptor.idVendor);
9752	int product_id = le16_to_cpu(udev->descriptor.idProduct);
9753	int vendor_id = le16_to_cpu(udev->descriptor.idVendor);
9754
9755	if (vendor_id == VENDOR_ID_LENOVO) {
9756	switch (product_id) {
9757	case DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB:
9758	case DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK:
9759	case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
9760	case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
9761	case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3:
9762	case DEVICE_ID_THINKPAD_USB_C_DONGLE:
9763	case DEVICE_ID_THINKPAD_HYBRID_USB_C_DOCK:
9764	return 1;
9765	}
9766	} else if (vendor_id == VENDOR_ID_REALTEK && parent_vendor_id == VENDOR_ID_LENOVO) {
9767	switch (product_id) {
9768	case 0x8153:
9769	return 1;
9770	}
9771	}
9772	return 0;
9773	}
9774
9775	static int rtl8152_probe_once(struct usb_interface *intf,
9776	const struct usb_device_id *id, u8 version)
9777	{
9778	struct usb_device *udev = interface_to_usbdev(intf);
9779	struct r8152 *tp;
9780	struct net_device *netdev;
9781	int ret;
9782
9783	usb_reset_device(dev: udev);
9784	netdev = alloc_etherdev(sizeof(struct r8152));
9785	if (!netdev) {
9786	dev_err(&intf->dev, "Out of memory\n");
9787	return -ENOMEM;
9788	}
9789
9790	SET_NETDEV_DEV(netdev, &intf->dev);
9791	tp = netdev_priv(dev: netdev);
9792	tp->msg_enable = 0x7FFF;
9793
9794	tp->udev = udev;
9795	tp->netdev = netdev;
9796	tp->intf = intf;
9797	tp->version = version;
9798
9799	tp->pipe_ctrl_in = usb_rcvctrlpipe(udev, 0);
9800	tp->pipe_ctrl_out = usb_sndctrlpipe(udev, 0);
9801	tp->pipe_in = usb_rcvbulkpipe(udev, 1);
9802	tp->pipe_out = usb_sndbulkpipe(udev, 2);
9803	tp->pipe_intr = usb_rcvintpipe(udev, 3);
9804
9805	switch (version) {
9806	case RTL_VER_01:
9807	case RTL_VER_02:
9808	case RTL_VER_07:
9809	tp->mii.supports_gmii = 0;
9810	break;
9811	default:
9812	tp->mii.supports_gmii = 1;
9813	break;
9814	}
9815
9816	ret = rtl_ops_init(tp);
9817	if (ret)
9818	goto out;
9819
9820	rtl_fw_init(tp);
9821
9822	mutex_init(&tp->control);
9823	INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
9824	INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
9825	tasklet_setup(t: &tp->tx_tl, callback: bottom_half);
9826	tasklet_disable(t: &tp->tx_tl);
9827
9828	netdev->netdev_ops = &rtl8152_netdev_ops;
9829	netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
9830
9831	netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9832	NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
9833	NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
9834	NETIF_F_HW_VLAN_CTAG_TX;
9835	netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9836	NETIF_F_TSO | NETIF_F_FRAGLIST |
9837	NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
9838	NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
9839	netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
9840	NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
9841	NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
9842
9843	if (tp->version == RTL_VER_01) {
9844	netdev->features &= ~NETIF_F_RXCSUM;
9845	netdev->hw_features &= ~NETIF_F_RXCSUM;
9846	}
9847
9848	tp->lenovo_macpassthru = rtl8152_supports_lenovo_macpassthru(udev);
9849
9850	if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
9851	(!strcmp(udev->serial, "000001000000") ||
9852	!strcmp(udev->serial, "000002000000"))) {
9853	dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
9854	tp->dell_tb_rx_agg_bug = 1;
9855	}
9856
9857	netdev->ethtool_ops = &ops;
9858	netif_set_tso_max_size(dev: netdev, RTL_LIMITED_TSO_SIZE);
9859
9860	/* MTU range: 68 - 1500 or 9194 */
9861	netdev->min_mtu = ETH_MIN_MTU;
9862	switch (tp->version) {
9863	case RTL_VER_03:
9864	case RTL_VER_04:
9865	case RTL_VER_05:
9866	case RTL_VER_06:
9867	case RTL_VER_08:
9868	case RTL_VER_09:
9869	case RTL_VER_14:
9870	netdev->max_mtu = size_to_mtu(9 * 1024);
9871	break;
9872	case RTL_VER_10:
9873	case RTL_VER_11:
9874	netdev->max_mtu = size_to_mtu(15 * 1024);
9875	break;
9876	case RTL_VER_12:
9877	case RTL_VER_13:
9878	case RTL_VER_15:
9879	netdev->max_mtu = size_to_mtu(16 * 1024);
9880	break;
9881	case RTL_VER_01:
9882	case RTL_VER_02:
9883	case RTL_VER_07:
9884	default:
9885	netdev->max_mtu = ETH_DATA_LEN;
9886	break;
9887	}
9888
9889	tp->mii.dev = netdev;
9890	tp->mii.mdio_read = read_mii_word;
9891	tp->mii.mdio_write = write_mii_word;
9892	tp->mii.phy_id_mask = 0x3f;
9893	tp->mii.reg_num_mask = 0x1f;
9894	tp->mii.phy_id = R8152_PHY_ID;
9895
9896	tp->autoneg = AUTONEG_ENABLE;
9897	tp->speed = SPEED_100;
9898	tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
9899	RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
9900	if (tp->mii.supports_gmii) {
9901	if (tp->support_2500full &&
9902	tp->udev->speed >= USB_SPEED_SUPER) {
9903	tp->speed = SPEED_2500;
9904	tp->advertising |= RTL_ADVERTISED_2500_FULL;
9905	} else {
9906	tp->speed = SPEED_1000;
9907	}
9908	tp->advertising |= RTL_ADVERTISED_1000_FULL;
9909	}
9910	tp->duplex = DUPLEX_FULL;
9911
9912	tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
9913	tp->rx_pending = 10 * RTL8152_MAX_RX;
9914
9915	intf->needs_remote_wakeup = 1;
9916
9917	if (!rtl_can_wakeup(tp))
9918	__rtl_set_wol(tp, wolopts: 0);
9919	else
9920	tp->saved_wolopts = __rtl_get_wol(tp);
9921
9922	tp->rtl_ops.init(tp);
9923	#if IS_BUILTIN(CONFIG_USB_RTL8152)
9924	/* Retry in case request_firmware() is not ready yet. */
9925	tp->rtl_fw.retry = true;
9926	#endif
9927	queue_delayed_work(wq: system_long_wq, dwork: &tp->hw_phy_work, delay: 0);
9928	set_ethernet_addr(tp, in_resume: false);
9929
9930	usb_set_intfdata(intf, data: tp);
9931
9932	netif_napi_add(dev: netdev, napi: &tp->napi, poll: r8152_poll);
9933
9934	ret = register_netdev(dev: netdev);
9935	if (ret != 0) {
9936	dev_err(&intf->dev, "couldn't register the device\n");
9937	goto out1;
9938	}
9939
9940	if (tp->saved_wolopts)
9941	device_set_wakeup_enable(dev: &udev->dev, enable: true);
9942	else
9943	device_set_wakeup_enable(dev: &udev->dev, enable: false);
9944
9945	/* If we saw a control transfer error while probing then we may
9946	* want to try probe() again. Consider this an error.
9947	*/
9948	if (test_bit(PROBE_SHOULD_RETRY, &tp->flags))
9949	goto out2;
9950
9951	set_bit(nr: PROBED_WITH_NO_ERRORS, addr: &tp->flags);
9952	netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
9953
9954	return 0;
9955
9956	out2:
9957	unregister_netdev(dev: netdev);
9958
9959	out1:
9960	tasklet_kill(t: &tp->tx_tl);
9961	cancel_delayed_work_sync(dwork: &tp->hw_phy_work);
9962	if (tp->rtl_ops.unload)
9963	tp->rtl_ops.unload(tp);
9964	rtl8152_release_firmware(tp);
9965	usb_set_intfdata(intf, NULL);
9966	out:
9967	if (test_bit(PROBE_SHOULD_RETRY, &tp->flags))
9968	ret = -EAGAIN;
9969
9970	free_netdev(dev: netdev);
9971	return ret;
9972	}
9973
9974	#define RTL8152_PROBE_TRIES 3
9975
9976	static int rtl8152_probe(struct usb_interface *intf,
9977	const struct usb_device_id *id)
9978	{
9979	u8 version;
9980	int ret;
9981	int i;
9982
9983	if (intf->cur_altsetting->desc.bInterfaceClass != USB_CLASS_VENDOR_SPEC)
9984	return -ENODEV;
9985
9986	if (!rtl_check_vendor_ok(intf))
9987	return -ENODEV;
9988
9989	version = rtl8152_get_version(intf);
9990	if (version == RTL_VER_UNKNOWN)
9991	return -ENODEV;
9992
9993	for (i = 0; i < RTL8152_PROBE_TRIES; i++) {
9994	ret = rtl8152_probe_once(intf, id, version);
9995	if (ret != -EAGAIN)
9996	break;
9997	}
9998	if (ret == -EAGAIN) {
9999	dev_err(&intf->dev,
10000	"r8152 failed probe after %d tries; giving up\n", i);
10001	return -ENODEV;
10002	}
10003
10004	return ret;
10005	}
10006
10007	static void rtl8152_disconnect(struct usb_interface *intf)
10008	{
10009	struct r8152 *tp = usb_get_intfdata(intf);
10010
10011	usb_set_intfdata(intf, NULL);
10012	if (tp) {
10013	rtl_set_unplug(tp);
10014
10015	unregister_netdev(dev: tp->netdev);
10016	tasklet_kill(t: &tp->tx_tl);
10017	cancel_delayed_work_sync(dwork: &tp->hw_phy_work);
10018	if (tp->rtl_ops.unload)
10019	tp->rtl_ops.unload(tp);
10020	rtl8152_release_firmware(tp);
10021	free_netdev(dev: tp->netdev);
10022	}
10023	}
10024
10025	/* table of devices that work with this driver */
10026	static const struct usb_device_id rtl8152_table[] = {
10027	/* Realtek */
10028	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8050) },
10029	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8053) },
10030	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8152) },
10031	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8153) },
10032	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8155) },
10033	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8156) },
10034
10035	/* Microsoft */
10036	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab) },
10037	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6) },
10038	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927) },
10039	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0c5e) },
10040	{ USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101) },
10041
10042	/* Lenovo */
10043	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x304f) },
10044	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x3054) },
10045	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x3062) },
10046	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x3069) },
10047	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x3082) },
10048	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x3098) },
10049	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x7205) },
10050	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x720c) },
10051	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x7214) },
10052	{ USB_DEVICE(VENDOR_ID_LENOVO, 0x721e) },
10053	{ USB_DEVICE(VENDOR_ID_LENOVO, 0xa359) },
10054	{ USB_DEVICE(VENDOR_ID_LENOVO, 0xa387) },
10055
10056	{ USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041) },
10057	{ USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff) },
10058	{ USB_DEVICE(VENDOR_ID_TPLINK, 0x0601) },
10059	{ USB_DEVICE(VENDOR_ID_TPLINK, 0x0602) },
10060	{ USB_DEVICE(VENDOR_ID_DLINK, 0xb301) },
10061	{ USB_DEVICE(VENDOR_ID_DELL, 0xb097) },
10062	{ USB_DEVICE(VENDOR_ID_ASUS, 0x1976) },
10063	{}
10064	};
10065
10066	MODULE_DEVICE_TABLE(usb, rtl8152_table);
10067
10068	static struct usb_driver rtl8152_driver = {
10069	.name = MODULENAME,
10070	.id_table = rtl8152_table,
10071	.probe = rtl8152_probe,
10072	.disconnect = rtl8152_disconnect,
10073	.suspend = rtl8152_suspend,
10074	.resume = rtl8152_resume,
10075	.reset_resume = rtl8152_reset_resume,
10076	.pre_reset = rtl8152_pre_reset,
10077	.post_reset = rtl8152_post_reset,
10078	.supports_autosuspend = 1,
10079	.disable_hub_initiated_lpm = 1,
10080	};
10081
10082	static int rtl8152_cfgselector_choose_configuration(struct usb_device *udev)
10083	{
10084	struct usb_host_config *c;
10085	int i, num_configs;
10086
10087	/* Switch the device to vendor mode, if and only if the vendor mode
10088	* driver supports it.
10089	*/
10090	if (__rtl_get_hw_ver(udev) == RTL_VER_UNKNOWN)
10091	return -ENODEV;
10092
10093	/* The vendor mode is not always config #1, so to find it out. */
10094	c = udev->config;
10095	num_configs = udev->descriptor.bNumConfigurations;
10096	for (i = 0; i < num_configs; (i++, c++)) {
10097	struct usb_interface_descriptor *desc = NULL;
10098
10099	if (!c->desc.bNumInterfaces)
10100	continue;
10101	desc = &c->intf_cache[0]->altsetting->desc;
10102	if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC)
10103	break;
10104	}
10105
10106	if (i == num_configs)
10107	return -ENODEV;
10108
10109	return c->desc.bConfigurationValue;
10110	}
10111
10112	static struct usb_device_driver rtl8152_cfgselector_driver = {
10113	.name = MODULENAME "-cfgselector",
10114	.choose_configuration = rtl8152_cfgselector_choose_configuration,
10115	.id_table = rtl8152_table,
10116	.generic_subclass = 1,
10117	.supports_autosuspend = 1,
10118	};
10119
10120	static int __init rtl8152_driver_init(void)
10121	{
10122	int ret;
10123
10124	ret = usb_register_device_driver(&rtl8152_cfgselector_driver, THIS_MODULE);
10125	if (ret)
10126	return ret;
10127
10128	ret = usb_register(&rtl8152_driver);
10129	if (ret)
10130	usb_deregister_device_driver(&rtl8152_cfgselector_driver);
10131
10132	return ret;
10133	}
10134
10135	static void __exit rtl8152_driver_exit(void)
10136	{
10137	usb_deregister(&rtl8152_driver);
10138	usb_deregister_device_driver(&rtl8152_cfgselector_driver);
10139	}
10140
10141	module_init(rtl8152_driver_init);
10142	module_exit(rtl8152_driver_exit);
10143
10144	MODULE_AUTHOR(DRIVER_AUTHOR);
10145	MODULE_DESCRIPTION(DRIVER_DESC);
10146	MODULE_LICENSE("GPL");
10147	MODULE_VERSION(DRIVER_VERSION);
10148