| 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | |
| 3 | /* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. |
| 4 | * Copyright (C) 2018-2024 Linaro Ltd. |
| 5 | */ |
| 6 | |
| 7 | /* DOC: IPA Interrupts |
| 8 | * |
| 9 | * The IPA has an interrupt line distinct from the interrupt used by the GSI |
| 10 | * code. Whereas GSI interrupts are generally related to channel events (like |
| 11 | * transfer completions), IPA interrupts are related to other events related |
| 12 | * to the IPA. Some of the IPA interrupts come from a microcontroller |
| 13 | * embedded in the IPA. Each IPA interrupt type can be both masked and |
| 14 | * acknowledged independent of the others. |
| 15 | * |
| 16 | * Two of the IPA interrupts are initiated by the microcontroller. A third |
| 17 | * can be generated to signal the need for a wakeup/resume when an IPA |
| 18 | * endpoint has been suspended. There are other IPA events, but at this |
| 19 | * time only these three are supported. |
| 20 | */ |
| 21 | |
| 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/pm_runtime.h> |
| 25 | #include <linux/pm_wakeirq.h> |
| 26 | #include <linux/types.h> |
| 27 | |
| 28 | #include "ipa.h" |
| 29 | #include "ipa_endpoint.h" |
| 30 | #include "ipa_interrupt.h" |
| 31 | #include "ipa_power.h" |
| 32 | #include "ipa_reg.h" |
| 33 | #include "ipa_uc.h" |
| 34 | |
| 35 | /** |
| 36 | * struct ipa_interrupt - IPA interrupt information |
| 37 | * @ipa: IPA pointer |
| 38 | * @irq: Linux IRQ number used for IPA interrupts |
| 39 | * @enabled: Mask indicating which interrupts are enabled |
| 40 | * @suspend_enabled: Bitmap of endpoints with the SUSPEND interrupt enabled |
| 41 | */ |
| 42 | struct ipa_interrupt { |
| 43 | struct ipa *ipa; |
| 44 | u32 irq; |
| 45 | u32 enabled; |
| 46 | unsigned long *suspend_enabled; |
| 47 | }; |
| 48 | |
| 49 | /* Clear the suspend interrupt for all endpoints that signaled it */ |
| 50 | static void ipa_interrupt_suspend_clear_all(struct ipa_interrupt *interrupt) |
| 51 | { |
| 52 | struct ipa *ipa = interrupt->ipa; |
| 53 | u32 unit_count; |
| 54 | u32 unit; |
| 55 | |
| 56 | unit_count = DIV_ROUND_UP(ipa->endpoint_count, 32); |
| 57 | for (unit = 0; unit < unit_count; unit++) { |
| 58 | const struct reg *reg; |
| 59 | u32 val; |
| 60 | |
| 61 | reg = ipa_reg(ipa, reg_id: IRQ_SUSPEND_INFO); |
| 62 | val = ioread32(ipa->reg_virt + reg_n_offset(reg, n: unit)); |
| 63 | |
| 64 | /* SUSPEND interrupt status isn't cleared on IPA version 3.0 */ |
| 65 | if (!val || ipa->version == IPA_VERSION_3_0) |
| 66 | continue; |
| 67 | |
| 68 | reg = ipa_reg(ipa, reg_id: IRQ_SUSPEND_CLR); |
| 69 | iowrite32(val, ipa->reg_virt + reg_n_offset(reg, n: unit)); |
| 70 | } |
| 71 | } |
| 72 | |
| 73 | /* Process a particular interrupt type that has been received */ |
| 74 | static void ipa_interrupt_process(struct ipa_interrupt *interrupt, u32 irq_id) |
| 75 | { |
| 76 | struct ipa *ipa = interrupt->ipa; |
| 77 | const struct reg *reg; |
| 78 | u32 mask = BIT(irq_id); |
| 79 | u32 offset; |
| 80 | |
| 81 | reg = ipa_reg(ipa, reg_id: IPA_IRQ_CLR); |
| 82 | offset = reg_offset(reg); |
| 83 | |
| 84 | switch (irq_id) { |
| 85 | case IPA_IRQ_UC_0: |
| 86 | case IPA_IRQ_UC_1: |
| 87 | /* For microcontroller interrupts, clear the interrupt right |
| 88 | * away, "to avoid clearing unhandled interrupts." |
| 89 | */ |
| 90 | iowrite32(mask, ipa->reg_virt + offset); |
| 91 | ipa_uc_interrupt_handler(ipa, irq_id); |
| 92 | break; |
| 93 | |
| 94 | case IPA_IRQ_TX_SUSPEND: |
| 95 | /* Clearing the SUSPEND_TX interrupt also clears the |
| 96 | * register that tells us which suspended endpoint(s) |
| 97 | * caused the interrupt, so defer clearing until after |
| 98 | * the handler has been called. |
| 99 | */ |
| 100 | ipa_interrupt_suspend_clear_all(interrupt); |
| 101 | fallthrough; |
| 102 | |
| 103 | default: /* Silently ignore (and clear) any other condition */ |
| 104 | iowrite32(mask, ipa->reg_virt + offset); |
| 105 | break; |
| 106 | } |
| 107 | } |
| 108 | |
| 109 | /* IPA IRQ handler is threaded */ |
| 110 | static irqreturn_t ipa_isr_thread(int irq, void *dev_id) |
| 111 | { |
| 112 | struct ipa_interrupt *interrupt = dev_id; |
| 113 | struct ipa *ipa = interrupt->ipa; |
| 114 | u32 enabled = interrupt->enabled; |
| 115 | struct device *dev = ipa->dev; |
| 116 | const struct reg *reg; |
| 117 | u32 pending; |
| 118 | u32 offset; |
| 119 | u32 mask; |
| 120 | int ret; |
| 121 | |
| 122 | ret = pm_runtime_get_sync(dev); |
| 123 | if (WARN_ON(ret < 0)) |
| 124 | goto out_power_put; |
| 125 | |
| 126 | /* The status register indicates which conditions are present, |
| 127 | * including conditions whose interrupt is not enabled. Handle |
| 128 | * only the enabled ones. |
| 129 | */ |
| 130 | reg = ipa_reg(ipa, reg_id: IPA_IRQ_STTS); |
| 131 | offset = reg_offset(reg); |
| 132 | pending = ioread32(ipa->reg_virt + offset); |
| 133 | while ((mask = pending & enabled)) { |
| 134 | do { |
| 135 | u32 irq_id = __ffs(mask); |
| 136 | |
| 137 | mask ^= BIT(irq_id); |
| 138 | |
| 139 | ipa_interrupt_process(interrupt, irq_id); |
| 140 | } while (mask); |
| 141 | pending = ioread32(ipa->reg_virt + offset); |
| 142 | } |
| 143 | |
| 144 | /* If any disabled interrupts are pending, clear them */ |
| 145 | if (pending) { |
| 146 | dev_dbg(dev, "clearing disabled IPA interrupts 0x%08x\n" , |
| 147 | pending); |
| 148 | reg = ipa_reg(ipa, reg_id: IPA_IRQ_CLR); |
| 149 | iowrite32(pending, ipa->reg_virt + reg_offset(reg)); |
| 150 | } |
| 151 | out_power_put: |
| 152 | (void)pm_runtime_put_autosuspend(dev); |
| 153 | |
| 154 | return IRQ_HANDLED; |
| 155 | } |
| 156 | |
| 157 | static void ipa_interrupt_enabled_update(struct ipa *ipa) |
| 158 | { |
| 159 | const struct reg *reg = ipa_reg(ipa, reg_id: IPA_IRQ_EN); |
| 160 | |
| 161 | iowrite32(ipa->interrupt->enabled, ipa->reg_virt + reg_offset(reg)); |
| 162 | } |
| 163 | |
| 164 | /* Enable an IPA interrupt type */ |
| 165 | void ipa_interrupt_enable(struct ipa *ipa, enum ipa_irq_id ipa_irq) |
| 166 | { |
| 167 | /* Update the IPA interrupt mask to enable it */ |
| 168 | ipa->interrupt->enabled |= BIT(ipa_irq); |
| 169 | ipa_interrupt_enabled_update(ipa); |
| 170 | } |
| 171 | |
| 172 | /* Disable an IPA interrupt type */ |
| 173 | void ipa_interrupt_disable(struct ipa *ipa, enum ipa_irq_id ipa_irq) |
| 174 | { |
| 175 | /* Update the IPA interrupt mask to disable it */ |
| 176 | ipa->interrupt->enabled &= ~BIT(ipa_irq); |
| 177 | ipa_interrupt_enabled_update(ipa); |
| 178 | } |
| 179 | |
| 180 | void ipa_interrupt_irq_disable(struct ipa *ipa) |
| 181 | { |
| 182 | disable_irq(irq: ipa->interrupt->irq); |
| 183 | } |
| 184 | |
| 185 | void ipa_interrupt_irq_enable(struct ipa *ipa) |
| 186 | { |
| 187 | enable_irq(irq: ipa->interrupt->irq); |
| 188 | } |
| 189 | |
| 190 | /* Common function used to enable/disable TX_SUSPEND for an endpoint */ |
| 191 | static void ipa_interrupt_suspend_control(struct ipa_interrupt *interrupt, |
| 192 | u32 endpoint_id, bool enable) |
| 193 | { |
| 194 | struct ipa *ipa = interrupt->ipa; |
| 195 | u32 mask = BIT(endpoint_id % 32); |
| 196 | u32 unit = endpoint_id / 32; |
| 197 | const struct reg *reg; |
| 198 | unsigned long weight; |
| 199 | u32 offset; |
| 200 | u32 val; |
| 201 | |
| 202 | WARN_ON(!test_bit(endpoint_id, ipa->available)); |
| 203 | |
| 204 | /* IPA version 3.0 does not support TX_SUSPEND interrupt control */ |
| 205 | if (ipa->version == IPA_VERSION_3_0) |
| 206 | return; |
| 207 | |
| 208 | weight = bitmap_weight(src: interrupt->suspend_enabled, nbits: ipa->endpoint_count); |
| 209 | if (weight == 1 && !enable) |
| 210 | ipa_interrupt_disable(ipa, ipa_irq: IPA_IRQ_TX_SUSPEND); |
| 211 | |
| 212 | reg = ipa_reg(ipa, reg_id: IRQ_SUSPEND_EN); |
| 213 | offset = reg_n_offset(reg, n: unit); |
| 214 | val = ioread32(ipa->reg_virt + offset); |
| 215 | |
| 216 | if (enable) |
| 217 | val |= mask; |
| 218 | else |
| 219 | val &= ~mask; |
| 220 | __change_bit(endpoint_id, interrupt->suspend_enabled); |
| 221 | |
| 222 | iowrite32(val, ipa->reg_virt + offset); |
| 223 | |
| 224 | if (!weight && enable) |
| 225 | ipa_interrupt_enable(ipa, ipa_irq: IPA_IRQ_TX_SUSPEND); |
| 226 | } |
| 227 | |
| 228 | /* Enable TX_SUSPEND for an endpoint */ |
| 229 | void |
| 230 | ipa_interrupt_suspend_enable(struct ipa_interrupt *interrupt, u32 endpoint_id) |
| 231 | { |
| 232 | ipa_interrupt_suspend_control(interrupt, endpoint_id, enable: true); |
| 233 | } |
| 234 | |
| 235 | /* Disable TX_SUSPEND for an endpoint */ |
| 236 | void |
| 237 | ipa_interrupt_suspend_disable(struct ipa_interrupt *interrupt, u32 endpoint_id) |
| 238 | { |
| 239 | ipa_interrupt_suspend_control(interrupt, endpoint_id, enable: false); |
| 240 | } |
| 241 | |
| 242 | /* Simulate arrival of an IPA TX_SUSPEND interrupt */ |
| 243 | void ipa_interrupt_simulate_suspend(struct ipa_interrupt *interrupt) |
| 244 | { |
| 245 | ipa_interrupt_process(interrupt, irq_id: IPA_IRQ_TX_SUSPEND); |
| 246 | } |
| 247 | |
| 248 | /* Configure the IPA interrupt framework */ |
| 249 | int ipa_interrupt_config(struct ipa *ipa) |
| 250 | { |
| 251 | struct ipa_interrupt *interrupt = ipa->interrupt; |
| 252 | unsigned int irq = interrupt->irq; |
| 253 | struct device *dev = ipa->dev; |
| 254 | const struct reg *reg; |
| 255 | int ret; |
| 256 | |
| 257 | interrupt->ipa = ipa; |
| 258 | |
| 259 | /* Initially all IPA interrupt types are disabled */ |
| 260 | interrupt->enabled = 0; |
| 261 | interrupt->suspend_enabled = bitmap_zalloc(nbits: ipa->endpoint_count, |
| 262 | GFP_KERNEL); |
| 263 | if (!interrupt->suspend_enabled) { |
| 264 | ret = -ENOMEM; |
| 265 | goto err_kfree; |
| 266 | } |
| 267 | |
| 268 | /* Disable IPA interrupt types */ |
| 269 | reg = ipa_reg(ipa, reg_id: IPA_IRQ_EN); |
| 270 | iowrite32(0, ipa->reg_virt + reg_offset(reg)); |
| 271 | |
| 272 | ret = request_threaded_irq(irq, NULL, thread_fn: ipa_isr_thread, IRQF_ONESHOT, |
| 273 | name: "ipa" , dev: interrupt); |
| 274 | if (ret) { |
| 275 | dev_err(dev, "error %d requesting \"ipa\" IRQ\n" , ret); |
| 276 | goto err_free_bitmap; |
| 277 | } |
| 278 | |
| 279 | ret = device_init_wakeup(dev, enable: true); |
| 280 | if (ret) { |
| 281 | dev_err(dev, "error %d enabling wakeup\n" , ret); |
| 282 | goto err_free_irq; |
| 283 | } |
| 284 | |
| 285 | ret = dev_pm_set_wake_irq(dev, irq); |
| 286 | if (ret) { |
| 287 | dev_err(dev, "error %d registering \"ipa\" IRQ as wakeirq\n" , |
| 288 | ret); |
| 289 | goto err_disable_wakeup; |
| 290 | } |
| 291 | |
| 292 | ipa->interrupt = interrupt; |
| 293 | |
| 294 | return 0; |
| 295 | |
| 296 | err_disable_wakeup: |
| 297 | (void)device_init_wakeup(dev, enable: false); |
| 298 | err_free_irq: |
| 299 | free_irq(interrupt->irq, interrupt); |
| 300 | err_free_bitmap: |
| 301 | bitmap_free(bitmap: interrupt->suspend_enabled); |
| 302 | err_kfree: |
| 303 | kfree(objp: interrupt); |
| 304 | |
| 305 | return ret; |
| 306 | } |
| 307 | |
| 308 | /* Inverse of ipa_interrupt_config() */ |
| 309 | void ipa_interrupt_deconfig(struct ipa *ipa) |
| 310 | { |
| 311 | struct ipa_interrupt *interrupt = ipa->interrupt; |
| 312 | struct device *dev = ipa->dev; |
| 313 | |
| 314 | ipa->interrupt = NULL; |
| 315 | |
| 316 | dev_pm_clear_wake_irq(dev); |
| 317 | (void)device_init_wakeup(dev, enable: false); |
| 318 | free_irq(interrupt->irq, interrupt); |
| 319 | bitmap_free(bitmap: interrupt->suspend_enabled); |
| 320 | } |
| 321 | |
| 322 | /* Initialize the IPA interrupt structure */ |
| 323 | struct ipa_interrupt *ipa_interrupt_init(struct platform_device *pdev) |
| 324 | { |
| 325 | struct ipa_interrupt *interrupt; |
| 326 | int irq; |
| 327 | |
| 328 | irq = platform_get_irq_byname(pdev, "ipa" ); |
| 329 | if (irq <= 0) |
| 330 | return ERR_PTR(error: irq ? : -EINVAL); |
| 331 | |
| 332 | interrupt = kzalloc(sizeof(*interrupt), GFP_KERNEL); |
| 333 | if (!interrupt) |
| 334 | return ERR_PTR(error: -ENOMEM); |
| 335 | interrupt->irq = irq; |
| 336 | |
| 337 | return interrupt; |
| 338 | } |
| 339 | |
| 340 | /* Inverse of ipa_interrupt_init() */ |
| 341 | void ipa_interrupt_exit(struct ipa_interrupt *interrupt) |
| 342 | { |
| 343 | kfree(objp: interrupt); |
| 344 | } |
| 345 | |